Memory bank fault analysis method and device, equipment and storage medium

Abstract

The invention discloses a memory bank fault analysis method, device and equipment and a storage medium, and relates to the technical field of server security management and control, the method comprises the following steps: reading an internal error state register of target memory equipment according to a preset monitoring period to obtain real-time error information; and performing fault prediction analysis based on the real-time error information to obtain a memory pre-fault judgment result corresponding to the target memory device. According to the method and the device, the internal hardware register is directly read to obtain the real-time error information, and the pre-fault state of the target memory equipment is accurately identified based on the real-time error information, so that the influence of a shielding effect of an on-chip error correction code on fault analysis can be avoided, and the accuracy and the reliability of fault prediction are improved. Therefore, the fault of the DDR5 memory bank can be recognized in advance by directly utilizing the data of the hardware register, and fault prediction of the DDR5 memory bank is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of server security management, and particularly relates to a memory bank fault analysis method and device, equipment and a storage medium. BACKGROUND

[0002] The RDIMM (Registered Dual In-Line Memory Module) used by a server usually has an ECC (Error Checking and Correcting) function, that is, when a single-bit flip occurs in a memory bank, it can be corrected, and the error at this time is called a CE (Corrected Error). However, the situation where two memory cells at each address have bit flips cannot be corrected in many cases, and this error is called a UCE (Uncorreted Error), which will cause the server to unexpectedly shut down, and the business may be affected.

[0003] Among them, the DDR5 (Double Data Rate 5 Synchronous Dynamic Random-Access Memory) memory bank adopts an On-die ECC (On-die Error Correction Code) technology, which masks single-bit errors and column faults, so that the traditional fault prediction method based on CE (Corrected Error) counting cannot work effectively, and the server equipped with the DDR5 memory bank may unexpectedly shut down due to the UCE (Uncorreted Error) uncorrectable error, affecting business continuity.

[0004] Therefore, how to propose a fault prediction method suitable for the DDR5 memory bank has become a problem to be solved. SUMMARY

[0005] The main purpose of the present application is to provide a memory bank fault analysis method, device, equipment and storage medium, which aims to solve the technical problem of how to propose a fault prediction method suitable for the DDR5 memory bank.

[0006] To achieve the above-mentioned purpose, the present application provides a memory bank fault analysis method, which comprises the following steps: reading an internal error state register of a target memory device according to a preset monitoring period to obtain real-time error information; performing fault prediction analysis based on the real-time error information to obtain a memory pre-fault determination result corresponding to the target memory device.

[0007] In an embodiment, the target memory device is a memory module supporting an on-chip error correction code. The internal error status register includes a mode register, which is accessed by an error patrol and clearing mode.

[0008] In an embodiment, the mode register includes a first error statistics register and a second error statistics register. The step of reading the internal error status register of the target memory device according to a preset monitoring period to obtain real-time error information includes: Obtaining a statistical object type corresponding to the first error statistics register, and reading a first statistical value corresponding to the first error statistics register according to a preset monitoring period and the statistical object type; Reading second statistical information corresponding to a target statistical dimension of the second error statistics register based on the preset monitoring period; Summarizing the first statistical value and the second statistical information as real-time error information.

[0009] In an embodiment, the statistical object type of the first error statistics register includes a number of error rows or a number of error code words; The target statistical dimension corresponding to the second error statistics register is a row with the most errors.

[0010] In an embodiment, the first statistical value is an error statistical result corresponding to the statistical object type; The second statistical information is address information corresponding to the row with the most errors.

[0011] In an embodiment, the step of performing fault prediction analysis based on the real-time error information to obtain a memory pre-fault determination result corresponding to the target memory device includes: Determining a preset monitoring parameter according to preconfigured information corresponding to the mode register, the preset monitoring parameter including a statistical threshold value corresponding to the first error statistics register, and a fault address information corresponding to the second error statistics register; Based on a comparison result between the first statistical value and the statistical threshold value, and / or an interaction relationship between the second statistical information and the fault address information, a memory pre-fault determination result corresponding to the target memory device is generated.

[0012] In an embodiment, the step of generating the memory pre-fault determination result corresponding to the target memory device based on the comparison result between the first statistical value and the statistical threshold value, and / or the interaction relationship between the second statistical information and the fault address information includes: If the first statistical value is greater than the statistical threshold value, it is determined that the target memory device is in a pre-failure state; Or, if the second statistical information belongs to the failure address information, it is determined that the target memory device is in a pre-failure state; Or, if the first statistical value is greater than the statistical threshold value, and the second statistical information belongs to the failure address information, it is determined that the target memory device is in a pre-failure state.

[0013] In addition, to achieve the above-mentioned purpose, the present application also provides a memory bank failure analysis device, which comprises: The data monitoring module is configured to read the internal error state register of the target memory device according to a preset monitoring period to obtain real-time error information. The failure analysis module is configured to perform failure prediction analysis based on the real-time error information to obtain a memory pre-failure determination result corresponding to the target memory device.

[0014] In addition, to achieve the above-mentioned purpose, the present application also provides a memory bank failure analysis device, which comprises:

[0015] In addition, to achieve the above-mentioned purpose, the present application also provides a storage medium, which is a computer readable storage medium, and a program for implementing a method is stored on the computer readable storage medium. The program for implementing the method is executed by a processor to implement the steps of the above-mentioned method.

[0016] The present application provides a memory bank failure analysis method, device, equipment and storage medium. The method comprises: reading the internal error state register of the target memory device according to a preset monitoring period to obtain real-time error information; performing failure prediction analysis based on the real-time error information to obtain a memory pre-failure determination result. The present application directly reads the internal hardware register to obtain real-time error information, and accurately identifies the pre-failure state of the target memory device based on the real-time error information, so as to bypass the shielding effect of the on-chip error correction code on the failure analysis, improve the accuracy and reliability of the failure prediction. Therefore, the present application can directly use the hardware register data to identify the failure of the DDR5 memory bank in advance, realize the failure prediction of the DDR5 memory bank, and ensure the safe operation of the server carrying the DDR5 memory bank. BRIEF DESCRIPTION OF DRAWINGS

[0017] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present application and, together with the specification, serve to explain the principles of the application.

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced as follows. Obviously, the drawings can also provide further understanding of the prior art for those of ordinary skill in the art without any creative effort.

[0019] Figure 1 The first flowchart of the memory fault analysis method in the embodiments of the present application is shown in FIG. 1. Figure 2 The second flowchart of the memory fault analysis method in the embodiments of the present application is shown in FIG. 2. Figure 3 The third flowchart of the memory fault analysis method in the embodiments of the present application is shown in FIG. 3. Figure 4 The first process diagram of the memory pre-fault analysis in the memory fault analysis method in the embodiments of the present application is shown in FIG. 4. Figure 5 The second process diagram of the memory pre-fault analysis in the memory fault analysis method in the embodiments of the present application is shown in FIG. 5. Figure 6 The module structure diagram of the memory fault analysis device in the embodiments of the present application is shown in FIG. 6. Figure 7 The device structure diagram of the hardware running environment involved in the memory fault analysis method in the embodiments of the present application is shown in FIG. 7.

[0020] The purposes, functional features and advantages of the present application will be further described with reference to the accompanying drawings in combination with the embodiments. DETAILED DESCRIPTION

[0021] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application, and are not used to limit the present application.

[0022] In order to better understand the technical solutions of the present application, the following will be described in detail in combination with the drawings in the specification and specific embodiments.

[0023] The main solution of the present application is: reading the internal error status register of the target memory device according to the preset monitoring period to obtain real-time error information; performing fault prediction analysis based on the real-time error information to obtain the memory pre-fault determination result corresponding to the target memory device.

[0024] At present, in order to solve this problem, in the era of SDRAM DDR4 memory, it is usually according to the total number of CE correctable errors of the memory bar to predict whether the memory bar will appear UCE uncorrectable error, so as to migrate the service in advance and avoid unexpected downtime. But this method needs to predict the fault on the basis of translating the address of the CE error unit into the physical address, which is not only a complicated process, and for DDR5 memory bar, due to the existence of on-die ECC, the internal single unit error is shielded, and part of the row / column fault cannot be displayed due to the same reason. But these invisible single-bit errors and part of the row / column faults may evolve into UCE uncorrectable error, which may cause the server to suddenly crash. Therefore, the traditional fault prediction method based on correctable error (CE) count cannot effectively work on DDR5 memory bar, and it is necessary to use a new method to predict the fault of DDR5 memory bar.

[0025] The present application directly reads the internal hardware register to obtain real-time error information, and realizes accurate identification of the pre-fault state of the target memory device based on the real-time error information, so as to bypass the shielding effect of on-die ECC on fault analysis and improve the accuracy and reliability of fault prediction. Therefore, the present application can directly use hardware register data to identify the fault of DDR5 memory bar in advance, realize the fault prediction of DDR5 memory bar, so as to gain time for service migration and reduce the downtime loss of servers carrying DDR5 memory bar.

[0026] It should be noted that the execution subject of the present embodiment can be a memory bar fault analysis system, or a computing service device with data processing, network communication and program running functions, such as a server, etc., or a memory bar fault analysis device connected with the server carrying the DDR5 memory bar, etc., which can realize the above functions, and the present embodiment does not make specific limitation. The following takes the memory bar fault analysis device (referred to as analysis device) as an example to illustrate the present embodiment and each of the following embodiments.

[0027] Based on this, the present embodiment provides a memory bar fault analysis method, referring to Figure 1 , Figure 1 The first flowchart of the memory bar fault analysis method of the present embodiment is shown in the figure.

[0028] In the present embodiment, the memory bar fault analysis method comprises steps S10-S20: Step S10, reading the internal error state register of the target memory device according to the preset monitoring period to obtain real-time error information; It is easy to understand that the above-mentioned preset monitoring period can be a time interval for periodically reading the internal error status register data of the target memory device. The interval can be flexibly configured according to the memory usage scene, stability requirement and hardware performance, for example, 24 hours (corresponding to the complete patrol period of the DDR5 SDRAM specification), and can also be adjusted to 12 hours, 8 hours, etc. according to actual needs.

[0029] It needs to be understood that the above-mentioned target memory device can be a memory product that needs to perform fault prediction analysis of UCE (Uncorreted Error, uncorrectable error), and in a feasible implementation manner, the target memory device in the embodiment is a memory module supporting on-die error correction code. The internal error status register includes a mode register, and the mode register is accessed through an error patrol and cleaning mode.

[0030] It can be understood that the above-mentioned memory module supporting on-die error correction code can be a memory module with built-in on-die error correction code (On-die ECC) function. The DRAM die of such memory module can realize single error correction (SEC, Single Error Correction) through an internal redundant array unit, and can calculate 8 ECC check bits using 128 data bits, and can automatically correct single-bit errors and column faults. In the embodiment, the target memory device can be preferably a DDR5 memory stick.

[0031] Meanwhile, in the embodiment, the target memory device can also be extended to subsequent memory products supporting on-die error correction code and error patrol and cleaning mode (ECS Mode, Error Check and Scrub Mode), such as DDR6, DDRn (n>6) and the like.

[0032] It needs to be noted that the above-mentioned internal error status register can be a hardware register in the target memory device for recording error-related information, and can be specifically a mode register (MR, Mode Register) defined in JESD79-5 (DDR5 SDRAM specification), which can realize data reading and writing and access through the error patrol and cleaning mode (ECS Mode).

[0033] It is easy to understand that the error patrol and cleaning mode is the memory internal error processing mode recommended by the DDR5 SDRAM specification, in which the DRAM can automatically read the memory cell, correct the error and write the corrected data back to the array (scrub error), while counting the error information to the corresponding mode register. In this embodiment, the error patrol and cleaning mode can be set to be triggered at least once every 24 hours (manual triggering can be performed by setting the fixed pin of the mode register, and automatic triggering can be performed by configuring the automatic ECS function in the self-refresh state of the memory controller), and a complete patrol and error cleaning is performed. After entering the ECS mode, the error statistics data in the mode register is in real-time updating state, and the analysis device can normally read the data in the mode register according to the preset monitoring period according to the specification instruction, to ensure the accuracy of the reading result.

[0034] It is understood that two MR (Mode Register) registers, EC (Error Counter) and EpRC (Error per Row Counter), are introduced in the execution process of the error patrol and cleaning mode. Therefore, in a possible implementation manner, with reference to Figure 2 , Figure 2 FIG. 2 is a second flowchart of the memory fault analysis method in the embodiment of the present application. In this embodiment, the mode register includes a first error statistics register and a second error statistics register, and step S10 includes steps A1-A3. Step A1, obtaining the statistical object type corresponding to the first error statistics register, and reading the first statistical value corresponding to the first error statistics register according to the preset monitoring period and the statistical object type; Step A2, reading the second statistical information corresponding to the target statistical dimension of the second error statistics register based on the preset monitoring period; Step A3, summarizing the first statistical value and the second statistical information into real-time error information.

[0035] It is understood that the first error statistics register described above can be a register in the mode register for counting error number related information, and specifically can be the EC register (which can correspond to MR20) described above, the statistical object of which can be configured through the MR14 register. Exemplarily, in this embodiment, the EC register can configure the statistical object type through the MR14 register, and the threshold of the EC register can be configured through the MR15 register. When the first statistical value corresponding to the statistical object type exceeds the threshold when the memory patrol and cleaning is performed at least once every 24 hours, the MR20 will be set to 1; if the number of errors is more, the multiple of the threshold is greater, and the value of the MR20 is greater.

[0036] The aforementioned second error statistics register can be a register in the mode register used to record specific error dimension information, namely the information of the aforementioned target statistical dimension, specifically the EpRC register (which can be stored in MR16~18). For example, in this embodiment, when a memory inspection and clearing is performed at least once every 24 hours, if any data row is found to meet the preset statistical conditions in the target statistical dimension, the second statistical information corresponding to that data row can be filled into MR16~18 of the EpRC register. If other data rows better meet the preset statistical conditions, the addresses of MR16~18 will be updated.

[0037] In one feasible implementation, in this embodiment, the statistical object type of the first error statistics register includes the number of rows with errors or the number of erroneous encoded words; The target statistical dimension corresponding to the second error statistics register is the row with the most errors.

[0038] It is easy to understand that in this embodiment, the statistical dimension of the first error statistics register (EC register), that is, the statistical object type mentioned above, may include two types: "number of rows with errors" and "number of code words with errors", which can be configured through the OP (Operand) bit [5] of the MR14 register. For example, if the user needs to focus on the error distribution at the memory row level and selects "number of rows with errors" as the statistical object type, it can be configured by setting the OP bit [5] of the MR14 register to 0; if the user needs to focus on the error details at the memory code word level and selects "number of code words with errors" as the statistical object type, it can be configured by setting the OP bit [5] of the MR14 register to 1.

[0039] The number of rows with errors can be the total number of rows with erroneous cells in each DRAM die. For example, if there is one or more erroneous cells in rows 10 and 25 of a die, then the number of rows with errors is 2.

[0040] The number of erroneous code words mentioned above can be the total number of erroneous code words in each DRAM die. In this embodiment, each code word can be composed of 128 data bits plus 8 ECC parity bits (compliant with DDR5 On-die ECC specification). If a data bit or parity bit in a code word is erroneous and is detected by ECS Mode, then the code word can be counted as an "erroneous code word".

[0041] It should be noted that in the embodiment, the statistical direction of the second error statistics register (EpRC register) described above, i.e., the target statistical dimension, can be "the row with the most errors", i.e., the row with the most error cells in each DRAM die is counted. For example, the 5th row of a die has 10 error cells, and the number of error cells in other rows is less than 10, so the 5th row can be the row with the most errors. In a specific implementation, the number of error cells in each row can be counted in real time when the ECS Mode is inspected, and the information of the row with the most errors is dynamically updated to the MR16-18 register corresponding to the EpRC register.

[0042] In a possible implementation, in the embodiment, the first statistical value is an error statistical result corresponding to the statistical object type; The second statistical information is address information corresponding to the row with the most errors.

[0043] Correspondingly, the first statistical value described above can be an error-related quantity value obtained by the first error statistics register (EC register) according to the configured statistical object type, after counting the memory errors. For example, when configured as "the number of rows with errors", the first statistical value parsed based on the OP[0]-OP[7] bit data of the MR20 register can be the total number of rows with errors in each die; when configured as "the number of code words with errors", the first statistical value based on the OP[0]-OP[7] bit data of the MR20 register can be the total number of code words with errors in each die. Therefore, the embodiment can select the statistical object at the row level and the code word level, so that the scheme can adapt to the fault monitoring requirements of different granularities, and improve the applicability of the scheme.

[0044] Correspondingly, the second statistical information described above can be complete address information (stored in the MR16-18 register) of the row with the most errors recorded by the second error statistics register (EpRC register), which can be composed of a bank group address (BG2-BG0), a bank address (BA1-BA0), and a row address (R17-R0), and the complete address information can uniquely identify a row in the memory. For example, assuming that the second statistical information is BG0=1, BG1=0, BG2=0, BA0=1, BA1=0, and R17-R0=0x1234.

[0045] Exemplarily, the analysis device can read the MR16-18 register data according to the following flow and parse according to the following rules: 1) Obtain the row address low 8 bits (R0-R7) from OP[0]-OP[7] of MR16; 2) Obtain the row address high 8 bits (R8-R15) from OP[0]-OP[7] of MR17; 3) obtain the row address highest 2 bits (R16~R17) from OP[0]~OP[1] of MR18, obtain the bank address (BA0~BA1) from OP[2]~OP[3] of MR18, and obtain the bank group address (BG0~BG2) from OP[4]~OP[6] of MR18 (OP[7] of MR18 is a reserved bit (RFU)); 4) combine the above analysis results to obtain the complete address information of the row with the most errors saved in the EpRC register, for example, BG2=0, BG1=1, BG0=0, BA1=1, BA0=0, R17~R0=0x0ABC.

[0046] Therefore, the embodiment can take the row with the most errors as a fixed target statistical dimension, thereby accurately capturing the risk point in the memory that is most likely to evolve into a serious fault and improving the pertinence of fault prediction.

[0047] Step S20, performing fault prediction analysis based on the real-time error information to obtain a memory pre-fault determination result corresponding to the target memory device.

[0048] It is easy to understand that after the real-time error information is summarized, the analysis device can combine a preset judgment rule to identify whether the target memory device has a risk of an uncorrectable error (UCE) to occur soon, that is, to perform the above fault prediction analysis, and then to determine whether the target memory device is in a pre-fault state.

[0049] At this time, the above memory pre-fault determination result can be a state conclusion of the target memory device obtained through the fault prediction analysis, and can include "in a UCE pre-fault state" and "not in a UCE pre-fault state". The result can be used to prompt a user to take measures such as business migration in advance to avoid unexpected server downtime.

[0050] In a feasible implementation manner, referring to Figure 3 , Figure 3 FIG. 3 is a third flowchart of a memory fault analysis method according to an embodiment of the present application. In the embodiment, step S20 includes steps B1~B2: Step B1, determining a preset monitoring parameter according to preconfigured information corresponding to the mode register, wherein the preset monitoring parameter includes a statistical threshold corresponding to the first error statistical register and fault address information corresponding to the second error statistical register; It can be understood that the pre-configuration information described above can be a configuration parameter related to the mode register pre-set in the detection program, which can be used to determine the judgment rule of the statistical threshold and the fault address information. It can be built-in configuration information in the analysis device, or it can be a parameter configured by the user through the server management interface. In this embodiment, the pre-configuration information can include a statistical threshold corresponding to the first error statistical register, and a fault address information corresponding to the second error statistical register. It can be understood that the specific content of the pre-configuration information can be adjusted according to the memory product specification, stability requirement and actual application scene, and this embodiment does not limit this.

[0051] It can be understood that the statistical threshold described above can be a preset value for judging whether the first statistical value stored in the first error statistical register exceeds the standard, and the fault address information described above can be address data that can indicate that the memory has a row fault, that is, the bank address and row address of the fault row.

[0052] Step B2, based on the comparison result between the first statistical value and the statistical threshold, and / or the interaction between the second statistical information and the fault address information, a memory pre-fault determination result corresponding to the target memory device is generated.

[0053] It can be understood that the conclusion obtained after comparing the first statistical value with the statistical threshold, that is, the comparison result, can include three cases: "the first statistical value is greater than the statistical threshold", "the first statistical value is equal to the statistical threshold" and "the first statistical value is less than the statistical threshold".

[0054] And the interaction described above can be the interaction between the second statistical information (address information) and the fault address information, which can include "the second statistical information belongs to the fault address information" and "the second statistical information does not belong to the fault address information".

[0055] At this time, in a possible implementation manner, in this embodiment, step B2 includes steps B21-B23: Step B21, if the first statistical value is greater than the statistical threshold, it is determined that the target memory device is in a pre-fault state; Or, step B22, if the second statistical information belongs to the fault address information, it is determined that the target memory device is in a pre-fault state; Or, step B23, if the first statistical value is greater than the statistical threshold, and the second statistical information belongs to the fault address information, it is determined that the target memory device is in a pre-fault state.

[0056] It can be understood that in this embodiment, the analysis device can pre-store two analysis memory pre-fault schemes. For ease of understanding, refer to Figure 4 and Figure 5Explanations are given, Figure 4 Fig. 1 is a schematic diagram of a first process of memory pre-failure analysis according to an embodiment of the memory strip failure analysis method, Figure 5 Fig. 2 is a schematic diagram of a second process of memory pre-failure analysis according to an embodiment of the memory strip failure analysis method.

[0057] It should be understood that the analysis device can read the storage data of the first error statistics register (i.e., the EC register (MR20)) and the second error statistics register (i.e., the EpRC register (MR16-18)) in a timing manner through a detection program (which can be configured in the processor or the BMC (Baseboard Management Controller) of the analysis device).

[0058] Then, as shown in Figure 4 , in the first memory pre-failure judgment scheme, when the analysis device detects that the first statistics value stored in the EC register exceeds the threshold (i.e., the first statistics value is greater than the statistics threshold), or the analysis device detects that the fault address information is filled in the second statistics information stored in the EpRC register (i.e., the second statistics information belongs to the fault address information), it can be determined that the target memory device is in a pre-failure state.

[0059] And as shown in the second memory pre-failure judgment scheme Figure 5 , the analysis device can only determine that the target memory device is in a pre-failure state when both the first statistics value exceeds the threshold and the second statistics information hits the valid address. If the two conditions are not met at the same time, it is determined that the target memory device is not in a pre-failure state.

[0060] At this time, the above three judgment methods can cover three core risk scenarios of memory error quantity exceeding the threshold, specific row failure, and error quantity exceeding the threshold and row failure coexisting, ensuring the comprehensiveness of failure prediction and avoiding missed judgment. Multi-condition combination judgment can also improve the accuracy of failure judgment, reduce the probability of misjudgment, and avoid unnecessary business migration or maintenance operations.

[0061] Finally, the analysis device can feed back the judgment result (target memory device pre-failure / non-pre-failure) to the user through the server management interface, email alarm, SMS notification, etc. At the same time, record the judgment time, the first statistics value, the second statistics information, etc. Data for subsequent tracing.

[0062] The embodiment provides a memory bank fault analysis method, which comprises the following steps: reading an internal error state register of a target memory device according to a preset monitoring period to obtain real-time error information; and performing fault prediction analysis based on the real-time error information to obtain a memory pre-fault determination result corresponding to the target memory device. The embodiment directly reads the internal hardware register of the memory device to obtain the error information, i.e., the real-time error information, and accurately identifies the pre-fault state of the target memory device based on the real-time error information, so that the shielding effect of the on-chip error correction code can be bypassed, and the accuracy and reliability of fault prediction are improved. Therefore, the embodiment can directly utilize the hardware register data to effectively identify the degradation risk of the DDR5 memory bank in advance, so that time for business migration is obtained, and server downtime loss is reduced.

[0063] It should be noted that the above examples are only used for understanding the present application and do not constitute a limitation on the memory bank fault analysis method of the present application. More forms of simple transformation based on the technical concept are within the protection scope of the present application.

[0064] The present application also provides a memory bank fault analysis device, please refer to Figure 6 , Figure 6 The present application also provides a memory bank fault analysis device, please refer to The present application also provides a memory bank fault analysis device, please refer to The data monitoring module 601 is configured to read an internal error state register of a target memory device according to a preset monitoring period to obtain real-time error information.

[0065] Optionally, in the embodiment, the target memory device is a memory module supporting on-chip error correction code. The internal error state register comprises a mode register, and the mode register is accessed through an error patrol and clearing mode.

[0066] Optionally, in the embodiment, the mode register comprises a first error statistical register and a second error statistical register. The data monitoring module 601 is further configured to obtain a statistical object type corresponding to the first error statistical register, read a first statistical value corresponding to the first error statistical register according to a preset monitoring period and the statistical object type, read second statistical information corresponding to a target statistical dimension of the second error statistical register based on the preset monitoring period, and summarize the first statistical value and the second statistical information into real-time error information.

[0067] Optionally, in the embodiment, the statistical object type of the first error statistical register includes the number of error rows or the number of error code words; and the target statistical dimension corresponding to the second error statistical register is the row with the most errors.

[0068] Optionally, in the embodiment, the first statistical value is an error statistical result corresponding to the statistical object type; and the second statistical information is address information corresponding to the row with the most errors.

[0069] Optionally, in the embodiment, the fault analysis module 602 is further configured to determine a preset monitoring parameter according to the preconfigured information corresponding to the mode register, the preset monitoring parameter including a statistical threshold corresponding to the first error statistical register and fault address information corresponding to the second error statistical register; and generate a memory pre-fault determination result of the target memory device based on a comparison result between the first statistical value and the statistical threshold and / or an interaction relationship between the second statistical information and the fault address information.

[0070] Optionally, in the embodiment, the fault analysis module 602 is further configured to determine that the target memory device is in a pre-fault state if the first statistical value is greater than the statistical threshold. Or, the fault analysis module 602 is further configured to determine that the target memory device is in a pre-fault state if the second statistical information belongs to the fault address information. Or, the fault analysis module 602 is further configured to determine that the target memory device is in a pre-fault state if the first statistical value is greater than the statistical threshold and the second statistical information belongs to the fault address information.

[0071] The memory stick fault analysis device provided in the application adopts the memory stick fault analysis method in the above embodiments, and can solve the technical problem of how to propose a fault prediction method suitable for DDR5 memory sticks. Compared with the prior art, the memory stick fault analysis device provided in the application has the same beneficial effects as the memory stick fault analysis method provided in the above embodiments, and other technical features in the memory stick fault analysis device are the same as the features disclosed in the above embodiments, which will not be repeated here.

[0072] The application provides a memory stick fault analysis device, which includes at least one processor and a memory connected with the at least one processor in communication; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the memory stick fault analysis method in the above embodiment one.

[0073] The following refers to Figure 7The diagram illustrates a structural schematic of a memory module fault analysis device suitable for implementing embodiments of this application. The memory module fault analysis device in this application may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Description), PMPs (Portable Media Players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 7 The memory module fault analysis device shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0074] like Figure 7 As shown, the memory module fault analysis device may include a processing unit 1001 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1002 or a program loaded from storage device 1003 into random access memory (RAM) 1004. The random access memory 1004 also stores various programs and data required for the operation of the memory module fault analysis device. The processing unit 1001, ROM 1002, and RAM 1004 are interconnected via a bus 1005. An input / output (I / O) interface 1006 is also connected to the bus. Typically, the following systems can be connected to I / O interface 1006: input devices 1007 including, for example, touchscreens, touchpads, keyboards, mice, image sensors, microphones, accelerometers, gyroscopes, etc.; output devices 1008 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1003 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1009. Communication device 1009 allows the memory module fault analysis device to communicate wirelessly or wiredly with other devices to exchange data. Although a memory module fault analysis device with various systems is shown in the figure, it should be understood that it is not required to implement or possess all the systems shown. More or fewer systems can be implemented alternatively.

[0075] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a memory module failure analysis program product, which includes a memory module failure analysis program carried on a computer readable medium, the memory module failure analysis program containing program codes for executing the method shown in the flowchart. In such embodiments, the memory module failure analysis program can be downloaded and installed from the network through the communication device, or installed from the storage device 1003, or installed from the read-only memory 1002. When the memory module failure analysis program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiments disclosed in the present application are executed.

[0076] The memory module failure analysis device provided by the present application adopts the memory module failure analysis method in the above-mentioned embodiments, and can solve the technical problem of how to propose a fault prediction method suitable for DDR5 memory modules. Compared with the prior art, the memory module failure analysis device provided by the present application has the same beneficial effects as the memory module failure analysis method provided by the above-mentioned embodiments, and other technical features in the memory module failure analysis device are the same as the features disclosed in the previous embodiment method, which will not be repeated here.

[0077] It should be understood that various parts of the present application can be realized by hardware, software, firmware or a combination thereof. In the description of the above-mentioned embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0078] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present application, which should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

[0079] The present application provides a storage medium having computer readable program instructions (i.e. a memory module failure analysis program) stored thereon, the computer readable program instructions being used to execute the memory module failure analysis method in the above-mentioned embodiments.

[0080] The storage medium provided in the present application may, for example, be a U disk, but is not limited to an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, system, or device, or any combination of the above. More specific examples of the storage medium may include, but are not limited to, an electrical connection having one or more conductive wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present embodiment, the storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, system, or device. The program code contained in the storage medium can be transmitted in any suitable medium, including but not limited to an electrical wire, an optical cable, an RF (Radio Frequency) cable, etc., or any suitable combination of the above.

[0081] The above-mentioned storage medium can be included in the memory bank fault analysis device; or can exist separately without being assembled into the memory bank fault analysis device.

[0082] The above-mentioned storage medium carries one or more programs, which, when executed by the memory bank fault analysis device, cause the memory bank fault analysis device to: analyze the memory bank fault.

[0083] The memory bank fault analysis program code for performing the operations of the present application can be written in one or more programming languages or combinations of the above, including an object-oriented programming language such as Java, Smalltalk, C++, or a conventional procedural programming language such as "C" language or similar programming languages. The program code can be executed entirely on a user computer, partially on a user computer, as a separate software package, partially on a user computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer can be connected to the user computer through any kind of network, including a LAN (Local Area Network) or a WAN (Wide Area Network), or can be connected to an external computer (for example, through the Internet using an Internet service provider).

[0084] The flowcharts and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods and memory bank failure analysis program products according to various embodiments of the present application. In this regard, each block in the flowcharts or block diagrams can represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently or the blocks may be executed in the reverse order, depending on the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations thereof, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or combinations of hardware and software.

[0085] The modules involved in the embodiments of the present application can be implemented in the form of software or in the form of hardware. Among them, the name of the module does not constitute a limitation of the unit itself in some cases.

[0086] The readable storage medium provided by the present application is a storage medium, and the storage medium stores computer readable program instructions (i.e. memory bank failure analysis program) for executing the above memory bank failure analysis method, which can solve the technical problem of how to propose a fault prediction method suitable for DDR5 memory bank. Compared with the prior art, the storage medium provided by the present application has the same beneficial effects as the memory bank failure analysis method provided by the above embodiments, and will not be repeated here.

[0087] The above is only some embodiments of the present application, and does not limit the scope of the present application, and any equivalent structural transformation made by using the content of the present application specification and drawings, or direct / indirect application in other related technical fields is included in the protection scope of the present application.

Claims

1. A memory bank failure analysis method, characterized by, The method comprises: reading an internal error state register of a target memory device according to a preset monitoring period to obtain real-time error information; performing fault prediction analysis based on the real-time error information to obtain a memory pre-fault determination result corresponding to the target memory device.

2. The memory bank failure analysis method of claim 1, wherein, The target memory device is a memory module supporting an on-chip error correction code. The internal error state register comprises a mode register, and the mode register is accessed through an error patrol and clearing mode.

3. The memory bank failure analysis method of claim 2, wherein, The mode register comprises a first error statistical register and a second error statistical register. The step of reading the internal error state register of the target memory device according to the preset monitoring period to obtain the real-time error information comprises: obtaining a statistical object type corresponding to the first error statistical register, and reading a first statistical value corresponding to the first error statistical register according to a preset monitoring period and the statistical object type; reading second statistical information corresponding to a target statistical dimension of the second error statistical register based on the preset monitoring period; summarizing the first statistical value and the second statistical information into real-time error information.

4. The memory bank failure analysis method of claim 3, wherein, The statistical object type of the first error statistical register comprises a number of error rows or a number of error code words; The target statistical dimension corresponding to the second error statistical register is a row with the most errors.

5. The memory bank failure analysis method of claim 4, wherein, The first statistical value is an error statistical result corresponding to the statistical object type; The second statistical information is address information corresponding to the row with the most errors.

6. The memory bank failure analysis method of claim 5, wherein, The step of performing fault prediction analysis based on the real-time error information to obtain the memory pre-fault determination result corresponding to the target memory device comprises: determining preset monitoring parameters according to preconfigured information corresponding to the mode register, wherein the preset monitoring parameters comprise a statistical threshold value corresponding to the first error statistical register and fault address information corresponding to the second error statistical register; generating the memory pre-fault determination result corresponding to the target memory device based on a comparison result between the first statistical value and the statistical threshold value and / or an interaction relationship between the second statistical information and the fault address information.

7. The memory bank failure analysis method of claim 6, wherein, The step of generating the memory pre-fault determination result corresponding to the target memory device based on the comparison result between the first statistical value and the statistical threshold value and / or the interaction relationship between the second statistical information and the fault address information comprises: if the first statistical value is greater than the statistical threshold value, determining that the target memory device is in a pre-fault state; or, if the second statistical information belongs to the fault address information, determining that the target memory device is in a pre-fault state; or, if the first statistical value is greater than the statistical threshold value and the second statistical information belongs to the fault address information, determining that the target memory device is in a pre-fault state.

8. A memory bank failure analysis apparatus, comprising: The memory bank fault analysis device comprises: a data monitoring module configured to read an internal error state register of a target memory device according to a preset monitoring period to obtain real-time error information; a fault analysis module configured to perform fault prediction analysis based on the real-time error information to obtain a memory pre-fault determination result corresponding to the target memory device.

9. A memory bank failure analysis device, comprising: The memory bank fault analysis device comprises a memory, a processor, and a memory bank fault analysis program stored on the memory and executable on the processor, and the memory bank fault analysis program is configured to implement the steps of the memory bank fault analysis method according to any one of claims 1 to 7.

10. A storage medium, characterized by The storage medium stores a memory bank fault analysis program, and the memory bank fault analysis program, when executed by a processor, implements the steps of the memory bank fault analysis method according to any one of claims 1 to 7.

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