Controller, operation method of controller, storage system and electronic equipment

Abstract

The invention provides a controller, an operation method of the controller, a storage system and electronic equipment, and is applied to the technical field of semiconductors. The controller includes a cache and a processor. The processor is coupled to the cache and is configured to send a plurality of first read instructions to the memory. The first read instruction includes an address of a first memory region of the memory, a reference read voltage, and a voltage offset. The voltage offsets in at least two of the plurality of first reading instructions are different. Obtaining a plurality of groups of first data and obtaining a log-likelihood ratio table according to the plurality of groups of first data. According to the embodiment, the LDPC decoding performance can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a controller, a method of operating the controller, a storage system, and an electronic device. Background Technology

[0002] To enhance the reliability of reading data from memory (such as NAND), low-density parity code (LDPC) can be used to decode the read data to obtain the target data. However, the performance of LDPC decoding may be reduced by changes in memory operating conditions. Summary of the Invention

[0003] Embodiments of this disclosure provide a controller, a method for operating the controller, a storage system, and an electronic device to improve LDPC decoding performance.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0005] In a first aspect, embodiments of this disclosure provide a controller, including a cache and a processor. The processor is coupled to the cache and configured to: send a plurality of first read instructions to a memory. Each first read instruction includes an address of a first storage region of the memory, a reference read voltage, and a voltage offset. At least two of the plurality of first read instructions have different voltage offsets. A plurality of sets of first data are acquired, and a log-likelihood ratio table is obtained based on the plurality of sets of first data.

[0006] In some possible implementations, the processor is further configured to: send a plurality of second read instructions to the memory. The second read instructions include an address of a second memory region, a reference read voltage, and a voltage offset. At least two of the plurality of second read instructions have different voltage offsets. Multiple sets of second data are acquired. Decoded data for the second memory region is obtained based on the multiple sets of second data and a log-likelihood table.

[0007] In some possible implementations, the processor is specifically configured to: determine feature values ​​of a first storage region based on multiple sets of first data; and obtain a log-likelihood ratio table based on the multiple sets of first data and the feature values ​​of the first storage region.

[0008] In some possible implementations, the processor is further configured to: send a plurality of second read instructions to the memory to acquire a plurality of sets of second data. The second read instructions include the address of a second storage region of the memory, a reference read voltage, and a voltage offset. At least two of the plurality of second read instructions have different voltage offsets. Based on the plurality of sets of second data, characteristic values ​​of the second storage region are determined. Based on the characteristic values ​​of the second storage region and a log-likelihood ratio table, decoded data for the second storage region is obtained.

[0009] In some possible implementations, the processor is further configured to: obtain a log-likelihood ratio table based on the target data and multiple sets of first data. The target data is obtained by the processor decoding data read from a first storage area.

[0010] In some possible implementations, the processor is specifically configured to: obtain multiple voltage ranges based on a reference read voltage and a voltage offset; and obtain a log-likelihood ratio table based on the target data and the multiple voltage ranges.

[0011] In some possible implementations, the processor is specifically configured to: obtain the log-likelihood ratio for each voltage range based on the target data and multiple voltage ranges; and obtain a log-likelihood ratio table based on the log-likelihood ratio for each voltage range.

[0012] In some possible implementations, the stored data in the first storage area is not reconstructed using a standalone redundant disk array (RAID).

[0013] In some possible implementations, the first read instruction includes a reference read voltage and a voltage offset, the reference read voltage being offset based on the voltage offset.

[0014] In some possible implementations, the first read command includes a first reference read voltage, a second reference read voltage, a first voltage offset, and a second voltage offset. The first reference read voltage is offset based on the first voltage offset. The second reference read voltage is offset based on the second voltage offset.

[0015] Secondly, embodiments of this disclosure provide a method for operating a controller, comprising: sending a plurality of first read instructions to a memory. Each first read instruction includes an address of a first storage region of the memory, a reference read voltage, and a voltage offset. At least two of the plurality of first read instructions have different voltage offsets. Acquiring a plurality of sets of first data. And obtaining a log-likelihood ratio table based on the plurality of sets of first data.

[0016] In some possible implementations, the controller's operation further includes: sending a plurality of second read instructions to the memory. Each second read instruction includes an address of a second storage region of the memory, a reference read voltage, and a voltage offset. At least two of the plurality of second read instructions have different voltage offsets. Multiple sets of second data are acquired. Decoded data for the second storage region is obtained based on the multiple sets of second data and a log-likelihood ratio table.

[0017] In some possible implementations, the controller's operation method further includes: determining feature values ​​of a first storage region based on multiple sets of first data; and obtaining a log-likelihood ratio table based on the multiple sets of first data and the feature values ​​of the first storage region.

[0018] In some possible implementations, the controller's operation method further includes: sending a plurality of second read instructions to the memory to acquire a plurality of sets of second data. The second read instructions include the address of a second storage region of the memory, a reference read voltage, and a voltage offset. At least two of the plurality of second read instructions have different voltage offsets. Based on the plurality of sets of second data, characteristic values ​​of the second storage region are determined. Based on the characteristic values ​​of the second storage region and a log-likelihood ratio table, decoded data for the second storage region is obtained.

[0019] In some possible implementations, obtaining a log-likelihood ratio table based on multiple sets of first data includes: obtaining a log-likelihood ratio table based on target data and multiple sets of first data. The target data is obtained by the controller decoding data read from a first storage area.

[0020] In some possible implementations, a log-likelihood ratio table is obtained based on target data and multiple sets of first data, including: obtaining multiple voltage ranges based on reference reading voltage and voltage offset; and obtaining the log-likelihood ratio table based on the target data and multiple voltage ranges.

[0021] In some possible implementations, a log-likelihood ratio table is obtained based on the target data and multiple voltage ranges, including: obtaining the log-likelihood ratio for each voltage range based on the target data and multiple voltage ranges; and obtaining a log-likelihood ratio table based on the log-likelihood ratio for each voltage range.

[0022] In some possible implementations, the stored data in the first storage area is not reconstructed using a standalone redundant disk array (RAID).

[0023] In some possible implementations, the first read instruction includes a reference read voltage and a voltage offset, the reference read voltage being offset based on the voltage offset.

[0024] In some possible implementations, the first read command includes a first reference read voltage, a second reference read voltage, a first voltage offset, and a second voltage offset. The first reference read voltage is offset based on the first voltage offset. The second reference read voltage is offset based on the second voltage offset.

[0025] Thirdly, embodiments of this disclosure provide a storage system including a memory and a controller, the controller being coupled to the memory. The controller includes a cache and a processor. The processor is coupled to the cache and configured to: send a plurality of first read instructions to the memory. Each first read instruction includes an address of a first storage region of the memory, a reference read voltage, and a voltage offset. At least two of the plurality of first read instructions have different voltage offsets. Multiple sets of first data are acquired. A log-likelihood ratio table is obtained based on the multiple sets of first data.

[0026] In some possible implementations, the controller is further configured to: send a plurality of second read instructions to the memory. The second read instructions include an address of a second storage region of the memory, a reference read voltage, and a voltage offset. At least two of the plurality of second read instructions have different voltage offsets. Multiple sets of second data are acquired. Decoded data for the second storage region is obtained based on the multiple sets of second data and a log-likelihood ratio table.

[0027] In some possible implementations, the controller is specifically configured to: determine feature values ​​of a first storage region based on multiple sets of first data; and obtain a log-likelihood ratio table based on the multiple sets of first data and the feature values ​​of the first storage region.

[0028] In some possible implementations, the controller is further configured to: send multiple second read instructions to the memory to acquire multiple sets of second data. The second read instructions include the address of a second storage region of the memory, a reference read voltage, and a voltage offset. At least two of the multiple second read instructions have different voltage offsets. Based on the multiple sets of second data, characteristic values ​​of the second storage region are determined. Based on the characteristic values ​​of the second storage region and a log-likelihood ratio table, decoded data for the second storage region is obtained.

[0029] In some possible implementations, the controller is also configured to: obtain a log-likelihood ratio table based on the target data and multiple sets of first data. The target data is obtained by the controller decoding data read from a first storage area.

[0030] In some possible implementations, the controller is specifically configured to: obtain multiple voltage ranges based on reference voltage readings and voltage offsets; and obtain a log-likelihood ratio table based on the target data and the multiple voltage ranges.

[0031] In some possible implementations, the controller is specifically configured to: obtain the log-likelihood ratio for each voltage range based on the target data and multiple voltage ranges; and obtain a log-likelihood ratio table based on the log-likelihood ratio for each voltage range.

[0032] In some possible implementations, the stored data in the first storage area is not reconstructed using a standalone redundant disk array (RAID).

[0033] In some possible implementations, the first read instruction includes a reference read voltage and a voltage offset, the reference read voltage being offset based on the voltage offset.

[0034] In some possible implementations, the first read command includes a first reference read voltage, a second reference read voltage, a first voltage offset, and a second voltage offset. The first reference read voltage is offset based on the first voltage offset. The second reference read voltage is offset based on the second voltage offset.

[0035] Fourthly, embodiments of this disclosure provide an operating method for a storage system, comprising: a controller sending a plurality of first read instructions to a memory. Each first read instruction includes an address of a first storage region of the memory, a reference read voltage, and a voltage offset. At least two of the plurality of first read instructions have different voltage offsets. The controller acquires a plurality of sets of first data. And based on the plurality of sets of first data, a log-likelihood ratio table is obtained.

[0036] In some possible implementations, the method of operating the storage system further includes: sending a plurality of second read instructions to the memory. Each second read instruction includes an address of a second storage region of the memory, a reference read voltage, and a voltage offset. At least two of the plurality of second read instructions have different voltage offsets. Multiple sets of second data are acquired. Decoded data for the second storage region is obtained based on the multiple sets of second data and a log-likelihood ratio table.

[0037] In some possible implementations, the operation method of the storage system further includes: determining feature values ​​of a first storage region based on multiple sets of first data; and obtaining a log-likelihood ratio table based on the multiple sets of first data and the feature values ​​of the first storage region.

[0038] In some possible implementations, the operation method of the storage system further includes: sending a plurality of second read instructions to the memory to acquire a plurality of sets of second data. The second read instructions include an address of a second storage region of the memory, a reference read voltage, and a voltage offset. At least two of the plurality of second read instructions have different voltage offsets. Based on the plurality of sets of second data, characteristic values ​​of the second storage region are determined. Based on the characteristic values ​​of the second storage region and a log-likelihood ratio table, decoded data of the second storage region is obtained.

[0039] In some possible implementations, obtaining a log-likelihood ratio table based on multiple sets of first data includes: obtaining a log-likelihood ratio table based on target data and multiple sets of first data. The target data is obtained by the controller decoding data read from a first storage area.

[0040] In some possible implementations, a log-likelihood ratio table is obtained based on target data and multiple sets of first data, including: obtaining multiple voltage ranges based on reference reading voltage and voltage offset; and obtaining the log-likelihood ratio table based on the target data and multiple voltage ranges.

[0041] In some possible implementations, a log-likelihood ratio table is obtained based on the target data and multiple voltage ranges, including: obtaining the log-likelihood ratio for each voltage range based on the target data and multiple voltage ranges; and obtaining a log-likelihood ratio table based on the log-likelihood ratio for each voltage range.

[0042] In some possible implementations, the stored data in the first storage area is not reconstructed using a standalone redundant disk array (RAID).

[0043] In some possible implementations, the first read instruction includes a reference read voltage and a voltage offset, the reference read voltage being offset based on the voltage offset.

[0044] In some possible implementations, the first read command includes a first reference read voltage, a second reference read voltage, a first voltage offset, and a second voltage offset. The first reference read voltage is offset based on the first voltage offset. The second reference read voltage is offset based on the second voltage offset.

[0045] Fifthly, embodiments of this disclosure provide an electronic device, the electronic device including a host and any of the storage systems described in the third aspect, the host and the storage system being coupled together.

[0046] Sixthly, embodiments of this disclosure provide a computer storage medium, the computer-readable storage medium including instructions. When the instructions are executed on a processor, the processor causes the processor to perform the operation method of any controller in the second aspect, or to perform the operation method of any storage system in the fourth aspect. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0048] Figure 1 This is a schematic diagram of the structure of an electronic device according to some embodiments. Figure 1 ;

[0049] Figure 2This is a schematic diagram of the structure of an electronic device according to some embodiments. Figure 2 ;

[0050] Figure 3 This is a schematic diagram of the structure of a memory card according to some embodiments;

[0051] Figure 4 This is a schematic diagram of the structure of a solid-state drive according to some embodiments;

[0052] Figure 5 This is a schematic diagram of the structure of a memory according to some embodiments. Figure 1 ;

[0053] Figure 6 This is a schematic diagram of the structure of a memory according to some embodiments. Figure 2 ;

[0054] Figure 7 This is a schematic diagram of the threshold voltage distribution of a memory cell according to some embodiments. Figure 1 ;

[0055] Figure 8 This is a schematic diagram of the threshold voltage distribution of a memory cell according to some embodiments. Figure 2 ;

[0056] Figure 9 This is a schematic diagram of the threshold voltage distribution of a memory cell according to some embodiments. Figure 3 ;

[0057] Figure 10 This is a schematic diagram of an error checking and correction process for reading data according to some embodiments;

[0058] Figure 11 This is a schematic diagram of two adjacent distribution states in the threshold voltage distribution of a memory cell according to some embodiments.

[0059] Figure 12 This is a confidence diagram of a different voltage range according to some embodiments;

[0060] Figure 13 This is a schematic diagram of a data reading method according to some embodiments. Figure 1 ;

[0061] Figure 14 This is a schematic diagram of a data reading method according to some embodiments. Figure 2 ;

[0062] Figure 15 This is a schematic diagram of a data reading method according to some embodiments. Figure 3 ;

[0063] Figure 16This is a schematic diagram of a data reading method according to some embodiments. Figure 4 ;

[0064] Figure 17 This is a schematic diagram of an LLR table optimization method according to some embodiments;

[0065] Figure 18 This is a schematic diagram of a data reading method according to some embodiments. Figure 5 ;

[0066] Figure 19 This is a schematic diagram of a data reading method according to some embodiments. Figure 6 ;

[0067] Figure 20 This is a schematic diagram of a data reading method according to some embodiments. Figure 7 ;

[0068] Figure 21 This is a schematic diagram of the threshold voltage distribution of a memory cell according to some embodiments. Figure 4 ;

[0069] Figure 22 This is a schematic diagram of the threshold voltage distribution of a memory cell according to some embodiments. Figure 5 ;

[0070] Figure 23 This is a schematic diagram of the threshold voltage distribution of a memory cell according to some embodiments. Figure 6 ;

[0071] Figure 24 This is a flowchart illustrating the operation method of a controller according to some embodiments. Figure 1 ;

[0072] Figure 25 This is a flowchart illustrating the operation method of a controller according to some embodiments. Figure 2 ;

[0073] Figure 26 This is a flowchart illustrating an operation method of a storage system according to some embodiments. Figure 1 ;

[0074] Figure 27 This is a flowchart illustrating an operation method of a storage system according to some embodiments. Figure 2 . Detailed Implementation

[0075] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0076] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0077] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0078] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0079] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0080] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0081] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0082] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0083] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0084] This disclosure is not limited to three-dimensional (3D) NAND memory devices, although 3D NAND memory devices may be used in some examples to illustrate the inventive concept. For example, the techniques disclosed herein can be applied to planar NAND memory devices and NOR memory devices, etc.

[0085] Figure 1 A structural diagram of an electronic device 10000 having a storage device is shown according to some aspects. The electronic device 10000 can be a mobile phone (e.g., a cell phone), desktop computer, tablet computer, laptop computer, server, in-vehicle device, game console, printer, positioning device, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), smart sensor, power bank, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1As shown, electronic device 10000 includes a storage system 11000 and a host 12000. Storage system 11000 includes one or more memories 11100 and a controller 11200, with the controller 11200 coupled to the memories 11100. Host 12000 can be a processor of the electronic device. Exemplarily, the processor can be a chip, specifically a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system-on-a-chip (SoC), a central processing unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), an application processor (AP), or other integrated chips.

[0086] According to some embodiments, controller 11200 is coupled to memory 11100 and host 12000 and is configured to control memory 11100. Controller 11200 can manage data stored in memory 11100 and communicate with host 12000. In some embodiments, controller 11200 is designed to operate in a low duty cycle environment, such as secure digital (SD) cards, compact flash cards (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, controller 11200 is designed to operate in a high duty cycle environment, such as solid-state drives (SSDs) or embedded multimedia cards (eMMCs), which are used as data storage devices for mobile electronic devices such as smartphones, tablets, personal computers, etc., and for enterprise storage arrays.

[0087] The controller 11200 can be configured to manage data stored in the memory 11100 and communicate with external devices (e.g., the host 12000). It controls the operation of the memory 11100, such as read, erase, and program operations. In some embodiments, the controller 11200 can also be configured to manage various functions related to data stored or to be stored in the memory 11100, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, and redundant array of independent disks (RAID).

[0088] In some implementations, the controller 11200 is also configured to process error correction codes (ECCs) related to data read from or written to the memory 11100. For example... Figure 2 In the illustrated electronic device 10000, the controller 11200 includes at least a cache 11240 and a processor 11220, and may also include a host interface circuit 11210, an error correction module 11230, a memory interface circuit 11250, and a connection bus 11260. In specific implementation, the electronic device 10000 is a complex device integrating a storage system 11000 and a host 12000. The storage system 11000 is responsible for data storage and retrieval, while the controller 11200 coordinates and manages these operations. The various modules within the controller 11200 achieve high-speed, reliable data transmission and command communication through the connection bus 11260. The host interface circuit 11210, acting as a bridge to the external host 12000, is connected to the processor 11220 via the connection bus 11260, responsible for receiving and sending data, commands, and status information, and can use interfaces such as USB, SATA, and PCIe. The processor 11220 is the brain of the controller 11200, which parses commands from the host 12000 and coordinates other modules to perform corresponding operations.

[0089] During the data writing process, the processor 11220 controls the error correction module 11230 to encode the raw data. Encoding is performed by adding ECC checksums, and the encoded data is then sent to the cache 11240 for temporary storage via the connection bus 11260. The cache 11240 serves as a temporary storage area to ensure the security and stability of the data before it is written to the memory 11100.

[0090] When data needs to be read, the processor 11220 sends a read command and address to the memory 11100 through the memory interface circuit 11250. After reading the data at the specified address, the memory 11100 returns the data to the controller 11200 through the memory interface circuit 11250. This data first enters the cache 11240, and then is decoded and error detected by the error correction module 11230. If there are no errors in the data, the error correction module 11230 transmits the data to the processor 11220 through the connection bus 11260; if an error is detected, the error correction module 11230 notifies the processor 11220, which then determines the error checking and correction method, such as performing a read retry, performing soft decoding in low-density parity check code (LDPC), performing internal RAID, or reporting the error to the host 12000.

[0091] Throughout the process, processor 11220 is also responsible for error handling and status reporting. If error correction module 11230 detects an error, processor 11220 will take appropriate measures based on the error type, such as retrying the read, reporting the error to host 12000, or executing other error handling procedures. Simultaneously, controller 11200 may also report information such as the status and error count of memory 11100 to host 12000 via host interface circuit 11210, so that host 12000 can promptly understand the operating status of storage system 11000. Through the coordinated work of various modules within controller 11200, storage system 11000 in electronic device 10000 achieves efficient and stable data storage and retrieval. The presence of connection bus 11260 ensures high-speed data transmission and command communication between modules, enabling the entire system to operate stably and efficiently.

[0092] Controller 11200 can also perform any other suitable functions, such as formatting memory 11100. Controller 11200 can communicate with external devices (e.g., host 12000) according to a specific communication protocol. For example, controller 11200 can communicate with external devices through at least one of various interface protocols, such as USB, Multimedia Card (MMC), Peripheral Component Interconnect (PCI), High-Speed ​​PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Device Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0093] Of course, controller 11200 can also perform any other suitable functions, such as formatting memory 11100. For example, controller 11200 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0094] It should be noted that the interface protocol includes at least one of the following: USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, and Firewire protocol.

[0095] The controller 11200 and one or more memories 11100 can be integrated into various types of storage systems 11000, for example, included in the same package, such as an embedded multimedia card (eMMC), universal flash storage (UFS) package, embedded multichip package (eMCP) package, or UFS-based multichip package (uMCP) package. Specifically, eMMC uses a unified MMC standard interface, encapsulating high-density NAND and the MMC controller in a ball grid array (BGA) package chip. UFS is an advanced version of eMMC, also an array-type storage module composed of multiple flash memory chips and a controller. UFS overcomes the limitation of eMMC, which only supports half-duplex operation (read and write must be performed separately), enabling full-duplex operation and thus doubling performance. eMCP is a package that incorporates volatile memory, such as static random-access memory (SRAM) or dynamic random-access memory (DRAM), on an eMMC.

[0096] In practical implementations, DRAM can be low-power double-data-rate synchronous dynamic random-access memory (LPDDR). uMCP is a packaged form of UFS with volatile memory (such as SRAM or DRAM) mounted on it, offering high performance and large capacity. In practical implementations, DRAM can be LPDDR. That is to say, the storage system 11000 can be implemented and packaged into different types of end electronic devices. For example... Figure 3 In one example shown, controller 11200 and a single memory 11100 can be integrated into memory card 400. Memory card 400 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 400 may also include a connection between memory card 400 and a host (e.g., Figure 1 The memory card connector 410 is coupled to the host 12000. In such a... Figure 4In another example shown, the controller 11200 and multiple memories 11100 can be integrated into the SSD 500. The SSD 500 may also include interfaces for connecting the SSD 500 to a host (e.g., a motherboard). Figure 1 or Figure 2 The SSD connector 510 is coupled to the host 12000. In some implementations, the storage capacity and / or operating speed of the SSD 500 is higher than that of the memory card 400.

[0097] Figure 5 A schematic circuit diagram of an exemplary memory 600, including peripheral circuitry 602, is shown according to some aspects of this disclosure. The memory 600 may be... Figure 1 An example of memory 11100 is shown. Memory 600 may include a memory cell array 601 and peripheral circuitry 602 coupled to the memory cell array 601. The memory cell array 601 may be a NAND flash memory cell array, wherein memory cells 606 are provided in the form of an array of NAND memory strings 608, all extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 608 includes a plurality of memory cells 606 coupled in series and stacked vertically. Each memory cell 606 is capable of holding a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 606. Each memory cell 606 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0098] In some implementations, each storage cell 606 is a single-level cell (SLC) with two possible storage states (levels) and thus capable of storing one bit of data. Specifically, each storage cell 606 can be configured to store 2... N One of the storage states (levels) stores N bits of data, where N is a natural number greater than 0. This 2 N The storage states include erase state and 2. N-1 non-erasable state. In some implementations, each memory cell 606 is a single-level cell (SLC) having two possible storage states (levels) and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a threshold voltage in a first range, and a second storage state "1" may correspond to a threshold voltage in a second range. In some implementations, each memory cell 606 is an xLC capable of storing more than one bit of data in four or more storage states (levels). For example, an xLC is capable of storing two bits per cell (multi-level cell, MLC), three bits per cell (triple-level cell, TLC), or four bits per cell (quad-level cell, QLC). Each xLC can be programmed to assume a range of possible nominal storage values. In one example, an MLC can be programmed from an erase state to assume one of three possible programming levels by writing one of three possible nominal storage values ​​(e.g., 01, 10, and 11) into memory cell 606. A fourth nominal storage value can be used for the erase state (e.g., 00).

[0099] like Figure 5 As shown, each NAND flash memory string 608 may further include a source select gate (SSG) transistor 610 at its source end and a drain select gate (DSG) transistor 612 at its drain end. The SSG transistor 610 and DSG transistor 612 can be configured to activate the selected NAND flash memory string 608 (column of the array) during read and program operations. In some embodiments, the sources of the NAND flash memory strings 608 in the same block 604 are coupled through the same source line (SL) 614 (e.g., common SL). In other words, according to some embodiments, all NAND flash memory strings 608 in the same block 604 have an array common source (ACS). According to some embodiments, the drain of each NAND flash memory string 608 is coupled to a corresponding bit line 616, enabling data to be read from or written to the corresponding bit line 616 via an output bus (not shown). In some implementations, each NAND memory string 608 is configured to be selected or deselected by applying a selection or deselection voltage to the gate of the corresponding DSG transistor 612 via one or more DSG lines 613 and / or by applying a selection or deselection voltage to the gate of the corresponding SSG transistor 610 via one or more SSG lines 615.

[0100] like Figure 5As shown, NAND memory strings 608 can be organized into multiple blocks 604, each of which may have a common source line 614, for example, coupled to the ACS. In some embodiments, each block 604 is the basic data unit for erase operations, i.e., all memory cells 606 on the same block 604 are erased simultaneously. To erase memory cells 606 in a selected block 604, the source lines 614 coupled to the selected block 604 and unselected blocks 604 in the same plane as the selected block 604 can be biased with an erase voltage (Vers), such as a high positive bias voltage (e.g., 20V or higher). Memory cells 606 of adjacent NAND memory strings 608 can be coupled via word lines (WL) 618, which selects which row of memory cells 606 is affected by read and program operations.

[0101] Peripheral circuitry 602 can be coupled to memory cell array 601 via bit line (BL) 616, word line 618, source line 614, SSG line 615, and DSG line 613. Peripheral circuitry 602 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory cell array 601 by applying and sensing voltage and / or current signals to and from each target memory cell 606 via bit line 616, word line 618, source line 614, SSG line 615, and DSG line 613. Peripheral circuitry 602 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0102] For example, Figure 6 Some exemplary peripheral circuitry is shown, including a page buffer / sensor amplifier 704, a column decoder / bit line driver 706, a row decoder / word line driver 708, a voltage generator 710, a control logic unit 712, a register 714, an interface (I / F) circuit 716, and a data bus 718. It should be understood that additional peripheral circuitry may be included. Figure 6 Additional peripheral circuitry not shown.

[0103] Page buffer / sensor amplifier 704 can be configured to read and program (write) data from and to memory cell array 601 according to control signals from control logic unit 712. In one example, page buffer / sensor amplifier 704 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 606 coupled to selected word line 618. In yet another example, page buffer / sensor amplifier 704 can also sense a low-power signal representing a data bit stored in memory cell 606 from bit line 616 during a read operation and amplify a small voltage swing to a recognizable logic level. As detailed below and consistent with the scope of this disclosure, during a programming operation, page buffer / sensor amplifier 704 may include a memory module (e.g., latch, cache, register, etc.) for temporarily storing a segment of N bits of data received from data bus 718 and using 2 N -2 N In each programming pass of the multi-pass programming operation, the N-bit data segment is provided to the corresponding target storage unit 606 via the corresponding bit line 616.

[0104] The column decoder / bit line driver 706 can be configured to be controlled by the control logic unit 712 and to select one or more NAND memory strings 608 by applying bit line voltages generated by the voltage generator 710. The row decoder / word line driver 708 can be configured to be controlled by the control logic unit 712 and to select / deselect block 604 of the memory cell array 601 and to select / deselect word lines 618 of block 604. The row decoder / word line driver 708 can also be configured to drive word lines 618 using word line voltages generated by the voltage generator 710. In some embodiments, the row decoder / word line driver 708 can also select / deselect and drive SSG lines 615 and DSG lines 613. The voltage generator 710 can be configured to be controlled by the control logic unit 712 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be provided to the memory cell array 601.

[0105] Control logic unit 712 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 714 can be coupled to control logic unit 712 and includes a status register, a command register, and an address register for storing status information, command operation code (OP), and command address for controlling the operation of each peripheral circuit. Interface circuitry 716 can be coupled to control logic unit 712 and acts as a control buffer to buffer data from the host (e.g., ...). Figure 1The host 2000 receives control commands and forwards them to the control logic unit 712, and buffers the status information received from the control logic unit 712 and forwards it to the host. The interface circuit 716 can also be coupled to the column decoder / bit line driver 706 via the data bus 718, and acts as a data input / output (I / O) interface and data buffer to buffer and forward data to and from the memory cell array 601.

[0106] In practical applications, since the structural dimensions and doping concentrations of the multiple memory cells 606 in the memory 600 cannot be exactly the same, the threshold voltages of the multiple memory cells 606 will not be exactly the same. Therefore, the threshold voltages for different data states (erase or program) are distributed within a certain range. Plotting the threshold voltage (Vth) on the x-axis and the number of memory cells (count) at different threshold voltages on the y-axis, we obtain the threshold voltage distribution (Vtdistribution). For different types of memory, the larger the storage capacity of a single memory cell, the narrower the width of the threshold voltage distribution corresponding to a single data state.

[0107] Taking each storage cell 606 as an example, configured to store three bits of data, Figure 7 A schematic diagram of the threshold voltage distribution of memory cells according to embodiments of the present disclosure is shown. The horizontal axis represents the threshold voltage of the memory cell (denoted by Vth). The vertical axis represents the number of memory cells corresponding to different threshold voltages.

[0108] exist Figure 7 In this context, these memory cells can be memory cells in 3D NAND memory devices corresponding to pages, code words (CW), word line memory cell strings, blocks, planes, dies, etc. These memory cells are TLC and can be programmed (or erased) to be in one of eight states (memory states): erase state ER, programmed states A, B, C, D, E, F, and G. The memory cell programmed (or erased) to be in a specific state can have a threshold voltage distributed within a voltage range. Accordingly, in Figure 7 In the diagram, each state (erase state ER, programmable states A, B, C, D, E, F, and G) is shown as having a threshold voltage distribution.

[0109] A TLC memory cell can represent three data bits, depending on the state in which the memory cell is located. In other words, three data bits can be encoded into one of the eight states. In different embodiments, the mapping between states and the corresponding three data bits can vary. For example, in... Figure 7In the diagram, the eight states from the erase state ER to the programmed states A, B, C, D, E, F, and G are mapped to 111, 011, 001, 101, 100, 000, 010, and 110, respectively. Figure 8 In this algorithm, the eight states from the erase state (ER) to the programming states (A, B, C, D, E, F, and G) are mapped to 111, 110, 100, 000, 010, 011, 001, and 101, respectively. The least significant bit (LSB) of these eight states belongs to the lowest page (LP). The center significant bit (CSB) of these eight states belongs to the middle page (MP). The most significant bit (MSB) of these eight states belongs to the highest page (UP).

[0110] by Figure 7 Taking the distribution shown as an example, in Figure 7 In this model, the seven default reference read voltages RA, RB, RC, RD, RE, RF, and RG lie between the corresponding memory cell threshold voltage distributions. Ideally, each memory cell threshold voltage distribution should be contained within two adjacent default reference read voltages. In other words, it is expected that programmed or erased memory cells will maintain their intended state and thus retain the three data bits they represent. However, the memory cell threshold voltage distribution may shift from one distribution to another due to factors such as program / erase (P / E) cycles, retention time, write or read interference, temperature variations, coupling interference from adjacent word lines (WL), etc. Figure 9 As shown. Because the threshold voltage distribution of this type of storage cell has a certain overlap, it can cause data read errors and reliability issues.

[0111] To reduce data reading errors and improve the reliability of data reading, this disclosure provides the following three methods for error checking and correction of read data in real time.

[0112] In a first possible implementation, error checking and correction are performed by executing a read retry scheme. See also [link to relevant documentation] for some examples. Figure 10 , Figure 10The flowcharts for three read schemes are shown. In step S110, the target data is read according to the default reference read voltage. If the read of the target data fails, step S120 is executed to retry the read. Step S120 specifically includes: traversing the read retry table, which is predefined and used to manage multiple offset values ​​of the default reference read voltage of the memory. The read retry table can also be called a pre-stored table. Based on the multiple offset values ​​obtained by traversing the read retry table, the default reference read voltage is shifted left or right to repeatedly read the memory. During the repeated read process, the number of bit errors in the target data read each time is counted using a bit error count method to find the optimal reference read voltage for reading the target data.

[0113] In a second possible embodiment, error checking and correction are performed by executing a soft decode read scheme in low-density paritycheck (LDPC) codes. In some examples, such as... Figure 10 As shown, after step S120, step S130 is executed to perform soft decoding in LDPC. Step S130 specifically includes: after determining that the target data read according to step S120 has failed, determining the reference read voltage based on the number of errors in the read retry scheme. The reference read voltage can be the reference read voltage corresponding to the minimum number of errors. Traversing the log-likelihood ratio (LLR) table, the LLR table is predefined, such as based on the operating conditions of the NAND memory device before it leaves the factory (such as P / E cycle, retention period, ambient temperature changes, etc.), used to manage multiple offset values ​​and the LLR value of the data read after each offset as the target data. Based on the multiple offset values ​​obtained by traversal, the reference read voltage is offset left and right within a limited range and decoded to repeatedly read the memory to obtain the target data.

[0114] For example, the predefined LLR table involved in LDPC software decoding can be determined in the following way.

[0115] First, divide any two adjacent distribution states (which can be an erase state and a programming state, or two adjacent programming states) into voltage ranges. For example... Figure 9 Taking the cross-distribution of threshold voltages in the memory cells as an example, two adjacent distribution states are selected for illustrative explanation, such as... Figure 11 As shown, Figure 11 The display shows seven reads, including the first read from R0, the second from R1, the third from R2, the fourth from R3, the fifth from R4, the sixth from R5, and the seventh from R6. The reference voltage for the first read from R0 can be as follows: Figure 9The diagram shows any of the reference read voltages RA, RB, RD, and RE. It also shows the conditions of different regions near the reference read voltage. For example, when reading data from LP in memory 600, the reference read voltage is as follows. Figure 9 Take RA as an example.

[0116] For critical regions near the reading voltage, such as... Figure 11 As shown. When data needs to be read from LP, RA is used as the read voltage to determine the data to be read: when the threshold voltage of the memory cell is greater than RA, the stored data is 0; otherwise, the stored data is 1. When the threshold voltage of a memory cell inside memory 600 shifts, some memory cells near R0 may cross RA and expand to another distribution after the voltage shift, resulting in overlap, such as... Figure 11 The shaded area. Areas that may overlap can be subdivided into different voltage ranges. Using RA as a reference, the voltage value is increased or decreased sequentially by a preset offset (dv), forming a pattern like... Figure 11 The voltage range shown is 0, 1, 2, 3, 4, 5, 6, 7. The voltage values ​​obtained by gradually increasing or decreasing dv around RA are denoted as V1, V2, V3, V4, V5, V6, etc.

[0117] It should be noted that the division of voltage ranges in this embodiment is only illustrative and not limiting. The specific voltage ranges can be determined based on actual conditions (such as the magnitude of the threshold voltage offset or the size of the overlapping area). For example, if the threshold voltage offset is small, the number of voltage range divisions can be reduced. Figure 14 The two adjacent distribution states are divided into four voltage ranges; for example... Figure 15 The middle part divides two adjacent distribution states into 6 voltage intervals; for example Figure 16 The two adjacent distribution states are divided into 8 voltage intervals.

[0118] from Figure 11 As can be seen, different relevant voltages can be used to distinguish different voltage ranges. For example, for voltage range 0, voltage V5 can be used; voltage ranges less than V5 are considered 0. For voltage range 6, voltages V4 and V6 can be used; voltage ranges less than V6 and greater than V4 are considered voltage range 6. Therefore, in the design of memory 600, different read voltages after dv offset can be used to determine the value of the voltage range. For different superposition regions near RA, the probability of the correct data value read by V2 or V5 should also be different. Generally speaking, data further away from the right side of R0 tends to be "0"; data further away from the left side of R0 tends to be "1".

[0119] Figure 12 The reliability of different voltage ranges is shown.Figure 12 The diagram shows that the reliability of the data read varies depending on its distance from the corresponding decision voltage RA. Regions closer to RA, such as voltage ranges 3 or 4, are more prone to errors when the voltage changes slightly. Conversely, voltage ranges 1 or 6, being farther from RA, generally have higher reliability even with larger voltage shifts. Therefore, as... Figure 12 As shown, different voltage ranges can be defined as "strong 0 voltage range" (6), "medium 0 voltage range" (5), "weak 0 voltage range" (4), "strong 1 voltage range" (1), "medium 1 voltage range" (2), and "weak 1 voltage range" (3). This means that among the data read after a small offset of the reading voltage, the error probability of values ​​in voltage range 3 or voltage range 4 is higher; while the error probability of values ​​in voltage range 1 or voltage range 6 is lower.

[0120] For the characteristics of the 600 read operation of the memory, a reference read voltage (such as...) is used. Figure 9 The values ​​RA, RB, RC, RD, RE, RF, and RG shown can be used to read hard bit data; by using an offset voltage, a new read voltage containing the offset voltage can be generated, which can be used to read soft bit data based on different critical voltage ranges.

[0121] Taking the reference reading voltage RA as an example, such as Figure 13 As shown, only the reference read voltage RA is used to perform a single hard read (1H) to determine the voltage value of the TLC memory cell and read the data. The data at this time is hard bit data.

[0122] Taking the reference reading voltage RA as an example, Figure 14 Based on the reference reading voltage RA, an offset voltage V1 and V2 are set on each side, where V2 = RA + dv and V1 = RA – dv. The data reading process is as follows: first, set the voltage value to RA, perform a hard read (1H), and read the hard bit data. At this time, the data value of the voltage range {0, 1, 2, 3} corresponds to the hard bit data "1100".

[0123] Then, a soft read is performed (1 second). During the 1 second process, the voltage V1 is used as the read voltage to read the data. At this time, the data values ​​of the voltage interval {0, 1, 2, 3} correspond to "1000" respectively. Then, the voltage V2 is used as the read voltage to read the data. At this time, the data values ​​of the voltage interval {0, 1, 2, 3} are "1110". The two sets of data are XORed (XORed) "1000" XOR "1110" to obtain the soft bit data "0110".

[0124] Secondly, set different quantization LLRs (the result of quantizing the LLR) for each voltage range. Based on the position of the voltage range {0, 1, 2, 3}, the probability of error is different, therefore different quantization LLR values ​​can be set. For example... Figure 14 As shown in Table 1, the quantization LLR for the voltage range {0, 1, 2, 3} can be set to {-5, -1, 1, 5}, but is not limited to.

[0125] Table 1

[0126] LLR voltage interval 0 1 2 3 hard bit data 1 1 0 0 soft bit data 0 1 1 0 quantized LLR -5 -1 1 5

[0127] For example, assuming the internal storage voltage of a TLC memory cell P is in the voltage range 3, although it cannot be directly measured, it can be obtained through... Figure 14 After the soft bit data is read and generated, the external data value is represented as hard bit data 0, soft bit data 0, and LLR quantization value 5. Therefore, it can be determined that the voltage of the TLC memory cell is far from the critical value, and the probability of the data being "0" is very high. If the internal storage voltage value of the TLC memory cell Q is in the voltage range of 1, the external data value is represented as hard bit data 1, soft bit data 1, and LLR quantization value -1, and the probability of the data being "1" is relatively low.

[0128] Taking the reference reading voltage RA as an example, Figure 15 Based on the read voltage RA, two offset voltages V2 / V4 and V1 / V3 are set on each side, where V2 = RA + dv, V4 = RA + 2dv, V1 = RA – dv, and V3 = RA – 2dv. The data reading process is as follows: [The text abruptly ends here, likely due to an incomplete translation or a missing section.] Figure 1 For example, first set the voltage value to RA, perform a hard read (1H), and read the hard bit data. At this time, the data value of the voltage range {0, 1, 2, 3, 4, 5} is the hard bit data "111000".

[0129] Then, two soft reads (2S) are performed. During the 2S process, firstly, the voltage V1 is used as the read voltage to read the data. At this time, the data value of the voltage range {0, 1, 2, 3, 4, 5} is "110000"; secondly, the voltage V2 is used as the read voltage to read the data. At this time, the data value of the voltage range {b3,b2,b1,a1,a2,b3} is "111100"; the two sets of data are XORed with "110000" to obtain the soft bit data "001100". Next, using voltage V3 as the reading voltage, read the data. At this time, the data value of the voltage range {0, 1, 2, 3, 4, 5} is "100000". Finally, using voltage V4 as the reading voltage, read the data. At this time, the data value of the voltage range {0, 1, 2, 3, 4, 5} is "111110". XOR the two sets of data "100000" with "111110" to obtain the soft data two "011110".

[0130] Thus, based on two soft reads, we can obtain soft bit data one "001100" and soft bit data two "011110". The "1" (regions 2 or 3) in soft bit data one indicates a region of low confidence. Then, by using the "1" in soft bit data two, we can further locate regions of medium confidence. In this way, through the generation of two soft bit data, we can locate six voltage intervals {0, 1, 2, 3, 4, 5}.

[0131] Based on the above discussion and the positions of the voltage range {0, 1, 2, 3, 4, 5}, different quantization LLR values ​​can be set. For example... Figure 15 As shown in Table 2, the quantization LLR for the voltage range {0, 1, 2, 3, 4, 5} can be set to {-7, -3, -1, 1, 3, 7}.

[0132] Table 2

[0133]

[0134] Taking the reference reading voltage RA as an example, Figure 16 Based on the read voltage RA, two offset voltages V2 / V4 / V6 and V1 / V3 / V5 are set on each side, where V2 = RA + dv, V4 = RA + 2dv, V6 = RA + 3dv, V1 = RA – dv, V3 = RA – 2dv, and V5 = RA – 3dv. Similarly, the quantization LLR for the voltage range {0, 1, 2, 3, 4, 5, 6, 7} can be obtained, as follows: Figure 16 As shown in Table 3.

[0135] Table 3

[0136] LLR voltage interval 0 1 2 3 4 5 6 7 hard bit data 1 1 1 1 0 0 0 0 soft bit data one 0 0 0 1 1 0 0 0 soft bit data two 0 0 1 1 1 1 0 0 soft bit data three 0 1 1 1 1 1 1 0 quantized LLR -7 -6 -3 -1 1 3 6 7

[0137] according to Figure 13, Figure 14 , Figure 15 , Figure 16 Tables 1, 2, and 3 yield the quantized LLR table shown in Table 4. This quantized LLR table can be stored in controller 11200 or loaded into controller 11200 after the storage system 11000 starts. During LDPC software decoding, the pre-set LLR table is used to input the original LLR values ​​to LDPC for decoding, thus improving the efficiency of LDPC decoding.

[0138] Table 4

[0139] LLR voltage interval 0 1 2 3 4 5 6 7 … 1H1S -5 0 0 -1 1 0 0 5 … 1H2S -7 0 -3 -1 1 3 0 7 … 1H3S -7 -6 -3 -1 1 3 6 7 …

[0140] In a third possible implementation, the target data is acquired by performing internal RAID. In some examples, such as... Figure 10 As shown, after step S130, step S140 is executed to obtain the target data based on the parity bit of the target data. Step S140 specifically includes: after determining that the target data read according to step S130 has failed, performing an XOR operation on the target data, and writing the target data and its parity bit together into the user data area. If one set of target data is lost, the lost target data can be deduced from the other sets of target data and their parity bits. However, when two or more sets of target data are lost, the lost target data cannot be recovered using RAID.

[0141] Among the three error checking and correction methods mentioned above, when performing LDPC software decoding, the pre-set LLR table is difficult to match all the operating conditions of the NAND storage device and the current state of the NAND storage device, which reduces the performance and efficiency of LDPC software decoding. This leads to the need to perform internal RAID to obtain the target data, resulting in low data reading efficiency and high latency.

[0142] To improve the efficiency of error checking and correction of read data by the controller 11200 and reduce data read latency, this disclosure provides an implementation method that optimizes a predefined LLR table based on the current operating conditions and status of the memory 11100. This optimizes the LLR table to more closely reflect the true characteristics of the storage medium, thereby significantly improving the matching degree between the LLR table and the memory 11100, improving the performance and efficiency of LDPC soft decoding, and also reducing the data read latency caused by obtaining target data through internal RAID.

[0143] like Figure 17 As shown, the LLR table optimization implementation method provided in this disclosure specifically includes steps S210-S240:

[0144] S210. Select the target storage area and divide it into voltage ranges.

[0145] In some possible implementations, the target storage region may be a page 620 in memory 11100 that meets preset conditions. The preset conditions met by the target storage region may include the following two conditions:

[0146] First, the data stored in the target storage area has not been reconstructed by RAID. If it enters the RAID process, it means that the memory 11100 itself may have physical damage, which is difficult to overcome by optimizing LDPC software decoding.

[0147] Secondly, data read from the target storage area can be decoded using LDPC software to obtain the target data (or decoded data). The reason why data read from the target storage area can be decoded using LDPC software requires optimization of the LLR table used in LDPC software decoding, mainly considering:

[0148] When data read from the target storage area is software decoded using the LLR table corresponding to 1H1S, and the decoded data is obtained after the first iteration, if the first iteration is greater than the first preset threshold, the LLR table corresponding to 1H1S is optimized in order to reduce the number of decoding iterations, improve decoding efficiency, and reduce data reading latency.

[0149] When software decoding of data read from the target storage area using the LLR table corresponding to 1H1S fails, software decoding using the LLR table corresponding to 1H2S is performed. When software decoding using the LLR table corresponding to 1H2S and obtaining decoded data after a second iteration, if the second iteration count is less than a second preset threshold, it indicates that the encoded data deviates from the correct data significantly. In this case, the LLR table corresponding to 1H1S can be optimized so that decoding can be successful using the optimized LLR table, thereby reducing the number of decoding iterations and improving decoding efficiency. If the second iteration count is greater than the second preset threshold, it indicates that the encoded data deviates significantly from the correct data. Therefore, the LLR table corresponding to 1H2S is optimized to reduce the number of decoding iterations and improve decoding efficiency. While optimizing the LLR table corresponding to 1H2S, the LLR table corresponding to 1H1S is also optimized. However, if the second iteration count is less than the second preset threshold, directly optimizing the LLR table corresponding to 1H2S would require a larger amount of data to be read, taking longer and affecting the operating efficiency of the memory 11100.

[0150] Similarly, if software decoding of data read from the target storage area using the LLR tables corresponding to 1H1S and 1H2S fails, software decoding is performed using the LLR table corresponding to 1H3S. After the third iteration, if the number of iterations is less than a third preset threshold, the LLR table corresponding to 1H2S is optimized (and the LLR table corresponding to 1H1S is also optimized). If the number of iterations is greater than the third preset threshold, the LLR table corresponding to 1H3S is optimized (and the LLR tables corresponding to 1H1S and 1H2S are also optimized).

[0151] In some possible implementations, voltage ranges are divided through multiple data reads. For example, if each memory cell 606 is configured to store three bits of data, the target storage region can be MP, CP, and LP in the memory. Figure 18 As shown in Table 5, the reference voltage is read (e.g.) Figure 9 Multiple data reads (RA, V1, V2, V3, V4, V5, V6) are performed using any of the reference read voltages RA, RB, RC, RD, RE, RF, and RG (RA as an example) and multiple voltage offsets (such as -8, +8, -16, +16, -24, +24) to obtain multiple sets of data. Based on these multiple sets of data, multiple voltage intervals are determined to belong to the threshold voltage of the memory cell in the target memory area. A voltage interval is the interval in which the data bits in two adjacent sets of data flip, that is, the voltage interval is used to characterize the bit flip (flipping from 1 to 0 or from 0 to 1) of the data read from the same location in the target memory area twice consecutively.

[0152] In some examples, when determining multiple voltage intervals (bit flip intervals), in Table 5, when performing the first R0 read based on the read voltage RA, the data "1" in the memory cell with a threshold voltage less than the read voltage RA and the data "0" in the memory cell with a threshold voltage greater than the read voltage RA can be divided into two voltage intervals, voltage interval 0 and voltage interval 1. When performing the second R1 read based on the read voltage V1, the data "1" in the memory cell with a threshold voltage less than the read voltage V1 and the data "0" in the memory cell with a threshold voltage greater than the read voltage V1. The data obtained from the first R0 read and the second R3 read will be determined as a voltage interval at the position where 1 (0) flips to 0 (1), that is, as shown in the second R3 read row in Table 5, the voltage interval 1 corresponding to 2 flips from 1 to 0, and the voltage interval division is further refined. When performing the third R4 read based on the read voltage V2, the data "1" in the memory cell with a threshold voltage less than the read voltage V2 and the data "0" in the memory cell with a threshold voltage greater than the read voltage V2. The data obtained from the second R3 read and the third R4 read will determine the position where 1(0) flips to 0(1) as a voltage interval. That is, as shown in Table 5, the voltage interval 2 corresponding to row 3 in the third R4 read, flips from 0 to 1, further refining the voltage interval division. Therefore, the 1H1S reading method can determine four voltage intervals from voltage interval 0 to voltage interval 3. Similarly, the 1H2S reading method can determine six voltage intervals from voltage interval 0 to voltage interval 5. The 1H3S reading method can determine eight voltage intervals from voltage interval 0 to voltage interval 7.

[0153] Table 5

[0154]

[0155] Multiple data reads can be performed using either of the following methods: TLC mode read and SLR (single level read) mode.

[0156] In one example, the TLC mode read method, due to different encoding methods, includes multiple read modes, such as 124 (LP read 1 time, CP read 2 times, and MP read 4 times) and 232 (LP read 2 times, CP read 3 times, and MP read 2 times). The controller 11200 sends a first read instruction to the memory 11100. The first read instruction includes the address of the first storage area of ​​the memory 11100, the reference read voltage, and the voltage offset. The address of the first storage area is the address of the target storage area.

[0157] like Figure 7The distribution shown is a 124 reading mode. LP is read once using the reference reading voltage RD, CP needs to be read twice using the reference reading voltages RB and RF, and MP needs to be read four times using the reference reading voltages RA, RC, RE, and RG.

[0158] like Figure 8 The distribution shown represents the 232 reading mode. LP is determined by reading twice using reference voltages RA and RE; CP is determined by reading three times using reference voltages RB, RD, and RF; and MP is determined by reading twice using reference voltages RC and RG. The encoding method for different programming states can be determined according to the actual situation.

[0159] like Figure 19 As shown, in order to Figure 8 The distribution shown is illustrated using the 232 to read LP from memory 11100 as an example. Controller 11200 sends a first read instruction to memory 11100. The first read instruction includes a first reference read voltage, a second reference read voltage, a first voltage offset, and a second voltage offset. The first reference read voltage is offset based on the first voltage offset, and the second reference read voltage is offset based on the second voltage offset.

[0160] For example, during the first R0 data read, the first read instruction includes a first reference read voltage of RA and a first voltage offset of 0, a second reference read voltage of RE and a second voltage offset of 0, to acquire the first set of data.

[0161] During the second R1 data read, the first read instruction includes the first reference read voltage being RA, the first voltage offset indicating that the first reference read voltage RA is offset to V1, the second reference read voltage being RE, and the second voltage offset indicating that the second reference read voltage RE is offset to V7, thereby acquiring the second set of data.

[0162] During the third R2 data read, the first read instruction includes the first reference read voltage being RA, the first voltage offset indicating that the first reference read voltage RA is offset to V2, the second reference read voltage being RE, and the second voltage offset indicating that the second reference read voltage RE is offset to V8, thereby acquiring the third set of data.

[0163] Optionally, during the third R2 data read, the first read instruction includes a first reference read voltage of V1, a first voltage offset indicating that the first reference read voltage V1 is offset to V2, a second reference read voltage of V7, and a second voltage offset indicating that the second reference read voltage V7 is offset to V8, thereby acquiring the third set of data.

[0164] The same applies to the fourth R3 data read, the fifth R4 data read, the sixth R5 data read, and the seventh R6 data read, and so on, so it will not be repeated here.

[0165] Based on the flipping of data bits 0 and 1, multiple voltage ranges (bit-flipping ranges) are determined for the threshold voltage of the memory cell in the target storage area. This involves merging bit-flipping ranges. For example, if there are eight predefined LLR voltage ranges (voltage ranges 0, 1, 2, 3, 4, 5, 6, and 7), after the controller 11200 sends a read command, the same bit-flipping ranges can be merged into one voltage range. If the first R0 data read is performed using the reference read voltage RA or RE, then voltage ranges 0, 1, 2, and 3 can be merged into one voltage range, and voltage ranges 4, 5, 6, and 7 can be merged into one voltage range. During the second R1 data read, if the read voltage is V1 (negative offset from the reference read voltage RA) or V7 (positive offset from the reference read voltage RE), then voltage ranges 0, 1, and 2 can be merged into one voltage range, and voltage ranges 3, 4, 5, 6, and 7 can be merged into one voltage range. During the third R2 data reading, the reading is performed using either reading voltage V2 (positive offset from the reference reading voltage RA) or V8 (negative offset from the reference reading voltage RE). Voltage intervals 0, 1, 2, 3, and 4 can be merged into one voltage interval, and voltage intervals 5, 6, and 7 can be merged into another. After three readings (1H1S), voltage intervals 0, 1, 2, 3, 4, 5, 6, and 7 can be merged into four voltage intervals, as shown in Table 6. Voltage intervals 0, 1, and 2 are merged into one voltage interval 0, voltage interval 3 into one voltage interval 3, voltage interval 4 into one voltage interval 4, and voltage intervals 5, 6, and 7 into one voltage interval 7. The same applies to 1H2S and 1H3S, as shown in Table 6. It should be noted that the voltage intervals are numbered during division, and the numbering may be discontinuous after merging. This is only for clarity and does not necessarily represent a mandatory setting in actual applications.

[0166] The division of voltage ranges is related to the number of data reads or the offset voltage. For example, the more data reads, the smaller the granularity of the voltage range division; the smaller the offset voltage, the smaller the granularity of the voltage range division.

[0167] Table 6

[0168] LLR voltage interval 0 1 2 3 4 5 6 7 1H1S 0+1+2 \ \ 3 4 \ \ 5+6+7 1H2S 0+1 \ 2 3 4 5 \ 7 1H3S 0 1 2 3 4 5 6 7

[0169] In another example, using the SLR read method, taking the reading of LP in memory 11100 as an example, such as... Figure 20As shown, the controller 11200 sends a data read command to the memory 11100. The read command includes a reference read voltage and a voltage offset, with the reference read voltage offset based on the voltage offset. For example, the command may include a reference read voltage RA and a voltage offset instructing the reference read voltage RA to offset, or the command may include a reference read voltage RE and an offset instructing the reference read voltage RE to offset. Compared to the TLC mode read method, the data read command sent by the controller 11200 to the memory 11100 in the SLC mode read method only contains a reference voltage and an offset. Therefore, the read time using the SLC mode is shorter than that of the TLC mode read method.

[0170] Based on the flipping behavior of data bit 0 and data bit 1, the bit flipping interval is determined, which also involves merging the bit flipping intervals, as shown in Table 7. The specific merging method is similar to the scheme shown in Table 6, and will not be repeated here.

[0171] Table 7

[0172]

[0173] S220. Determine the characteristic values ​​of the target storage area.

[0174] In some examples, eigenvalues ​​can be used to characterize the distribution of storage cells in different states within a current storage region. When determining the eigenvalues ​​of a storage region, the distribution of storage cells in different states within the region can be used as a basis. Typically, the distribution of storage cells in different states within a storage region follows a normal distribution. However, the operating conditions of storage cells can be affected by data storage time and the number of write / erase (P / E) cycles, causing the distribution of storage cells in different states to no longer be perfectly normal.

[0175] Taking the 1H2S reading method as an example, such as Figure 21 As shown, the distribution characteristics of memory cells in different states in the memory region of memory 11100 are normally distributed, and the critical region near the read voltage is symmetrical based on the reference read voltage (taking RA as an example). The number of memory cells whose encoded data is flipped from 1 to 0 (1-0) on both sides of the symmetry is approximately equal to the number of memory cells whose encoded data is flipped from 0 to 1 (0-1).

[0176] like Figure 22 or Figure 23 As shown, the distribution characteristics of storage cells in different states within the storage region are no longer perfectly normal. For example... Figure 22As shown, in the critical region near the read voltage, to the left of the reference read voltage RA, the number of memory cells where the encoded data flips from 1 to 0 (1-0) is greater than the number of memory cells where the encoded data flips from 0 to 1 (0-1) to the right of the reference read voltage RA. Figure 22 As shown, in the critical region near the read voltage, to the left of the reference read voltage RA, the number of memory cells where the encoded data is flipped from 1 to 0 (1-0) is less than the number of memory cells where the encoded data is flipped from 0 to 1 (0-1) to the right of the reference read voltage RA.

[0177] Therefore, the distribution characteristics of storage cells in different states in the storage area of ​​memory 11100 can reflect or represent the current state of the storage area in memory 11100.

[0178] Eigenvalues ​​can be defined as:

[0179]

[0180] As shown in Table 8, Figure 21 The characteristic value 'a' of the distribution shown is approximately equal to 1. Figure 22 The characteristic value b of the distribution shown is approximately equal to 2. Figure 23 The characteristic value c of the distribution shown is approximately equal to 0.5.

[0181] Table 8

[0182] eigenvalue a b c \ \ …

[0183] Each feature value can correspond to multiple LLR tables (1H1S, 1H2S, 1H3S). As shown in Table 9, taking feature value 'a' as an example.

[0184] Table 9

[0185]

[0186] S230. Count the number of bits 0 and bits 1 in the original data of each voltage range.

[0187] In some examples, the raw data can be decoded (or target data) by LDPC software decoding as shown in step S130, including but not limited to software decoding based on 1H1S LLR table, or 1H2S LLR table, or 1H3S LLR table.

[0188] S240. Calculate the LLR value L(x) for each voltage range and generate an LLR table.

[0189] In some examples, L(x) can be calculated using the following formula (1):

[0190]

[0191] Where p(x=0) represents the probability of bit 0 in the original programming data x; p(x=1) represents the probability of bit 1 in the original programming data x.

[0192] Quantizing L(x) yields a quantized LLR.

[0193] Step S250: Based on the characteristic values ​​of the storage area, the LLR tables are classified to form an LLR table pool.

[0194] In some examples, as shown in Table 8, the LLR table pool includes multiple features. Each feature includes multiple LLR tables, as shown in Table 9.

[0195] For example, when optimizing the LLR table based on the current state of a certain storage area in memory 11100, if the feature value d of the current storage area is not in the LLR table pool as shown in Table 8, then the feature value d and the corresponding LLR table are added to the table pool, as shown in Table 10.

[0196] Table 10

[0197] eigenvalue a b c d \ …

[0198] If the feature value of the current storage area exists in the LLR table pool as shown in Table 8, then the optimized LLR table corresponding to that feature value is updated in the table pool.

[0199] Through the above-disclosed implementation method, after optimizing the predefined LLR table in LDPC software decoding, when the controller 11200 decodes the data read from the memory 11100, it first determines the feature value of the storage area where the read data is located. Based on the feature value, it then selects the corresponding LLR table from the optimized LLR table pool to decode the read data and obtain the decoded data or target data.

[0200] Based on the foregoing Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 and Figure 6 The electronic devices, storage systems, controllers, and memory shown can achieve, for example... Figure 24 The diagram shows the operation method of the controller, including the following steps S310-S370. The specific steps include:

[0201] S310. Obtain the target data based on the data read from the memory.

[0202] In some instances, such asFigure 2 As shown, the controller 11200 includes at least a cache 11240 and a processor 11220, which are coupled together. The processor 11220 can obtain the target data through LDPC soft decoding as shown in step S130, including but not limited to soft decoding based on the 1H1S LLR table, or the 1H2S LLR table, or the 1H3S LLR table.

[0203] S320: Send a plurality of first read instructions to the memory. The first read instruction includes the address of a first storage region of the memory, a reference read voltage, and a voltage offset; at least two of the plurality of first read instructions have different voltage offsets.

[0204] In some instances, such as Figure 19 As shown, the first read instruction may include a first reference read voltage, a second reference read voltage, a first voltage offset, and a second voltage offset; the first reference read voltage is offset based on the first voltage offset; the second reference read voltage is offset based on the second voltage offset. For details, please refer to... Figure 19 The embodiments shown are not described in detail here.

[0205] In some instances, such as Figure 20 As shown, the first read instruction may include a reference read voltage and a voltage offset, wherein the reference read voltage is offset based on the voltage offset. For details, please refer to... Figure 20 The embodiments shown are not described in detail here.

[0206] In some instances, the address of the first storage region is used to determine the target storage region in step S210. The storage data in the first storage region has not been reconstructed using a Redundant Array of Independent Disks (RAID). For details, please refer to the embodiment shown in step S210; further elaboration is omitted here.

[0207] S330: According to multiple first read instructions, the memory sends multiple sets of first data to the processor.

[0208] In some examples, please refer to the following: Figure 19 or Figure 20 In the illustrated embodiment, the multiple sets of first data include a first set of data, a second set of data, and a third set of data, etc., which will not be described in detail here.

[0209] S340. Based on the target data and multiple sets of first data, obtain the log-likelihood ratio table.

[0210] In some examples, multiple voltage ranges are determined based on multiple sets of first data to which the threshold voltage of the memory cell in the first memory region belongs. The voltage range is the interval where data bits in two adjacent sets of first data flip. For details, please refer to...Figure 18 The implementation methods shown in Table 5.

[0211] For example, if multiple sets of first data include at least a first set of data and a second set of data, the threshold voltage in the first storage region is partitioned according to the first set of data to obtain a first partitioning result; the threshold voltage in the first storage region is partitioned according to the second set of data to obtain a second partitioning result; and multiple voltage ranges to which the threshold voltage of the storage cell in the first storage region belongs are determined according to the first partitioning result and the second partitioning result.

[0212] Specifically, such as Figure 18 As shown in Table 5, the first set of data can be the data 11110000 read during the first read based on the read voltage RA. Based on the first set of data 11110000, the threshold voltage in the first storage area is partitioned to obtain two voltage intervals, namely the voltage interval of the storage cell with a threshold voltage of "1" and the voltage interval of the storage cell with a threshold voltage of 0. The second set of data can be the data 11100000 read during the second read based on the read voltage V1. Two voltage intervals are obtained, namely the voltage interval of the storage cell with a threshold voltage of "1" and the voltage interval of the storage cell with a threshold voltage of 0. The position of 1 (0) flipped to 0 (1) in the first set of data 11110000 and the second set of data 11100000 is determined as a voltage interval, thus obtaining multiple voltage intervals to which the threshold voltage of the storage cell in the first storage area belongs.

[0213] Of course, the first set of data can also be the data read during the second read based on the reading voltage V1, and the second set of data can also be the data read during the third read based on the reading voltage V2. For details, please refer to... Figure 18 The implementation methods shown in Table 5.

[0214] For example, the characteristic value of the first storage region is determined based on a plurality of voltage ranges of threshold voltage in the first storage region.

[0215] Specifically, you can refer to, for example Figure 21 , Figure 22 and Figure 23 The implementation method shown.

[0216] For example, the log-likelihood ratio of each voltage range is obtained based on the target data and multiple voltage ranges of the threshold voltage in the first storage region.

[0217] Specifically, the implementation method shown in step S240 can be referred to.

[0218] For example, a log-likelihood ratio table is obtained based on the log-likelihood ratio of each voltage interval of the threshold voltage in the first storage region and the characteristic value of the first storage region.

[0219] Specifically, the implementation method shown in step S240 can be referred to.

[0220] S350: Send a plurality of second read instructions to the memory. The second read instructions include the address of a second storage region of the memory, a reference read voltage, and a voltage offset; at least two of the plurality of second read instructions have different voltage offsets.

[0221] In some examples, the execution process of step S350 is similar to that of step S320, and you can refer to the implementation method shown in step S320 for details.

[0222] S360. According to multiple second read instructions, the memory sends multiple sets of second data to the processor.

[0223] In some examples, the execution process of step S360 is similar to that of step S330, and you can refer to the implementation method shown in step S330 for details.

[0224] S370. Based on multiple sets of second data and the log-likelihood ratio table, obtain the decoded data for the second storage area.

[0225] In some examples, such as Figure 25 As shown, step S370 includes steps S371-S372:

[0226] S371. Determine the characteristic values ​​of the second storage area based on multiple sets of second data;

[0227] For example, the determination of the feature values ​​of the second storage region can refer to... Figure 21 , Figure 22 and Figure 23 The implementation method shown.

[0228] S372. Based on the eigenvalues ​​and log-likelihood ratio table of the second storage area, obtain the decoded data of the second storage area.

[0229] For example, after optimizing the predefined LLR table in LDPC software decoding, when the controller 11200 decodes the data read from the memory 11100, it first determines the feature value of the storage area where the read data is located. Based on the feature value, it then selects the corresponding LLR table from the optimized LLR table pool to decode the read data and obtain the decoded data or target data.

[0230] Based on the foregoing Figure 1 , Figure 2 , Figure 3 ,Figure 4 , Figure 5 and Figure 6 The electronic devices, storage systems, and memory shown can achieve the following: Figure 26 The method for operating the storage system shown includes the following steps S410-S470, and the specific steps include:

[0231] S410. Obtain the target data based on the data read from the memory.

[0232] In some instances, such as Figure 1 , Figure 2 , Figure 3 and Figure 4 As shown, the storage system 11000 includes a controller 11200 and a memory 11100, which are coupled together. The controller 11200 can obtain the target data through LDPC soft decoding as shown in step S130, including but not limited to soft decoding based on 1H1S LLR table, or 1H2S LLR, or 1H3S LLR table.

[0233] S420: Send a plurality of first read instructions to the memory. The first read instruction includes the address of a first storage region of the memory, a reference read voltage, and a voltage offset; at least two of the plurality of first read instructions have different voltage offsets.

[0234] In some instances, such as Figure 19 As shown, the first read instruction may include a first reference read voltage, a second reference read voltage, a first voltage offset, and a second voltage offset; the first reference read voltage is offset based on the first voltage offset; the second reference read voltage is offset based on the second voltage offset. For details, please refer to... Figure 19 The embodiments shown are not described in detail here.

[0235] In some instances, such as Figure 20 As shown, the first read instruction may include a reference read voltage and a voltage offset, wherein the reference read voltage is offset based on the voltage offset. For details, please refer to... Figure 20 The embodiments shown are not described in detail here.

[0236] In some instances, the address of the first storage region is used to determine the target storage region in step S210. The storage data in the first storage region has not been reconstructed using a Redundant Array of Independent Disks (RAID). For details, please refer to the embodiment shown in step S210; further elaboration is omitted here.

[0237] S430: According to multiple first read instructions, the memory sends multiple sets of first data to the controller.

[0238] In some examples, please refer to the following: Figure 19 or Figure 20 In the illustrated embodiment, the multiple sets of first data include a first set of data, a second set of data, and a third set of data, etc., which will not be described in detail here.

[0239] S440. Based on the target data and multiple sets of first data, obtain the log-likelihood ratio table.

[0240] In some examples, multiple voltage ranges are determined based on multiple sets of first data to which the threshold voltage of the memory cell in the first memory region belongs. The voltage range is the interval where data bits in two adjacent sets of first data flip. For details, please refer to... Figure 18 The implementation methods shown in Table 5.

[0241] For example, if multiple sets of first data include at least a first set of data and a second set of data, the threshold voltage in the first storage region is partitioned according to the first set of data to obtain a first partitioning result; the threshold voltage in the first storage region is partitioned according to the second set of data to obtain a second partitioning result; and multiple voltage ranges to which the threshold voltage of the storage cell in the first storage region belongs are determined according to the first partitioning result and the second partitioning result.

[0242] Specifically, such as Figure 18 As shown in Table 5, the first set of data can be the data 11110000 read during the first read based on the read voltage RA. Based on the first set of data 11110000, the threshold voltage in the first storage area is partitioned to obtain two voltage intervals, namely the voltage interval of the storage cell with a threshold voltage of "1" and the voltage interval of the storage cell with a threshold voltage of 0. The second set of data can be the data 11100000 read during the second read based on the read voltage V1. Two voltage intervals are obtained. Based on the second set of data 11100000 and the first set of data 11110000, two voltage intervals are obtained, namely the voltage interval of the storage cell with a threshold voltage of "1" and the voltage interval of the storage cell with a threshold voltage of 0. The position of 1 (0) flipped to 0 (1) in the first set of data 11110000 and the second set of data 11100000 is determined as a voltage interval, thus obtaining multiple voltage intervals to which the threshold voltage of the storage cell in the first storage area belongs.

[0243] Of course, the first set of data can also be the data read during the second read based on the reading voltage V1, and the second set of data can also be the data read during the third read based on the reading voltage V2. For details, please refer to... Figure 18 The implementation methods shown in Table 5.

[0244] For example, the characteristic value of the first storage region is determined based on a plurality of voltage ranges of threshold voltage in the first storage region.

[0245] Specifically, you can refer to, for example Figure 21 , Figure 22 and Figure 23 The implementation method shown.

[0246] For example, the log-likelihood ratio of each voltage interval is obtained based on the decoded data and the multiple voltage intervals to which the threshold voltage of the storage cell in the first storage region belongs.

[0247] Specifically, the implementation method shown in step S240 can be referred to.

[0248] For example, a log-likelihood ratio table is obtained based on the log-likelihood ratio of each voltage interval of the threshold voltage in the first storage region and the characteristic value of the first storage region.

[0249] Specifically, the implementation method shown in step S240 can be referred to.

[0250] S450: Send a plurality of second read instructions to the memory. The second read instructions include the address of a second storage region of the memory, a reference read voltage, and a voltage offset; at least two of the plurality of second read instructions have different voltage offsets.

[0251] In some examples, the execution process of step S450 is similar to that of step S420, and you can refer to the implementation method shown in step S420 for details.

[0252] S460. According to multiple second read instructions, the memory sends multiple sets of second data to the controller.

[0253] In some examples, the execution process of step S460 is similar to that of step S430, and you can refer to the implementation method shown in step S430 for details.

[0254] S470. Based on multiple sets of second data and the log-likelihood ratio table, obtain the decoded data for the second storage area.

[0255] In some examples, such as Figure 27 As shown, step S470 includes steps S471-S472:

[0256] S471. Determine the feature values ​​of the second storage area based on multiple sets of second data;

[0257] For example, the determination of the feature values ​​of the second storage region can refer to... Figure 21 , Figure 22 and Figure 23 The implementation method shown.

[0258] S472. Based on the eigenvalues ​​and log-likelihood ratio table of the second storage area, obtain the decoded data of the second storage area.

[0259] For example, after optimizing the predefined LLR table in LDPC software decoding, when the controller 11200 decodes the data read from the memory 11100, it first determines the feature value of the storage area where the read data is located. Based on the feature value, it then selects the corresponding LLR table from the optimized LLR table pool to decode the read data and obtain the decoded data or target data.

[0260] This application provides a controller, a method for operating the controller, a storage system, and an electronic device. By deeply considering the actual working state of the storage areas in the memory 11100, it achieves precise optimization of the LLR table, enabling the optimized LLR table to more closely reflect the true characteristics of the storage medium, thereby significantly improving the matching degree with the memory 11100. Furthermore, by introducing an LLR table classification method based on storage area feature values, the controller 11200 can quickly and accurately match the most suitable LLR table during the decoding process based on these feature values. This not only simplifies the matching process but also significantly improves the performance and efficiency of LDPC software decoding, while simultaneously enhancing the overall performance of the storage system 11000.

[0261] This application also provides a computer-readable storage medium including instructions. When the instructions are executed on the electronic device or storage system described in the above embodiments, the electronic device or storage system causes the electronic device or storage system to perform the controller operation method or storage system operation method described in the above embodiments.

[0262] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A controller, characterized in that, include: cache; and The processor, coupled to the cache, is configured to: A plurality of first read instructions are sent to the memory; each first read instruction includes an address of a first storage region of the memory, a reference read voltage, and a voltage offset; at least two of the plurality of first read instructions have different voltage offsets. Obtain multiple sets of first data; and Based on the multiple sets of first data, a log-likelihood ratio table is obtained.

2. The controller according to claim 1, characterized in that, The processor is also configured to: A plurality of second read instructions are sent to the memory; each second read instruction includes an address of a second storage region of the memory, a reference read voltage, and a voltage offset; at least two of the plurality of second read instructions have different voltage offsets. Obtain multiple sets of second data; The decoded data for the second storage area is obtained based on the multiple sets of second data and the log-likelihood ratio table.

3. The controller according to claim 1, characterized in that, The processor is specifically configured as follows: Based on the multiple sets of first data, determine the feature values ​​of the first storage area; The log-likelihood ratio table is obtained based on the multiple sets of first data and the feature values ​​of the first storage area.

4. The controller according to claim 3, characterized in that, The processor is also configured to: Multiple second read instructions are sent to the memory to acquire multiple sets of second data; each second read instruction includes the address of a second storage region of the memory, a reference read voltage, and a voltage offset; at least two of the multiple second read instructions have different voltage offsets. Based on the multiple sets of second data, determine the feature values ​​of the second storage area; The decoded data of the second storage area is obtained based on the feature values ​​of the second storage area and the log-likelihood ratio table.

5. The controller according to claim 1, characterized in that, The processor is also configured to: The controller is specifically configured to: obtain the log-likelihood ratio table based on the target data and the plurality of first data sets; the target data is obtained by the processor decoding the data read from the first storage area.

6. The controller according to claim 5, characterized in that, The processor is specifically configured to: obtain multiple voltage ranges based on the reference reading voltage and the voltage offset; The log-likelihood ratio table is obtained based on the target data and the multiple voltage ranges.

7. The controller according to claim 6, characterized in that, The processor is specifically configured as follows: Based on the target data and the multiple voltage ranges, the log-likelihood ratio of each voltage range is obtained; The log-likelihood ratio table is obtained based on the log-likelihood ratio of each voltage range.

8. The controller according to claim 5, characterized in that, The storage data in the first storage area was not reconstructed using a standalone redundant disk array (RAID).

9. The controller according to any one of claims 1-8, characterized in that, The first read instruction includes a reference read voltage and a voltage offset, wherein the reference read voltage is offset based on the voltage offset.

10. The controller according to any one of claims 1-8, characterized in that, The first read instruction includes a first reference read voltage, a second reference read voltage, a first voltage offset, and a second voltage offset; the first reference read voltage is offset based on the first voltage offset. The second reference reading voltage is offset based on the second voltage offset.

11. A method for operating a controller, characterized in that, include: Send a plurality of first read instructions to the memory; the first read instruction includes the address of a first storage region of the memory, a reference read voltage, and a voltage offset; At least two of the plurality of first read instructions have different voltage offsets; Obtain multiple sets of first data; and Based on the multiple sets of first data, a log-likelihood ratio table is obtained.

12. The method of operating the controller according to claim 11, characterized in that, The operation method of the controller also includes: A plurality of second read instructions are sent to the memory; each second read instruction includes an address of a second storage region of the memory, a reference read voltage, and a voltage offset; at least two of the plurality of second read instructions have different voltage offsets. Obtain multiple sets of second data; The decoded data for the second storage area is obtained based on the multiple sets of second data and the log-likelihood ratio table.

13. The method of operating the controller according to claim 11, characterized in that, The operation method of the controller also includes: Based on the multiple sets of first data, determine the feature values ​​of the first storage area; The log-likelihood ratio table is obtained based on the multiple sets of first data and the feature values ​​of the first storage area.

14. The method of operating the controller according to claim 13, characterized in that, The operation method of the controller also includes: Multiple second read instructions are sent to the memory to acquire multiple sets of second data; each second read instruction includes the address of a second storage region of the memory, a reference read voltage, and a voltage offset; at least two of the multiple second read instructions have different voltage offsets. Based on the multiple sets of second data, determine the feature values ​​of the second storage area; The decoded data of the second storage area is obtained based on the feature values ​​of the second storage area and the log-likelihood ratio table.

15. The method of operating the controller according to claim 11, characterized in that, The step of obtaining the log-likelihood ratio table based on the multiple sets of first data includes: The log-likelihood ratio table is obtained based on the target data and the multiple sets of first data; the target data is obtained by the processor decoding the data read from the first storage area.

16. The method of operating the controller according to claim 15, characterized in that, The step of obtaining the log-likelihood ratio table based on the target data and the multiple sets of first data includes: Based on the reference reading voltage and the voltage offset, multiple voltage ranges are obtained; The log-likelihood ratio table is obtained based on the target data and the multiple voltage ranges.

17. The method of operating the controller according to claim 16, characterized in that, The step of obtaining the log-likelihood ratio table based on the target data and the multiple voltage ranges includes: Based on the target data and the multiple voltage ranges, the log-likelihood ratio of each voltage range is obtained; The log-likelihood ratio table is obtained based on the log-likelihood ratio of each voltage range.

18. The method of operating the controller according to claim 15, characterized in that, The storage data in the first storage area was not reconstructed using a standalone redundant disk array (RAID).

19. The method of operating the controller according to any one of claims 11-18, characterized in that, The first read instruction includes a reference read voltage and a voltage offset, wherein the reference read voltage is offset based on the voltage offset.

20. The method of operating the controller according to any one of claims 11-18, characterized in that, The first read instruction includes a first reference read voltage, a second reference read voltage, a first voltage offset, and a second voltage offset; The first reference reading voltage is offset based on the first voltage offset; The second reference reading voltage is offset based on the second voltage offset.

21. A storage system, characterized in that, The storage system includes a memory and a controller as described in any one of claims 1-10, the controller being coupled to the memory.

22. An electronic device, characterized in that, The electronic device includes a host and a storage system as described in claim 21, wherein the host and the storage system are coupled.

23. A computer storage medium, characterized in that, The computer-readable storage medium includes instructions; when the instructions are executed on a processor, the processor causes the processor to perform the method of operation of the controller as described in any one of claims 11-20.

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