Pre-operational amplifier circuit applied to comparator and signal amplification method

Abstract

The invention provides a front operational amplifier circuit applied to a comparator and a signal amplification method, which can be applied to the technical field of integrated circuits. The circuit comprises a bias module used for generating bias current; the common-mode feedback module is used for generating common-mode control voltage based on the voltage of the first output end and the voltage of the second output end; the amplification module is connected to the bias module, the common-mode feedback module, the first input end, the second input end, the first output end and the second output end; the load module is used for controlling a current flowing through a current path between a power supply end and a grounding end based on a bias current and a voltage of a feedback end under the control of a common mode control voltage, so as to amplify a differential mode input voltage between a first input signal and a second input signal based on the current and the amplification module together, a first output signal and a second output signal are output through the first output end and the second output end respectively, and the differential mode output voltage between the first output signal and the second output signal is larger than the differential mode input voltage.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more specifically to a preamplifier circuit and signal amplification method applied to a comparator. Background Technology

[0002] A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is a circuit structure that converts analog signals into digital signals and is one of the important modules in integrated circuit design. The comparator is a crucial component of the SAR ADC, playing a vital role. In related technologies, a preamplifier circuit is typically used at the front end of the comparator to improve its speed, reduce comparator mismatch, and eliminate thermal noise (kT / C noise). Due to the limitations of the input signal range of the preamplifier circuit, its output voltage difference may be smaller than the input voltage difference, thus affecting the comparator's response time. Summary of the Invention

[0003] In view of the above problems, this disclosure provides a preamplifier circuit and signal amplification method for use in comparators.

[0004] According to a first aspect of this disclosure, a preamplifier circuit for a comparator is provided, comprising: a bias module connected to a power supply terminal and a current source, and used to generate a bias current; a common-mode feedback module connected to a first output terminal, a second output terminal, and a feedback terminal, and used to generate a common-mode control voltage based on the voltage of the first output terminal and the voltage of the second output terminal; an amplification module connected to the bias module, the common-mode feedback module, a first input terminal, a second input terminal, a first output terminal, and a second output terminal; and a load module connected to the power supply terminal, a ground terminal, the amplification module, the first output terminal, and the second output terminal, used to control the current flowing through the current path between the power supply terminal and the ground terminal based on the bias current and the voltage of the feedback terminal under the control of the common-mode control voltage, so as to amplify the differential input voltage between the first input signal at the first input terminal and the second input signal at the second input terminal based on the current and the amplification module, and output a first output signal and a second output signal through the first output terminal and the second output terminal respectively, wherein the differential output voltage between the first output signal and the second output signal is greater than the differential input voltage.

[0005] According to embodiments of this disclosure, the amplification module includes a first set of input transistors and a second set of input transistors connected together; the load module includes a first load unit and a second load unit connected together; the first set of input transistors is also connected to the first load unit, and the second set of input transistors is also connected to the second load unit; wherein, when any one of the input transistors in the first set of input transistors is operating in the cutoff region, the first load unit provides a current path as a load to obtain a first output signal; when any one of the input transistors in the second set of input transistors is operating in the cutoff region, the second load unit provides a current path as a load to obtain a second output signal.

[0006] According to an embodiment of this disclosure, the first input pair includes: a first transistor with a control terminal connected to a first input terminal, a first terminal connected to a bias module, and a second terminal connected to a first load unit; and a second transistor with a control terminal connected to the first input terminal, a first terminal connected to a feedback terminal, and a second terminal connected to the first load unit; the common-mode feedback module is further used to control the static DC operating point of the first transistor and the second transistor.

[0007] According to an embodiment of this disclosure, the second set of input transistors includes: a third transistor, with its control terminal connected to the second input terminal, its first terminal connected to the bias module, and its second terminal connected to the second load unit; and a fourth transistor, with its control terminal connected to the second input terminal, its first terminal connected to the feedback terminal, and its second terminal connected to the second load unit; the common-mode feedback module is also used to control the static DC operating point of the third transistor and the fourth transistor.

[0008] According to an embodiment of this disclosure, the first load unit includes: a fifth transistor, with its control terminal connected to a common-mode feedback module, its first terminal connected to a second load unit, and its second terminal connected to a second terminal of the second transistor; and a sixth transistor, with its control terminal connected to the common-mode feedback module, its first terminal connected to a ground terminal, and its second terminal connected to a second terminal of the first transistor.

[0009] According to an embodiment of this disclosure, the second load unit includes: a seventh transistor, with its control terminal connected to the common-mode feedback module, its first terminal connected to the first terminal of the fifth transistor, and its second terminal connected to the second terminal of the fourth transistor; and an eighth transistor, with its control terminal connected to the common-mode feedback module, its first terminal connected to the first terminal of the sixth transistor, and its second terminal connected to the second terminal of the third transistor.

[0010] According to an embodiment of this disclosure, the common-mode feedback module includes: a ninth transistor, a control terminal connected to the control terminal of a sixth transistor, a first terminal connected to a ground terminal, and a second terminal connected to a feedback terminal.

[0011] According to an embodiment of this disclosure, the common-mode feedback module further includes: a first resistor, the first end of which is connected to the second end of the fifth transistor, and the second end of which is connected to the control terminal of the fifth transistor; and a second resistor, the first end of which is connected to the second end of the first resistor, and the second end of which is connected to the second end of the seventh transistor.

[0012] According to an embodiment of this disclosure, the biasing module includes: a tenth transistor, with a control terminal connected to a second terminal of the tenth transistor and a first terminal connected to a power supply terminal; and an eleventh transistor, with a control terminal connected to the control terminal of the tenth transistor, a first terminal connected to a power supply terminal, and a second terminal connected to a first terminal of the first transistor.

[0013] The second aspect of this disclosure provides a signal amplification method based on the aforementioned preamplifier circuit, comprising: generating a common-mode control voltage based on the voltage of a first output terminal and the voltage of a second output terminal; adjusting the common-mode control voltage to obtain a target common-mode control voltage; and, under the control of the target common-mode control voltage, controlling the current flowing through the current path between the power supply terminal and the ground terminal based on the bias current and the voltage of the feedback terminal, so as to amplify the differential-mode input voltage between the first input signal at the first input terminal and the second input signal at the second input terminal based on the current and the amplification module, and outputting a first output signal and a second output signal through the first output terminal and the second output terminal respectively, wherein the differential-mode output voltage between the first output signal and the second output signal is greater than the differential-mode input voltage.

[0014] A third aspect of this disclosure provides a comparator including the aforementioned preamplifier circuitry used in the comparator.

[0015] A fourth aspect of this disclosure provides an analog-to-digital converter including the comparator described above.

[0016] According to the preamplifier circuit for a comparator provided in this disclosure, the bias module provides a bias current to the amplification module, the common-mode feedback module generates a common-mode control voltage based on the voltage of the first output terminal and the voltage of the second output terminal, and the load module is used to control the current flowing through the current path between the power supply terminal and the ground terminal based on the bias current and the voltage of the feedback terminal under the control of the common-mode control voltage, so as to amplify the differential input voltage between the first input signal at the first input terminal and the second input signal at the second input terminal together with the amplification module, and output the first output signal and the second output signal through the first output terminal and the second output terminal respectively, and the differential output voltage between the first output signal and the second output signal is greater than the differential input voltage. When the voltages of the first and second input signals are too high or too low, the load module provides a current path as a load. That is, under the control of the common-mode control voltage, the current flowing through the current path between the power supply terminal and the ground terminal is controlled based on the bias current and the voltage at the feedback terminal. This achieves a gain greater than 0dB for the preamplifier circuit across the entire input range. Furthermore, since the differential output voltage between the first and second output signals is greater than the differential input voltage, the swing of the preamplifier circuit can be effectively enhanced across the entire input range, thereby reducing the impact of the reduced swing of the preamplifier circuit on the comparator response delay. Attached Figure Description

[0017] The foregoing contents, as well as other objects, features, and advantages of this disclosure, will become clearer from the following description of embodiments with reference to the accompanying drawings, in which:

[0018] Figure 1 A preamplifier circuit applied to a comparator according to an embodiment of the present disclosure is schematically shown;

[0019] Figure 2 This illustration schematically depicts an embodiment according to the present disclosure. Figure 1 The simulation diagram of the preamplifier circuit shown is shown.

[0020] Figure 3 A schematic diagram illustrates the structure of a preamplifier circuit applied to a comparator according to an embodiment of the present disclosure;

[0021] Figure 4 A preamplifier circuit applied to a comparator according to yet another embodiment of the present disclosure is illustrated schematically;

[0022] Figure 5A The diagram schematically illustrates a gain simulation of a preamplifier circuit for a comparator applied to a 40nm process according to an embodiment of the present disclosure.

[0023] Figure 5BThe schematic diagram illustrates a transient simulation of a preamplifier circuit for a comparator applied to a 40nm process according to another embodiment of the present disclosure;

[0024] Figure 6 A flowchart illustrating a signal amplification method based on a preamplifier circuit according to an embodiment of the present disclosure is shown schematically.

[0025] Figure 7 A schematic diagram of a comparator according to an embodiment of the present disclosure is shown.

[0026] Figure 8 A schematic diagram of a digital-to-analog converter according to an embodiment of the present disclosure is shown.

[0027] Figure 9A A schematic diagram illustrating the structure of a comparator applied to a 40nm process according to an embodiment of the present disclosure is shown.

[0028] Figure 9B This schematically illustrates a structural diagram of a comparator applied to a 40nm process according to another embodiment of the present disclosure;

[0029] Figure 10A This illustration schematically shows an equivalent mismatch simulation diagram of a comparator applied to a 40nm process according to an embodiment of the present disclosure;

[0030] Figure 10B The illustration schematically shows an equivalent mismatch simulation diagram of a comparator applied to a 40nm process according to another embodiment of the present disclosure. Detailed Implementation

[0031] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0032] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0033] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0034] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0035] SAR ADCs are widely used in high-precision measurement systems and communication equipment. The response speed and accuracy of the core comparator are crucial in the entire ADC conversion process. The front end of the comparator typically uses a preamplifier circuit to pre-amplify the input signal to accelerate the comparison process. The preamplifier circuit also serves to cancel thermal noise (kT / C noise) and compensate for comparator offset voltage. However, when the input signal exceeds the input range of the preamplifier circuit, the gain of the preamplifier circuit drops significantly, even to less than 0dB. This results in the output voltage difference of the preamplifier circuit being less than the input voltage difference, which in turn affects the response time of the subsequent comparator stage. This response delay directly affects the conversion time, thus reducing the ADC's conversion rate and accuracy.

[0036] Figure 1 The illustration schematically shows a preamplifier circuit applied to a comparator according to an embodiment of the present disclosure.

[0037] In implementing a preamplifier circuit used in a comparator, one implementation method is as follows: Figure 1 As shown, the preamplifier circuit used in the comparator may include transistors M1, M2, M3, M4, M5, M6, and M7, two resistors R1 and R2, and a power supply. The two power supplies are electrically connected to transistors M6 and M7, respectively. Transistors M6 and M7 can form a current mirror structure to provide current to transistors M1 and M3. The gate terminals of transistors M1 and M2 are connected to the differential input terminal, and the gate terminals of transistors M3 and M4 are connected to another differential input terminal. The drain terminals of transistors M1 and M2 are electrically connected to the first resistor R1 to achieve the first output, and the drain terminals of transistors M3 and M4 are electrically connected to the second resistor R2 to achieve the second output.

[0038] Figure 2 This illustration schematically depicts an embodiment according to the present disclosure. Figure 1The simulation diagram of the preamplifier circuit is shown.

[0039] The input voltage of the preamplifier circuit used in the comparator is determined by the preceding stage circuit, such as... Figure 1 As shown, when the input voltage continues to decrease, the input pair transistors M2 and M4 will enter the linear region until they reach the cutoff region; when the input voltage continues to increase, the input pair transistors M1 and M3 will enter the linear region until they reach the cutoff region. Figure 2 As shown, the top leftmost red line represents the gain, the middle leftmost green line represents the input voltage, and the bottom leftmost yellow line represents the output voltage. When the input transistors enter the linear region, the gain decreases, and the output voltage no longer changes linearly with the input signal. When the input transistors enter the cutoff region, the output voltage saturates, and the gain drops below 0dB, thus affecting the input voltage difference of the subsequent comparator and reducing the comparator's response speed.

[0040] Therefore, based on the above Figure 1 The preamplifier circuit shown for the comparator may experience output voltage saturation when the input signal range is large, resulting in the output voltage difference being less than the input voltage difference, which in turn affects the response time of the next stage comparator.

[0041] In view of this, the present disclosure provides a preamplifier circuit for a comparator, comprising: a bias module connected to a power supply terminal and a current source, and used to generate a bias current; a common-mode feedback module connected to a first output terminal, a second output terminal, and a feedback terminal, and used to generate a common-mode control voltage based on the voltage of the first output terminal and the voltage of the second output terminal; an amplification module connected to the bias module, the common-mode feedback module, a first input terminal, a second input terminal, a first output terminal, and a second output terminal; and a load module connected to a power supply terminal, a ground terminal, the amplification module, the first output terminal, and the second output terminal, used to control the current flowing through the current path between the power supply terminal and the ground terminal based on the bias current and the voltage of the feedback terminal under the control of the common-mode control voltage, so as to amplify the differential input voltage between the first input signal at the first input terminal and the second input signal at the second input terminal based on the current and the amplification module, and output a first output signal and a second output signal through the first output terminal and the second output terminal respectively, wherein the differential output voltage between the first output signal and the second output signal is greater than the differential input voltage.

[0042] Figure 3 A schematic diagram of a preamplifier circuit applied to a comparator according to an embodiment of the present disclosure is shown.

[0043] like Figure 3 As shown, the preamplifier circuit 300 applied to the comparator in this embodiment includes a bias module 310, a common-mode feedback module 320, an amplification module 330, and a load module 340.

[0044] The bias module 310 is connected to the power supply and the current source and is used to generate bias current.

[0045] The common-mode feedback module 320 is connected to the first output terminal, the second output terminal, and the feedback terminal, and is used to generate a common-mode control voltage based on the voltage of the first output terminal and the voltage of the second output terminal.

[0046] Amplification module 330 is connected to a bias module, a common-mode feedback module, a first input terminal, a second input terminal, a first output terminal, and a second output terminal. Amplification module 330 receives the bias current generated by bias module 310. In one implementation, the first input terminal can be a positive input terminal, and the second input terminal can be a negative input terminal. In another implementation, the first input terminal can be a negative input terminal, and the second input terminal can be a positive input terminal.

[0047] The load module 340 is connected to the power supply terminal, the ground terminal, the amplification module 330, the first output terminal, and the second output terminal. It is used to control the current flowing through the current path between the power supply terminal and the ground terminal based on the bias current and the voltage of the feedback terminal under the control of the common-mode control voltage. That is, the voltage of the feedback terminal is adjusted by the common-mode control voltage so as to amplify the differential input voltage between the first input signal of the first input terminal and the second input signal of the second input terminal based on the current and the amplification module. The first output signal and the second output signal are output through the first output terminal and the second output terminal, respectively. The differential output voltage between the first output signal and the second output signal is greater than the differential input voltage.

[0048] The first input signal and the second input signal can be differential input signals. The first input signal and the second input signal can be input to a first voltage terminal and a second voltage terminal, respectively. In one implementation, the first input signal can be input to a first input terminal, and the second signal can be input to a second input terminal. In another implementation, the first input signal can be input to a second input terminal, and the second signal can be input to a first input terminal.

[0049] The first output signal and the second output signal can be differential mode output signals, and the first output signal and the second output signal can be output from a first output terminal and a second output terminal, respectively. In one implementation, the first output signal can be output from the first output terminal, and the second output signal can be output from the second output terminal. In another implementation, the first output signal can be output from the second output terminal, and the second output signal can be output from the first output terminal.

[0050] Within the full input range, whether the first or second input signal is too large or too small, the load module and the amplification module can work together to control the current flowing through the current path between the power supply terminal and the ground terminal based on the bias current and the voltage at the feedback terminal, under the control of the common-mode control voltage. This amplifies the first and second input signals, making the differential input voltage between the first and second output signals greater than the differential input voltage.

[0051] The bias module provides bias current to the amplification module. The common-mode feedback module generates a common-mode control voltage based on the voltages of the first and second output terminals. The load module, under the control of the common-mode control voltage, controls the current flowing through the current path between the power supply terminal and the ground terminal based on the bias current and the voltage of the feedback terminal. This amplifies the differential input voltage between the first input signal at the first input terminal and the second input signal at the second input terminal, together with the amplification module. The load module outputs a first output signal and a second output signal through the first and second output terminals, respectively, and the differential output voltage between the first and second output signals is greater than the differential input voltage. When the voltages of the first and second input signals are too high or too low, the load module provides a current path as a load. That is, under the control of the common-mode control voltage, the current flowing through the current path between the power supply terminal and the ground terminal is controlled based on the bias current and the voltage at the feedback terminal. This achieves a gain greater than 0dB for the preamplifier circuit across the entire input range. Furthermore, since the differential output voltage between the first and second output signals is greater than the differential input voltage, the swing of the preamplifier circuit can be effectively enhanced across the entire input range, thereby reducing the impact of the reduced swing of the preamplifier circuit on the comparator response delay.

[0052] The amplification module may include a first set of input transistors and a second set of input transistors connected together; the load module may include a first load unit and a second load unit connected together; the first set of input transistors may also be connected to the first load unit, and the second set of input transistors may also be connected to the second load unit.

[0053] In one implementation, the first set of input pairs may include two input transistors, and the second set of input pairs may include two input transistors.

[0054] The two input transistors in the first and second input pairs can be different types of metal-oxide-semiconductor field-effect transistors (MOS transistors). In one implementation, the two input transistors in the first input pair can be an N-type MOS transistor and a P-type MOS transistor, respectively. In another implementation, the two input transistors in the second input pair can be an N-type MOS transistor and a P-type MOS transistor, respectively.

[0055] In some embodiments, the input transistor can operate in the cutoff region, saturation region, or subthreshold region. The cutoff region, also known as the off-state region, is when the input transistor is completely off. The saturation region is when the input transistor is fully on, representing the core operating area when the input transistor is used as an "amplifier." The subthreshold region lies between complete off and significant on.

[0056] When any one of the input transistors in the first input pair is operating in the cutoff region, the first load unit provides a current path as a load to obtain the first output signal. When any one of the input transistors in the second input pair is operating in the cutoff region, the second load unit provides a current path as a load to obtain the second output signal.

[0057] In one implementation, when the first input transistor in the first input pair operates in the cutoff region, the feedback terminal voltage is adjusted by a common-mode control voltage. The first load unit can act as a load to provide a current path, causing the second input transistor in the first input pair to operate in the saturation region, thereby obtaining the first output signal. Alternatively, when the second input transistor in the first input pair operates in the cutoff region, the feedback terminal voltage is adjusted by a common-mode control voltage, and the first load unit can act as a load to provide a current path, causing the first input transistor in the first input pair to operate in the saturation region, thereby obtaining the first output signal.

[0058] In one implementation, when the first input transistor in the second input pair operates in the cutoff region, the feedback terminal voltage is adjusted by a common-mode control voltage. The second load unit can act as a load to provide a current path, causing the second input transistor in the second input pair to operate in the saturation region, thereby obtaining the second output signal.

[0059] When any one of the input transistors in the first input pair operates in the saturation or subthreshold region, the feedback voltage is adjusted by a common-mode control voltage. The first load unit can also act as a load to provide a current path, causing the first input pair to operate in the saturation region to obtain the first output signal. When any one of the input transistors in the second input pair operates in the saturation or subthreshold region, the feedback voltage is adjusted by a common-mode control voltage. The second load unit can also act as a load to provide a current path, causing the second input pair to operate in the saturation region to obtain the second output signal.

[0060] The preamplifier circuit applied to the comparator not only achieves an output voltage difference greater than the input voltage difference when the input transistors are operating in the saturation or subthreshold regions, but also, when any one of the input transistors in the first input pair is operating in the cutoff region, the feedback voltage is adjusted by a common-mode control voltage, and the first load unit provides a current path, causing the other input transistor in the first input pair to operate in the saturation region, thus obtaining the first output signal. Similarly, when any one of the input transistors in the second input pair is operating in the cutoff region, the feedback voltage is adjusted by a common-mode control voltage, and the second load unit provides a current path, causing the other input transistor in the second input pair to operate in the saturation region, thus obtaining the second output signal. The differential output voltage between the first and second output signals is greater than the differential input voltage between the first and second input signals, thereby ensuring that the gain of the preamplifier circuit is always greater than 0dB across the entire input range. This effectively enhances the swing of the preamplifier circuit across the entire input range, thereby reducing the impact of the reduced swing of the preamplifier circuit on the comparator response delay.

[0061] In some implementations, a transistor may include a first terminal, a second terminal, and a control terminal. In one implementation, the first terminal may be the source terminal of the transistor, the second terminal may be the drain terminal of the transistor, and the control terminal may be the gate terminal of the transistor.

[0062] In one implementation, the biasing module may include a tenth transistor and an eleventh transistor. The control terminal of the tenth transistor is connected to its second terminal, and its first terminal is connected to a power supply terminal. The control terminal of the eleventh transistor is connected to the control terminal of the tenth transistor, its first terminal is connected to a power supply terminal, and its second terminal is connected to the first terminal of the first transistor.

[0063] The tenth and eleventh transistors in the bias module can form a current mirror structure. The tenth and eleventh transistors share a common gate, which can enable the tenth and eleventh transistors to have the same or equal current.

[0064] Based on the bias current provided by the bias module to the amplification module, the common-mode feedback module generates a common-mode control voltage. Under the control of the common-mode control voltage, the amplification module and the load module work together to amplify the first input signal and the second input signal, thereby enhancing the output swing of the preamplifier circuit.

[0065] In one implementation, the common-mode feedback module may include a ninth transistor, the control terminal of which is connected to the control terminal of a sixth transistor. A first terminal of the ninth transistor is connected to ground, and a second terminal of the ninth transistor is connected to the feedback terminal. In another implementation, the common-mode feedback module may further include a first resistor and a second resistor. The first terminal of the first resistor is connected to the second terminal of a fifth transistor, and the second terminal of the first resistor is connected to the control terminal of the fifth transistor. The first terminal of the second resistor is connected to the second terminal of the first resistor, and the second terminal of the second resistor is connected to the second terminal of a seventh transistor.

[0066] Based on the first and second output voltages, a common-mode control voltage is generated. On this basis, the common-mode feedback module can control the DC operating point based on the tenth transistor, the first resistor, and the second resistor, thereby achieving a stable DC operating point and maximizing the dynamic output range.

[0067] In one implementation, the first input pair may include a first transistor and a second transistor. The control terminal of the first transistor is connected to the first input terminal, the first terminal of the first transistor is connected to the bias module, and the second terminal of the first transistor is connected to the first load unit; the control terminal of the second transistor is connected to the first input terminal, the first terminal of the second transistor is connected to the feedback terminal, and the second terminal of the second transistor is connected to the first load unit; the common-mode feedback module is also used to control the static DC operating point of the first transistor and the second transistor.

[0068] In one implementation, the second input pair may include a third transistor and a fourth transistor. The control terminal of the third transistor is connected to the second input terminal, the first terminal of the third transistor is connected to the bias module, and the second terminal of the third transistor is connected to the second load unit; the control terminal of the fourth transistor is connected to the second input terminal, the first terminal of the fourth transistor is connected to the feedback terminal, and the second terminal of the fourth transistor is connected to the second load unit; the common-mode feedback module is also used to control the static DC operating point of the third and fourth transistors.

[0069] The control terminal of the first transistor is electrically connected to the first input terminal, the control terminal of the second transistor is electrically connected to the first input terminal, the control terminal of the third transistor is electrically connected to the second input terminal, and the control terminal of the fourth transistor is electrically connected to the second input terminal, thereby enabling the differential input signals, the first input signal and the second input signal, to be input to the amplification module.

[0070] The first terminal of the first transistor and the first terminal of the third transistor are electrically connected to the bias module, allowing the input transistor pair to receive the bias current provided by the bias module. The first terminal of the second transistor and the first terminal of the fourth transistor are electrically connected to the feedback terminal. By adjusting the voltage at the feedback terminal through a common-mode control voltage, the first, second, third, and fourth transistors all operate in the saturation region, thereby amplifying the differential input signal and obtaining the differential output signal.

[0071] The static DC operating point of a transistor can characterize the set of operating parameters of a transistor under DC bias when it is subjected to an input signal.

[0072] The common-mode feedback module adjusts the voltage at the feedback terminal based on the common-mode control voltage generated by the first and second output voltages to control the static direct operating point of the first and second transistors, thereby achieving a stable output DC operating point and maximizing the dynamic output range.

[0073] By using the first and second transistors in the first input pair and the third and fourth transistors in the second input pair, the feedback voltage can be adjusted based on the common-mode control voltage to amplify the first and second input signals when at least one of the first or second input transistors is operating in the saturation or subthreshold region. This amplifies the first and second input signals, thereby outputting a first and a second output signal. The differential-mode output voltage of the first and second output signals is greater than or equal to the differential-mode input voltage of the first and second input signals, thereby enhancing the output swing of the preamplifier circuit.

[0074] In one implementation, the first load unit may include a fifth transistor and a sixth transistor. The control terminal of the fifth transistor is connected to the common-mode feedback module, the first terminal of the fifth transistor is connected to the second load unit, and the second terminal of the fifth transistor is connected to the second terminal of the second transistor; the control terminal of the sixth transistor is connected to the common-mode feedback module, the first terminal of the sixth transistor is connected to the ground terminal, and the second terminal of the sixth transistor is connected to the second terminal of the first transistor.

[0075] In one implementation, the second load unit may include a seventh transistor and an eighth transistor. The control terminal of the seventh transistor is connected to the common-mode feedback module, the first terminal of the seventh transistor is connected to the first terminal of the fifth transistor, and the second terminal of the seventh transistor is connected to the second terminal of the fourth transistor; the control terminal of the eighth transistor is connected to the common-mode feedback module, the first terminal of the seventh transistor is connected to the first terminal of the sixth transistor, and the second terminal of the seventh transistor is connected to the second terminal of the third transistor.

[0076] The control terminals of the fifth, sixth, seventh, and eighth transistors are electrically connected to the common-mode feedback module. The first terminal of the fifth transistor is electrically connected to the second load unit; that is, the first terminal of the fifth transistor is electrically connected to the first terminal of the seventh transistor, and both the first terminals of the fifth and seventh transistors are electrically connected to the power supply terminal. The first terminal of the sixth transistor is electrically connected to the first terminal of the eighth transistor and is also electrically connected to the ground terminal. Based on the above connection relationships between the first and second load units, under the control of the common-mode control voltage, and based on the bias current and the voltage at the feedback terminal, the amplification module and the load module can amplify the first and second input signals across the entire input range.

[0077] Through the first load unit and the second load unit, under the control of the common-mode control voltage, based on the bias current and the voltage at the feedback terminal, and with any one of the input transistors in the first or second input pair operating in the cutoff region, the first and second input signals can be amplified, and the first and second output signals can be output. This ensures that the gain of the preamplifier circuit is always greater than 0dB across the entire input range, and consequently, that the differential output voltage of the preamplifier circuit is greater than the differential input voltage.

[0078] Figure 4 The illustration schematically shows a preamplifier circuit applied to a comparator according to yet another embodiment of the present disclosure.

[0079] like Figure 4 As shown, the preamplifier circuit 400 applied to the comparator in this embodiment has a first input terminal that can be a negative input terminal VIN, a second input terminal that can be a positive input terminal VIP, a first input pair of transistors including a first transistor M1 and a second transistor M2, a second input pair of transistors including a third transistor M3 and a fourth transistor M4, a first load unit including a fifth transistor M5 and a sixth transistor M6, a second load unit including a seventh transistor M7 and an eighth transistor M8, a common-mode feedback module including a ninth transistor M9, a first resistor R1 and a second resistor R2, and a bias module including a tenth transistor M10 and an eleventh transistor M11. The first terminals of the tenth transistor M10 and the eleventh transistor M11 are both electrically connected to the power supply terminal. The tenth transistor is electrically connected to the current source. The control terminals of the fifth transistor M5 and the seventh transistor M7 are electrically connected, and the first terminals of the fifth transistor M5 and the seventh transistor M7 are electrically connected to the power supply terminal.

[0080] The gate-source voltage is represented by Vgs, the overdrive voltage by Vdsat, the positive supply voltage by VDD, the negative supply voltage by VSS, and the sum of the first input voltage VIN and the second input voltage VIP is always equal to the positive supply voltage VDD.

[0081] In one implementation, taking the first input signal input to the first input terminal as an example, when the voltage VIN at the first input terminal is greater than or equal to the sum of the gate-source voltage and the overdrive voltage, and less than or equal to the difference between the positive power supply voltage and the gate-source voltage and the overdrive voltage, that is, when Vgs+Vdsat≤VIN≤VDD-Vgs-Vdsat, the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 all operate in the saturation region. At this time, the equivalent transconductance satisfies the following formula (1), the output impedance satisfies the following formula (2), and therefore, the gain satisfies the following formula (3).

[0082] (1)

[0083] (2)

[0084] (3)

[0085] Where gm1 represents the equivalent transconductance of the circuit under the condition Vgs+Vdsat≤VIN≤VDD-Vgs-Vdsat, gm1 represents the transconductance of the first transistor, gm2 represents the transconductance of the second transistor, Ro1 represents the output impedance of the circuit under the condition Vgs+Vdsat≤VIN≤VDD-Vgs-Vdsat, ro1 represents the output impedance of the first transistor, ro2 represents the output impedance of the second transistor, ro5 represents the output impedance of the fifth transistor, ro6 represents the output impedance of the sixth transistor, R1 represents the resistance value of the first resistor, / / indicates parallel connection, and G1 represents the gain of the circuit under the condition Vgs+Vdsat≤VIN≤VDD-Vgs-Vdsat.

[0086] When the voltage VIN at the first input terminal is greater than or equal to the negative power supply voltage and less than the sum of the gate-source voltage and the overdrive voltage, that is, VSS≤VIN<Vgs+Vdsat, the first transistor M1 operates in the saturation region as an amplifying transistor, the second transistor M2 will enter the subthreshold region or even the cutoff region, and the sixth transistor M6 and the seventh transistor M7 provide current paths as main load transistors. In the extreme case, that is, when VIN=VSS, the output impedance satisfies the following formula (4), and the gain satisfies the following formula (5).

[0087] (4)

[0088] (5)

[0089] Where Ro2 represents the output impedance of the circuit when VIN=VSS, and G2 represents the gain of the circuit when VIP=VSS.

[0090] When the voltage at the first input terminal is less than or equal to the positive power supply voltage and greater than the difference between the positive power supply voltage, the gate-source voltage, and the overdrive voltage, that is, when VDD - Vgs - Vdsat < VIN ≤ VDD, the second transistor M2 operates in the saturation region as an amplifying transistor, the first transistor M1 will enter the subthreshold region or even the cutoff region, and the fifth transistor M5 and the eighth transistor M8 provide current paths as main load transistors. In the extreme case, that is, when VIN = VDD, the output impedance satisfies the following formula (6), and the gain satisfies the following formula (7).

[0091] (6)

[0092] (7)

[0093] Where Ro3 represents the output impedance of the circuit when VIP=VDD, and G3 represents the gain of the circuit when VIP=VDD.

[0094] In one implementation, taking the second input signal input to the second input terminal as an example, when the voltage VIP at the second input terminal is greater than or equal to the sum of the gate-source voltage and the overdrive voltage, and less than the difference between the positive power supply voltage, the gate-source voltage, and the overdrive voltage, that is, Vgs+Vdsat≤VIP≤VDD-Vgs-Vdsat, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 all operate in the saturation region. At this time, the equivalent transconductance satisfies the following formula (8), the output impedance satisfies the following formula (9), and therefore, the gain satisfies the following formula (10).

[0095] (8)

[0096] (9)

[0097] (10)

[0098] Where gm2 represents the equivalent transconductance of the circuit when Vgs+Vdsat≤VIP≤VDD-Vgs-Vdsat, gm1 represents the transconductance of the first transistor, gm2 represents the transconductance of the second transistor, gm3 represents the transconductance of the third transistor, Ro4 represents the output impedance of the circuit when Vgs+Vdsat≤VIP≤VDD-Vgs-Vdsat, ro1 represents the output impedance of the first transistor, ro2 represents the output impedance of the second transistor, ro5 represents the output impedance of the fifth transistor, ro6 represents the output impedance of the sixth transistor, R1 represents the resistance value of the first resistor, / / indicates parallel connection, and G4 represents the gain of the circuit when Vgs+Vdsat≤VIP≤VDD-Vgs-Vdsat.

[0099] When the voltage VIP at the second input terminal is greater than or equal to the negative power supply voltage and less than the sum of the gate-source voltage and the overdrive voltage, that is, VSS≤VIP<Vgs+Vdsat, the third transistor M3 operates in the saturation region as an amplifying transistor, the fourth transistor will enter the subthreshold region or even the cutoff region, and the eighth transistor M8 provides the current path as the main load transistor. In the extreme case, that is, when VIP=VSS, the output impedance satisfies the following formula (11), and the gain satisfies the following formula (12).

[0100] (11)

[0101] (12)

[0102] Where Ro5 represents the output impedance of the circuit when VIP=VSS, Ro3 represents the output impedance of the third transistor, Ro7 represents the output impedance of the seventh transistor, Ro8 represents the output impedance of the eighth transistor, R2 represents the resistance value of the second resistor, and G5 represents the gain of the circuit when VIP=VSS.

[0103] When the voltage at the second input terminal is less than or equal to the positive power supply voltage and greater than the difference between the positive power supply voltage, the gate-source voltage, and the overdrive voltage, that is, when VDD - Vgs - Vdsat < VIP ≤ VDD, the fourth transistor M4 operates in the saturation region as an amplifying transistor, the third transistor M3 will enter the subthreshold region or even the cutoff region, and the seventh transistor M7 provides the current path as the main load transistor. In the extreme case, that is, when VIP = VDD, the output impedance satisfies the following formula (13), and the gain satisfies the following formula (14).

[0104] (13)

[0105] (14)

[0106] Where Ro6 represents the output impedance of the circuit when VIP=VDD, ro4 represents the output impedance of the fourth transistor, G6 represents the gain of the circuit when VIP=VDD, and gm4 represents the transconductance of the fourth transistor.

[0107] Figure 5A The diagram illustrates a gain simulation of a preamplifier circuit for a comparator applied to a 40nm process according to an embodiment of the present disclosure. Figure 5B The diagram illustrates a transient simulation of a preamplifier circuit for a comparator applied to a 40nm process according to another embodiment of the present disclosure.

[0108] like Figure 5AAs shown, the red curve below represents the data based on the above. Figure 1 The diagram shown is a simulation illustration of the gain of the preamplifier circuit 100 applied to the comparator. The yellow curve at the top represents the gain based on the above... Figure 4 The diagram shown illustrates the gain simulation of the preamplifier circuit 400 used in the comparator. Figure 5B As shown, the first yellow-green line from the top on the far left represents the line based on the above. Figure 1 The input signal (VIPP) of the preamplifier circuit 100 applied to the comparator shown is represented by the second purple line from the top on the left, indicating the signal based on the above. Figure 1 The input signal (VINN) of the preamplifier circuit 100 applied to the comparator shown is represented by the third blue line from the top on the left, indicating the signal based on the above. Figure 4 The output signal (OP1) of the preamplifier circuit 400 used in the comparator shown is represented by the fourth magenta line from the top on the left, indicating the signal based on the above. Figure 4 The output signal (ON1) of the preamplifier circuit 400 used in the comparator shown is represented by the fifth green line from the top on the left, indicating the signal based on the above. Figure 1 The output signal (ON2) of the preamplifier circuit 100 used in the comparator shown is represented by the sixth orange-yellow line from the top on the left, indicating the signal based on the above. Figure 1 The output signal (OP2) of the preamplifier circuit 100 used in the comparator shown is represented by the seventh yellow line from the top on the far left, indicating the signal based on the above. Figure 4 The differential output voltage (delta_vout) of the preamplifier circuit 400 used in the comparator is shown. The eighth emerald green line from the top on the far left represents the voltage based on the above. Figure 1 and Figure 4 The differential input voltage (delta_vin) of the preamplifier circuit used in the comparator is shown. The ninth blue line from the top on the left represents the voltage based on the above. Figure 1 The differential output voltage (delta_vout_REF) of the preamplifier circuit 100 applied to the comparator is shown.

[0109] Based on the above Figure 5A and Figure 5B It can be seen that, based on the above Figure 1 The gain curve of the preamplifier circuit 100 applied to the comparator shown has a gain of less than 0dB in both the (0~152mV) and (865mV~1.1V) input ranges, meaning the output differential voltage (OP2-OP1) is less than the input differential voltage (VIPP-VINN). Figure 4The gain curve of the preamplifier circuit 400 applied to the comparator shown shows that the gain is always greater than 0dB across the entire input range (0~1.1V), meaning that the output differential voltage always has an amplifying effect relative to the input differential voltage, which is beneficial to the comparator's response speed.

[0110] Based on the aforementioned preamplifier circuit used in the comparator, this disclosure also provides a signal amplification method, which will be discussed below in conjunction with... Figure 6 The method is described in detail.

[0111] Figure 6 A flowchart illustrating a signal amplification method based on a preamplifier circuit according to an embodiment of the present disclosure is shown schematically.

[0112] like Figure 6 As shown, the signal amplification method 600 based on the preamplifier circuit in this embodiment includes operations S610 to S630.

[0113] In operation of S610, a common-mode control voltage is generated based on the voltage at the first output terminal and the voltage at the second output terminal.

[0114] By operating S620, the common-mode control voltage is adjusted to obtain the target common-mode control voltage.

[0115] In operation S630, under the control of the target common-mode control voltage, the current flowing through the current path between the power supply terminal and the ground terminal is controlled based on the bias current and the voltage of the feedback terminal. The differential input voltage between the first input signal at the first input terminal and the second input signal at the second input terminal is amplified based on the current and the amplification module. The first output signal and the second output signal are output through the first output terminal and the second output terminal, respectively. The differential output voltage between the first output signal and the second output signal is greater than the differential input voltage.

[0116] The bias current can be generated by the bias module, thereby providing bias current to the amplification module.

[0117] A common-mode control voltage can be generated based on the voltages at the first and second output terminals. The target common-mode control voltage can be obtained by adjusting the common-mode control voltage using the power supply voltage, the first input signal, the second input signal, and the bias current.

[0118] Under the control of the target common-mode control voltage, the current flowing through the current path between the power supply terminal and the ground terminal is controlled based on the bias current and the voltage at the feedback terminal. The differential input voltage between the first input signal at the first input terminal and the second input signal at the second input terminal is amplified by the current and the amplification module. The first output signal and the second output signal are output through the first output terminal and the second output terminal, respectively. The differential output voltage between the first output signal and the second output signal is greater than the differential input voltage.

[0119] Based on the above Figure 4 The preamplifier circuit shown, when the voltage at the first input terminal is too high (e.g., when the voltage at the first input terminal is VDD), the PMOS transistor in the first input pair, i.e., the first transistor, is in the cutoff region, and the NMOS transistor in the second input pair, i.e., the fourth transistor, is in the cutoff region. The main current path is formed by the second, third, fifth, and eighth transistors. When the voltage at the first input terminal is too low (e.g., when the voltage at the first input terminal is VSS), the NMOS transistor in the first input pair, i.e., the second transistor, is in the cutoff region, and the PMOS transistor in the second input pair, i.e., the third transistor, is in the cutoff region. The main current path is formed by the first, fourth, sixth, and seventh transistors. The situation regarding the voltage at the second input terminal being too high or too low is similar to that at the first input terminal and will not be described further here. When the voltage at the first or second input terminal is too high or too low, the voltage at the feedback terminal can be adjusted by the common-mode control voltage, which can achieve amplification across the entire input range. That is, across the entire input range, the differential output voltage between the first and second output signals is greater than the differential input voltage between the first and second input signals. In other words, the gain of the preamplifier circuit is always greater than 0dB, which can effectively enhance the swing of the preamplifier circuit across the entire input range, thereby reducing the impact of the reduced swing of the preamplifier circuit on the comparator response delay.

[0120] Based on the aforementioned preamplifier circuit 400 applied to the comparator, this disclosure also provides a comparator.

[0121] Figure 7 A schematic diagram of a comparator according to an embodiment of the present disclosure is shown.

[0122] like Figure 7 As shown, the comparator 700 in this embodiment includes a preamplifier circuit 400 applied to the comparator.

[0123] Since the aforementioned preamplifier circuit 400 applied to the comparator can achieve a gain greater than 0dB throughout the entire input range, it can effectively enhance the swing of the preamplifier circuit throughout the entire input range, thereby reducing the impact of the reduced swing of the preamplifier circuit on the comparator response delay and improving the speed of the comparator.

[0124] Based on the comparator described above, this disclosure also provides a digital-to-analog converter.

[0125] Figure 8 A schematic diagram of a digital-to-analog converter according to an embodiment of the present disclosure is shown.

[0126] like Figure 8 As shown, the digital-to-analog converter 800 of this embodiment includes a comparator 700.

[0127] Since the aforementioned preamplifier circuit 400 applied to the comparator can achieve a gain greater than 0dB throughout the entire input range, it can effectively enhance the swing of the preamplifier circuit throughout the entire input range. This reduces the impact of the reduced swing of the preamplifier circuit on the comparator response delay, greatly shortens the comparison cycle, and thus improves the sampling speed and quantization accuracy of the analog-to-digital converter.

[0128] Figure 9A A schematic diagram of a comparator applied to a 40nm process according to an embodiment of the present disclosure is shown. Figure 9B A schematic diagram of a comparator applied to a 40nm process according to another embodiment of the present disclosure is shown. Figure 10A The illustration schematically shows an equivalent mismatch simulation diagram of a comparator applied to a 40nm process according to an embodiment of the present disclosure. Figure 10B The illustration schematically shows an equivalent mismatch simulation diagram of a comparator applied to a 40nm process according to another embodiment of the present disclosure.

[0129] like Figure 9A and Figure 9B As shown, Figure 9A For comparator CMP without preamplifier circuitry, Figure 9B This refers to the comparator CMP, which includes the aforementioned preamplifier circuit 400 (OP) used in the comparator.

[0130] like Figure 10A and Figure 10B As shown, Figure 10A This is a simulation diagram of the equivalent mismatch of a comparator excluding the preamplifier circuit. Figure 10B This diagram illustrates the equivalent mismatch simulation of the comparator, including the preamplifier circuit 400 used in the comparator described above. (Example:) Figure 10A and 10BAs shown, the simulated mismatch of the comparator CMP without the preamplifier circuit is μ=5.87mV and σ=34.91mV. The simulated mismatch of the comparator including the preamplifier circuit 400 applied to the comparator is μ=1.35mV and σ=5.66mV. It can be seen from the above that the comparator including the preamplifier circuit 400 applied to the comparator can achieve KT / C noise cancellation and mismatch compensation, effectively reducing the mismatch by 84%.

[0131] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0132] Those skilled in the art will understand that the features described in the various embodiments of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0133] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A preamplifier circuit for use in a comparator, characterized in that, include: The bias module is connected to the power supply and current source and is used to generate bias current. A common-mode feedback module is connected to a first output terminal, a second output terminal, and a feedback terminal, and is used to generate a common-mode control voltage based on the voltage of the first output terminal and the voltage of the second output terminal. An amplification module is connected to the bias module, the common-mode feedback module, the first input terminal, the second input terminal, the first output terminal, and the second output terminal; A load module, connected to the power supply terminal, the ground terminal, the amplification module, the first output terminal, and the second output terminal, is used to control the current flowing through the current path between the power supply terminal and the ground terminal based on the bias current and the voltage of the feedback terminal under the control of the common-mode control voltage. This control, together with the amplification module, amplifies the differential input voltage between the first input signal at the first input terminal and the second input signal at the second input terminal. The load module then outputs a first output signal and a second output signal through the first output terminal and the second output terminal, respectively. The differential output voltage between the first output signal and the second output signal is greater than the differential input voltage.

2. The preamplifier circuit according to claim 1, wherein the amplification module includes a first set of input transistors and a second set of input transistors connected together; the load module includes a first load unit and a second load unit connected together; the first set of input transistors is also connected to the first load unit, and the second set of input transistors is also connected to the second load unit; in, When any one of the input transistors in the first set of input pairs is operating in the cutoff region, the first load unit provides a current path as a load to obtain the first output signal. When any one of the input transistors in the second set of input pairs is operating in the cutoff region, the second load unit provides a current path as a load to obtain the second output signal.

3. The preamplifier circuit according to claim 2, wherein the first set of input transistors comprises: The first transistor has a control terminal connected to the first input terminal, a first terminal connected to the bias module, and a second terminal connected to the first load unit. The second transistor has a control terminal connected to the first input terminal, a first terminal connected to the feedback terminal, and a second terminal connected to the first load unit. The common-mode feedback module is also used to control the static DC operating point of the first transistor and the second transistor.

4. The preamplifier circuit according to claim 2, wherein the second set of input transistors comprises: The third transistor has its control terminal connected to the second input terminal, its first terminal connected to the bias module, and its second terminal connected to the second load unit. The fourth transistor has its control terminal connected to the second input terminal, its first terminal connected to the feedback terminal, and its second terminal connected to the second load unit. The common-mode feedback module is also used to control the static DC operating point of the third transistor and the fourth transistor.

5. The preamplifier circuit according to claim 3, wherein the first load unit comprises: The fifth transistor has its control terminal connected to the common-mode feedback module, its first terminal connected to the second load unit, and its second terminal connected to the second terminal of the second transistor. The sixth transistor has its control terminal connected to the common-mode feedback module, its first terminal connected to the ground terminal, and its second terminal connected to the second terminal of the first transistor.

6. The preamplifier circuit according to claim 4, wherein the second load unit comprises: The seventh transistor has its control terminal connected to the common-mode feedback module, its first terminal connected to the first terminal of the fifth transistor, and its second terminal connected to the second terminal of the fourth transistor. The eighth transistor has its control terminal connected to the common-mode feedback module, its first terminal connected to the first terminal of the sixth transistor, and its second terminal connected to the second terminal of the third transistor.

7. The preamplifier circuit according to claim 5, wherein the common-mode feedback module comprises: The ninth transistor has its control terminal connected to the control terminal of the sixth transistor, its first terminal connected to the ground terminal, and its second terminal connected to the feedback terminal.

8. The preamplifier circuit according to claim 5, wherein the common-mode feedback module further comprises: A first resistor, with its first end connected to the second end of the fifth transistor and its second end connected to the control terminal of the fifth transistor; The second resistor has its first end connected to the second end of the first resistor, and its second end connected to the second end of the seventh transistor.

9. The preamplifier circuit according to claim 3, wherein the bias module comprises: The tenth transistor has a control terminal connected to its second terminal and a first terminal connected to the power supply terminal. The eleventh transistor has a control terminal connected to the control terminal of the tenth transistor, a first terminal connected to the power supply terminal, and a second terminal connected to the first terminal of the first transistor.

10. A signal amplification method based on the preamplifier circuit as described in any one of claims 1 to 9, characterized in that, include: A common-mode control voltage is generated based on the voltage at the first output terminal and the voltage at the second output terminal. The common-mode control voltage is adjusted to obtain the target common-mode control voltage; Under the control of the target common-mode control voltage, based on the bias current and the voltage at the feedback terminal, the current flowing through the current path between the power supply terminal and the ground terminal is controlled, so that the differential input voltage between the first input signal at the first input terminal and the second input signal at the second input terminal is amplified based on the current and the amplification module, and the first output signal and the second output signal are output through the first output terminal and the second output terminal respectively, wherein the differential output voltage between the first output signal and the second output signal is greater than the differential input voltage.

Images