Pulse generation method, system, converter and medium with adjustable time length

Abstract

The application relates to a pulse generation method, system, converter and medium with adjustable time length. The method comprises the following steps: in a rising edge generation stage, a rising edge increment is determined according to a target rising edge time length, a pulse amplitude maximum value and a predetermined scaling factor, and DAC output data is updated to generate a pulse rising edge according to the rising edge increment; then, a high amplitude stable stage is entered to keep the output; in a falling edge generation stage, a falling edge decrement is determined according to a target falling edge time length, the pulse amplitude maximum value and the scaling factor, and DAC output data is updated to generate a pulse falling edge according to the falling edge decrement. By using the method, the rising edge time and the falling edge time of the pulse can be independently controlled flexibly and accurately through software or hardware parameters, a high-quality pulse signal with a smooth and adjustable edge can be generated, and the defect that the edge time is fixed in a traditional lookup table method is overcome.

Description

Technical Field

[0001] This application relates to the fields of digital signal processing and field-programmable gate array (FPGA) technology, and in particular to a method, system, converter, and medium for generating pulses with adjustable edge timing and adjustable duration in an FPGA. Background Technology

[0002] In the field of digital signal synthesis and waveform generation, digital-to-analog converters (DACs) combined with lookup tables are commonly used to generate basic waveforms such as sine waves, square waves, and triangle waves. However, when generating pulse signals, the rise and fall times are usually fixed, determined by the DAC's update frequency and the lookup table step size, making it difficult to flexibly adjust the edge times. This limits the application of pulse signals in scenarios such as precision control, communication modulation, and test and measurement.

[0003] Therefore, a pulse generation method that can flexibly adjust the pulse edge time and adapt to different application requirements is needed. Summary of the Invention

[0004] Therefore, it is necessary to provide a pulse generation method, system, converter, and medium with adjustable pulse rise and fall times that can flexibly adjust the pulse rise and fall times to address the above-mentioned technical problems.

[0005] A pulse generation method with adjustable duration, the method comprising:

[0006] During the rising edge generation stage, the rising edge increment is determined based on the target rising edge duration, the maximum pulse amplitude, and a predetermined scaling factor, and the DAC output data is updated according to the rising edge increment to generate a pulse rising edge.

[0007] After the rising edge generation stage ends, the pulse high amplitude stabilization stage begins, maintaining the DAC output data at the maximum value corresponding to the pulse amplitude.

[0008] During the falling edge generation stage, the falling edge decrement is determined based on the target falling edge duration, the maximum pulse amplitude, and the scaling factor, and the DAC output data is updated based on the falling edge decrement to generate a pulse falling edge.

[0009] Wherein, the scaling factor is used to... The output data is converted to a high-precision computing domain for processing.

[0010] In one embodiment, the rising edge increment is:

[0011] ;

[0012] in, The increment value for the rising edge. The maximum value of the pulse amplitude corresponds to Data value, For a predefined scaling factor, The rising edge time of the target is [length]. This refers to the data update cycle.

[0013] In one embodiment, the update is performed incrementally based on the rising edge. The output data includes:

[0014] Will the current Output data amplification Multiply by 1 to obtain the first intermediate data;

[0015] The first intermediate data and the rising edge increment Accumulate the data to obtain the second intermediate data;

[0016] Reduce the second intermediate data Times, as the updated Output data.

[0017] In one embodiment, the high-amplitude stabilization phase of the pulse includes:

[0018] Counting is performed according to the clock's beat;

[0019] When the count value reaches the preset HIGH_COUNT value, the high-amplitude pulse stabilization phase ends.

[0020] HIGH_COUNT represents the number of DAC data update cycles required for the high amplitude of the pulse.

[0021] In one embodiment, the falling edge decrement is:

[0022] ;

[0023] in, The decrease in the falling edge, This is the data value corresponding to the maximum pulse amplitude. For a predefined scaling factor, The target's fall edge time length, This refers to the data update cycle.

[0024] In one embodiment, updates are made based on the falling edge decrement. The output data includes:

[0025] Will the current Output data amplification Double the result to obtain the third intermediate data;

[0026] Combine the third intermediate data with the falling edge decrement. Subtracting the two values ​​yields the fourth intermediate data.

[0027] Reduce the size of the fourth intermediate data Times, as the updated Output data.

[0028] In one embodiment, it further includes:

[0029] The rising edge generation stage, the high-amplitude pulse stabilization stage, and the falling edge generation stage are repeatedly executed to generate a repeating pulse sequence.

[0030] A pulse generation system with adjustable duration, the system comprising:

[0031] The rising edge generation module is configured to perform the rising edge generation stage and the pulse high amplitude stabilization stage in the above method;

[0032] The falling edge generation module is configured to perform the falling edge generation phase in the above method.

[0033] A converter, comprising:

[0034] A digital-to-analog converter; and a controller, configured to provide data codes to the digital-to-analog converter by performing the above-described time-adjustable pulse generation method, such that the digital-to-analog converter outputs a pulse signal with adjustable edge time.

[0035] A computer-readable storage medium having a computer program stored thereon, the computer program performing the following steps when executed by a processor:

[0036] During the rising edge generation stage, the rising edge increment is determined based on the target rising edge duration, the maximum pulse amplitude, and a predetermined scaling factor, and the DAC output data is updated according to the rising edge increment to generate a pulse rising edge.

[0037] After the rising edge generation stage ends, the pulse high amplitude stabilization stage begins, maintaining the DAC output data at the maximum value corresponding to the pulse amplitude.

[0038] During the falling edge generation stage, the falling edge decrement is determined based on the target falling edge duration, the maximum pulse amplitude, and the scaling factor, and the DAC output data is updated based on the falling edge decrement to generate a pulse falling edge.

[0039] Wherein, the scaling factor is used to... The output data is converted to a high-precision computing domain for processing.

[0040] This application provides a pulse generation method with adjustable pulse length. By introducing a high-precision computation mechanism and a configurable edge control strategy, it achieves flexible and precise adjustment of the rising and falling edge times of the pulse signal. Specifically, in the rising edge generation stage, by calculating and gradually accumulating increments, the DAC output data smoothly increases from the initial value to the target amplitude, effectively avoiding the shortcomings of fixed edge time and obvious step changes in traditional lookup table methods, and achieving adjustable edge slope and smooth transition. In the high-amplitude stabilization stage of the pulse, the high-level duration is controlled by clock counting to ensure precise control of the pulse width and enhance the time consistency of the waveform. In the falling edge generation stage, a decreasing mechanism symmetrical to the rising edge is adopted to gradually reduce the output amplitude, ensuring the independent configurability of the falling and rising edges and meeting the generation requirements of asymmetric pulses. By cyclically executing the above three stages, this method supports the generation of continuously adjustable pulse sequences, and each edge time parameter can be configured in real time without redesigning hardware or updating the lookup table. Throughout the process, the calculation is extended to a high-precision domain by using a scaling factor, effectively avoiding edge distortion caused by data rounding and improving the overall quality and reliability of the pulse signal. In summary, this method significantly improves the flexibility and accuracy of pulse generation while maintaining a simple hardware structure. It can be widely used in fields such as communication modulation, precision testing, medical instruments, and industrial control, and has good practical value and promising prospects for promotion. Attached Figure Description

[0041] Figure 1 This is an application scenario diagram of a pulse generation method with adjustable time length in one embodiment;

[0042] Figure 2 This is a flowchart illustrating a pulse generation method with adjustable duration in one embodiment;

[0043] Figure 3 This is a block diagram of a pulse generator in one embodiment;

[0044] Figure 4 This is a flowchart illustrating a pulse generation method with adjustable time length in another embodiment;

[0045] Figure 5 This is a block diagram of a pulse generation system with adjustable time length in one embodiment. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0047] The pulse generation method with adjustable duration provided in this application can be applied to, for example... Figure 1 In the application environment shown, the FPGA controller 102 is connected to the digital-to-analog converter (DAC) 104 via a data bus. The FPGA controller 102 is responsible for executing the time-adjustable pulse generation algorithm described in this invention, generating a digital code stream and sending it to the DAC 104. Upon receiving the digital code stream, the DAC 104 converts it into an analog voltage waveform output, ultimately generating a pulse signal with adjustable edge time. This signal can be used to drive subsequent circuits or as a test stimulus signal. The FPGA controller 102 can be implemented based on various field-programmable gate array (FPGA) chips, and the DAC 104 can be a high-speed DAC with various resolutions (e.g., 16-bit) and update rates.

[0048] In one embodiment, such as Figure 2 As shown, a pulse generation method with adjustable time length is provided, which can be applied to... Figure 1 Taking the FPGA controller as an example, the following steps are included:

[0049] Step 202: In the rising edge generation stage, determine the rising edge increment based on the target rising edge duration, the maximum pulse amplitude, and the predetermined scaling factor, and update the pulse based on the rising edge increment. Output data to generate a pulse rising edge.

[0050] Specifically, the system determines the target's rise time based on the target's rise time. The maximum value of the pulse amplitude corresponds to Data value and the predetermined scaling factor Determine a rising edge increment Subsequently, in each Data update cycle Within, update the output according to this incremental change. The data code makes The output analog voltage starts from an initial value and gradually and smoothly increases to the target amplitude, thus generating a rising edge with a controllable duration. The core of this process lies in calculating and controlling the data increment for each clock cycle, replacing the traditional fixed lookup table method, and achieving flexible adjustment of the rising edge time.

[0051] Step 204: After the rising edge generation phase ends, the pulse enters the high-amplitude stabilization phase and remains stable. The output data is the data corresponding to the maximum value of the pulse amplitude.

[0052] Specifically, when the rising edge generation phase ends, that is, when the output data reaches... Afterwards, the system enters a stable phase with high pulse amplitude. During this phase, The output data will remain as If the value remains unchanged, the corresponding analog output will be the high-level plateau of the pulse. The duration of this phase is controlled by a preset counting period HIGH_COUNT, i.e., it lasts for HIGH_COUNT DAC data update cycles. Precise control of the width of this segment can be achieved using a simple counter.

[0053] Step 206: In the falling edge generation stage, the falling edge decrement is determined based on the target falling edge duration, the maximum pulse amplitude, and the scaling factor. The DAC output data is then updated according to the falling edge decrement to generate the pulse falling edge. The scaling factor is used to... The output data is converted to a high-precision computing domain for processing.

[0054] Specifically, after the high-amplitude stabilization phase ends, the system enters the falling edge generation phase. This phase is similar in principle to the rising edge generation phase but the process is reversed. The system determines the falling edge generation time based on the target falling edge duration. , And with the same scaling factor G, determine a falling edge decrement. In each During the period, the output is gradually reduced according to this decreasing amount until... The data code allows the analog voltage to smoothly drop from a high level to its initial value, forming a falling edge with a controllable time length.

[0055] The scaling factor G is a key preset parameter. Its main function is to amplify, for example, 16-bit DAC output data with limited precision, and transform it into a higher precision, such as 32-bit, operational domain through amplification, such as left shift operations. This mechanism effectively avoids errors caused by data rounding or truncation when calculating small increments. It is the foundation for ensuring that the edge time can be finely adjusted and extended, thus achieving a wide range and high precision pulse edge adjustment function that is difficult to achieve with traditional methods. The pulse generation method with adjustable time length generates a complete pulse with independently set edge time by sequentially executing the above three stages. To generate a continuous pulse sequence, this process is repeated.

[0056] This application provides a pulse generation method with adjustable pulse length. By introducing a high-precision computation mechanism and a configurable edge control strategy, it achieves flexible and precise adjustment of the rising and falling edge times of the pulse signal. Specifically, in the rising edge generation stage, by calculating and gradually accumulating increments, the DAC output data smoothly increases from the initial value to the target amplitude, effectively avoiding the shortcomings of fixed edge time and obvious step changes in traditional lookup table methods, and achieving adjustable edge slope and smooth transition. In the high-amplitude stabilization stage of the pulse, the high-level duration is controlled by clock counting to ensure precise control of the pulse width and enhance the time consistency of the waveform. In the falling edge generation stage, a decreasing mechanism symmetrical to the rising edge is adopted to gradually reduce the output amplitude, ensuring the independent configurability of the falling and rising edges and meeting the generation requirements of asymmetric pulses. By cyclically executing the above three stages, this method supports the generation of continuously adjustable pulse sequences, and each edge time parameter can be configured in real time without redesigning hardware or updating the lookup table. Throughout the process, the calculation is extended to a high-precision domain by using a scaling factor, effectively avoiding edge distortion caused by data rounding and improving the overall quality and reliability of the pulse signal. In summary, this method significantly improves the flexibility and accuracy of pulse generation while maintaining a simple hardware structure. It can be widely used in fields such as communication modulation, precision testing, medical instruments, and industrial control, and has good practical value and promising prospects for promotion.

[0057] In one embodiment, the rising edge increment is:

[0058] ;

[0059] in, The increment is the rising edge. The maximum value of the pulse amplitude Data value, For a predefined scaling factor, The target rise time. This refers to the data update cycle.

[0060] In practical implementation, the total data change that needs to be completed during the entire rising edge process will be... That is, the total span represented in the high-precision domain, evenly distributed across the rising edges. Number of data update cycles / This allows us to obtain the data step size that needs to be accumulated in the high-precision domain within each data update cycle, i.e. Using this formula, the system can adapt to different time requirements. The corresponding step size is dynamically calculated.

[0061] In one embodiment, the rising edge is incremented for updates. The output data includes the current Output data amplification The first intermediate data is obtained by multiplying the first intermediate data by the increment of the rising edge; the first intermediate data is then multiplied by the increment of the rising edge. Accumulate the data to obtain the second intermediate data; then reduce the size of the second intermediate data. Times, as the updated Output data.

[0062] In practical implementation, the currently output DAC data code is denoted as DAC_CODE. When G is a power of 2, this operation can be achieved through a simple left shift. Taking a 16-bit wide DAC output as an example, first set... Then, the value of DAC_CODE is amplified by 65536 times, that is, the value of DAC_CODE is shifted left by 16 bits to obtain a 32-bit wide DAC_CODE value, which is the first intermediate data. Then, the amplified DAC_CODE is incremented along with the rising edge. The data is directly accumulated to obtain the second intermediate data. Then, the high 16 bits of the accumulated DAC_CODE value (which is essentially amplified DAC_CODE value reduced by a factor of 65536, or right-shifted DAC_CODE value by 16 bits) are taken as the final code value DAC_CODE output to the DAC in this data update cycle. This operation maps the data from the high-precision arithmetic domain back to the actual DAC input domain.

[0063] The above process is repeated in the FPGA until the amplified DAC_CODE value is determined to be greater than or equal to... When the rising edge occurs, it indicates the end of the rising edge process. This method uses shifting instead of multiplication and division, greatly saving hardware logic resources.

[0064] In one embodiment, the high-amplitude stabilization phase of the pulse includes counting under clock ticks;

[0065] When the count value reaches the preset HIGH_COUNT value, the high-amplitude pulse stabilization phase ends; where HIGH_COUNT represents the number of DAC data update cycles required for the high-amplitude pulse.

[0066] In practical implementation, when DAC_CODE > DAC_AMP, the rising edge ends, and the system transitions to a high-amplitude stabilization phase. The main purpose of this phase is to maintain output stability and precisely control the duration. Simultaneously, the system starts a counter, which is activated at the rising edge of each DAC data update clock, i.e., every... The counter increments by one periodically. The initial value of this counter is typically zero. A preset threshold, HIGH_COUNT, represents the number of DAC data update cycles required for the high amplitude of the pulse.

[0067] During execution, the DAC output data remains constant at DAC_AMP. The system continuously compares the current value of the counter with HIGH_COUNT. When the counter value reaches the preset HIGH_COUNT value, it indicates that the high level has lasted for a sufficiently long time, i.e., the duration is HIGH_COUNT × ... At this point, the high-amplitude stable phase ends, the system state transitions, and it prepares to enter the falling edge generation phase. This pure counting method is simple to implement and provides precise and reliable time control.

[0068] In one embodiment, the falling edge decrement is:

[0069] ;

[0070] in, The amount of decrease on the falling edge. This is the DAC data value corresponding to the maximum pulse amplitude. For a predefined scaling factor, For the target falling edge time length, This refers to the data update cycle.

[0071] In practical implementation, the total data change that needs to be completed during the entire falling edge process will be... That is, the total span represented in the high-precision domain, evenly distributed across the falling edges. Number of data update cycles / This ensures that the signal continues on the falling edge. Within a given timeframe, the system can achieve high-precision computation in a uniform step size. In each The DAC output data is decreased during the cycle to achieve a smooth and controllable transition from high to low level.

[0072] In one embodiment, the falling edge decrement is updated. The output data includes the current Output data amplification The third intermediate data is obtained by multiplying the data by the factor of time; the third intermediate data is then compared with the decreasing amount at the falling edge. Subtract the two numbers to obtain the fourth intermediate data; then reduce the size of the fourth intermediate data. Times, as the updated Output data.

[0073] In practical implementation, the currently output DAC data code is denoted as DAC_CODE. When G is a power of 2, this operation can be achieved through a simple left shift. Taking a 16-bit wide DAC output as an example, first set... Then, the DAC_CODE value is amplified by 65536 times, that is, the DAC_CODE value is shifted left by 16 bits to obtain a 32-bit DAC_CODE value, which is the third intermediate data. Then, the amplified DAC_CODE is decremented along with the falling edge. The high 16 bits of the subtracted DAC_CODE value are then taken as the final code value output to the DAC in this data update cycle. The high 16 bits of the subtracted DAC_CODE value are then shifted 16 bits to the right (that is, the amplified DAC_CODE value is reduced by 65536 times).

[0074] Repeat the above steps until a judgment is made. When the pulse falls to its lowest point, the pulse ends. The pulse then enters the next stage, the low-amplitude stabilization stage. Assume the low-amplitude duration is LOW_COUNT pulses. Then, you only need to count during the clock tick. When the counter value is equal to the LOW_COUNT value, the low amplitude stabilization phase of the pulse ends.

[0075] like Figure 3 The diagram shows a block diagram of a pulse generator. The input device in the diagram converts the pulse amplitude to DAC_AMP and the rising edge increment. Falling edge increment The pulse high count value (HIGH_COUNT), pulse low count value (LOW_COUNT), pulse count (PULSE_COUNT), and pulse offset (OFFSET) are pre-calculated and sent to the parameter receiving and distributing module. The pulse state machine controls the output of the rising edge generation unit, pulse high generation unit, falling edge generation unit, and pulse low generation unit based on the received parameters. Simultaneously, the pulse state machine... Figure 3 Under the conditions shown, the START1 → START2 → START3 → START4 signals are issued sequentially in time, which respectively control the 4-to-1 multiplexer to output DAC_CODE to the digital-to-analog converter.

[0076] In one embodiment, the rising edge generation phase, the high-amplitude pulse stabilization phase, and the falling edge generation phase are repeatedly executed to generate a repeating pulse sequence.

[0077] In practical implementation, after a complete pulse generation is completed, which includes a rising edge, a high level, and a falling edge, by adding a loop control logic or state machine, the system can automatically reinitialize and start the rising edge phase of the next pulse after completing the falling edge phase of a pulse, thus realizing the generation of a continuous pulse sequence.

[0078] like Figure 4 As shown, by repeatedly executing the above process, a periodic pulse sequence can be generated. In this mode, the user can independently set the rise time of each pulse. The duration of the high level is controlled by HIGH_COUNT, and the falling edge time... The duration of the low level is controlled by LOW_COUNT and the interval between pulses. For example, this can be achieved by adding a low-level hold phase and similarly using a counter, thereby generating complex and varied pulse waveforms. Figure 4 In this configuration, HIGH_CNT represents the count register for the high-level plateau phase of the pulse, and LOW_CNT represents the count register for the low-level plateau phase. This provides extremely high waveform customization flexibility, enabling the generation of complex pulse trains with variable duty cycles and edge slopes to meet diverse application needs.

[0079] It should be understood that, although Figure 2 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 2 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.

[0080] In one embodiment, such as Figure 5 As shown, a pulse generation system with adjustable duration is provided, including: a rising edge generation module 502 and a falling edge generation module 504, wherein:

[0081] Rising edge generation module 502 is configured to perform a rising edge generation phase and a pulse high amplitude stabilization phase.

[0082] Falling edge generation module 504 is configured to perform the falling edge generation phase.

[0083] In one embodiment, the rising edge generation module 502 is also used as a parameter configuration and calculation unit.

[0084] The increment on the rising edge is:

[0085] ;

[0086] in, The increment is the rising edge. The maximum value of the pulse amplitude Data value, For a predefined scaling factor, The target rise time. This refers to the data update cycle.

[0087] In one embodiment, the rising edge generation module 502 is also used in the high-precision accumulation control unit.

[0088] Incremental update on rising edge The output data includes the current Output data amplification The first intermediate data is obtained by multiplying the first intermediate data by the increment of the rising edge; the first intermediate data is then multiplied by the increment of the rising edge. Accumulate the data to obtain the second intermediate data; then reduce the size of the second intermediate data. Times, as the updated Output data.

[0089] In one embodiment, the rising edge generation module 502 is also used for the high-level counting unit.

[0090] The counting is performed under the clock tick; when the count value reaches the preset HIGH_COUNT value, the high-amplitude pulse stabilization phase ends; where HIGH_COUNT represents the number of DAC data update cycles required for the high-amplitude pulse.

[0091] In one embodiment, the falling edge generation module 504 is also used as a parameter configuration and calculation unit.

[0092] The decrease in the falling edge is:

[0093] ;

[0094] in, The amount of decrease on the falling edge. This is the data value corresponding to the maximum pulse amplitude. For a predefined scaling factor, For the target falling edge time length, This refers to the data update cycle.

[0095] In one embodiment, the falling edge generation module 504 is also used in a high-precision decrement control unit.

[0096] Falling edge decrement update The output data includes the current Output data amplification The third intermediate data is obtained by multiplying the data by the factor of time; the third intermediate data is then compared with the decreasing amount at the falling edge. Subtract the two numbers to obtain the fourth intermediate data; then reduce the size of the fourth intermediate data. Times, as the updated Output data.

[0097] Specific limitations regarding the pulse generation system with adjustable duration can be found in the limitations of the pulse generation method with adjustable duration described above, and will not be repeated here. Each module in the aforementioned pulse generation system with adjustable duration can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in a computer device, or stored in software in the memory of a computer device, so that the processor can call and execute the corresponding operations of each module.

[0098] In one embodiment, a converter is provided, the device including a digital-to-analog converter (DAC) and a controller.

[0099] A digital-to-analog converter (DAC) has a specific data bit width, such as 16 bits, and a data update rate; its data update cycle is... It receives the digital code value DAC_CODE provided by the controller and converts it into a corresponding analog voltage output at each update clock edge, thereby generating the final analog pulse signal.

[0100] The controller is configured to execute a pulse generation method with adjustable time length as described in any of the foregoing method embodiments. The controller is typically implemented by a field-programmable gate array (FPGA), a microprocessor (MCU), or a digital signal processor (DSP), and its internal logic or software program implements the method flow of this application.

[0101] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0102] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A pulse generation method with adjustable duration, characterized in that, include: The following stages are executed under the control of the pulse generation state machine: During the rising edge generation stage, the rising edge increment is determined based on the target rising edge duration, the maximum pulse amplitude, and a predetermined scaling factor, and the DAC output data is updated according to the rising edge increment to generate a pulse rising edge. After the rising edge generation stage ends, the pulse high amplitude stabilization stage begins, maintaining the DAC output data at the maximum value corresponding to the pulse amplitude. During the falling edge generation stage, the falling edge decrement is determined based on the target falling edge duration, the maximum pulse amplitude, and the scaling factor, and the DAC output data is updated based on the falling edge decrement to generate a pulse falling edge. Under the control of the state machine, a 4-to-1 multiplexer selects and outputs the DAC output data for the corresponding stage. Wherein, the scaling factor is used to... The output data is converted to a high-precision computation domain for processing. The rising edge increment is: in, The increment value for the rising edge. The maximum value of the pulse amplitude corresponds to Data value, For a predefined scaling factor, The rising edge time of the target is [length]. For data update cycle; Update based on the rising edge increment The output data includes: Will the current Output data amplification Multiply by 1 to obtain the first intermediate data; The first intermediate data and the rising edge increment Accumulate the data to obtain the second intermediate data; Reduce the second intermediate data Times, as the updated Output data; The high-amplitude stable phase of the pulse includes: Counting is performed according to the clock's beat; When the count value reaches the preset HIGH_COUNT value, the high-amplitude pulse stabilization phase ends. Wherein, HIGH_COUNT represents the number of DAC data update cycles required for the high amplitude of the pulse; The falling edge decrement is: in, The decrease in the falling edge, This is the data value corresponding to the maximum pulse amplitude. For a predefined scaling factor, The target's fall edge time length, For data update cycle; Update based on the falling edge decrement The output data includes: Will the current Output data amplification Double the result to obtain the third intermediate data; Combine the third intermediate data with the falling edge decrement. Subtracting the two values ​​yields the fourth intermediate data. Reduce the size of the fourth intermediate data Times, as the updated Output data.

2. The method according to claim 1, characterized in that, Also includes: The rising edge generation stage, the high-amplitude pulse stabilization stage, and the falling edge generation stage are repeatedly executed to generate a repeating pulse sequence.

3. A pulse generation system with adjustable duration, characterized in that, include: The rising edge generation module is configured to perform the rising edge generation stage and the pulse high amplitude stabilization stage in the method of any one of claims 1 to 2; The falling edge generation module is configured to perform the falling edge generation stage in the method of any one of claims 1 to 2.

4. A converter, characterized in that, include: Digital-to-analog converter; as well as The controller is configured to provide data codes to the digital-to-analog converter by performing the pulse generation method with adjustable time length according to any one of claims 1 to 2, such that the digital-to-analog converter outputs a pulse signal with adjustable edge time.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 2.

Images