Communication method and communication device based on LDPC (Low Density Parity Check)

Abstract

The invention provides a coding method and a decoding method based on LDPC (Low Density Parity Check). In the method, the communication device obtains a first matrix, and partial rows of the first matrix are obtained by replacing partial rows of a second matrix with a third matrix; and the communication device performs LDPC coding on a bit sequence to be coded based on the first matrix to obtain a coded sequence. According to the coding method and the decoding method provided by the invention, a part of rows of the LDPC check matrix can be replaced by matrixes of other types of codes, so that the storage overhead of the LDPC check matrix for LDPC coding or LDPC decoding can be saved.

Description

Technical Field

[0001] This application relates to the field of coding, and more particularly to a communication method and communication device based on LDPC. Background Technology

[0002] Low-density parity-check (LDPC) codes are linear block codes with sparse parity-check matrices. LDPC codes not only exhibit good performance approaching the Shannon limit, but also have low decoding complexity and flexible structure. Therefore, they have been widely used in some communication systems.

[0003] Currently, when using base graphs (BG)1 and BG2 defined in the New Radio (NR) protocol for LDPC encoding, in order to obtain better encoding and decoding performance, all rows of the LDPC parity check matrix can be replaced with a matrix of Cordaro-Wagner codes. However, this method significantly increases the storage overhead of the LDPC parity check matrix. Summary of the Invention

[0004] This application provides a communication method and communication device based on LDPC, aiming to reduce the storage overhead of LDPC parity-check matrix.

[0005] Firstly, an LDPC-based encoding method is provided, which can be executed by a communication device or a module applied to the communication device (e.g., a processor, chip, circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the communication device). The communication device is also referred to as an encoding device. The method may include: the communication device acquiring a first matrix of size X×Y, wherein the X1 rows of the first matrix are obtained based on the N1 rows of a second matrix and N1 third matrices, the N1 rows of the second matrix correspond one-to-one with the N1 third matrices, the number of columns in each of the N1 third matrices is the same as the row weight of the corresponding row in the N1 rows of the second matrix, and the remaining rows in the first matrix excluding the X1 rows are the same as the remaining rows in the second matrix excluding the N1 rows, where N1 < X1 < X, and X, Y, X1, and N1 are all positive integers; the communication device performing LDPC encoding on the bit sequence to be encoded based on the aforementioned first matrix to obtain an encoded sequence.

[0006] The encoding method provided in this application can replace some rows of the LDPC check matrix with matrices of other code types, thereby saving the storage overhead of the LDPC check matrix used for LDPC encoding.

[0007] Secondly, an LDPC-based decoding method is provided, which can be executed by a communication device or a module applied to the communication device (e.g., a processor, chip, circuit, etc., or a logic module, hardware, and / or software capable of implementing all or part of the functions of the communication device). The communication device is also called a decoding device. The method may include: the communication device acquiring a first matrix of size X×Y, wherein the X1 rows of the first matrix are obtained based on the N1 rows of a second matrix and N1 third matrices, the N1 rows of the second matrix correspond one-to-one with the N1 third matrices, the number of columns in each of the N1 third matrices is the same as the row weight of the corresponding row in the N1 rows of the second matrix, and the remaining rows in the first matrix excluding the X1 rows are the same as the remaining rows in the second matrix excluding the N1 rows, where N1 < X1 < X, and X, Y, X1, and N1 are all positive integers; the communication device performing LDPC decoding on the encoded sequence based on the first matrix to obtain the decoded bit sequence.

[0008] The decoding method provided in this application can replace some rows of the LDPC parity check matrix with matrices of other code types, thereby saving the storage overhead of the LDPC parity check matrix used for LDPC decoding.

[0009] In some implementations of the first or second aspect, if the number of rows of the i-th third matrix among the aforementioned N1 third matrices is P, the X1 rows in the aforementioned first matrix are obtained based on the N1 rows in the second matrix and the N1 third matrices, including: the j-th non-zero element of the i-th row among the N1 rows is replaced by the j-th column of the i-th third matrix among the N1 third matrices, and each zero element of the i-th row among the N1 rows is replaced by a P×1 all-zero matrix, thereby obtaining P rows among the X1 rows; the N1 rows of the aforementioned second matrix correspond one-to-one with the N1 third matrices, including: the i-th row among the N1 rows corresponds to the i-th third matrix among the N1 third matrices; where 1≤i≤N1, and i, j, and P are all positive integers.

[0010] Specifically, the above method shows that the i-th row of the N1 rows of the second matrix is ​​replaced with P rows of the X1 rows of the first matrix. In fact, each row of the N1 rows of the second matrix will be replaced with multiple rows of the X1 rows of the first matrix, which will not be listed here.

[0011] For example, the N1 third matrices corresponding to the N1 rows of the second matrix can be all the same, partially the same, or all different, and this application does not limit this.

[0012] The above method provides a way to replace some rows of the second matrix with matrices of other code types, and the second matrix can be replaced with the first matrix according to the target code rate.

[0013] In some implementations of the first or second aspect, the N1 rows of the second matrix mentioned above include a portion of the rows in the core matrix of the second matrix.

[0014] Specifically, the N1 rows of the second matrix mentioned above may include some, but not all, rows of the core matrix of the second matrix.

[0015] The above method not only saves storage overhead for the LDPC parity-check matrix, but also allows the core matrix of the second matrix to correspond to a higher code rate, making the code rate applicable range of the LDPC parity-check matrix wider.

[0016] In some implementations of the first or second aspect, if the first matrix and the second matrix are base matrices, the communication device performs LDPC encoding based on the first matrix, including: the communication device obtaining a first parity check matrix based on the first matrix; the communication device performing LDPC encoding or LDPC decoding based on the first parity check matrix; the communication device obtaining the first parity check matrix based on the first matrix includes: the communication device expanding each non-zero element in the first matrix into a Z×Z cyclic shift matrix and expanding each zero element in the first matrix into a Z×Z all-zero matrix, thereby obtaining the first parity check matrix, where Z is a positive integer greater than or equal to 1.

[0017] The above method first replaces some rows of the second matrix with matrices of other code types, and then expands the replaced matrix into a parity check matrix. This method can save the storage overhead of the LDPC parity check matrix.

[0018] In some implementations of the first or second aspect, if the first matrix and the second matrix are parity check matrices, the second matrix is ​​obtained based on the first basis matrix; the second matrix is ​​obtained based on the first basis matrix by: expanding each non-zero element in the first basis matrix into a Z×Z cyclic shift matrix, and expanding each zero element in the first basis matrix into a Z×Z all-zero matrix, thereby obtaining the second matrix, where Z is a positive integer greater than or equal to 1.

[0019] The above method first expands the base matrix into a parity check matrix, and then replaces some rows of the expanded parity check matrix with matrices of other code types. This method not only saves the storage overhead of the LDPC parity check matrix, but also makes the code rate of the obtained LDPC parity check matrix more widely applicable.

[0020] In some implementations of the first or second aspect, each of the aforementioned N1 third matrices is a linear algebraic matrix.

[0021] For example, each of the above N1 third matrices can be a matrix of Hamming code, BCH code, RS code, polar code, or LDPC code, and this application does not limit it in this way.

[0022] The third matrix in the above method can be a linear algebra matrix, which increases the flexibility of the configuration of the third matrix.

[0023] Thirdly, a communication device is provided, which has the function of implementing the method in the first aspect or any possible implementation of the first aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0024] Fourthly, a communication device is provided, which has the function of implementing the method in the second aspect or any possible implementation of the second aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0025] Fifthly, a communication device is provided, comprising at least one processor configured to cause the communication device to execute the method of the first aspect or any possible implementation thereof; or to execute the method of the second aspect or any possible implementation thereof. Optionally, the at least one processor is coupled to at least one memory for storing computer programs or instructions, and the at least one processor is configured to call and run the computer program or instructions from the at least one memory, causing the communication device to execute the method of the first aspect or any possible implementation thereof; or to execute the method of the second aspect or any possible implementation thereof. Optionally, the at least one processor may be included in the communication device or may be configured outside the communication device. Optionally, the communication device further includes the at least one memory. Optionally, the communication device further includes at least one communication interface. As an example, the communication interface may include an input interface and / or an output interface, or may be an interface circuit.

[0026] Sixthly, a communication device is provided, comprising a communication interface and a circuit. The communication interface is configured to receive a signal to be processed and transmit the signal to the circuit. The circuit is configured to process the signal to perform a method as described in the first aspect or any possible implementation thereof; or to perform a method as described in the second aspect or any possible implementation thereof. Optionally, the communication interface is further configured to output a signal processed by the circuit. Optionally, the signal may include information and / or data. Optionally, the communication device may be a chip (e.g., a baseband chip) or a chip system.

[0027] A seventh aspect provides a computer-readable storage medium storing computer program code or instructions that, when executed on a computer, cause the method of the first aspect or any possible implementation thereof to be implemented; or, the method of the second aspect or any possible implementation thereof to be implemented.

[0028] Eighthly, a computer program product is provided, the computer program product comprising computer program code or instructions, which, when executed on a computer, cause the method in the first aspect or any possible implementation thereof to be implemented; or, as in the second aspect or any possible implementation thereof, the method to be implemented.

[0029] A ninth aspect provides a wireless communication system, including a communication device as described in the third aspect and a communication device as described in the fourth aspect. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of a communication system applicable to the methods provided in the embodiments of this application;

[0031] Figure 2 These are schematic diagrams illustrating several different communication scenarios applicable to the methods provided in the embodiments of this application;

[0032] Figure 3 This is a schematic diagram of the signal processing process of the physical layer provided in the embodiments of this application;

[0033] Figure 4 This is a schematic block diagram of a device used to implement physical layer processing;

[0034] Figure 5 This is an example of a Tanner diagram provided in an embodiment of this application;

[0035] Figure 6 This is a schematic diagram of the structure of the verification matrix provided in the embodiments of this application;

[0036] Figure 7 These are two different dimensions of Raptor-like structures provided in the embodiments of this application;

[0037] Figure 8 This is a schematic diagram illustrating the relationship between base graph (BG) selection and transport block size (TBS) and rate provided in the embodiments of this application.

[0038] Figure 9 This is a schematic flowchart illustrating an LDPC-based encoding or decoding method provided in an embodiment of this application.

[0039] Figure 10 This is a schematic diagram of obtaining the first matrix;

[0040] Figure 11 This is another schematic diagram for obtaining the first matrix;

[0041] Figure 12 This is another schematic diagram for obtaining the first matrix;

[0042] Figure 13 These are performance simulation diagrams provided in the embodiments of this application;

[0043] Figure 14 A schematic structural diagram of the communication device 1000 provided in this application;

[0044] Figure 15 A schematic structural diagram of another communication device 1100 provided in this application;

[0045] Figure 16 A schematic structural diagram of the chip provided in this application. Detailed Implementation

[0046] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0047] The technical solutions provided in this application can be applied to various communication systems, such as: 5th generation (5G) or new radio (NR) systems, long term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, wireless local area network (WLAN) systems, satellite communication systems, future communication systems, or integrated systems of multiple systems. The technical solutions provided in this application can also be applied to device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, peer-to-peer (P2P) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), and Internet of Things (IoT) communication systems or other communication systems.

[0048] In a communication system, a device can send signals to or receive signals from another device. These signals can include information, signaling, or data. The device can also be replaced by an entity, network entity, communication equipment, communication module, node, communication node, etc.; this application uses a device as an example. For instance, a communication system can include at least one terminal device and at least one network device. The network device can send downlink signals to the terminal device, and / or the terminal device can send uplink signals to the network device. It is understood that the terminal device in this application can be replaced by an encoding device, and the network device can be replaced by a decoding device; or, the terminal device in this application can be replaced by a decoding device, and the network device can be replaced by an encoding device, with both performing the corresponding communication methods described in this application.

[0049] The radio access network (RAN) device in this application is a device with wireless transceiver capabilities. The RAN device can provide wireless communication services, enabling terminal devices to access the wireless network. The RAN can also be called an access network device or a network device. In the embodiments of this application, the network device can refer to a radio access network (RAN) node (or device) used in a cellular network (or mobile network) to connect terminal devices to the wireless network. It can also be a Zigbee base station, a Bluetooth master (BTmaster), a Bluetooth Low Energy (BLE) master, a long-range radio (Lora) base station, or a Wi-Fi access point.

[0050] Network equipment can be a base station. The term "base station" can broadly encompass, or be interchangeable with, various names including: NodeB, evolved NodeB (eNB), next-generation NodeB (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), master station, auxiliary station, motor slide retainer (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. A base station can be a macro base station, micro base station, relay node, donor node, or similar entities, or combinations thereof. A base station can also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station can also be a mobile switching center, a device that performs base station functions in D2D, V2X, and M2M communications, or a device that performs base station functions in future communication systems. A base station can support networks with the same or different access technologies. Optionally, a RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). The embodiments of this application do not limit the specific technology or equipment form used in the network equipment. In some deployments, the network equipment mentioned in the embodiments of this application can be a device including a CU, or a DU, or a device including both CU and DU, or a control plane CU node (central unit-control plane (CU-CP)) and a user plane CU node (central unit-user plane (CU-UP)) and a DU node. For example, the network equipment can include gNB-CU-CP, gNB-CU-UP, and gNB-DU.

[0051] In some deployments, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes each implementing some of the base station's functions. For example, RAN nodes can be CUs, DUs, CU-CPs, CU-UPs, or RUs. CUs and DUs can be configured separately or included in the same network element, such as a BBU. RUs can be included in radio frequency equipment or radio frequency units, such as RRUs, AAUs, or RRHs.

[0052] RAN nodes can support one or more types of fronthaul interfaces, each corresponding to a DU and RU with different functions. If the fronthaul interface between the DU and RU is a common public radio interface (CPRI), the DU is configured to implement one or more baseband functions, and the RU is configured to implement one or more radio frequency functions. If the fronthaul interface between the DU and RU is another type of interface, relative to CPRI, some downlink and / or uplink baseband functions, such as, for downlink, one or more of precoding, beamforming (BF), or inverse fast Fourier transform (IFFT) / adding a cyclic prefix (CP), are moved from the DU to the RU; and for uplink, one or more of beamforming (BF), or fast Fourier transform (FFT) / removing CP, are moved from the DU to the RU. In one possible implementation, the interface can be an enhanced common public radio interface (eCPRI). Under the eCPRI architecture, the segmentation between DU and RU differs, corresponding to different categories (Cat) of eCPRI, such as eCPRI Cat A, B, C, D, E, and F.

[0053] Taking eCPRI Cat A as an example, for downlink transmission, layer mapping is used as the dividing line. The DU is configured to implement one or more functions preceding layer mapping (i.e., coding, rate matching, scrambling, modulation, and layer mapping itself), while other functions following layer mapping (e.g., resource element (RE) mapping, digital BF, or IFFT / CP addition) are implemented in the RU. For uplink transmission, de-RE mapping is used as the dividing line. The DU is configured to implement one or more functions preceding de-mapping (i.e., decoding, rate matching de-matching, descrambling, demodulation, inverse discrete Fourier transform (IDFT), channel equalization, and de-RE mapping itself), while other functions following de-mapping (e.g., digital BF or FFT / CP removal) are implemented in the RU. It is understood that descriptions of the functions of the DU and RU corresponding to various types of eCPRI can be found in the eCPRI protocol and will not be elaborated upon here.

[0054] In one possible design, the processing unit in the BBU used to implement baseband functions is called the baseband high (BBH) unit, and the processing unit in the RRU / AAU / RRH used to implement baseband functions is called the baseband low (BBL) unit.

[0055] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an open-RAN (O-RAN or ORAN) system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules. The network device in this application can be a virtualized device, for example, implemented through general-purpose hardware and instantiated virtualization functions, or dedicated hardware and instantiated virtualization functions. Among them, general-purpose hardware can be a server, such as a cloud server.

[0056] In this embodiment, the apparatus for implementing the functions of a network device can be a network device itself; it can also be an apparatus capable of supporting the network device in implementing those functions, such as a chip system, hardware circuit, software module, or a hardware circuit plus a software module. This apparatus can be installed in the network device or used in conjunction with the network device. In this embodiment, the example of a network device being used to implement the functions of a network device is provided only and does not constitute a limitation on the solutions described in this embodiment.

[0057] The terminal equipment in this application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent, or user device.

[0058] Terminal devices can be devices that provide voice / data, such as handheld devices with wireless connectivity, in-vehicle devices, etc. Currently, examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, wearable devices, terminal devices in 5G networks, or future public land mobile communication networks. Terminal devices in a network (PLMN), devices in a Zigbee network, devices in a LoRa network, Bluetooth slaves, Bluetooth Low Energy slaves, Wi-Fi stations (STAs), etc. This application does not limit the scope of the embodiments.

[0059] Terminal devices can also be terminal devices in an IoT system, also known as IoT nodes. IoT is an important component of future information technology development. Its main technical characteristic is connecting objects to networks through communication technologies, thereby realizing an intelligent network that enables human-machine interconnection and machine-to-machine interconnection. Connectivity can be achieved through broadband or narrowband technologies. IoT technology, for example, can achieve massive connectivity, deep coverage, and low terminal power consumption through narrowband (NB) technology. IoT technologies include reflective communication technology, spread spectrum technology, and ultra-wideband (UWB), which will not be elaborated further.

[0060] In addition, terminal devices may also include sensors such as smart printers, train detectors, and gas stations. Their main functions include collecting data (for some terminal devices), receiving control information and downlink data from network devices, and sending electromagnetic waves to transmit uplink data to network devices.

[0061] By way of example and not limitation, in this embodiment, the terminal device can also be a wearable device. Wearable devices, also known as wearable smart devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not merely hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include those that are feature-rich, large in size, and can achieve complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses, as well as those that focus on a specific type of application function and require the use of other devices such as smartphones, such as various smart bracelets and smart jewelry for vital sign monitoring.

[0062] In this embodiment, the device for implementing the functions of the terminal device can be the terminal device itself, or it can be any device capable of supporting the terminal device in implementing those functions, such as a chip system. This device can be installed in or used in conjunction with the terminal device. In this embodiment, the chip system can be composed of chips or may include chips and other discrete components. This embodiment only uses the terminal device as an example to illustrate the device for implementing the functions of the terminal device, and does not constitute a limitation on the solution of this embodiment.

[0063] The terminal device in this application can be a hardware device, a software function running on dedicated hardware, or a software function running on general-purpose hardware. It can also be a virtualized device, for example, implemented through general-purpose hardware and instantiated virtualization functions, or dedicated hardware and instantiated virtualization functions. Among them, the general-purpose hardware can be a server, such as a cloud server.

[0064] Network devices and / or terminal devices can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; they can also be deployed on water; and they can also be deployed in the air on airplanes, balloons, and satellites. This application does not limit the scenario in which the network devices and terminal devices are located.

[0065] Figure 1 This is a schematic diagram of the architecture of the communication system 10 used in the embodiments of this application. Figure 1 A schematic diagram of a possible, non-limiting system architecture is shown. (e.g.) Figure 1As shown, the communication system 10 includes a radio access network (RAN) 100 and a core network 200. Optionally, the communication system 10 also includes an Internet 300. The RAN 100 may include at least one RAN node (e.g., Figure 1 110a and 110b in the above), may also include at least one terminal device (such as Figure 1 (120a-120j in the RAN 100). Terminal devices can connect to radio access network (RAN) devices wirelessly. Terminal devices can connect to each other, and RAN devices can connect to each other via wired or wireless means. RAN nodes 110a or 110b connect to the core network 200 wirelessly or via wired means. The core network devices in the core network 200 and RAN nodes 110a or 110b in the RAN 100 can be different physical devices, or they can be the same physical device integrating core network logical functions and RAN access network logical functions.

[0066] Figure 1 This is just an illustration; the communication system 10 may also include other network devices, such as wireless repeaters and wireless backhaul devices. Figure 1 It is not shown in the middle.

[0067] RAN 100 can be a cellular system related to the 3rd Generation Partnership Project (3GPP), such as 4G, 5G mobile communication systems, or future-oriented evolution systems. RAN 100 can also be ORAN, cloud radio access network (CRAN), Zigbee network systems, or Wi-Fi systems. RAN 100 can also be a communication system that integrates two or more of the above systems.

[0068] The RAN node can be an airborne base station, such as satellite base station 110a; or an indoor base station, such as a micro base station or indoor station 110b. It should be understood that this application does not limit the specific technology or device form used in the wireless access network equipment. For ease of description, the following description uses a base station as an example of a wireless access network device.

[0069] The terminal device can be a terminal device deployed in the air, such as... Figure 1 The 120i can be a helicopter or drone; it can also be a terminal device deployed on the ground, such as... Figure 1 Among them are mobile phones 120a, 120e, 120f and 120j, vehicles 120b, computers 120g, printers 120h, gas stations 120c, smart home devices 120d, etc.

[0070] Alternatively, the terminal device can also be used as a RAN node. For example, the UE can act as a scheduling entity, providing sidelink signaling between terminal devices in V2X, D2D, or P2P, etc.

[0071] RAN nodes and terminal devices can be fixed or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; on water; or in the air on aircraft, balloons, and satellites. The embodiments of this application do not limit the application scenarios of the RAN nodes and terminal devices.

[0072] The roles of RAN nodes and terminal devices can be relative, for example, Figure 1 The helicopter or drone 120i can be configured as a RAN node. For terminal devices 120j that access RAN 100 via 120i, terminal device 120i is a RAN node; however, for RAN node 110a, 120i is a terminal device, meaning that 110a and 120i communicate via a wireless air interface protocol. Alternatively, 110a and 120i can also communicate via an interface protocol between RAN nodes; in this case, 120i is also a RAN node relative to 110a. Therefore, both RAN nodes and terminal devices can be collectively referred to as communication devices. Figure 1 110a, 110b, and 120a-120j can be referred to as communication devices with their respective corresponding functions, such as communication devices with RAN node functions or communication devices with terminal functions.

[0073] In the embodiments of this application, the functions of the RAN node can be executed by modules (such as chips) within the RAN node, or by a control subsystem that includes RAN node functions. This control subsystem, including RAN node functions, can be a control center in the aforementioned terminal application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities. The functions of the terminal device can also be executed by modules (such as chips) within the terminal device, or by a device that includes terminal device functions. This application does not limit the scope of these limitations.

[0074] Figure 2 These are schematic diagrams illustrating several different communication scenarios applicable to the communication methods provided in the embodiments of this application. For example, point-to-point transmission between RAN nodes and terminals or between terminals (such as...). Figure 2 (a) in the text refers to point-to-point transmission between RAN nodes and terminals, and multi-hop transmission between RAN nodes and terminals (e.g., ...). Figure 2 (b) Figure 2(c) Transmission, dual connectivity (DC) of multiple RAN nodes and terminals (e.g.) Figure 2 (d) or multiple connections, etc. It should be noted that the specific communication application scenarios mentioned above are merely examples and do not constitute limitations. In particular, from a business perspective, the embodiments of this application are applicable to many business scenarios, such as data encoding scenarios and high-capacity uplink scenarios in extended reality (XR) services. Furthermore, Figure 2 This application does not impose any restrictions on the network architecture applicable to this application, and it does not restrict uplink, downlink, access link, backhaul link, sidelink (SL) and other transmissions.

[0075] Figure 3 This is a schematic diagram of the signal processing process of the physical layer applicable to embodiments of this application. The signal processing of the physical layer can be divided into downlink processing and uplink processing.

[0076] Downlink processing is the process of processing information data from higher layers using the physical layer before transmitting it. For example, downlink processing includes: performing channel coding (or simply coding) on ​​the layer 2 (L2) information data, modulation, layer mapping, precoding, framing, IFFT, and frequency conversion using radio frequency (RF) or intermediate radio frequency (IRF) to convert it into an air interface signal to be transmitted.

[0077] More specifically, the data transmitter can divide the data from Layer 2 into multiple TBs based on the system's supported transport block (TBS) size (TBS), and add a cyclic redundancy check (CRC) code to each TB. If the size of the TB after adding the CRC code exceeds the maximum code block length, the TB can be segmented to obtain multiple code blocks (CBs). Each segmented CB can be further coded with a CRC code to obtain the input to be encoded corresponding to each CB. This input to be encoded is a sequence of bits to be encoded, specifically including the information bits and check bits (i.e., the CRC code) in its corresponding CB. The transmitter can perform channel coding on this input to be encoded, such as LDPC coding, to obtain the corresponding coded code blocks. Rate matching is performed on the coded code blocks, and the rate-matched coded code blocks are concatenated to form codewords (CWs). The transmitter can scramble the codewords to generate scrambled bits. The scrambled bits are modulated to obtain modulation symbols. After being mapped by resource elements (REs), the modulation symbols are mapped onto multiple REs, thus obtaining the value carried on each RE. Based on the values ​​carried on these REs, the transmitter can generate a baseband signal. The baseband signal can then be processed by RF or IRF and transmitted by the antenna.

[0078] Uplink processing is the process of physical layer processing of signals received through the air interface. For example, uplink processing includes: performing IRF processing on the received signal to obtain the baseband signal, and then completing physical layer signal processing through FFT, deframing, demodulation, and decoding, and then handing the obtained information data to layer 2.

[0079] More specifically, the signal receiver performs RF or IRF processing on the signal received from the antenna to obtain the baseband signal. Subsequently, the receiver's physical layer can sequentially perform RE mapping, demodulation, descrambling, rate matching de-matching, and channel decoding on the signal to obtain the bit sequence before encoding, which may specifically include information bits and parity bits.

[0080] Optionally, after completing RE mapping and before demodulation, the receiver can perform channel equalization. Channel equalization is based on the channel estimated by the channel, and the influence of the channel is removed by using an equalization algorithm, thereby ensuring correct signal demodulation.

[0081] Optionally, after modulation but before RE mapping, the transmitting end can perform layer mapping and precoding. For example, the transmitting end can map the modulation symbols to multiple layers, and the layer-mapped modulation symbols are then precoded to obtain a precoded signal. The precoded signal is then mapped to multiple REs via RE mapping. Correspondingly, after performing de-layer mapping, the receiving end performs channel equalization and then demodulation; or, the receiving end can perform de-layer mapping and then demodulation after completing channel equalization; or it can perform de-layer mapping and then channel equalization after completing deframe.

[0082] because Figure 3 The specific implementation methods for each step can be achieved using existing technologies or future solutions; see the Third Generation Partnership Program (3). rd The relevant sections of the Generation Partnership Project (3GPP) technical specification (TS) 38.211 are not detailed here.

[0083] The apparatus for implementing the above-described physical layer processing can be a communication device, such as a network device or terminal, or a mobile communication chip, such as a baseband chip; this application does not limit this. Based on different functions, the apparatus can be divided into multiple units (or modules). For example, Figure 4 This is a schematic block diagram of a device used to implement physical layer processing. Figure 4 (a) and (b) show apparatus 400A and apparatus 400B, respectively. Apparatus 400A can be used to implement uplink processing, and apparatus 400B can be used to implement downlink processing.

[0084] like Figure 4 As shown in (a) and (b), devices 400A and 400B respectively include a computing unit, a control unit, and a storage unit. The computing unit is responsible for processing the logical operations of the device, specifically including encoding and / or decoding logical operations. The storage unit is responsible for storing data during the computing process, and can also be used to store information related to encoding and decoding, such as base maps. The control unit is responsible for scheduling and controlling the computing unit and storage resources.

[0085] For example, such as Figure 4 As shown in (a), the computing unit of device 400A can be used to perform operations such as TB CRC calculation, BG selection, code block segmentation, CB CRC calculation, LDPC encoding, and code block concatenation. The BG selection can be made from the BGs stored in the storage unit.

[0086] For example, such as Figure 4 As shown in (b), the computing unit of device 400B can be used to perform operations such as rate matching, hybrid automatic repeat request (HARQ) merging, LDPC decoding, CB CRC check, and TBCRC check.

[0087] In another possible implementation, the module in device 400A used for LDPC encoding is an encoder. In yet another possible implementation, the encoder can not only implement LDPC encoding but also perform LDPC encoding preprocessing and / or post-processing. LDPC encoding preprocessing includes, for example, one or more of the following: TB CRC calculation, BG selection, code block segmentation, or CB CRC calculation. LDPC encoding post-processing includes, for example, code block concatenation. For example, device 400A is an encoder. Of course, the encoder can also implement other functions besides LDPC encoding and its preprocessing and post-processing listed above, and this application does not limit this.

[0088] In one possible implementation, the module in device 400B used for LDPC decoding is a decoder. In another possible implementation, the decoder can not only perform LDPC decoding, but also perform LDPC decoding preprocessing and / or post-processing. LDPC decoding preprocessing includes, for example, one or more of the following: rate matching or HARQ merging. LDPC post-processing includes, for example, one or more of the following: CB CRC or TB CRC. For example, device 400B is a decoder. Of course, the decoder can also perform other functions besides LDPC decoding and its preprocessing and post-processing listed above, and this application does not limit this.

[0089] To facilitate understanding of the embodiments of this application, the following is a brief explanation of several terms used in this document.

[0090] Channel coding: Encoding information transmitted through unreliable channels in digital communication to improve the reliability of information transmission. In channel coding, the transmitting end can adopt a certain coding type to convert the original information (such as information bits) into encoded data of a certain format and transmit it through the channel; the receiving end needs to decode the received data and restore the original information. The most critical part of channel coding is forward error correcting coding (FEC). The purpose of error correcting coding is to ensure that the receiving end can automatically correct errors that occur in data transmission with the least possible redundancy overhead. At the same bit error rate, the smaller the overhead required, the higher the coding efficiency. Traditional channel coding types generally include linear block codes (LBCs) (such as Hamming codes, Gray codes, BCH codes (Bose-Chaudhuri-Hocquenghem codes), RS codes (Reed-Solomon codes), etc.), convolutional codes, and concatenated codes. These codes have their own different characteristics and performance, and are suitable for different scenarios.

[0091] Code rate: The proportion of useful information to total information in the encoded data stream. In this paper, useful information is denoted as information bits, and the encoded data stream is denoted as encoded bits. Encoded bits include information bits and parity bits (or redundancy bits). For example, if there are K information bits and N encoded bits after channel coding, then the coding code rate is K / N. The number of encoded bits after channel coding can also be called the code length. It can be understood that high redundancy results in a low coding code rate and strong anti-interference capability, but low transmission efficiency; conversely, low redundancy results in a high coding code rate and weak anti-interference capability, but high transmission efficiency.

[0092] LDPC code: A type of linear block code. Because the parity-check matrix of this linear block code has a sparse property, with elements having a value of 1 accounting for a very small proportion, it is also called an LDPC code. For an LDPC code with K information bits and N code length, its parity-check matrix has a dimension of (N-K)×N, and the corresponding codeword c can be defined by the parity-check matrix H:

[0093]

[0094] Where c represents K information bits; w represents (N+D-K) check bits; [cw] T This represents a column vector of length (N+D) consisting of K information bits and (N+D-K) check bits; D represents the number of puncture bits, where D is a positive integer, for example, D is 2^Z. c Z cZ represents the minimum value of Z, which is the lifting size. The value of Z can be predefined and is an integer greater than or equal to 1.

[0095] The process of LDPC encoding based on the parity-check matrix H is to obtain the encoded output [cw] given the parity-check matrix H and the input c to be encoded. T The process; the process of LDPC decoding based on the parity-check matrix H, that is, given the parity-check matrix H and the input to be decoded [cw] T The process of recovering the input c to be encoded.

[0096] Parity-check matrix: Used for LDPC encoding or decoding. In this application, the parity-check matrix is ​​denoted as a matrix H of dimension M×N. Here, M is the number of parity bits, which satisfies: M = N - K. Therefore, the dimension of the parity-check matrix can also be denoted as (N - K)×N.

[0097] In this parity-check matrix H, each row corresponds to a parity-check equation of the LDPC code, and (N-K) parity-check equations correspond to (N-K) parity-check nodes of the LDPC code; each column corresponds to a symbol of the LDPC code, and N symbols correspond to N variable nodes of the LDPC code. The non-zero elements h in the parity-check matrix H... m,n This indicates that the m-th check node and the n-th variable node are connected, where m can be an integer greater than or equal to 0 and less than or equal to (M-1), and n can be an integer greater than or equal to 0 and less than or equal to (N-1). The number of non-zero elements in each row of the check matrix H represents the degree of the check node, and the number of non-zero elements in each column represents the degree of the variable node. If all check nodes have the same degree, and all variable nodes also have the same degree, the corresponding LDPC code is a regular code; otherwise, it is an irregular code.

[0098] For example, the parity-check matrix H of a regular LDPC code with a code length of 10 and a code rate of 1 / 2 is as follows:

[0099]

[0100] In this verification matrix H, each row includes 10 variable nodes and each column includes 5 verification nodes. If we use c0, c1, ..., c9 to represent variable nodes and p0, p1, ..., p4 to represent verification nodes, the verification matrix H can be represented by a graphical model, such as a Tanner graph, a factor graph, or a tree graph.

[0101] Figure 5 An example of a Tanner diagram is shown. Figure 5 The Tanner graph shown corresponds to the parity check matrix H listed above, and the degree of a node is equal to the number of edges connected to that node in the Tanner graph. For example, h in the parity check matrix H above...0,0 If the value is 1, then the variable node c0 and the check node p0 in the Tanner graph are connected; similarly, h in the check matrix... 1,1 If the value is 0, then the variable node c1 and the check node p1 in the Tanner graph are not connected; and so on, without further enumeration.

[0102] In a Tanner graph, a closed path consisting of edges that start from a vertex, follow the edges between vertices, pass through different vertices, and return to the same vertex can be called a "cycle". The number of edges traversed is called the length of the cycle (or simply, the cycle length). Figure 5 For example, starting from variable node c0, the edge between variable node c0 and check node p0 leads to check node p0. Then, the edge between check node p0 and variable node c6 leads to variable node c6. Next, the edge between variable node c6 and check node p1 leads to check node p1. Finally, the edge between check node p1 and variable node c0 leads back to variable node c0. This forms a cycle of length 4 (e.g., ...). Figure 5 (As shown by the thick black line).

[0103] In LDPC codes, iterative probabilistic decoding involves the exchange and transmission of information between nodes. Rings inevitably affect the decoding results. Information originating from a node in the ring is continuously transmitted along the ring's nodes and returns to that node itself, causing the information within that node to accumulate and increasing the probability of decoding failure. The shorter the ring, the shorter the path required for information to return, the faster errors propagate during iteration, and the higher the probability of decoding failure. In other words, short rings severely impact decoding performance.

[0104] Quasi-cyclic low-density parity-check (QC-LDPC) codes: a subclass of LDPC. The parity check matrix of a QC-LDPC has quasi-cyclic properties, and its representation can be simplified based on the quasi-cyclic structure. For example, for an (N, K) QC-LDPC code, its parity check matrix H can be represented as:

[0105]

[0106] Where M = m b ×Z, N=n b ×Z, P i,j A cyclic shift matrix represents a Z×Z cyclic shift matrix (also called a cyclic shift square matrix or a cyclic shift submatrix) or a Z×Z all-zero matrix (also called an all-zero submatrix or an all-zero square matrix). A cyclic shift matrix can be represented by its corresponding cyclic shift coefficient V. i,jTo simplify the representation, for example, the cyclic shift matrix can be defined as a cyclic right shift matrix of an identity matrix, where each element "1" in the identity matrix can be based on the cyclic shift coefficient V. i,j Perform a circular shift to the right. Where V... i,j When P = -1, i,j V is a Z×Z matrix containing all zeros; i,j When P = 0, i,j V is a Z×Z identity matrix, which is obtained by cyclically shifting each "1" in the identity matrix to the right by 0 bits (or, in other words, without shifting); i,j ∈[-1, Z max When P = -1], i,j Circularly shift each element "1" in a Z×Z identity matrix to the right by V. i,j The matrix obtained by Z max It is the maximum value of Z, Z≤Z max .

[0107] The process of converting elements Pi,j in the parity check matrix H into a cyclic shift matrix or a zero matrix can be achieved using the conversion function g(V). i,j Z) represents the following:

[0108]

[0109] Where % represents the modulo operation; V i,j The value can be predefined, for example, through a protocol, such as in Tables 5.3.2-2 and 5.3.2-3 of the 3rd Generation Partnership Project (3GPP) technical specification (TS) 38.212.

[0110] With Z=4, Z max For example, if the value is 8, the element P in the check matrix... i,j The correspondence between these matrices and cyclic shift matrices or all-zero matrices is as follows:

[0111] The matrix corresponding to the element "-1" That is, an all-zero matrix; elements "0" to "7" correspond to a cyclic shift matrix, where elements "0" and "4" correspond to a matrix The matrix corresponding to elements "1" and "5" The matrix corresponding to elements "2" and "6" The matrix corresponding to elements "3" and "7"

[0112] Base graph and base matrix: In some implementations, the base graph can be simplified as a table, array, or sequence indicating the row and column positions of non-zero elements. In other implementations, the base graph can be identified by a base matrix.

[0113] A base graph can be represented as a graph of dimension m. b ×n b The basis matrix is ​​m. The basis matrix can be used to construct the parity-check matrix of a QC-LDPC code. b ×n b The corresponding check matrix has a dimension of (m) b ×Z)×(n b As can be seen, each element in the basis matrix can be replaced with a matrix of dimension Z×Z, which can be called a submatrix of dimension Z×Z in the parity matrix.

[0114] It should be noted that the terms "Z×Z matrix" and "Z×Z submatrix" mentioned above refer to different objects. A single element in the base matrix can replace a Z×Z matrix, which is only a part of the parity check matrix and can therefore be called a submatrix of the parity check matrix.

[0115] A basis matrix can include zero elements and non-zero elements. Zero elements in a basis matrix can be replaced with a Z×Z matrix of all zeros; non-zero elements in a basis matrix can be a Z×Z cyclic parity check matrix P. i,j Let i and j represent the row and column positions of the non-zero elements in the basis matrix, respectively. The specific cyclic shift matrix that Pi,j is replaced with can be determined using the transformation function g(V) mentioned above. i,j The determination is made by Z, which will not be elaborated here.

[0116] In the basis matrix, zero elements can be represented by 0, and non-zero elements can be represented by 1. The number of bits for cyclic shift can be determined according to the conversion function g(V) mentioned above. i,j The value can be determined by (Z); or, zero elements can be represented by -1, non-zero elements by 0, and the number of bits for the circular shift can be determined by the conversion function g(V) mentioned above. i,j The value can be determined by (Z); or, a zero element can be represented by -1, a non-zero element can be represented by a value greater than or equal to 0, and the number of digits in a cycle can be indicated by the value of the non-zero element. This application does not limit this.

[0117] Currently, the NR protocol defines two base maps: BG 1 and BG 2. BG 1 defines a base matrix with a dimension of 46×68 and a core matrix with a dimension of 4×26, and is mainly used for scenarios with high throughput requirements, high bit rate, and long code length. BG 2 defines a base matrix with a dimension of 42×52 and a core matrix with a dimension of 4×14, and is mainly used for scenarios with low throughput requirements, low bit rate, and short code length.

[0118] Figure 6 This is a schematic diagram of the structure of the verification matrix provided in the embodiments of this application. Figure 6 The structure of the verification matrix shown is a Raptor-like structure, which is quite common in 5G. For example... Figure 6 As shown, the parity check matrix of the Raptor-like LDPC structure includes the following five parts:

[0119] Part A: Information bits of the core array;

[0120] Part B: The parity bit portion of the core array, which has a double diagonal structure.

[0121] Part C: All-zero matrix;

[0122] Part D: The information bit portion of the extended array;

[0123] Part E: The parity bit portion of the extended matrix, which has a single diagonal structure.

[0124] It should be understood that the descriptions of the core matrix, all-zero matrix, and extended matrix mentioned above are all relative to their respective parts. In the parity check matrix, the core matrix can be called the core submatrix, the all-zero matrix can be called the all-zero submatrix (or simply, the all-zero submatrix), and the extended matrix can be called the extended submatrix.

[0125] The verification matrix includes the core matrix H core and extended array H ext Among them, the core array H core include Figure 6 Parts A and B (shown in thick black boxes in the diagram) constitute a high-bitrate parity-check matrix, which can be represented as [AB]. Its dimension is M. core ×N core M core ≤M, N core ≤N, and also satisfies: N core =M core +K. Based on the core array H core Scalable generation of extended matrix H ext , can correspond to Figure 6 The D and E parts. Extended array H extEach additional row adds one column to the parity check matrix H. It should be understood that the names of the various parts above are for ease of distinction only and should not constitute any limitation on this application. For example, part A can also be called the high-bitrate information column region, part B can also be called the high-bitrate core parity check region, and parts D and E can also be called incremental redundancy regions.

[0126] It should be noted that since the parity-check matrix can be generated based on the basis matrix, and each element in the basis matrix can be converted into a Z×Z matrix, the dimension M of the core matrix is... core ×N core It can also correspond to a basis matrix with dimension (M) core / Z)×(N core The parity-check matrix is ​​a submatrix of ( / Z). Since part C of the parity-check matrix is ​​an all-zero submatrix and part E is a diagonal submatrix, both having relatively regular structures, the description of the parity-check matrix or basis matrix can primarily focus on parts A, B, and D. For ease of explanation and understanding, parts C and E will not be described in detail later, but those skilled in the art will understand that once the core matrix and extended matrix are determined, the other parts can be obtained based on the aforementioned structure, thus yielding the complete parity-check matrix.

[0127] It should also be noted that in some implementations, the core matrix may include rows and / or columns other than parts A and B. For example, the number of rows in the core matrix is ​​the number of rows in matrix [AB] + 1, and the number of columns in the core matrix is ​​the number of columns in matrix [AB] + 1. The core matrix is ​​defined exemplarily for the convenience of understanding the embodiments of this application and should not constitute any limitation on this application. This application does not limit the dimensions of the core matrix. Unless otherwise specified, the core matrix will still be understood as [AB] below.

[0128] For example, Figure 7 These are two different dimensions of Raptor-like structures provided in the embodiments of this application. The 5G protocol defines two different BGs: BG 1 and BG 2, as follows: Figure 7 As shown in (a) and (b) in the figure. Figure 7 In the structure shown in (a), BG 1 has a size of 46×68, and the core array H core Its size is 4×26, and it is mainly used in scenarios with high throughput requirements, high bit rate, and long bit length. Figure 7 In the structure shown in (b), BG 2 has a size of 42×52, and the core array H core The size is 4×14, and it is mainly used in scenarios with low throughput requirements, low bit rate, and short bit length.

[0129] In practical applications, the choice of which BG to use to generate the parity check matrix, and then for LDPC encoding and decoding, can be determined based on the TBS and the code rate R. Figure 8 An example illustrating the relationship between BG selection, TBS, and bit rate is shown. As illustrated, if TBS ≤ 292; or TBS ≤ 3824 and R ≤ 0.67; or R ≤ 0.25, BG 2 is selected; otherwise, BG 1 is selected. Here, TBS is the TBS excluding CRC, and R can be the bit rate indicated by the modulation and coding scheme (MCS) index, which can be understood as the desired bit rate, referred to as the target bit rate, rather than the actual bit rate.

[0130] Currently, when using parity-check matrices generated by BG 1 and BG 2 for LDPC encoding and decoding, the block error rate (BLER) decreases significantly with increasing signal-to-noise ratio (SNR) in the lower symbol signal-to-noise ratio (SNR) range; this range can be termed the waterfall region. However, in the higher SNR range, the decreasing trend of BLER with increasing SNR slows down, resulting in a more pronounced error leveling; this range can be termed the leveling region. This may lead to low decoding performance in the leveling region, posing potential risks and impacts, especially in scenarios with high reliability requirements.

[0131] Currently, all rows of the LDPC parity-check matrix can be replaced with a matrix of Cordaro-Wagner codes. While this method can achieve better encoding and decoding performance, it significantly increases the storage overhead of the LDPC parity-check matrix.

[0132] In view of this, this application provides an encoding and decoding method based on LDPC, which can reduce the storage overhead of the LDPC parity matrix.

[0133] Figure 9 This is an example of an illustrative flowchart illustrating the LDPC-based encoding and decoding method provided in this application. Figure 9 The method shown can be executed by an encoding device and a decoding device, which can be a communication device, such as a network device or a terminal device, or a component configured in the communication device, such as a circuit or chip inside the communication device (such as a modem chip, also known as a baseband chip, or a SoC chip or SIP chip containing a modem core, etc.), or a logic module or software that can implement some or all of the functions of the communication device, etc. This application does not limit it in this regard.

[0134] Figure 9 The method 900 shown may include steps S910 to S918. The following describes... Figure 9 Each step in the method 900 shown is described in detail.

[0135] In step S910, the encoding device acquires the first matrix.

[0136] Specifically, the size of the first matrix is ​​X×Y, and the size of the second matrix is ​​M×N.

[0137] Specifically, the X1 rows of the first matrix are obtained based on the N1 rows of the second matrix and the N1 third matrices. The N1 rows of the second matrix correspond one-to-one with the N1 third matrices. The remaining rows in the first matrix, excluding the aforementioned X1 rows, are the same as the remaining rows in the second matrix, excluding the aforementioned N1 rows. Furthermore, the number of columns in each of the N1 third matrices is the same as the row weight of the corresponding row in the N1 rows of the second matrix.

[0138] Where N1 < X1 < X, N1 < N, and X, X1, Y, M, N, and N1 are all positive integers.

[0139] For example, the row weight mentioned above refers to the number of non-zero elements in a row.

[0140] It should be understood that a portion of the rows in the first matrix is ​​derived from a portion of the rows in the second matrix.

[0141] For example, the first matrix and the second matrix described above can be either base matrices or parity matrices, and this application does not limit them in this regard.

[0142] The following sections provide detailed descriptions of the cases where the first and second matrices are the base matrices and the parity check matrices, respectively.

[0143] I. The first and second matrices are the basis matrices.

[0144] Figure 10 A second matrix of size 10×18 is shown, wherein the core matrix of the second matrix is ​​4×12, the information columns of the core matrix are columns 1 to 8, and the core check columns of the core matrix are columns 9 to 12.

[0145] Specifically, the N1 rows of the second matrix and the N1 third matrices can be used to obtain the X1 rows of the first matrix, and the N1 rows of the second matrix correspond one-to-one with the N1 third matrices.

[0146] Example 1: such as Figure 10 As shown, assume N = 10, N1 = 1, and the row of the second matrix that needs to be replaced is the first row of the second matrix. Figure 10The row weight of the first row of the second matrix shown is 7, therefore the number of columns of the third matrix corresponding to the first row is also 7. Specifically, the number of rows of the third matrix is ​​P, and the number of rows P of the third matrix can be less than the number of columns of the third matrix. This application uses a third matrix with 3 rows as an example for illustration. Figure 10 An example of a third matrix of size 3×7 is also shown.

[0147] Specifically, the j-th non-zero element in the i-th row of the N1 rows of the second matrix is ​​replaced by the j-th column of the i-th third matrix in the N1 third matrices, and each zero element in the i-th row of the N1 rows is replaced by a P×1 matrix of all zeros, resulting in P rows in the X1 rows of the first matrix. Here, 1≤i≤N1, and i, j, and p are all positive integers.

[0148] For example, Figure 10 The element in the first row and first column of the second matrix shown is the first non-zero element in the first row; the element in the first row and second column is the second non-zero element in the first row; the element in the first row and third column is the third non-zero element in the first row; the element in the first row and fourth column is the fourth non-zero element in the first row; the element in the first row and seventh column is the fifth non-zero element in the first row; the element in the first row and ninth column is the sixth non-zero element in the first row; and the element in the first row and tenth column is the seventh non-zero element in the first row. All other elements in the first row are zero elements. The first non-zero element in the first row of the second matrix is ​​replaced by the first column of the third matrix; the second non-zero element in the first row of the second matrix is ​​replaced by the second column of the third matrix; the third non-zero element in the first row of the second matrix is ​​replaced by the third column of the third matrix; the fourth non-zero element in the first row of the second matrix is ​​replaced by the fourth column of the third matrix; the fifth non-zero element in the first row of the second matrix is ​​replaced by the fifth column of the third matrix; the sixth non-zero element in the first row of the second matrix is ​​replaced by the sixth column of the third matrix; and the seventh non-zero element in the first row of the second matrix is ​​replaced by the seventh column of the third matrix. Each other element in the first row is replaced with a 3×1 matrix of all zeros, thus obtaining X1 rows of the first matrix. Figure 10 The X1 rows of the first matrix shown are rows 1 to 3 of the first matrix.

[0149] Furthermore, the remaining rows in the first matrix, excluding the X1 rows, are the same as the remaining rows in the second matrix, excluding the N1 rows. Figure 10 The remaining rows of the first matrix, excluding the X1 rows, are rows 4 to 12 of the first matrix. The remaining rows of the second matrix, excluding the N1 rows, are rows 2 to 10 of the second matrix. Rows 4 to 12 of the first matrix are the same as rows 2 to 10 of the second matrix.

[0150] In Example 1, the highest bitrate of the second matrix is ​​8 / 12 = 2 / 3, and the highest bitrate of the first matrix is ​​(8-2) / 12 = 1 / 2. It can be seen that the bitrate of the first matrix is ​​reduced after replacing the first row of the second matrix with a third matrix. However, compared with the first matrix obtained by replacing all rows of the second matrix with a third matrix, the highest bitrate of the first matrix obtained in this embodiment is higher, thus making the applicable range of bitrate wider.

[0151] Example 2: such as Figure 11 As shown, Figure 11 The second matrix shown is the same as the one described above. Figure 10 The second matrix shown is the same, assuming N=10, N1=1, and the row of the second matrix that needs to be replaced is the second row of the second matrix. Figure 11 The second row of the second matrix shown has a row weight of 8, therefore the third matrix corresponding to this second row also has 8 columns. Specifically, the third matrix has P rows, and the number of rows P of the third matrix can be less than the number of columns of the third matrix. This application uses a third matrix with 4 rows as an example for illustration. Figure 10 An example of a third matrix of size 4×8 is also shown.

[0152] Specifically, the j-th non-zero element in the i-th row of the N1 rows of the second matrix is ​​replaced by the j-th column of the i-th third matrix in the N1 third matrices, and each zero element in the i-th row of the N1 rows is replaced by a P×1 matrix of all zeros, resulting in P rows in the X1 rows of the first matrix. Here, 1≤i≤N1, and i, j, and p are all positive integers.

[0153] For example, Figure 11The element in the 2nd row and 1st column of the second matrix shown is the first non-zero element in the 2nd row; the element in the 2nd row and 4th column is the second non-zero element in the 2nd row; the element in the 2nd row and 5th column is the third non-zero element in the 2nd row; the element in the 2nd row and 6th column is the fourth non-zero element in the 2nd row; the element in the 2nd row and 7th column is the fifth non-zero element in the 2nd row; the element in the 2nd row and 8th column is the sixth non-zero element in the 2nd row; the element in the 2nd row and 10th column is the seventh non-zero element in the 2nd row; and the element in the 2nd row and 11th column is the eighth non-zero element in the 2nd row. All other elements in the 2nd row are zero elements. The first non-zero element in the second row of the second matrix is ​​replaced by the first column of the third matrix; the second non-zero element in the second row of the second matrix is ​​replaced by the second column of the third matrix; the third non-zero element in the second row of the second matrix is ​​replaced by the third column of the third matrix; the fourth non-zero element in the second row of the second matrix is ​​replaced by the fourth column of the third matrix; the fifth non-zero element in the second row of the second matrix is ​​replaced by the fifth column of the third matrix; the sixth non-zero element in the second row of the second matrix is ​​replaced by the sixth column of the third matrix; the seventh non-zero element in the second row of the second matrix is ​​replaced by the seventh column of the third matrix; and the eighth non-zero element in the second row of the second matrix is ​​replaced by the eighth column of the third matrix. Each element in the other elements of the second row is replaced with a 4×1 matrix of all zeros, thus obtaining X1 rows of the first matrix. Figure 11 The X1 rows of the first matrix shown are rows 2 to 5 of the first matrix.

[0154] Furthermore, the remaining rows in the first matrix, excluding the X1 rows, are the same as the remaining rows in the second matrix, excluding the N1 rows. Figure 11 The remaining rows of the first matrix, excluding X1 rows, are rows 1 and 6-13 of the first matrix. The remaining rows of the second matrix, excluding N1 rows, are rows 1 and 3-10 of the second matrix. The first row of the first matrix is ​​the same as the first row of the second matrix, and rows 6-13 of the first matrix are the same as rows 3-10 of the second matrix.

[0155] In Example 2, the highest bitrate of the second matrix is ​​8 / 12 = 2 / 3, and the highest bitrate of the first matrix is ​​(8-3) / 12 = 5 / 12. It can be seen that the bitrate of the first matrix is ​​reduced after replacing the second row of the second matrix with a third matrix. However, compared with the first matrix obtained by replacing all rows of the second matrix with a third matrix, the highest bitrate of the first matrix obtained in this embodiment is higher, thus making the applicable range of bitrate wider.

[0156] Example 3: [The rest of the text appears to be a list of characters and symbols, possibly related to a computer program or similar device. Figure 10 and Figure 11 The combination is performed, i.e., N=10, N1=2, and the rows of the second matrix that need to be replaced are the first and second rows of the second matrix. The replacement method for the first row of the second matrix is ​​detailed above. Figure 10 For the corresponding description and the replacement method for the second row of the second matrix, please refer to the above. Figure 11 The corresponding description will not be repeated here. In this example, the first row of the second matrix corresponds to the first third matrix among the N1 third matrices, that is, the first row of the second matrix is ​​replaced by the first third matrix among the N1 third matrices; the second row of the second matrix corresponds to the second third matrix among the N1 third matrices, that is, the second row of the second matrix is ​​replaced by the second third matrix among the N1 third matrices.

[0157] The above examples respectively show that a row of the second matrix (e.g., row 1 or row 2) is replaced by a third matrix, and each row of two rows of the second matrix (e.g., row 1 and row 2) is replaced by a third matrix. In fact, the replacement of each row of some rows of all rows of the second matrix by a third matrix is ​​within the scope of protection of this application, and this application does not limit it.

[0158] In Example 3, the highest bitrate of the second matrix is ​​8 / 12 = 2 / 3, and the highest bitrate of the first matrix is ​​(8-2-3) / 12 = 1 / 4. It can be seen that the bitrate of the first matrix after replacing the first and second rows of the second matrix with the third matrix is ​​lower. However, compared to the first matrix obtained by replacing all rows of the second matrix with the third matrix, the highest bitrate of the first matrix obtained in this embodiment is higher, thus allowing for a wider applicable bitrate range.

[0159] Optionally, the N1 rows of the second matrix described above include a portion of the rows of the core matrix of the second matrix. In other words, the N1 rows of the second matrix described above include a portion of the rows of the core matrix of the second matrix, rather than all of them. For example, Figure 10 The N1 rows shown are the first row of the core matrix of the second matrix, or... Figure 11 The N1 rows shown are the second row of the core matrix of the second matrix, or... Figure 10 and Figure 11 The N1 rows of the combination are the first and second rows of the second matrix.

[0160] When the first matrix mentioned above is the base matrix, it is also necessary to obtain a first parity check matrix based on the first matrix, and perform LDPC encoding or LDPC decoding based on the first parity check matrix. Specifically, each non-zero element in the first matrix can be expanded into a Z×Z cyclic shift matrix, and each zero element in the first matrix can be expanded into a Z×Z all-zero matrix.

[0161] II. The first and second matrices are check matrices.

[0162] If the second matrix and the first matrix are parity check matrices, the second matrix can be obtained based on the first basis matrix. Specifically, each non-zero element in the first basis matrix can be expanded into a Z×Z cyclic shift matrix, and each zero element in the first basis matrix can be expanded into a Z×Z all-zero matrix.

[0163] The embodiments of this application are as follows: Figure 10 Or such as Figure 11 The following example uses a 10×18 matrix as the first basis matrix. The core matrix of this first basis matrix is ​​4×12, the information columns of the core matrix are columns 1 to 8, and the core check columns of the core matrix are columns 9 to 12.

[0164] like Figure 12 As shown, Figure 12 The elements of the core matrix in the first row of the first basis matrix are shown. Assuming Z = 3, each non-zero element in the first row of the first basis matrix is ​​expanded into a 3×3 cyclic shift matrix, and each zero element in the first row of the first basis matrix is ​​expanded into a 3×3 all-zero matrix. The other rows of the first basis matrix are similarly expanded to obtain the second matrix. The size of the second matrix after expanding the first basis matrix is ​​(10×3)×(18×3) = 30×54, and the size of the core matrix of the second matrix is ​​(4×3)×(12×3) = 12×36.

[0165] Example 4: Figure 12 As shown, assume N = 10, N1 = 1, and the row of the second matrix that needs to be replaced is the first row of the second matrix. Figure 12 The row weight of the first row of the second matrix shown is 7, therefore the number of columns of the third matrix corresponding to the first row is also 7. Specifically, the number of rows of the third matrix is ​​P, and the number of rows P of the third matrix can be less than the number of columns of the third matrix. This application uses a third matrix with 3 rows as an example for illustration. Figure 12 An example of a third matrix of size 3×7 is also shown.

[0166] Specifically, the j-th non-zero element in the i-th row of the N1 rows of the second matrix is ​​replaced by the j-th column of the i-th third matrix in the N1 third matrices, and each zero element in the i-th row of the N1 rows is replaced by a P×1 matrix of all zeros, resulting in P rows in the X1 rows of the first matrix. Here, 1≤i≤N1, and i, j, and p are all positive integers.

[0167] For example, Figure 12The element in the first row and first column of the second matrix shown is the first non-zero element in the first row; the element in the first row and fifth column is the second non-zero element in the first row; the element in the first row and ninth column is the third non-zero element in the first row; the element in the first row and tenth column is the fourth non-zero element in the first row; the element in the first row and twentyth column is the fifth non-zero element in the first row; the element in the first row and twenty-seventh column is the sixth non-zero element in the first row; and the element in the first row and twenty-eighth column is the seventh non-zero element in the first row. All other elements in the first row are zero elements. The first non-zero element in the first row of the second matrix is ​​replaced by the first column of the third matrix; the second non-zero element in the first row of the second matrix is ​​replaced by the second column of the third matrix; the third non-zero element in the first row of the second matrix is ​​replaced by the third column of the third matrix; the fourth non-zero element in the first row of the second matrix is ​​replaced by the fourth column of the third matrix; the fifth non-zero element in the first row of the second matrix is ​​replaced by the fifth column of the third matrix; the sixth non-zero element in the first row of the second matrix is ​​replaced by the sixth column of the third matrix; and the seventh non-zero element in the first row of the second matrix is ​​replaced by the seventh column of the third matrix. Each other element in the first row is replaced with a 3×1 matrix of all zeros, thus obtaining X1 rows of the first matrix. Figure 12 The X1 rows of the first matrix shown are rows 1 to 3 of the first matrix.

[0168] Furthermore, the remaining rows in the first matrix, excluding the X1 rows, are the same as the remaining rows in the second matrix, excluding the N1 rows. Figure 12 The remaining rows of the first matrix, excluding the X1 rows, are rows 4 to 32 of the first matrix. The remaining rows of the second matrix, excluding the N1 rows, are rows 2 to 30 of the second matrix. Rows 4 to 32 of the first matrix are the same as rows 2 to 30 of the second matrix.

[0169] In Example 4, the highest bitrate of the second matrix is ​​(8×3) / (12×3) = 2 / 3, and the highest bitrate of the first matrix is ​​(8×3-2) / (12×3) = 11 / 18. It can be seen that replacing the first row of the second matrix with a third matrix reduces the bitrate of the first matrix. However, compared to the first matrix obtained by replacing all rows of the second matrix with a third matrix, the highest bitrate of the first matrix obtained in this embodiment is higher, thus making the applicable bitrate range wider. Furthermore, compared to Example 1 above, Example 4 obtains a higher highest bitrate for the first matrix, further expanding the applicable bitrate range.

[0170] For example, each of the above N1 third matrices is a linear algebra matrix. For instance, each third matrix can be a matrix of Hamming code, BCH code, RS code, Polar code, or LDPC code. This application does not limit the specific form of the third matrix.

[0171] In step S912, the encoding device performs LDPC encoding or LDPC decoding on the bit sequence to be encoded based on the first matrix to obtain the encoded sequence.

[0172] For example, when the first matrix and the second matrix are base matrices, the communication device obtains a first parity check matrix based on the first matrix and performs LDPC encoding or LDPC decoding based on the first parity check matrix; when the first matrix and the second matrix are parity check matrices, the communication device performs LDPC encoding or LDPC decoding based on the first matrix.

[0173] For example, the encoding device can divide the bit sequence to be encoded into groups of 'a' bits each, and then the encoder performs linear operations on these 'a' information bits to obtain 'g' parity bits. These 'a' information bits and 'g' parity bits are then combined to obtain an encoded sequence of length v = a + g. The mapping relationship from information bits of length 'a' to codewords of length 'v' can be represented by the aforementioned first matrix or first parity check matrix. The encoding process can be completed by generating an encoded sequence based on the aforementioned first matrix or first parity check matrix.

[0174] In step S914, the encoding device sends the encoded sequence to the decoding device.

[0175] In step S916, the decoding device acquires the first matrix.

[0176] Specifically, the method by which the decoding device obtains the first matrix can refer to the method by which the encoding device obtains the first matrix in step S910 above, and will not be repeated here.

[0177] In step S918, the decoding device performs LDPC decoding on the encoded sequence based on the first matrix to obtain the decoded bit sequence.

[0178] The LDPC-based encoding and decoding methods provided in this application not only save on the storage overhead of the parity check matrix, but also make the code rate applicable range of the parity check matrix wider.

[0179] Figure 13 This is a performance simulation diagram provided in the embodiments of this application. Figure 13 The horizontal axis represents the symbol signal-to-noise ratio (Es / N0), which is the ratio of the energy (Es) of each symbol to the noise power spectral density (N0). The vertical axis represents BLER. Es / N0 is directly proportional to SNR, and their conversion relationship is as follows:

[0180] For complex signals: Es / N0(dB) = 10log 10 (Tsym / T samp )+SNR(dB);

[0181] For a real signal: Es / N0(dB) = 10log 10 (0.5T sym / T samp )+SNR(dB);

[0182] The units are all decibels (dB), Tsym represents the symbol period, and Tsamp represents the sampling interval.

[0183] This shows that the larger Es / N0 is, the larger the SNR is; the smaller Es / N0 is, the smaller the SNR is. Therefore, the relationship between Es / N0 and BLER reveals the relationship between signal-to-noise ratio and BLER.

[0184] Figure 13 The figure shows the BLER performance simulation results of a first matrix with a code rate of 0.33 and an information bit length K of 160 provided in this application embodiment, as well as the BLER performance simulation results of a conventional 5G LDPC matrix with a code rate of 0.33 and an information bit length K of 160. As can be seen from the figure, throughout the entire symbol signal-to-noise ratio range, the BLER curve of the first matrix provided in this application embodiment is below the BLER curve of the conventional 5G LDPC matrix. That is, the BLER of the first matrix decoding provided in this application embodiment is 0.2 dB lower than that of the conventional 5G LDPC matrix decoding, indicating that the first matrix provided in this application embodiment has better decoding performance.

[0185] The communication device provided in this application is described below.

[0186] Figure 14 This is a schematic structural diagram of the communication device 1000 provided in this application. The communication device 1000 can be an encoding-side device, or a device applied to the encoding-side device and capable of implementing the corresponding functions of the encoding-side device in the method embodiments of this application, such as a chip, processor, or circuit. Alternatively, the communication device 1000 can be a decoding-side device, or a device applied to the decoding-side device and capable of implementing the corresponding functions of the decoding-side device in the method embodiments of this application, such as a chip, processor, or circuit.

[0187] Optionally, the communication device 1000 includes a processing module 1001, which may be a processor, a processing board, a processing unit, or a processing device, etc. When the communication device 1000 is an encoding-side device or a device applied to an encoding-side device, the processing module 1001 is used for LDPC encoding based on a first matrix, etc. Specific processes can be found in the detailed descriptions of the corresponding steps in the method embodiments, and will not be repeated here. When the communication device 1000 is a decoding-side device or a device applied to a decoding-side device, the processing module 1001 is used for LDPC decoding based on a first matrix, etc. Specific processes can be found in the detailed descriptions of the corresponding steps in the method embodiments, and will not be repeated here.

[0188] Optionally, the communication device 1000 further includes a communication module 1002, which may also be referred to as a transceiver module, transceiver, transceiver unit, or transceiver device, etc., for performing receiving (or input) and / or sending (or output) operations. For example, when the communication device 1000 is an encoding-side device or a device applied to an encoding-side device, the communication module 1002 can be used to acquire a bit sequence to be encoded and transmit the bit sequence to be encoded to the processing module 1001; and output the encoded sequence obtained by the processing module 1001. Similarly, when the communication device 1000 is a decoding-side device or a device applied to a decoding-side device, the communication module 1002 can be used to receive an encoded sequence and send the encoded sequence to the processing module 1001; and output the decoded bit sequence obtained by the processing module 1001 decoding the encoded sequence. Furthermore, it should be noted that the aforementioned communication module and / or processing module can be implemented through virtual modules. For example, the processing module can be implemented through a software functional unit or a virtual device, and the communication module can be implemented through a software function or a virtual device. Alternatively, the processing module or communication module can also be implemented by a physical device, such as a chip / circuit (e.g., an integrated circuit or logic circuit). The communication module can be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operation) and output operations (corresponding to the aforementioned sending operation); the processing module is an integrated processor, microprocessor, or circuit (e.g., an integrated circuit, logic circuit).

[0189] The module division in this application is illustrative and represents only one logical functional division. In actual implementation, other division methods are possible. Furthermore, the functional modules in the various examples of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware, as software functional modules, or a combination of hardware and software.

[0190] Figure 15This is a schematic structural diagram of another communication device 1100 provided in this application. The communication device 1100 can be used to implement the functions of any communication device (e.g., an encoding-side device or a decoding-side device) in the communication system described in the foregoing examples. The communication device 1100 may include at least one processor 1110. Optionally, the processor 1110 (or processing device) is coupled to a memory, which may be located within the communication device, integrated with the processor, or located outside the communication device. For example, the communication device 1100 may also include at least one memory 1120. The memory 1120 stores computer programs, instructions, or data necessary for implementing any of the above method embodiments; the processor 1110 may execute the computer programs, instructions, or data stored in the memory 1120 to perform the corresponding functions of the encoding-side device or decoding-side device in any of the above embodiments.

[0191] Optionally, the communication device 1100 may further include a communication interface 1130, through which the communication device 1100 can interact with other devices. For example, the communication interface 1130 may be a transceiver, circuit, bus, module, pin, or other type of communication interface. When the communication device 1100 is a chip-type device or circuit, the communication interface 1130 in the device 1100 may also be an input / output circuit, capable of inputting information (or receiving information) and / or outputting information (or sending information). The processor may be an integrated circuit or logic circuit, etc., and the processor can determine the output information based on the input information.

[0192] The coupling in this application refers to indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, used for information exchange between devices, units, or modules. The processor 1110 may operate in conjunction with the memory 1120 and the communication interface 1130. This application does not limit the connection medium between the processor 1110, the memory 1120, and the communication interface 1130.

[0193] Figure 16 This is a schematic structural diagram of the chip provided in this application. Chip 30 includes circuit 31 and communication interface 32. Circuit 31 can be a logic circuit, integrated circuit, etc., and communication interface 32 can also be called input / output circuit, input / output interface, interface circuit, etc., which can input information (or receive information) or output information (or send information). Chip 30 can execute the methods executed by the encoding-side device or decoding-side device in the various embodiments of this application.

[0194] In addition, this application also provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause operations and / or processes performed by an encoding-side device or a decoding-side device in the various method embodiments of this application to be executed.

[0195] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the encoding-side device or decoding-side device in the various method embodiments of this application are executed.

[0196] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by an encoding-side device or a decoding-side device in any method embodiment are executed. Further, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Further, the chip may also include the memory.

[0197] This application provides a communication system, including the encoding-side device and decoding-side device in the above method embodiments.

[0198] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0199] In the embodiments of this application, "instruction" can include direct instruction, indirect instruction, explicit instruction, and implicit instruction. When describing a certain instruction information for instructing A, it can be understood that the instruction information carries A, which can be a direct instruction to A or an indirect instruction to A. Indirect instruction can refer to directly instructing B through the instruction information, and the correspondence between B and A, to achieve the purpose of instructing A through the instruction information. The correspondence between B and A can be predefined by the protocol, pre-stored, or obtained through configuration between network elements.

[0200] The processor in this application embodiment has signal processing capabilities and can be a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in this application can be directly implemented by the hardware processor, or implemented by a combination of hardware and software modules within the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0201] In the embodiments of this application, the memory can be volatile memory or non-volatile memory, or it can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0202] The technical solutions provided in this application can be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal device, an access network device, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media, etc.

[0203] In the embodiments of this application, "at least one" refers to one or more items. "More than one" means two or more items. "And / or" is used to describe the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0204] The term "comprising" and any variations thereof used in the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0205] In this application, examples may reference each other without logical contradiction. For example, methods and / or terms between method embodiments may reference each other, functions and / or terms between device embodiments may reference each other, and functions and / or terms between device examples and method examples may reference each other.

[0206] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0207] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0208] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0209] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0210] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0211] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A coding method based on low-density parity-check code (LDPC), characterized by, include: Obtain a first matrix of size X×Y. The X1 rows of the first matrix are obtained based on the N1 rows of the second matrix and N1 third matrices. The N1 rows of the second matrix correspond one-to-one with the N1 third matrices. The number of columns of each of the N1 third matrices is the same as the row weight of the corresponding row in the N1 rows of the second matrix. The remaining rows in the first matrix other than the X1 rows are the same as the remaining rows in the second matrix other than the N1 rows. Where N1 < X1 < X, and X, Y, X1, and N1 are all positive integers. Based on the first matrix, the bit sequence to be encoded is LDPC encoded to obtain the encoded sequence.

2. A decoding method based on low-density parity-check (LDPC), characterized by, include: Obtain a first matrix of size X×Y. The X1 rows of the first matrix are obtained based on the N1 rows of the second matrix and N1 third matrices. The N1 rows of the second matrix correspond one-to-one with the N1 third matrices. The number of columns of each of the N1 third matrices is the same as the row weight of the corresponding row in the N1 rows of the second matrix. The remaining rows in the first matrix other than the X1 rows are the same as the remaining rows in the second matrix other than the N1 rows. Where N1 < X1 < X, and X, Y, X1, and N1 are all positive integers. The encoded sequence is then subjected to LDPC decoding based on the first matrix to obtain the decoded bit sequence.

3. The method according to claim 1 or 2, characterized in that, If the number of rows in the i-th third matrix among the N1 third matrices is P, The X1 rows in the first matrix are obtained based on the N1 rows in the second matrix and the N1 third matrices, including: the j-th non-zero element of the i-th row in the N1 rows is replaced by the j-th column of the i-th third matrix in the N1 third matrices, and each zero element of the i-th row in the N1 rows is replaced by a P×1 matrix of all zeros, thus obtaining the P rows in the X1 rows; The N1 rows of the second matrix correspond one-to-one with the N1 third matrices, including: the i-th row of the N1 rows corresponds to the i-th third matrix of the N1 third matrices; Where 1≤i≤N1, and i, j, and P are all positive integers.

4. The method according to any one of claims 1 to 3, characterized in that, The N1 rows of the second matrix include some rows from the core matrix of the second matrix.

5. The method according to any one of claims 1 to 4, characterized in that, If the first matrix and the second matrix are basis matrices The step of performing LDPC encoding based on the first matrix includes: obtaining a first parity check matrix based on the first matrix; and performing LDPC encoding or LDPC decoding based on the first parity check matrix. The step of obtaining the first check matrix based on the first matrix includes: expanding each non-zero element in the first matrix into a Z×Z cyclic shift matrix, and expanding each zero element in the first matrix into a Z×Z all-zero matrix to obtain the first check matrix, where Z is a positive integer greater than or equal to 1.

6. The method according to any one of claims 1 to 4, characterized in that, If the first matrix and the second matrix are parity check matrices, the second matrix is ​​obtained based on the first basis matrix; The second matrix is ​​obtained based on the first base matrix, including: each non-zero element in the first base matrix is ​​expanded into a Z×Z cyclic shift matrix, and each zero element in the first base matrix is ​​expanded into a Z×Z all-zero matrix, to obtain the second matrix, where Z is a positive integer greater than or equal to 1.

7. The method according to any one of claims 1 to 6, characterized in that, Each of the N1 third matrices is a linear algebraic matrix.

8. An encoding device, characterized in that, include: A communication module is used to obtain a first matrix, the first matrix having a size of X×Y. The X1 rows of the first matrix are obtained based on the N1 rows of the second matrix and N1 third matrices. The N1 rows of the second matrix correspond one-to-one with the N1 third matrices. The number of columns in each of the N1 third matrices is the same as the row weight of the corresponding row in the N1 rows of the second matrix. The remaining rows in the first matrix, excluding the X1 rows, are the same as the remaining rows in the second matrix, excluding the N1 rows. Wherein, N1 < X1 < X, and X, Y, X1, and N1 are all positive integers. The processing module is used to perform LDPC encoding on the bit sequence to be encoded based on the first matrix to obtain the encoded sequence; The communication module is also used to output the encoded sequence.

9. A decoding device, characterized in that, include: A communication module is used to obtain a first matrix, the first matrix having a size of X×Y. The X1 rows of the first matrix are obtained based on the N1 rows of the second matrix and N1 third matrices. The N1 rows of the second matrix correspond one-to-one with the N1 third matrices. The number of columns in each of the N1 third matrices is the same as the row weight of the corresponding row in the N1 rows of the second matrix. The remaining rows in the first matrix, excluding the X1 rows, are the same as the remaining rows in the second matrix, excluding the N1 rows. Wherein, N1 < X1 < X, and X, Y, X1, and N1 are all positive integers. The processing module is used to perform LDPC decoding on the encoded sequence based on the first matrix to obtain the decoded bit sequence; The communication module is also used to output the decoded bit sequence.

10. A communication device, characterized in that, The system includes a communication interface and circuitry. The communication interface is used to acquire information required to perform the method as described in any one of claims 1, 3-7, and to send the information to the circuitry, which is used to perform the method as described in any one of claims 1, 3-7 based on the received information; or... The communication interface is used to acquire information required to perform the method as described in any one of claims 2-7, and to send the information to the circuit, which is used to perform the method as described in any one of claims 2-7 based on the received information.

11. A communication device, characterized in that, Includes modules or units for performing the method as described in any one of claims 1-7.

12. A communication device, characterized in that, The device includes a processor coupled to a memory, the processor being configured to execute a computer program or instructions stored in the memory to cause the communication device to perform the method as described in any one of claims 1-7.

13. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer, implement the method as described in any one of claims 1-7.

Images