Clock synchronization circuit and system

Abstract

The invention provides a clock synchronization circuit and system which can be applied to the technical field of signal transmission. The clock synchronization circuit comprises: a first node comprising: a first port unit configured to send downlink data to a second node via a downlink according to a first sending reference clock obtained based on an input reference clock, and obtain a first recovery clock according to uplink data returned by the second node via an uplink, performing phase adjustment on the first sending reference clock according to the first phase adjustment step length number; a second port unit configured to output a first measurement reference clock according to an input reference clock; the first phase measurement unit is configured to sample an input reference clock and a first recovery clock according to a first measurement reference clock and output a first phase adjustment step length number; and the second node is configured to obtain the second recovery clock according to the downlink data received by the downlink, and send the uplink data through the uplink according to the second sending reference clock.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal transmission, and more particularly to a clock synchronization circuit and system. BACKGROUND

[0002] In high-energy physics experiments or distributed detection nodes in distributed measurement and control systems, the clock synchronization stability needs to be kept at the picosecond level to realize the accuracy of data acquisition, triggering and event matching.

[0003] In some applications, the clock is transmitted through a cable to reduce costs, but due to the influence of factors such as attenuation or electromagnetic interference, the clock signal is distorted, so in a high-precision clock distribution and synchronization system, an optical fiber link is usually used to ensure the quality of the clock signal. However, link temperature changes and circuit power-on and power-off will still cause clock delay drift. Therefore, delay compensation needs to be performed on the clock signal to maintain clock synchronization between distributed nodes. However, the clock synchronization circuit in the related art has a complex circuit structure and low integration. SUMMARY

[0004] Therefore, the embodiments of the present application provide a clock synchronization circuit and system.

[0005] One aspect of the embodiments of the present application provides a clock synchronization circuit, comprising: a first node, the first node comprising: a first port unit configured to transmit downlink data to a second node via a downlink according to a first transmission reference clock obtained based on an input reference clock, and obtain a first recovered clock according to uplink data returned by the second node via an uplink, and perform phase adjustment on the first transmission reference clock according to a first phase adjustment step number from a first phase measurement unit; a second port unit configured to output a first measurement reference clock with a different frequency from the input reference clock according to the input reference clock; a first phase measurement unit configured to sample the input reference clock and the first recovered clock according to the first measurement reference clock, and output a first phase adjustment step number to the first port unit; and the second node configured to obtain a second recovered clock according to the downlink data received by the downlink, and transmit the uplink data to the first node via the uplink according to a second transmission reference clock obtained based on the second recovered clock.

[0006] According to an embodiment of the present application, the first port unit comprises: a first sending port subunit configured to send the downlink data to the second node via the downlink according to the first sending reference clock obtained based on the input reference clock; a first receiving port subunit configured to obtain the first recovery clock based on the uplink data returned by the second node via the uplink; and a first phase adjustment subunit configured to adjust the phase of the first sending reference clock according to the first phase adjustment step number from the first phase measurement unit based on the phase adjustment step of the first phase adjustment subunit.

[0007] According to an embodiment of the present application, the second port unit comprises: a second phase adjustment subunit configured to adjust the phase of the input reference clock and output the first measurement reference clock, wherein the period difference between the first measurement reference clock and the input reference clock is 2X times of the phase adjustment step of the first phase adjustment subunit, and X is a positive integer.

[0008] According to an embodiment of the present application, the first phase measurement unit comprises: a first input port configured to receive the input reference clock; a second input port configured to receive the first recovery clock; a third input port configured to receive the first measurement reference clock; a first reference clock output unit configured to sample the input reference clock according to the first measurement reference clock and output a first beat clock; a second reference clock output unit configured to sample the first recovery clock according to the first measurement reference clock and output a second beat clock; and an output port configured to output the first phase adjustment step number according to the phase difference between the first beat clock and the second beat clock.

[0009] According to an embodiment of the present application, the first node further comprises: a second phase measurement unit configured to output a second phase adjustment step number to the first port unit according to the first measurement reference clock, the input reference clock and the first sending reference clock; and the first port unit is further configured to adjust the phase of the first sending reference clock according to the second phase adjustment step number.

[0010] According to an embodiment of the present application, the second node comprises: a third port unit configured to receive the downlink data via the downlink, obtain the second recovery clock, and send the uplink data to the first node via the uplink according to the second sending reference clock obtained based on the second recovery clock.

[0011] According to an embodiment of the present application, the second node further comprises: a fourth port unit, configured to output a second measurement reference clock with a frequency different from the second recovered clock according to the second recovered clock; and a third phase measurement unit, configured to output a third phase adjustment step number to the third port unit according to the second measurement reference clock, the second recovered clock and the second transmission reference clock.

[0012] According to an embodiment of the present application, the third port unit comprises: a second receiving port subunit, configured to receive the downlink data via the downlink to obtain the second recovered clock; a second transmission port subunit, configured to transmit the uplink data to the first node via the uplink according to the second transmission reference clock obtained based on the second recovered clock; and a third phase adjustment subunit, configured to receive the third phase adjustment step number and adjust the phase of the second transmission reference clock according to the third phase adjustment step number based on a phase adjustment step of the third phase adjustment subunit.

[0013] According to an embodiment of the present application, the downlink and the uplink are implemented by at least one of dense wavelength division multiplexing optics or fiber loopback.

[0014] Another aspect of the embodiments of the present application provides a clock synchronization system, comprising: a clock source, configured to provide an input reference clock; and a clock synchronization circuit as described above.

[0015] According to an embodiment of the present application, the first node comprises not only the first port unit that can be used for data interaction with the second node, but also a second port unit and a first phase measurement unit. The second port unit can output a first measurement reference clock as a sampling reference clock of the first phase measurement unit. The first phase measurement unit can sample the input reference clock and the first recovered clock based on the first measurement reference clock to obtain a first phase adjustment step number. The first port unit can adjust the phase of the first transmission reference clock according to the first phase adjustment step number. The embodiments of the present application can integrate the phase measurement of the input reference clock and the first recovered clock, the adjustment and control of the first transmission reference clock in the first node, so that the integration degree is high, and the second port unit and the first phase measurement unit can be added to the first node to achieve the structure, which is simple. In addition, the embodiments of the present application can reduce the interaction of delay variation information between the first node and the second node, and reduce the occupation of data link bandwidth. BRIEF DESCRIPTION OF DRAWINGS

[0016] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application, taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 A schematic diagram of a clock synchronization circuit is shown in one example.

[0018] Figure 2 A schematic diagram of a clock synchronization circuit according to embodiments of the present application is shown.

[0019] Figure 3 A schematic diagram of a phase measurement circuit according to embodiments of the present application is shown.

[0020] Figure 4 A waveform diagram of an input clock and an output clock of a phase measurement circuit according to embodiments of the present application is shown.

[0021] Figure 5 A schematic diagram of a phase adjustment circuit according to embodiments of the present application is shown.

[0022] Figure 6 A schematic diagram of a clock synchronization circuit according to embodiments of the present application is shown.

[0023] Figure 7 A schematic diagram of a clock synchronization circuit according to embodiments of the present application is shown.

[0024] Figure 8 A block diagram of a clock synchronization system according to embodiments of the present application is shown. DETAILED DESCRIPTION

[0025] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It is to be understood, however, that the description is merely exemplary of the present application, and is not intended to limit the scope of the present application. In the following detailed description of the embodiments of the present application, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without these specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring aspects of the present application.

[0026] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the term "includes" and tautological expressions thereof, such as "including," "includes," "include," "contains," "containing," and so forth, shall not be taken to exclude

[0027] All terms used herein including technical and scientific terms have the same meanings as commonly understood by one of ordinary skill in the art unless otherwise defined herein. It should be noted that the terms "comprises", "comprising", or other variations such as "comprises", "comprising", and / or "including", used herein, shall not be interpreted as a limitation on the present application but rather as an acknowledgement of the presence of a stated feature, step, operation, and / or component. It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application.

[0028] In the case of using expressions like "at least one of A, B, and C", it will be understood that such phrases are meant to encompass the options for "A only," "B only," "C only," "A and B but not C," "A and C but not B," "B and C but not A," and "A and B and C," as well as combinations that have fewer than all of the elements listed.

[0029] In high-precision clock distribution and synchronization systems, optical fiber links are usually employed in combination with fiber-based clock distribution and automatic synchronization protocols to achieve high-precision phase alignment. The following will be described in combination with Figure 1 illustrations.

[0030] Figure 1 A schematic diagram of a clock synchronization circuit in one example is shown.

[0031] As Figure 1 shown in the clock synchronization circuit, the transmitting end (TX) of the first node embeds the input reference clock into a serial data stream, which can be converted into an optical signal (i.e., downlink data) by electro-optical conversion and transmitted to the second node by an optical fiber. Before the second node, the optical signal is first converted into an electrical signal by photoelectric conversion, and the receiving end (RX) of the second node can obtain a second recovered clock from the serial data stream through the embedded clock data recovery circuit. In order to maintain the stability of synchronization, the second recovered clock also needs to be sent to the first node in the same way, and the transmitting end (TX) of the second node embeds the second recovered clock into a serial data stream, which can be converted into an optical signal (i.e., uplink data) by electro-optical conversion and transmitted to the first node by an optical fiber. The first node can obtain a first recovered clock through the clock data recovery circuit to form a complete data transmission loop. In the loop, the input reference clock is transmitted from the first node to the second node and then transmitted from the second node to the first node, wherein the transmission time in the downlink is t LF , the transmission time in the uplink is t FL , and the total transmission time of the loop is t loop .

[0032] In a synchronous protocol based on a fiber link (such as the White Rabbit protocol) and similar circuit architectures, a phase adjustment circuit is located at the second node. In order to compensate for the delay of the downlink changing with temperature, the first node needs to continuously send the loop delay change information to the second node, which occupies the data link bandwidth. Although the synchronous protocol based on the fiber link can adaptively compensate for the link delay caused by the temperature change, the circuit implementation relies on an analog loop and an external clock device, resulting in high circuit complexity and low integration. Moreover, the performance of the circuit is limited by the temperature drift compensation accuracy or the link asymmetry, and can only maintain a synchronization stability of tens of picoseconds to hundreds of picoseconds. In addition, the delay stability of these schemes after power-on of the electronic system is also difficult to achieve picosecond level.

[0033] In view of this, the embodiment of the present application proposes a clock synchronization circuit, which integrates a second port unit capable of outputting a first measurement reference clock and a first phase measurement unit for phase measurement at the first node, so that the first measurement reference clock output by the second port unit can be used as the sampling reference clock of the first phase measurement unit at the first node, and the first phase measurement unit can sample the input reference clock and the first recovered clock based on the first measurement reference clock, thereby obtaining the first phase adjustment step number. The first port unit can adjust the phase of the first transmission reference clock according to the first phase adjustment step number. The embodiment of the present application can integrate the phase measurement of the input reference clock and the first recovered clock, the adjustment and control of the first transmission reference clock in the first node, which has high integration, and only needs to add the second port unit and the first phase measurement unit in the first node to realize, which has simple structure, can also reduce the interaction of delay change information between the first node and the second node, and reduce the occupation of the data link bandwidth.

[0034] Figure 2 A schematic diagram of a clock synchronization circuit according to an embodiment of the present application is shown.

[0035] As shown in Figure 2 The clock synchronization circuit 200 can include a first node 210 and a second node 220.

[0036] The first node 210 can include a first port unit 211, a second port unit 212, and a first phase measurement unit 213.

[0037] The first port unit 211 can be configured to transmit downlink data to the second node via the downlink according to the first transmission reference clock obtained based on the input reference clock, and obtain the first recovered clock according to the uplink data returned by the second node via the uplink, and adjust the phase of the first transmission reference clock according to the first phase adjustment step number from the first phase measurement unit.

[0038] The second port unit 212 can be configured to output a first measurement reference clock with a frequency different from the input reference clock according to the input reference clock.

[0039] The first phase measurement unit 213 can be configured to sample the input reference clock and the first recovery clock according to the first measurement reference clock, and output a first phase adjustment step number to the first port unit.

[0040] The second node 220 can be configured to obtain a second recovery clock according to downlink received downlink data, and send uplink data to the first node via an uplink according to a second sending reference clock obtained based on the second recovery clock.

[0041] The first port unit can be a unit for sending and receiving data. The input reference clock can be a clock taken as a reference at the first node. The downlink data can be data containing information sent by the first node to the second node. The uplink data can be data containing information sent by the second node to the first node. The first sending reference clock can be obtained at the first port unit with the input reference clock as a reference, the downlink data is sent to the second node based on the first sending reference clock, and the first recovery clock is obtained according to the uplink data returned by the second node. Due to the transmission through the downlink and the uplink, the first recovery clock will be delayed compared with the input reference clock, so it is necessary to adjust the phase of the first sending reference clock of the first port unit to compensate for the delay, so that the delay between the first recovery clock and the input reference clock is reduced.

[0042] The first measurement reference clock with a frequency different from the input reference clock can be output by the second port unit, and the first measurement reference clock can be taken as a reference clock for sampling the first recovery clock and the input reference clock by the first phase measurement unit, so that the second port unit can measure the phase difference between the first recovery clock and the input reference clock based on the first measurement reference clock.

[0043] Since the first recovery clock is obtained after the input reference clock is transmitted in the downlink and the uplink, the first recovery clock is a clock with the same frequency as the input reference clock but different phase. Therefore, there is a frequency difference between the first measurement reference clock and the first recovery clock and the input reference clock. Based on this, the phase difference between the first measurement reference clock and the first recovery clock and the input reference clock can be determined, and the first recovery clock and the input reference clock can be sampled. After the first measurement reference clock accumulates for a certain period, an amplified representation of the phase difference between the first recovery clock and the input reference clock can be obtained, so that the first phase adjustment step number can be output based on the number of periods accumulated by the first measurement reference clock. The first phase adjustment step number can be the number of times of phase adjustment of the first sending reference clock by the first port unit.

[0044] According to the embodiment of the present application, the first node not only includes the first port unit which can be used for data interaction between the first node and the second node, but also includes the second port unit and the first phase measurement unit, the second port unit can output the first measurement reference clock as the sampling reference clock of the first phase measurement unit, and the first phase measurement unit can sample the input reference clock and the first recovery clock based on the first measurement reference clock, so as to obtain the first phase adjustment step number, so that the first port unit can adjust the phase of the first sending reference clock according to the first phase adjustment step number, the embodiment of the present application can integrate the phase measurement of the input reference clock and the first recovery clock, the adjustment and control of the first sending reference clock in the first node, so that the integration degree is high, and the second port unit and the first phase measurement unit can be added in the first node, so that the structure is simple, and the interaction of the delay variation information between the first node and the second node can be reduced, and the occupation of the data link bandwidth can be reduced.

[0045] According to the embodiment of the present application, the downlink and the uplink are implemented by at least one of dense wavelength division multiplexing optics or a fiber circulator.

[0046] Since the influence of temperature on the transmission delay of the optical fiber link is much greater than the influence on the circuit delay, selecting a suitable delay symmetric optical link (such as using dense wavelength division multiplexing optics or a fiber circulator) for the uplink and the downlink can be considered that the delay variation of the uplink and the downlink is symmetric, so that the delay variation amount of the uplink and the downlink is the same.

[0047] The delay variation amount of the first recovery clock in the loopback (the loopback refers to the process that the input reference clock is transmitted from the first node to the second node, and then transmitted from the second node to the first node) can satisfy the following formula (1).

[0048] (1);

[0049] Wherein, is the delay variation amount of the downlink, is the delay variation amount of the loopback, that is, the total delay variation amount of the downlink and the uplink.

[0050] In the clock synchronization circuit, only the delay stability of the downlink needs to be ensured, and the uplink delay does not need to be concerned. Therefore, the main problem is how to measure the delay variation amount of the entire loopback in the first node , and then the delay variation amount of the downlink , so as to compensate the delay variation of the downlink. Since the influence of temperature on the delay of the optical fiber link usually does not exceed the signal period of one clock, only influences the phase of the clock, and thus only needs to select a proper clock phase measurement circuit and phase adjustment circuit to realize the compensation of the delay variation of the downlink.

[0051] In order to better understand the signal synchronization circuit of the present application, the phase measurement circuit and the phase adjustment circuit used in the present application are first introduced as follows.

[0052] Figure 3 A schematic diagram of the phase measurement circuit according to an embodiment of the present application is shown.

[0053] Figure 4 A waveform diagram of the input clock and the output clock in the phase measurement circuit according to an embodiment of the present application is shown.

[0054] As shown in Figure 3 and Figure 4 , the phase measurement circuit can be a circuit based on a digital dual mixer time difference phase detector (DDMTD). The DDMTD can measure the phase difference between two same frequency to-be-measured clocks (i.e. the first to-be-measured clock u1 and the second to-be-measured clock u2), and can realize a measurement precision of picoseconds. Figure 2 The structure of the first phase measurement unit shown in Figure 3 can refer to the phase measurement circuit in

[0055] The key of the phase measurement circuit is to need a reference clock u ddmtd with a slight deviation from the frequency of the to-be-measured clock, to sample the to-be-measured clock by a D flip-flop and generate two beat clocks corresponding to the two to-be-measured clocks respectively (i.e. the first beat clock u beat1 corresponding to the first to-be-measured clock u1 and the second beat clock u beat2 corresponding to the second to-be-measured clock u2). The to-be-measured clock can be input as the D terminal of the D flip-flop, and the reference clock u ddmtd can be input as the clock (clk) terminal of the D flip-flop, and the beat clock output from the Q terminal of the D flip-flop can be deburred. As shown in Figure 4 , the phase difference between the two output beat clocks is actually the amplification of the original phase difference between the first to-be-measured clock u1 and the second to-be-measured clock u2. Finally, the phase measurement circuit can output the reference clock u ddmtd through a counter to count the phase difference between the two beat clocks .

[0056] If the frequency of the to-be-measured clock is the frequency of the reference clock The following formula (2) can be satisfied.

[0057] (2) ;

[0058] wherein N' is a positive integer.

[0059] The measurement resolution of the phase measurement circuit can satisfy the following formula (3) for the two to-be-measured clocks and the reference clock.

[0060] (3) ;

[0061] wherein represents the measurement resolution of the phase measurement circuit.

[0062] The phase difference between the two to-be-measured clocks can satisfy the following formula (4).

[0063] (4).

[0064] In order to reduce the measurement error, the average value of the phase difference between the two to-be-measured clocks can be obtained by using the way of multiple measurements and averaging, satisfying the following formula (5).

[0065] (5) ;

[0066] wherein represents the average value of the phase difference between the two to-be-measured clocks, represents the reference clock u ddmtd the average value of the period count of the phase difference between the two to-be-measured clocks.

[0067] Figure 5 A schematic diagram of a phase adjustment circuit according to an embodiment of the present application is shown.

[0068] As Figure 5As shown, this explanation focuses on the transmitting end of a node. To achieve picosecond-level clock synchronization performance, a phase adjustment circuit with picosecond-level adjustment accuracy is required. A phase adjustment module, such as a phase interpolator (PI), can be integrated into the transmitting end, which is based on a multi-gigabit transceiver (MGT). The transmitting end's TX reference clock is multiplied by a factor of D×N via a phase-locked loop, its phase is adjusted by the phase interpolator, and then divided by a factor of D by the first frequency divider to output the TX bit clock. The TX bit clock is then divided by a factor of N by the second frequency divider to output the TX word clock. The parallel-in serial-out module uses the TX bit clock and the TX word clock to output the TX parallel data as TX serial data. The TX word clock can be used as the transmitting reference clock for the transmitting end.

[0069] The phase of the TX word clock can be adjusted by controlling the PI controller via the phase interpolation control port. The PI controller has two operating modes: the first is step mode, where the phase difference between the TX word clock and the TX reference clock is gradually adjusted, thus changing the delay of the TX word clock relative to the TX reference clock. The second is continuous mode, where the phase of the TX word clock is continuously adjusted, resulting in a deviation between the period of the TX word clock and the TX reference clock. The TX word clock output by the phase adjustment circuit in continuous mode can be used as... Figure 3 Reference clock u in ddmtd . Figure 2 The function of the first port unit shown in the figure to adjust the phase of the first transmission reference clock can be achieved through Figure 5 The phase adjustment circuit shown is implemented.

[0070] In step mode, the phase adjustment step size of PI can satisfy the following formula (6).

[0071] (6);

[0072] in, The frequency of the TX reference clock. It is a controllable variable, with a value ranging from 1 to 15. D and N are the division values ​​of the two frequency dividers, respectively. The PI controller can also control the adjustment direction of the TX reference clock.

[0073] In continuous mode, the period difference between the TX word clock and the TX reference clock can satisfy the following formula (7).

[0074] (7);

[0075] Among them, except It also adds a controllable variable. , the integer value ranges from 1 to 7. In addition, the positive and negative of the period difference can be controlled by the PI.

[0076] Figure 6 The circuit structure schematic diagram of the clock synchronization circuit according to the embodiment of the application is shown.

[0077] As shown in Figure 6 , the first node can include a first port unit MGT1, a second port unit MGT2 and a first phase measurement unit DDMTD1. The second node can include a third port unit MGT3.

[0078] The first port unit MGT1 can include a first transmission port subunit TX1_1, a first reception port subunit RX1 and a first phase adjustment subunit PI1.

[0079] The first transmission port subunit TX1_1 can be configured to transmit downlink data to the second node via a downlink according to a first transmission reference clock obtained based on an input reference clock. The first reception port subunit RX1 can be configured to obtain a first recovery clock according to uplink data returned by the second node via an uplink. The first phase adjustment subunit PI1 can be configured to perform phase adjustment on the first transmission reference clock according to a first phase adjustment step number from the first phase measurement unit based on a phase adjustment step of the first phase adjustment subunit.

[0080] The first phase adjustment subunit PI1 can be embedded in the first transmission port subunit TX1_1, and the specific structure can refer to the foregoing Figure 5 . The first reception port subunit RX1 is used to receive downlink data and output a first recovery clock. The phase adjustment step of the first phase adjustment subunit PI1 can be determined according to formula (6). The first phase adjustment subunit PI1 can perform phase adjustment on the first transmission reference clock according to a step mode, so as not to change the period and frequency of the first transmission reference clock. The structure of the first phase adjustment subunit PI1 can refer to the phase adjustment circuit shown in Figure 5 . Among them, the input reference clock is the TX reference clock of the phase adjustment circuit, that is, for the first phase adjustment subunit PI1, Figure 5 , the frequency of the TX reference clock is the same as that of the input reference clock.

[0081] By setting the first phase adjustment subunit PI1 in the first node to perform phase adjustment on the first transmission reference clock, the delay between the first recovery clock and the input reference clock is compensated in the first node, without the need for interaction with the second node.

[0082] ​The first phase measurement unit DDMTD1 can include a first input port, a second input port, a third input port, a first reference clock output unit, and a second reference clock output unit.

[0083] The first input port can be configured to receive an input reference clock. The second input port can be configured to receive a first recovered clock. The third input port can be configured to receive a first measurement reference clock. The first reference clock output unit can be configured to sample the input reference clock according to the first measurement reference clock and output a first beat clock. The second reference clock output unit can be configured to sample the first recovered clock according to the first measurement reference clock and output a second beat clock. The output port can be configured to output a first phase adjustment step number according to a phase difference between the first beat clock and the second beat clock.

[0084] The specific structure of the first phase measurement unit DDMTD1 can refer to Figure 3 . The input reference clock and the first recovered clock correspond to a first to-be-measured clock u1 and a second to-be-measured clock u2 in Figure 3 respectively, and the first measurement reference clock corresponds to a reference clock u Figure 3 in ddmtd . The first beat clock and the second beat clock correspond to a first beat clock u beat1 and a second beat clock u beat2 in Figure 3 respectively.

[0085] As shown in Figure 6 , the second port unit MGT2 can further include a third sending port subunit TX1_2 and a second phase adjustment subunit PI2.

[0086] The second phase adjustment subunit PI2 can be configured to adjust the phase of the input reference clock and output a first measurement reference clock, wherein the period difference between the first measurement reference clock and the input reference clock is 2X times of the phase adjustment step of the first phase adjustment subunit, and X is a positive integer. The third sending port subunit TX1_2 can be configured to send the first measurement reference clock to the first phase adjustment subunit DDMTD1. The structure of the second phase adjustment subunit PI2 can refer to the phase adjustment circuit shown in Figure 5 . The input reference clock is the TX reference clock of the phase adjustment circuit, that is, for the second phase adjustment subunit PI2, the frequency of the TX reference clock in Figure 5 is the same as the frequency of the input reference clock in .

[0087] ​The second phase adjustment subunit PI2 can perform phase adjustment on the input reference clock in a continuous mode, so that a first measurement reference clock with a different frequency period from the input reference clock can be output.

[0088] The phase adjustment circuit of the embodiment of the present application combines the step mode and the continuous mode (the first phase adjustment subunit is in the step mode, and the second phase adjustment subunit is in the continuous mode). In the continuous mode, the second phase adjustment subunit outputs a first measurement reference clock (i.e. Figure 5 TX word clock) according to the input reference clock (i.e. Figure 5 TX reference clock) as the reference clock of the first phase measurement unit. In the step mode, the first phase adjustment subunit serves as a phase adjuster, so that the circuit implementation of formula (1) becomes simple. Specifically, the following is performed.

[0089] The first port unit MGT1 of the first node distributes a first transmission reference clock obtained based on the input reference clock to the second node and keeps synchronization, and the first phase adjustment subunit PI1 in the first node compensates for the delay variation of the downlink as a phase adjuster. The first measurement reference clock generated by the second port unit MGT2 serves as the reference clock of the first phase measurement unit DDMTD1, and at this time, the measurement resolution of the first phase measurement unit DDMTD1 can satisfy formula (8) as follows.

[0090] (8).

[0091] The parameters of the second phase adjustment subunit PI2 of the second port unit MGT2 can be set as = 4X, = 1, and X is a positive integer. In the embodiment of the present application, X can take values of 1, 2, and 3. The measurement resolution of the first phase measurement unit DDMTD1 can further satisfy formula (9) as follows.

[0092] (9).

[0093] Then, the delay variation of the loop measured by the first phase measurement unit DDMTD1 can satisfy formula (10) as follows.

[0094] (10);

[0095] Wherein, is the delay variation of the loop is the variation of the average value of the period count of the phase difference measured by the first phase measurement unit DDMTD1.

[0096] The parameters of the first phase adjustment subunit PI1 of the first port unit MGT1 are further configured as = 1, the phase adjustment step of the first phase adjustment subunit PI1 can satisfy the following formula (11).

[0097] (11).

[0098] The frequency division coefficients D and N of the first phase adjustment subunit PI1 and the second phase adjustment subunit PI2 can be kept the same, and the measurement resolution of the first phase measurement unit DDMTD1 can be made 2X times of the PI adjustment step. Therefore, when the first phase measurement unit DDMTD1 detects that the loop delay variation is , the first phase adjustment step number of the phase adjustment step of the first phase adjustment subunit PI1 can satisfy the following formula (12).

[0099] (12);

[0100] wherein, represents an integer truncation operation.

[0101] It can be seen that the integer multiple (X times) of the first phase adjustment step number output by the first phase measurement unit is the number of phase adjustment steps that the first phase adjustment subunit needs to adjust. In the case of X = 1, the first phase adjustment step number output by the first phase measurement unit can directly correspond to the number of steps that the first phase adjustment subunit needs to adjust, realizing seamless transition from phase difference measurement to delay compensation, and the adjustment is independent of frequency, avoiding complex control logic.

[0102] The third port unit MGT3 can be configured to receive downlink data via a downlink to obtain a second recovered clock, and transmit uplink data to the first node via an uplink according to a second transmission reference clock obtained based on the second recovered clock. The third port unit MGT3 can include a second receiving port subunit RX2 and a second transmission port subunit TX2_1.

[0103] The second receiving port subunit RX2 can be configured to receive downlink data via a downlink to obtain a second recovered clock. The second transmission port subunit TX2_1 can be configured to transmit uplink data to the first node via an uplink according to a second transmission reference clock obtained based on the second recovered clock. The second receiving port subunit and the second transmission port subunit are similar to the first receiving port subunit and the first transmission port subunit of the first node, and will not be described here.

[0104] The clock synchronization circuit is unstable after the link is powered off, and the source of instability comes from the transmitting end. Specifically, at the transmitting end (such as Figure 5As shown, the phase of the TX word clock obtained by frequency multiplication and frequency division of the TX reference clock through a phase-locked loop has multiple possibilities after power-on and power-off. One stabilization scheme is that after power-on and power-off each time, the phase difference between the TX reference clock and the TX word clock is measured using the DDMTD, and after the offset from the preset fixed value is calculated, the PI is used as a phase adjuster to compensate for the offset.

[0105] As shown in Figure 6 , the first phase adjustment subunit PIl in the first node of the clock synchronization circuit can be controlled by a PI controller. The second phase adjustment subunit PI2 can also be controlled by the PI controller.

[0106] In order to realize the delay automatic stabilization of the power-on and power-off of the clock sending end, the embodiment of the present application adds a phase measurement circuit on the basis of the circuit in Figure 6 , the added phase measurement circuit shares an input reference clock with the aforementioned first phase measurement unit DDMTD1, and both are adjusted by the first phase adjustment subunit PIl to adjust the phase of the first sending reference clock.

[0107] Figure 7 A circuit structure schematic diagram of another clock synchronization circuit according to an embodiment of the present application is shown.

[0108] As shown in Figure 7 , on the basis of Figure 6 , the first node can further include a second phase measurement unit DDMTD2. The structure of the second phase measurement unit DDMTD2 can be the same as that of the first phase measurement unit DDMTD1.

[0109] The second phase measurement unit DDMTD2 can be configured to output a second phase adjustment step number to the first port unit MGT1 according to the first measurement reference clock, the input reference clock and the first sending reference clock.

[0110] The first port unit MGT1 can be configured to adjust the phase of the first sending reference clock according to the second phase adjustment step number.

[0111] Since no data is transmitted during the power-on and power-off process, only the sending end of the respective node has a delay impact on the clock, and only the delay variation of the one-way link needs to be considered. For the first node of the embodiment of the present application, the delay compensation of the first sending reference clock only needs to consider the delay variation of the downlink. The measurement resolution of the second phase measurement unit DDMTD2 can be set to be 2 times the phase adjustment step of the PI, and at this time, 2X times the output of the second phase measurement unit DDMTD2 is the step number that the PI should adjust. The second phase adjustment step number can satisfy the following formula (13).

[0112] (13).

[0113] In order to ensure that the second node keeps the clock synchronized after power-on and power-off, the third port unit MGT3 of the second node can also fix the delay in the same way. As shown in Figure 7 The second node can also include a fourth port unit MGT4 and a third phase measurement unit DDMTD3.

[0114] The fourth port unit MGT4 can be configured to output a second measurement reference clock with a different frequency from the second recovery clock according to the second recovery clock. The third phase measurement unit DDMTD3 can be configured to output a third phase adjustment step number to the third port unit according to the second measurement reference clock, the second recovery clock and the second transmission reference clock. The third port unit can also be configured to perform phase adjustment on the second transmission reference clock according to the third phase adjustment step number. The structure of the third phase measurement unit DDMTD3 can be the same as that of the first phase measurement unit DDMTD1.

[0115] The third port unit MGT3 can also include a third phase adjustment subunit PI3. The fourth port unit MGT4 can also include a fourth phase adjustment subunit PI4 and a fourth transmission port subunit TX2_2. The structure of the third phase adjustment subunit PI3 can refer to the phase adjustment circuit shown in Figure 5 .

[0116] The third phase adjustment subunit PI3 can be configured to receive the third phase adjustment step number and perform phase adjustment on the second transmission reference clock according to the third phase adjustment step number based on the phase adjustment step of the third phase adjustment subunit.

[0117] The fourth phase adjustment subunit PI4 can be configured to adjust the phase of the second recovery clock and output the second measurement reference clock, where the period difference between the second measurement reference clock and the second recovery clock is 2X times the phase adjustment step of the third phase adjustment subunit. The structure of the fourth phase adjustment subunit PI4 can refer to the phase adjustment circuit shown in Figure 5 .

[0118] The fourth transmission port subunit TX2_2 can be configured to output a second measurement reference clock with a different frequency from the second recovery clock according to the second recovery clock.

[0119] The third phase adjustment subunit PI3 in the second node of the clock synchronization circuit can also be controlled by a PI controller.

[0120] The third phase adjustment step number can be a basis for delay compensation of the second sending reference clock in the second node in the power-up and power-down situation. Since the structures of the first node and the second node that keep power-up and power-down synchronization are similar, the third phase measurement unit, the third phase adjustment sub-unit, the fourth phase adjustment sub-unit PI4, the parameter setting and application thereof can refer to the second phase measurement unit, the first phase adjustment sub-unit and the second phase adjustment sub-unit of the first node, and details are not described herein.

[0121] The embodiments of the present application can also realize automatic stabilization of clock synchronization after power-up and power-down of the link. The delay automatic stabilization circuit after power-up and power-down of the TX sending end of the MGT of each node (such as the first sending port sub-unit TX1_1 of the first node and the second sending port sub-unit TX2_1 of the second node) can share the phase adjustment sub-unit and the phase measurement unit with the automatic stabilization circuit of the link delay changing with temperature, thereby saving resources.

[0122] The reason for the unstable delay of the RX receiving end (such as the first receiving port sub-unit RX1 of the first node and the second receiving port sub-unit RX2 of the second node) of the MGT after power-up and power-down is slightly different from that of the TX sending end. The stabilization scheme can be fixed to a preset value through multiple reset modes according to the number of bit slips when aligning the data packet header, which can be selected according to actual needs, and details are not described herein.

[0123] Figure 8 A block diagram of a clock synchronization system according to an embodiment of the present application is shown.

[0124] As shown in Figure 8 , the clock synchronization system 800 includes a clock source 810 and a clock synchronization circuit 200. The clock source 810 is configured to provide an input reference clock.

[0125] The clock synchronization circuit 200 can be implemented based on a Field Programmable Gate Array (FPGA). The specific construction is as follows.

[0126] Referring to Figure 7In the first node, two DDMTD-based phase measurement units (e.g., a first phase measurement unit DDMTD1 and a second phase measurement unit DDMTD2) can be constructed. The first measurement reference clock output by the second phase adjustment subunit PI2 is used as the reference clock of the two phase measurement units, the input reference clock and the first recovered clock obtained by the first receiving port subunit RX1 are used as the to-be-measured clock of the first phase measurement unit DDMTD1, and the input reference clock and the first transmission reference clock output by the first transmission port subunit TX1_1 are used as the to-be-measured clock of the second phase measurement unit DDMTD2. In the second node, a DDMTD-based phase measurement unit (e.g., a third phase measurement unit DDMTD3) is also constructed to stabilize the delay of the second transmission reference clock output by the second transmission port subunit TX2_1. The uplink and downlink between the first node and the second node can be optical links based on dense wavelength division multiplexing technology to ensure that the uplink and downlink delays are approximately the same, and the uplink and downlink can also be implemented by using a fiber loop.

[0127] The first phase adjustment subunit PI1 of the first node and the third phase adjustment subunit PI3 of the second node can be configured in a step mode, the second phase adjustment subunit PI2 of the first node and the fourth phase adjustment subunit PI4 of the second node can be configured in a continuous mode, and the input reference clock and the second recovered clock are respectively sent to the second phase adjustment subunit PI2 of the first node and the fourth phase adjustment subunit PI4 of the second node to obtain the first measurement reference clock and the second measurement reference clock.

[0128] The first phase adjustment subunit PI1 of the first node and the third phase adjustment subunit PI3 of the second node can be configured in a step mode, the second phase adjustment subunit PI2 of the first node and the fourth phase adjustment subunit PI4 of the second node can be configured in a continuous mode, and the input reference clock and the second recovered clock are respectively sent to the second phase adjustment subunit PI2 of the first node and the fourth phase adjustment subunit PI4 of the second node to obtain the first measurement reference clock and the second measurement reference clock.

[0129] The first phase adjustment subunit PI1 of the first node and the third phase adjustment subunit PI3 of the second node can be configured in a step mode, the second phase adjustment subunit PI2 of the first node and the fourth phase adjustment subunit PI4 of the second node can be configured in a continuous mode, and the input reference clock and the second recovered clock are respectively sent to the second phase adjustment subunit PI2 of the first node and the fourth phase adjustment subunit PI4 of the second node to obtain the first measurement reference clock and the second measurement reference clock.

[0130] The first phase adjustment subunit PI1 of the first node and the third phase adjustment subunit PI3 of the second node can be configured in a step mode, the second phase adjustment subunit PI2 of the first node and the fourth phase adjustment subunit PI4 of the second node can be configured in a continuous mode, and the input reference clock and the second recovered clock are respectively sent to the second phase adjustment subunit PI2 of the first node and the fourth phase adjustment subunit PI4 of the second node to obtain the first measurement reference clock and the second measurement reference clock. ×2X times of phase step adjustment. The second node performs similar operations. The first phase measurement unit DDMTD1 of the first node measures the loop phase delay at this time and outputs the preset value at this time. ×2X times of phase step adjustment. The second node performs similar operations. The first phase measurement unit DDMTD1 of the first node measures the loop phase delay at this time and outputs the preset value at this time.

[0131] After a period of time, the first phase measurement unit DDMTD1 measurement value is compared with the last change and input into the PI controller, converted into a control signal, and then the first phase adjustment subunit PIl is used to adjust the phase step size . After that, this step is continuously performed to compensate for the change in downlink delay with temperature in real time, thereby maintaining synchronization.

[0132] The embodiments of the present application can realize automatic stabilization of clock synchronization after temperature change of a link. The embodiments of the present application can also realize automatic stabilization of clock synchronization after power-on and power-off of a link. The delay automatic stabilization circuit after power-on of the transmitting end of each node can share the phase adjustment subunit, the phase measurement unit, and the PI controller with the automatic stabilization circuit of the link delay changing with temperature, thereby saving resources.

[0133] The embodiments of the present application simplify the connection between the phase measurement unit and the phase adjustment subunit by combining the two modes of the phase adjustment subunit, and do not need an external clock source to provide a reference clock for the phase measurement unit. All the logic can be integrated in an FPGA, which improves the integration level and facilitates transplantation.

[0134] The flowcharts and block diagrams in the drawings illustrate the possible implementation architectures, functions, and operations of the systems, methods, and computer program products according to various embodiments of the present application. In this regard, each block in the flowcharts or block diagrams can represent a module, a program segment, or a part of code, which includes one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in different orders than those noted in the drawings. For example, two blocks that are shown in succession can actually be executed in parallel, and they can also be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams or flowcharts, and the combination of blocks in the block diagrams or flowcharts, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions. Those skilled in the art can understand that the features described in various embodiments of the present application can be combined and / or integrated in various combinations, even if such combinations or integrations are not explicitly described in the present application. In particular, the features described in various embodiments of the present application can be combined and / or integrated in various combinations without departing from the spirit and teachings of the present application. All such combinations and / or integrations fall within the scope of the present application.

[0135] The embodiments of the application have been described. However, these embodiments are merely for illustration and are not intended to limit the scope of the application. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Various alternatives and modifications to the embodiments described herein will be apparent to those skilled in the art in view of the foregoing description. Such alternatives and modifications are intended to fall within the scope of the application.

Claims

1. A clock synchronization circuit, characterized in that, include: The first node includes: The first port unit is configured to transmit downlink data to the second node via the downlink based on the first transmission reference clock obtained based on the input reference clock, and to obtain the first recovery clock based on the uplink data returned by the second node via the uplink, and to perform phase adjustment on the first transmission reference clock based on the first phase adjustment step size from the first phase measurement unit. The second port unit is configured to output a first measurement reference clock with a frequency different from the input reference clock, based on the input reference clock. The first phase measurement unit is configured to sample the input reference clock and the first recovery clock according to the first measurement reference clock, and output the first phase adjustment step size to the first port unit; The second node is configured to obtain a second recovery clock based on the downlink data received from the downlink, and to send the uplink data to the first node via the uplink based on a second transmission reference clock obtained from the second recovery clock.

2. The clock synchronization circuit according to claim 1, characterized in that, The first port unit includes: The first transmitting port subunit is configured to transmit the downlink data to the second node via the downlink according to the first transmitting reference clock obtained based on the input reference clock; The first receiving port subunit is configured to obtain the first recovery clock based on the uplink data returned by the second node via the uplink; The first phase adjustment subunit is configured to adjust the phase of the first transmission reference clock based on the phase adjustment step size of the first phase adjustment subunit and according to the first phase adjustment step size number from the first phase measurement unit.

3. The clock synchronization circuit according to claim 2, characterized in that, The second port unit includes: The second phase adjustment subunit is configured to adjust the phase of the input reference clock and output the first measurement reference clock, wherein the period difference between the first measurement reference clock and the input reference clock is 2X times the phase adjustment step size of the first phase adjustment subunit, where X is a positive integer.

4. The clock synchronization circuit according to any one of claims 1 to 3, characterized in that, The first phase measurement unit includes: The first input port is configured to receive the input reference clock; The second input port is configured to receive the first recovery clock. The third input port is configured to receive the first measurement reference clock. The first reference clock output unit is configured to sample the input reference clock according to the first measurement reference clock and output the first beat clock; The second reference clock output unit is configured to sample the first recovery clock according to the first measurement reference clock and output a second clock cycle. The output port is configured to output the first phase adjustment step size based on the phase difference between the first clock cycle and the second clock cycle.

5. The clock synchronization circuit according to any one of claims 1 to 3, characterized in that, The first node also includes: The second phase measurement unit is configured to output a second phase adjustment step size to the first port unit based on the first measurement reference clock, the input reference clock, and the first transmission reference clock. The first port unit is further configured to perform phase adjustment on the first transmission reference clock according to the second phase adjustment step size.

6. The clock synchronization circuit according to any one of claims 1 to 3, characterized in that, The second node includes: The third port unit is configured to receive the downlink data via the downlink, obtain the second recovery clock, and send the uplink data to the first node via the uplink according to the second transmission reference clock obtained based on the second recovery clock.

7. The clock synchronization circuit according to claim 6, characterized in that, The second node also includes: The fourth port unit is configured to output a second measurement reference clock with a frequency different from the second recovery clock, based on the second recovery clock. The third phase measurement unit is configured to output a third phase adjustment step size to the third port unit based on the second measurement reference clock, the second recovery clock and the second transmission reference clock; The third port unit is further configured to perform phase adjustment on the second transmission reference clock according to the third phase adjustment step size.

8. The clock synchronization circuit according to claim 7, characterized in that, The third port unit includes: The second receiving port subunit is configured to receive the downlink data via the downlink to obtain the second recovery clock; The second transmitting port subunit is configured to transmit the uplink data to the first node via the uplink according to the second transmitting reference clock obtained based on the second recovery clock. The third phase adjustment subunit is configured to receive the third phase adjustment step size and, based on the phase adjustment step size of the third phase adjustment subunit, adjust the phase of the second transmission reference clock according to the third phase adjustment step size.

9. The clock synchronization circuit according to any one of claims 1 to 3, characterized in that, The downlink and the uplink are implemented by at least one of dense wavelength division multiplexing optics or fiber optic circulators.

10. A clock synchronization system, characterized in that, include: Clock source, configured to provide an input reference clock; The clock synchronization circuit as described in any one of claims 1 to 9.

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