Gray code-binary code hybrid counter for image sensor

Abstract

The invention provides a Gray code-binary code hybrid counter for an image sensor. Gray code counting is adopted for low m bits, and binary counting is adopted for high n bits; comprising an exclusive-OR gate, (m + 1) latches and n D triggers, the latches are a latch 1, a latch 2,..., a latch (m + 1) in sequence; the D triggers are DFF1, DFF2,..., DFF (n) in sequence; an output port Q of the latch 1 (m + 1) is connected with an input port CK of the trigger DFF1; an input port D and an output port Q of the trigger DFF1 are connected with an input port A of the exclusive-OR gate; an input port B of the exclusive-OR gate is connected with an input signal G (m-1); and an output port Z of the exclusive-OR gate is connected with an input port D of the latch (m). The method has the beneficial effects that correlation is generated between the highest bit D (m-1) output by the Gray code and the lowest bit D (m) output by the binary code, so that the error code generated by the phase difference cannot be amplified by the weight of the binary code when the Gray code and the binary code are turned at the same time.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, and in particular relates to a Gray code-binary code hybrid counter for image sensors. Background Technology

[0002] The frame rate of an image sensor determines its minimum temporal resolution when capturing high-speed scenes such as bullet flight, bomb explosion, and rocket launch. The higher the frame rate of an image sensor, the more complete the recording of information about rapidly changing scenes. To improve the frame rate of an image sensor, it is necessary to increase the conversion rate of the analog-to-digital converter (ADC) in the image sensor, and the counting frequency of the counter is the determining factor of the ADC conversion rate. The higher the counting frequency of the counter, the shorter the time for the ADC to complete one quantization, and the higher the conversion rate of the ADC. The counter usually adopts a ripple counter structure, which is composed of multiple D flip-flops (DFFs) connected end to end. To increase the counting frequency of the counter, there are usually three ways: (1) increase the clock frequency of the counter; (2) adopt a double data rate (DDR) counter structure, which counts on both the rising and falling edges of the clock, and can count twice in one clock cycle; (3) adopt a Gray code (GC) counter structure. Although method (1) effectively increases the clock frequency, according to the power consumption formula of digital circuits, P=1 / 2fCV 2 It is known that as the clock frequency f increases, the power consumption of the counter will also increase, and it will also cause the IR drop phenomenon to worsen. Therefore, directly increasing the clock frequency f has limited ways to increase the counting frequency. Compared with method (1), method (2) utilizes both the rising and falling edges of the clock, and can make the counting frequency twice that of method (1) without changing the power consumption. The disadvantage of method (2) is that the DDR structure is usually composed of latches. For the design of DDR counters in image sensors, it is impossible to complete the precise bit-by-bit inversion operation. An additional correction circuit needs to be designed to complete the Correlated Double Sampling (CDS) or Correlated Multiple Sampling (CMS) operation. Its complexity and layout area are higher than that of method (1). Method (3) uses a Gray code-encoded counter. For an N-bit counter, compared with method (1) and method (2), the advantage of the Gray code counter is that the counter jumps only 1 bit per clock cycle, avoiding the power consumption caused by the carry operation in the binary counter. Therefore, the Gray code counter can have lower power consumption and higher conversion rate.

[0003] However, since Gray code is an unweighted code and cannot be used for algebraic operations, Gray code must be converted to binary code before CDS and CMS operations. In image sensors, converting N-bit Gray code to binary code before operations would be unacceptable in terms of area and logic operation time for the widely used column-parallel ADC architecture. Therefore, Gray code counters in image sensors typically use Gray code for low-order bits and binary code for high-order bits. Low-order data is converted to binary code before CDS and CMS operations, while high-order data can be directly processed internally using bit-inverting circuits to perform CDS and CMS operations within the counter. Finally, the low-order and high-order data are added together to obtain the final count result. However, in this counter that combines Gray code and binary code, the Gray code and binary code will flip simultaneously at the boundary between them. Since the delays of different clocks during transmission cannot be strictly consistent, the flip times of the Gray code and the binary code may have a certain phase difference, which can lead to bit errors. Summary of the Invention

[0004] In view of this, the present invention aims to propose a Gray code-binary code hybrid counter for image sensors to solve the problem that errors are easily generated at the junction of Gray code and binary code, causing a large offset in the quantization result.

[0005] To achieve the above objectives, the technical solution of the present invention is implemented as follows: A Gray code-binary code hybrid counter for image sensors, wherein the lower m bits are counted using Gray code and the higher n bits are counted using binary code; It includes XOR gates, m+1 latches, and n D flip-flops; The m+1 latches are sequentially named latch1, latch2, ..., latch(m+1); The n D flip-flops are DFF1, DFF2, ..., DFF(n) in sequence; The latch includes an input port G, an input port D, and an output port Q; The D flip-flop includes an input port D, an input port CK, and an output port. Q; The XOR gate includes input port A, input port B, and output port Z; The output port Q of latch1(m+1) is connected to the input port CK of trigger DFF1; The input port D and output port of the trigger DFF1 Q is connected to the input port A of the XOR gate; The input port B of the XOR gate is connected to the input signal G(m-1); The output port Z of the XOR gate is connected to the input port D of the latch(m).

[0006] Furthermore, the input port G of the latch is connected to the input signal cmp.

[0007] Furthermore, the input ports D of the latches latch1, latch2, ... latch(m-1) are connected sequentially to the input signals G0, G1, ... G(m-2); The input port D of the latch(m+1) is connected to the input signal G(m).

[0008] Furthermore, the output ports Q of the latches latch1, latch2, ... latch(m) sequentially output D0, D1, ... D(m-1).

[0009] Furthermore, the output port of the trigger DFF1 Q outputs D(m).

[0010] Furthermore, the timing sequence of the counter includes: Before counting begins, the input signal cmp changes from logic 0 to logic 1, and the latch changes from a locked state to a transparent state. After starting the count: The input signals G0, G1, ... G(m-1) are all transformed based on the Gray code truth table; The initial state of the input signal G(m) is logic 0, and the period is 2 to the power of m; The output ports Q of latches latch1, latch2, ... latch(m-1) follow the input signals G0, G1, ... G(m-2) in sequence, and output D0, D1, ... D(m-2) in sequence; Based on the input signal G(m), the output port of flip-flop DFF1 Q outputs D(m), and after D(m) is XORed with the input signal G(m-1), it is input to the input port D of the latch (m), and the output port Q of the latch (m) outputs D(m-1). When the input signal cmp changes from logic 1 to logic 0, the counter stops counting, completing one ADC conversion.

[0011] Furthermore, D(m) is a frequency division of G(m) by two, and D(m) flips when G(m) falls.

[0012] Compared with existing technologies, the Gray code-binary code hybrid counter for image sensors described in this invention has the following advantages: This invention uses the XOR result of the output D(m) of the flip-flop DFF1 and the input signal G(m-1) as the input signal of the D terminal of the latch (m), so that the highest bit D(m-1) of the Gray code output is correlated with the lowest bit D(m) of the binary code output, so that the bit error caused by the phase difference when the Gray code and the binary code are flipped at the same time will not be amplified by the weight of the binary code. Attached Figure Description

[0013] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of a counter structure in Embodiment 1 of the present invention, in which the lower 3 bits use Gray code and the higher 1 bit uses binary code. Figure 2 This is a schematic diagram of the working timing of the Gray code-binary code hybrid counter according to Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the decimal number-Gray code truth value representation as described in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram illustrating an error in the Gray code-binary code hybrid counter according to an embodiment of the present invention; Figure 5 This is a schematic diagram illustrating the case where the phase of the binary code clock G3 is advanced compared to the Gray code clocks G1, G2, and G3, as described in an embodiment of the present invention. Figure 6 This is a schematic diagram illustrating the situation where the phase of the binary code clock G3 is delayed compared to the Gray code clocks G1, G2, and G3, as described in an embodiment of the present invention. Figure 7 This is a schematic diagram of a counter structure in Embodiment 2 of the present invention, in which the lower 3 bits use Gray code and the higher 8 bits use binary code. Figure 8 This is a schematic diagram of the working timing of the Gray code-binary code hybrid counter according to Embodiment 2 of the present invention. Detailed Implementation

[0014] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0015] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0016] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0017] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0018] A Gray code-binary code hybrid counter for image sensors, wherein the lower m bits use Gray code counting and the higher n bits use binary counting; comprising an XOR gate, m+1 latches, and n D flip-flops; the m+1 latches are sequentially named latch1, latch2, ..., latch(m+1); the n D flip-flops are sequentially named DFF1, DFF2, ..., DFF(n); each latch includes an input port G, an input port D, and an output port Q; each D flip-flop includes an input port D, an input port CK, and an output port Q. Q; The XOR gate includes input port A, input port B, and output port Z; The output port Q of the latch1(m+1) is connected to the input port CK of the flip-flop DFF1; The input port D and output port of the flip-flop DFF1 are... Q is connected to the input port A of the XOR gate; the input port B of the XOR gate is connected to the input signal G(m-1); the output port Z of the XOR gate is connected to the input port D of the latch (m). The input port G of the latch is connected to the input signal cmp. The input ports D of latches 1, 2, ..., 1 (m-1) are connected to the input signals G0, G1, ..., G(m-2) sequentially; the input port D of latch (m+1) is connected to the input signal G(m). The output ports Q of latches 1, 2, ..., 1 (m-1) sequentially output D0, D1, ..., D(m-1). The output port of the trigger DFF1 is... Q outputs D(m). The timing sequence includes: Before counting begins, the input signal cmp changes from logic 0 to logic 1, and the latch changes from a locked state to a transparent state. After starting the count: The input signals G0, G1, ... G(m-1) are all transformed based on the Gray code truth table; The initial state of the input signal G(m) is logic 0, and the period is 2 to the power of m; The output ports Q of latches latch1, latch2, ... latch(m-1) follow the input signals G0, G1, ... G(m-2) in sequence, and output D0, D1, ... D(m-2) in sequence; Based on the input signal G(m), the output port of flip-flop DFF1 Q outputs D(m), and after D(m) is XORed with the input signal G(m-1), it is input to the input port D of the latch (m), and the output port Q of the latch (m) outputs D(m-1). When the input signal cmp changes from logic 1 to logic 0, the counter stops counting, completing one ADC conversion.

[0019] D(m) is a frequency division of G(m) by 2, and D(m) flips when G(m) falls.

[0020] Example 1: like Figure 1The diagram shows a counter structure where the lower 3 bits use Gray code and the higher 1 bit uses binary code. The counter includes four latches (latch1, latch2, latch3, and latch4), one D flip-flop (DFF1), and one XOR gate (XOR1). Latches 1, 2, 3, and 4 each have input ports G and D, and an output port Q. The XOR gate (XOR1) has input ports A and B, and an output port Z. The D flip-flop (DFF1) has input ports D and CK, and an output port Q. The input signal cmp is connected to the gate (G) terminals of latches 1, 2, 3, and 4 simultaneously. Input signal G0 is connected to the drain (D) terminal of latch 1, input signal G1 to the D terminal of latch 2, input signal G2 to the base (B) terminal of XOR gate 1, and input signal G3 to the D terminal of latch 4. The output of XOR gate 1 is connected to the D input of latch 3. The output Q of latch 4 is connected to the input CK terminal of DFF1. The output Q of latch 1 is the output D0 of the counter, the output Q of latch 2 is the output D1 of the counter, the output Q of latch 3 is the output D2 of the counter, and the output of DFF1... Q is the output D3 of the counter. D3 is connected to the input A of the XOR gate and the input D of the D flip-flop DFF1.

[0021] like Figure 2 The diagram shows the timing sequence. Before counting begins, the input signal cmp changes from logic 0 to logic 1, and latch1, latch2, latch3, and latch4 change from locked to transparent, allowing input signals G0, G1, G2, and G3 to change the state of the output Q of latch1, latch2, latch3, and latch4. After counting begins, input signals G0, G1, and G2 follow the sequence as follows: Figure 3 The Gray code truth table shown changes sequentially from 0 to 7. Input signal G3 is a periodic signal with an initial state of logic 0 and a period of 8. The output D0 of latch1 follows the input G0, the output D1 of latch2 follows the input G1, and the output Q of latch4 is connected to the input CK of DFF1, making DFF1 a binary ripple counter. The output D3 of DFF1 is XORed with the input G2 and then input to the D terminal of latch3. The Q terminal of latch3 outputs D2. When cmp changes from logic 1 to logic 0, the counter stops counting, the ADC completes one conversion, and at this point, D0, D1, and D2 output Gray code, while D3 outputs binary code.

[0022] Example 2: like Figure 7The diagram shows a counter structure where the lower 3 bits use Gray code and the higher 8 bits use binary code. Each Gray code counter is followed by two latches, used to latch the Gray code count results during RST quantization and SIG quantization, respectively. The binary counter consists of eight D flip-flops connected in series. The output of each D flip-flop is passed through a bit-wise inverter (BWI) circuit and then connected to the CK terminal of the next D flip-flop. The BWI circuit is used to invert the binary code count result, thereby performing a subtraction operation within the counter.

[0023] like Figure 8 The diagram shows the timing sequence. During the RST quantization phase, when cmp is logic 1, the Gray code outputs D<2:0> and binary code outputs D<11:3> follow the input clock. When cmp becomes logic 0, the first quantization ends, and the Gray code outputs D<2:0> and binary code outputs D<11:3> stop quantizing. After the RST quantization phase ends, the latch_rst pulse latches the quantization result of the Gray code in the RST phase to Drst<2:0>, and the BWI_ctr pulse makes the count result of the binary code in the RST phase negative. During the SIG quantization phase, cmp becomes logic 1, the Gray code outputs D<2:0> restart counting from 0, and the binary code outputs D<11:3> continue counting from their previous count. When cmp becomes logic 0, the second quantization ends, and the Gray code output D<2:0> and binary code output D<11:3> stop fluctuating. After the SIG quantization phase ends, the latch_sig pulse latches the quantization result of the Gray code in the SIG phase into Dsig<2:0>, and the binary code count result D<11:3> is stored in the counter. Finally, Drst<2:0>, Dsig<2:0>, and D<11:3> are read out. In the digital processing circuit or outside the chip, the Gray codes Drst<2:0> and Dsig<2:0> are first converted into the corresponding binary codes Drst_bin<2:0> and Dsig_bin<2:0>, and then the operation Dout = 8 × D<11:3> + Dsig_bin<2:0> - Drst_bin<2:0> is performed to obtain the final quantization result Dout.

[0024] Advantages and benefits of this invention: When using a Gray code-binary code hybrid counter, the Gray code and binary code will flip simultaneously after the Gray code count completes one cycle. Due to inconsistencies between clock signal lines in actual circuits, there is a phase difference between the Gray code input clock and the binary code input clock. Therefore, a certain phase difference will occur between the Gray code flipping moment and the binary code flipping moment, such as... Figure 4As shown. This phase difference can cause the binary code counting result and the Gray code counting result to not match perfectly, resulting in a large negative or positive error in the output of the counter, which should be strictly increasing. This invention uses the XOR result of the output D3 of DFF1 and the input signal G2 as the D input signal of latch 3, so that the highest bit D2 of the Gray code output is determined by the lowest bit D3 of the binary code output and the Gray code input G2. After the Gray code counting completes one cycle, the logic of the highest bit G2 of the Gray code input remains unchanged; only the logic of the lowest bit D3 of the binary code output is flipped. Therefore, at this error-prone position, the Gray code output D2 is determined only by the binary code output D3, and the phase of D2 changes along with the phase of D3, as shown. Figure 5 and Figure 6 As shown. This ensures the time consistency between Gray code output and binary code output, avoiding counter errors caused by clock phase differences.

[0025] like Figure 1 As shown, the present invention uses the XOR result of the output D3 of the flip-flop DFF1 and the input signal G2 as the D input signal of the latch 3, so that the highest bit D2 of the Gray code output is correlated with the lowest bit D3 of the binary code output, so that the bit error caused by the phase difference when the Gray code and the binary code are flipped at the same time will not be amplified by the weight of the binary code.

[0026] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A Gray code-binary code hybrid counter for an image sensor, characterized in that: The lower m bits are counted using Gray code, and the higher n bits are counted using binary code. It includes XOR gates, m+1 latches, and n D flip-flops; The m+1 latches are sequentially named latch1, latch2, ..., latch(m+1); The n D flip-flops are DFF1, DFF2, ..., DFF(n) in sequence; The latch includes an input port G, an input port D, and an output port Q; The D flip-flop includes an input port D, an input port CK, and an output port. Q; The XOR gate includes input port A, input port B, and output port Z; The output port Q of latch1(m+1) is connected to the input port CK of trigger DFF1; The input port D and output port of the trigger DFF1 Q is connected to the input port A of the XOR gate; The input port B of the XOR gate is connected to the input signal G(m-1); The output port Z of the XOR gate is connected to the input port D of the latch(m).

2. The Gray code-binary code hybrid counter for an image sensor according to claim 1, characterized in that: The input port G of the latch is connected to the input signal cmp.

3. A Gray code-binary code hybrid counter for an image sensor according to claim 1, characterized in that: The input ports D of the latches latch1, latch2, ... latch(m-1) are connected to the input signals G0, G1, ... G(m-2) in sequence; The input port D of the latch(m+1) is connected to the input signal G(m).

4. A Gray code-binary code hybrid counter for an image sensor according to claim 1, characterized in that: The output ports Q of the latches latch1, latch2, ..., latch(m) sequentially output D0, D1, ..., D(m-1).

5. A Gray code-binary code hybrid counter for an image sensor according to claim 1, characterized in that: The output port of the trigger DFF1 Q outputs D(m).

6. A Gray code-binary code hybrid counter for an image sensor according to claim 2, 3, 4, or 5, characterized in that: The work sequence includes: Before counting begins, the input signal cmp changes from logic 0 to logic 1, and the latch changes from a locked state to a transparent state. After starting the count: The input signals G0, G1, ... G(m-1) are all transformed based on the Gray code truth table; The initial state of the input signal G(m) is logic 0, and the period is 2 to the power of m; The output ports Q of latches latch1, latch2, ... latch(m-1) follow the input signals G0, G1, ... G(m-2) in sequence, and output D0, D1, ... D(m-2) in sequence; Based on the input signal G(m), the output port of flip-flop DFF1 Q outputs D(m), and after D(m) is XORed with the input signal G(m-1), it is input to the input port D of the latch (m), and the output port Q of the latch (m) outputs D(m-1). When the input signal cmp changes from logic 1 to logic 0, the counter stops counting, completing one ADC conversion.

7. A Gray code-binary code hybrid counter for an image sensor according to claim 6, characterized in that: D(m) is a frequency division of G(m) by 2, and D(m) flips when G(m) falls.

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