Transistor preparation method and device, transistor and computer readable storage medium

Abstract

The invention provides a transistor preparation method and device, a transistor and a computer readable storage medium, and the method comprises the steps: obtaining the size of a top opening of a target source region metal contact hole, and carrying out the matching of the target boron content corresponding to the target source region metal contact hole; a dielectric layer is prepared on the gate layer, the dielectric layer is prepared from silicon dioxide and boron-phosphorosilicate glass, and the boron content of the boron-phosphorosilicate glass is the target boron content; opening the dielectric layer to obtain a source region metal contact hole; and preparing a metal layer on the dielectric layer. The size of the top opening of the target source region metal contact hole needing to be prepared is determined, and the corresponding target boron content is matched, so that under the target boron content, proper fluidity setting of the boron-phosphorosilicate glass is realized, and after the annealing operation is executed, the yield of the boron-phosphorosilicate glass is improved. The dielectric layer shrinks to cause the size of the top opening of the source region metal contact hole to reach the size of the target source region metal contact hole, so that secondary etching does not need to be carried out again, and the subsequent opening enlarging process is saved.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to a method for manufacturing a transistor, an apparatus, a transistor, and a computer-readable storage medium. Background Technology

[0002] In the manufacturing process of silicon carbide SiC-VDMOS (Vertical Double-diffused MOSFET), BPSG (Boro-Phospho-Silicate Glass) is usually used as the gate-source interlayer dielectric, which has good planarization performance and filling energy.

[0003] The introduction of boron into BPSG films can significantly increase their fluidity, enabling them to flow and achieve planarization after high-temperature reflow. Phosphorus in BPSG films can absorb metallic impurities such as Na+ and K+, preventing these impurities from diffusing into the underlying silicon carbide film layer, thereby reducing device leakage and defects.

[0004] However, the boron precipitated in BPSG is prone to absorbing water and moisture, which can lead to metal corrosion and leakage problems. On the other hand, too little boron content reduces its fluidity, thus affecting the size of the opening at the top of the source region and the subsequent metal filling effect. Therefore, how to select BPSG with a suitable boron content is an urgent problem to be solved. Summary of the Invention

[0005] The main objective of this invention is to provide a method, apparatus, transistor, and computer-readable storage medium for transistor fabrication, aiming to solve the problem of how to select a suitable boron content in BPSG in the prior art.

[0006] To achieve the above objectives, the present invention provides a method for fabricating a transistor, the method comprising the following steps: Obtain the top opening size of the metal contact hole in the target source region and match it with the target boron content corresponding to the metal contact hole in the target source region; A dielectric layer is prepared on the gate layer, wherein the dielectric layer is prepared by silicon dioxide and borosilicate glass, and the boron content of the borosilicate glass is the target boron content; The dielectric layer is perforated to obtain source region metal contact holes; After the annealing process, a metal layer is prepared on the dielectric layer.

[0007] Optionally, the fabrication of the dielectric layer on the gate layer includes: An oxide layer is prepared on the gate layer, and the oxide layer is prepared using silicon dioxide. The borosilicate glass is prepared on the oxide layer.

[0008] Optionally, the fabrication of the dielectric layer on the gate layer includes: An oxide layer is prepared on the gate layer using silicon dioxide; Borophosphosilicate glass is deposited on the oxide layer to obtain a borophosphosilicate glass layer; The borophosphosilicate glass layer is reflowed to obtain a dense borophosphosilicate glass layer; The boron and phosphorus on the surface of the dense borophosphorus silicon glass layer are cleaned to obtain the dielectric layer.

[0009] Optionally, the step of creating a hole in the dielectric layer to obtain a source region metal contact hole includes: Photoresist is applied to the dielectric layer at a location other than the metal contact hole location in the source region; A dry etching process is performed to remove the corresponding portion of the dielectric layer that is not coated with photoresist, thereby exposing the silicon carbide substrate layer under the gate layer. Remove the photoresist.

[0010] Optionally, the step of preparing a metal layer on the dielectric layer after the annealing process includes: An ohmic contact layer is prepared at the bottom of the metal contact hole in the source region; The metal layer is prepared on the ohmic contact layer.

[0011] Optionally, the step of preparing the metal layer on the ohmic contact layer includes: A barrier metal layer is prepared on the ohmic contact layer; A tungsten metal layer is prepared in the barrier metal layer to fill the metal contact hole in the source region; A source metal layer is prepared on the tungsten metal layer.

[0012] Optionally, the step of fabricating the dielectric layer on the gate layer includes: The gate layer is formed on the front side of the silicon carbide substrate, and the gate layer includes a gate oxide layer and a polysilicon layer.

[0013] To achieve the above objectives, the present invention also provides a transistor fabrication apparatus, the transistor fabrication apparatus comprising: The first acquisition module is used to acquire the size of the top opening of the metal contact hole in the target source region and match it with the target boron content corresponding to the metal contact hole in the target source region. The first preparation module is used to prepare a dielectric layer on the gate layer, wherein the dielectric layer is prepared using silicon dioxide and borosilicate glass, and the boron content of the borosilicate glass is the target boron content; The first aperture module is used to create apertures in the dielectric layer to obtain source region metal contact holes; The second preparation module is used to prepare a metal layer on the dielectric layer after the annealing process.

[0014] Optionally, the first preparation module includes: The first fabrication unit is used to fabricate an oxide layer on the gate layer, wherein the oxide layer is fabricated using silicon dioxide; The second preparation unit is used to prepare the borosilicate glass on the oxide layer.

[0015] Optionally, the first preparation module includes: The first deposition unit is used to prepare an oxide layer on the gate layer using silicon dioxide; Borophosphosilicate glass is deposited on the oxide layer to obtain a borophosphosilicate glass layer; The first reflow unit is used to reflow the borophosphosilicate glass layer to obtain a dense borophosphosilicate glass layer. The first cleaning unit is used to clean the boron and phosphorus on the surface of the dense borophosphorus silicon glass layer to obtain the dielectric layer.

[0016] Optionally, the first opening module includes: The first coating unit is used to coat photoresist on the dielectric layer at a location other than the source region metal contact hole location; The first execution unit is used to perform a dry etching process to remove the corresponding portion of the dielectric layer that is not coated with photoresist and expose the silicon carbide substrate layer under the gate layer. The first removal unit is used to remove the photoresist.

[0017] Optionally, the second preparation module includes: The third fabrication unit is used to fabricate an ohmic contact layer at the bottom of the metal contact hole in the source region. The fourth preparation unit is used to prepare the metal layer on the ohmic contact layer.

[0018] Optionally, the fourth preparation unit includes: The first fabrication subunit is used to fabricate a barrier metal layer on the ohmic contact layer; The first filling subunit is used to prepare a tungsten metal layer in the barrier metal layer to fill the metal contact hole in the source region; The second preparation subunit is used to prepare a source metal layer on the tungsten metal layer.

[0019] Optionally, the device further includes: The fourth fabrication module is used to fabricate the gate layer on the front side of the silicon carbide substrate, the gate layer comprising a gate oxide layer and a polysilicon layer.

[0020] To achieve the above objectives, the present invention also provides a transistor, which is prepared by the transistor preparation method described above.

[0021] To achieve the above objectives, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the transistor fabrication method described above.

[0022] This invention proposes a transistor fabrication method, apparatus, transistor, and computer-readable storage medium. The method involves obtaining the top opening size of a target source region metal contact hole and matching it with a target boron content corresponding to the target source region metal contact hole. A dielectric layer is fabricated on a gate layer, wherein the dielectric layer is prepared from silicon dioxide and borosilicate glass, and the boron content of the borosilicate glass is the target boron content. A hole is created in the dielectric layer to obtain the source region metal contact hole. After an annealing process, a metal layer is fabricated on the dielectric layer. By determining the required top opening size of the target source region metal contact hole and matching it with the corresponding target boron content, a suitable flowability setting for the borosilicate glass is achieved at the target boron content. After annealing, the dielectric layer prepared from the borosilicate glass shrinks, causing the top opening size of the source region metal contact hole to reach the target size. Furthermore, since the top opening size of the source metal contact hole meets the requirements, a secondary etching is unnecessary, saving subsequent processes for increasing the opening size. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic flowchart of the first embodiment of the transistor fabrication method of the present invention; Figure 2 This is a schematic diagram of metal pore filling when the boron content is 1%; Figure 3 This is a schematic diagram of metal pore filling when the boron content is 2.5%; Figure 4 This is a schematic diagram of metal pore filling when the boron content is 4.5%; Figure 5 This is a schematic diagram showing the relationship between the thickness of the metal at the bottom and sidewalls of the metal contact hole in the source region and the boron content. Figure 6 This is a schematic diagram of the preparation of the dielectric layer in the transistor fabrication method of the present invention; Figure 7 This is a schematic diagram illustrating the fabrication of the source region metal contact hole in the transistor fabrication method of the present invention; Figure 8 This is a schematic diagram of the metal layer fabrication process in the transistor fabrication method of the present invention; Figure 9 This is a schematic diagram of the gate layer fabrication process in the transistor fabrication method of the present invention; Figure 10 This is a schematic diagram of the module structure of the electronic device of the present invention.

[0026] Explanation of icon numbers: Detailed Implementation

[0027] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0028] This invention provides a method for fabricating a transistor, referring to... Figure 1 , Figure 1 This is a schematic flowchart of the first embodiment of the transistor fabrication method of the present invention, the method comprising the following steps: Step S10: Obtain the top opening size of the metal contact hole in the target source region and match it with the target boron content corresponding to the metal contact hole H in the target source region; The specific type of transistor used in this application can be set according to actual needs, such as SiC-VDMOS transistor.

[0029] The source region metal contact hole H is a vertical through-hole structure etched in the interlayer dielectric to achieve electrical connection between the drain region semiconductor material and the upper metal layer.

[0030] The target source region metal contact hole size is the opening size of the source region metal contact hole H required by the transistor.

[0031] It is understandable that the source region metal contact hole H is used to fill the metal layer to connect the drain region semiconductor material with the metal layer. Therefore, the opening size of the source region metal contact hole H needs to be able to be penetrated by the metal layer to achieve reliable connection between the semiconductor material and the metal layer.

[0032] The specific size of the metal contact hole H in the target source area can be set based on actual needs.

[0033] The target boron content is the boron content of the borosilicate glass set to achieve the desired opening size at the top of the metal contact hole in the target source region.

[0034] It is understandable that the higher the boron content in borosilicate glass, the higher its fluidity. However, in the preparation of the ohmic contact layer 5, an annealing process is required. Under the action of the annealing process, the higher the fluidity of the borosilicate glass, the higher its shrinkage rate. When the shrinkage rate of the borosilicate glass is too high, it will result in a thinner dielectric layer 4, which will make the distance between the gate and the source smaller, causing problems such as breakdown and leakage.

[0035] For example, boron phosphosilicate glass in the prior art often uses a boron content of 4% to 5%. At this boron content, the shrinkage rate of boron phosphosilicate glass after annealing is too high, resulting in a small gap between the gate and the source.

[0036] In this embodiment, the boron content of borosilicate glass and the opening size of the source region metal contact hole H caused by shrinkage after annealing are statistically analyzed to obtain the correlation between the boron content of borosilicate glass and the size of the source region metal contact hole. Thus, when a specific target source region metal contact hole size is required, the required target boron content can be matched through the correlation.

[0037] Specifically, see Figures 2-4 , Figure 2 This is a schematic diagram of metal pore filling when the boron content is 1%; Figure 3 This is a schematic diagram of metal pore filling when the boron content is 2.5%; Figure 4 This is a schematic diagram of metal via filling when the boron content is 4.5%. As shown in the figure, the higher the boron content, the larger the top opening. After subsequent Ti / TiN metal layer deposition, the thickness of the metal layer at the bottom and sidewalls of the source region metal contact hole H is greater, and the tungsten via filling and seam are smaller. For the variation of the top opening size of the source region metal contact hole H and the metal via filling effect, see [link to relevant documentation]. The variation of Ti / TiN metal thickness at the bottom and sidewalls of the source region metal contact hole H with the boron content in BPSG is also shown in [reference needed]. Figure 5 , combined Figures 2-3 The experimental results show that when the boron content in borosilicate glass is 2.5%-3%, the device morphology and metal filling effect are better. It should be noted that in practical applications, the specific structures of different types or models of transistors vary, leading to different correlations between the boron content of borosilicate glass and the size of the source region metal contact holes. Therefore, in practical applications, experiments can be conducted on transistors of the same type beforehand to obtain and store the actual correlation between the boron content of the borosilicate glass and the size of the source region metal contact holes. During specific fabrication, the target boron content can be determined based on this correlation. The target boron content can be selected within the range of 1% to 4.5%. Compared to the existing 4%-5% boron content, this approach achieves a certain planarization effect and allows for the determination of the specific target boron content within the range based on the actual target size of the source region metal contact holes, thereby enabling controllable control over the size of the source region metal contact holes.

[0038] Step S20: A dielectric layer 4 is prepared on the gate layer 3, wherein the dielectric layer 4 is prepared by silicon dioxide and borosilicate glass, and the boron content of the borosilicate glass is the target boron content; See Figure 6 Gate layer 3 is a conductive layer in the transistor used to apply control voltage.

[0039] The dielectric layer 4 is a film layer located between the gate layer 3 and the source metal layer for electrically isolating the gate and the source.

[0040] In this embodiment, the dielectric layer 4 is prepared using silicon dioxide and borosilicate glass as materials.

[0041] The target boron content was determined by the size of the metal contact hole in the target source region. Therefore, the target boron content was used as the boron content of the boron phosphosilicate glass in the dielectric layer 4 to prepare the source region metal contact hole H with the size of the target source region metal contact hole.

[0042] Step S30: Open a hole in the dielectric layer 4 to obtain a source region metal contact hole H; See Figure 7 The source region metal contact hole H is used to realize the electrical connection between the drain region semiconductor material and the upper metal layer. It is a vertical through-hole structure etched in the dielectric layer 4.

[0043] The opening size that needs to be set for the source region metal contact hole H is the target source region metal contact hole size.

[0044] Step S40: After the annealing process, a metal layer is prepared on the dielectric layer 4.

[0045] During the annealing process, the process temperature is relatively high, such as 800~1000℃. At high temperatures, the borosilicate glass of the dielectric layer 4 shrinks, and the degree of shrinkage of the borosilicate glass is determined based on the boron content of the borosilicate glass. Therefore, when the boron content of the borosilicate glass is the target boron content, after the annealing process, the shrinkage of the dielectric layer 4 causes the opening size of the source metal contact hole H to be the target source metal contact hole size.

[0046] Annealing processes can be either part of the transistor fabrication process or additional annealing processes.

[0047] During the fabrication of the metal layer, the metal is filled into the source region metal contact hole H. Since the dielectric layer 4 shrinks after the annealing process, the opening size of the source region metal contact hole H is the same as the target source metal contact size. Therefore, the metal can be reliably filled into the source region metal contact hole H, thereby ensuring the electrical connection between the drain region semiconductor material and the upper metal layer.

[0048] This embodiment determines the size of the top opening of the target source region metal contact hole to be prepared and matches it with the corresponding target boron content. This achieves a suitable flowability setting for the boron phosphosilicate glass at the target boron content. After annealing, the dielectric layer 4 prepared by the boron phosphosilicate glass shrinks, causing the size of the top opening of the source region metal contact hole H to reach the size of the top opening of the target source region metal contact hole H. Since the size of the top opening of the source metal contact hole meets the requirements, there is no need to perform secondary etching, saving the subsequent process of increasing the opening size.

[0049] Furthermore, in the second embodiment of the transistor fabrication method of the present invention based on the first embodiment, step S20 includes the following steps: Step S21: An oxide layer is prepared on the gate layer 3, and the oxide layer is prepared using silicon dioxide; Step S22: Prepare the borosilicate glass on the oxide layer.

[0050] When boron and phosphorus are deposited in the borosilicate glass in dielectric layer 4, if they diffuse to the gate, they will affect the device performance and may even cause breakdown or leakage. In this embodiment, to avoid this problem, an oxide layer is added between the gate layer 3 and the borosilicate glass.

[0051] The oxide layer is prepared using silicon dioxide; the specific type of oxide layer can be set according to actual needs, such as LPETOS (Low-Pressure Tetraethyl Orthosilicate), PETEOS (Plasma-Enhanced TEOS), and PEOX (Plasma-Enhanced Oxide).

[0052] The oxide layer prepared from silicon dioxide has the characteristic of high isolation, thus it can effectively achieve isolation between the gate and the source; however, the oxide layer has the problem of poor flatness.

[0053] In this embodiment, an oxide layer is added between the gate layer 3 and the borosilicate glass, which provides an isolation effect and isolates the boron and phosphorus precipitated from the borosilicate glass outside the gate layer 3, preventing corrosion of the gate metal. The borosilicate glass above the oxide layer has good flatness. By combining the oxide layer and the borosilicate glass, the isolation effect is improved while ensuring the flatness of the intermediate film layer, combining the advantages of different materials.

[0054] The specific preparation method of the oxide layer can be set according to actual needs. For example, an oxide layer can be deposited on the gate layer 3 by chemical vapor deposition. The thickness of the oxide layer can be set according to actual needs, such as 2000-6000 Å. The oxide layer has better leakage protection and breakdown resistance than borosilicate glass, and can also protect the gate from boron and phosphorus penetration into the gate and affect device performance.

[0055] Furthermore, in the third embodiment of the transistor fabrication method of the present invention based on the first embodiment, step S20 includes the following steps: Step S23: An oxide layer is prepared on the gate layer 3 using silicon dioxide; Step S24: Deposit borosilicate glass on the oxide layer to obtain a borosilicate glass layer; Step S25: Reflow the borophosphosilicate glass layer to obtain a dense borophosphosilicate glass layer; Step S26: Clean the boron and phosphorus on the surface of the dense borophosphorus silicon glass layer to obtain the dielectric layer 4.

[0056] When preparing dielectric layer 4, borosilicate glass is first deposited. Specifically, a layer of borosilicate glass is deposited by chemical vapor deposition. The deposition thickness can be set according to actual needs, such as 4000~8000 Å.

[0057] The surface of the deposited borosilicate glass layer will form an uneven groove structure, so it is necessary to smooth the surface of the borosilicate glass layer.

[0058] Reflow refers to a process in which the deposited glassy dielectric film, namely borosilicate glass layer, is softened by high-temperature heat treatment and flows by surface tension, thereby achieving surface planarization.

[0059] By reflowing the borosilicate glass layer to melt it and fill the grooves, a dense borosilicate glass layer with a smooth surface and a compact structure is obtained.

[0060] The specific parameters for the reflux operation can be set based on actual needs, such as setting the reflux temperature to 900℃.

[0061] During the reflow process, boron and phosphorus will precipitate on the surface of the boron-phosphorus-silicon glass. In order to further avoid the influence of the precipitated boron and phosphorus on the adhesion of the metal and subsequent film layers, the dense boron-phosphorus-silicon glass layer is cleaned to remove the precipitated boron and phosphorus on the surface of the dense boron-phosphorus-silicon glass layer, thus obtaining the final prepared dielectric layer 4.

[0062] The specific cleaning operation can be set according to actual needs, such as using a wet cleaning process.

[0063] The above description of the preparation of dielectric layer 4 is only an example. In practical applications, the specific preparation method can be set according to actual needs.

[0064] Furthermore, in the fourth embodiment of the transistor fabrication method of the present invention based on the first embodiment, step S30 includes the following steps: Step S31: Apply photoresist to the dielectric layer 4 at a location other than the source region metal contact hole H. Step S32: Perform a dry etching process to remove the corresponding portion of the dielectric layer 4 that is not coated with photoresist, and expose the silicon carbide substrate layer 2 under the gate layer 3. Step S33: Remove the photoresist.

[0065] Photoresist can protect the underlying material from being etched.

[0066] The source region metal contact hole H is obtained by etching on the dielectric layer 4. Therefore, in order to etch only the location of the source region metal contact hole H to obtain the source region metal contact hole H, in this embodiment, photoresist is coated on the part outside the location of the source region metal contact hole H, so that the subsequent etching process will not affect the part outside the source region metal contact hole H.

[0067] When applying photoresist, it is possible to first apply it completely to the dielectric layer 4, and then expose the photoresist at the source region metal contact hole H.

[0068] After the photoresist coating is completed, a dry etching process is performed to remove the uncoated portion of the dielectric layer 4, thereby realizing the preparation of the source region metal contact hole H.

[0069] It is understandable that the source region metal contact hole H is used to connect the drain region semiconductor material and the metal layer. Therefore, the source region metal contact hole H needs to be etched into the silicon carbide substrate layer 2 under the gate layer 3. This allows the metal layer to connect with the silicon carbide substrate layer 2 after the source region metal contact hole H is filled with the metal layer.

[0070] The silicon carbide substrate 2 is the basic material and starting wafer for transistor manufacturing. The silicon carbide substrate 2 not only provides mechanical support, but also directly constitutes the key part of the drain region and current path of the device; specifically, in this embodiment, the silicon carbide substrate 2 serves as the drain region.

[0071] After etching the source region metal contact hole H, the photoresist can be removed to prepare for the subsequent film layer.

[0072] In this embodiment, photoresist and dry etching are specifically used to prepare the source region metal contact hole H, which improves the reliability of the preparation of the source region metal contact hole H.

[0073] Further, see Figure 8 In the fifth embodiment of the transistor fabrication method of the present invention based on the first embodiment, step S40 includes the following steps: Step S41: An ohmic contact layer 5 is prepared at the bottom of the metal contact hole H in the source region; Step S42: Prepare the metal layer on the ohmic contact layer 5.

[0074] The ohmic contact layer 5 refers to a low-resistance, non-rectifying electrical interface layer formed between a metal and a heavily doped semiconductor region.

[0075] Ohmic contact layer 5 is used to achieve efficient and stable current injection or extraction.

[0076] The ohmic contact layer 5 is disposed at the bottom of the metal contact hole H in the source region and is in direct contact with the silicon carbide substrate layer 2.

[0077] The specific preparation method of the ohmic contact layer 5 can be set according to actual needs, such as sequentially performing nickel deposition, rapid thermal annealing, nickel removal, and secondary rapid thermal annealing to form the ohmic contact layer 5.

[0078] It is understandable that an annealing process is involved in the preparation of the ohmic contact layer 5; at the same time, the preparation of the ohmic contact layer 5 is after the preparation of the dielectric layer 4 and before the preparation of the metal layer. Therefore, the annealing process in the ohmic contact layer 5 can meet the shrinkage requirements of the borosilicate glass in the dielectric layer 4, and no additional annealing process is required.

[0079] Further, step S42 includes the following steps: Step S421: Prepare a barrier metal layer 6 on the ohmic contact layer 5; Step S422: A tungsten metal layer 7 is prepared on the blocking metal layer 6 to fill the source region metal contact hole H; Step S423: Prepare a source metal layer 8 on the tungsten metal layer 7.

[0080] The barrier metal layer 6 is used to enhance the adhesion between the metal and the semiconductor / dielectric, prevent the metal atoms from diffusing into each other, and provide a good nucleation surface to facilitate subsequent metal filling.

[0081] The specific material of the barrier metal layer 6 can be set according to actual needs, such as using a double-layer thin film structure composed of a bottom titanium Ti and an upper titanium nitride TiN; the bottom titanium mainly serves as an adhesion layer, and the upper titanium nitride TiN mainly serves as a diffusion barrier layer.

[0082] The specific preparation method of the barrier metal layer 6 can be set according to actual needs, such as physical vapor deposition.

[0083] Tungsten metal layer 7 fills the metal contact holes with high-melting-point, low-stress, and electromigration-resistant tungsten metal, connecting the lower ohmic contacts to the upper metal wiring. Tungsten metal layer 7 is used to form a low-resistance, high-reliability vertical interconnect structure.

[0084] The barrier layer between the tungsten metal layer 7 and the ohmic contact layer 5 can prevent the tungsten metal layer 7 from reacting harmfully with the underlying material.

[0085] The specific preparation method of the tungsten metal layer 7 can be set according to actual needs, such as tungsten plug metal sputtering.

[0086] It should be noted that the larger the opening of the source region metal contact hole H, the greater the thickness of the barrier metal layer 6 at the bottom and side of the source region metal contact hole H after the barrier metal layer 6 is prepared, and the smaller the tungsten metal layer 7 fills the hole and merges the gap.

[0087] Source metal layer 8 is the topmost metal wiring layer of the transistor, used for metal wiring, pads, and lead-out of device electrodes.

[0088] The source metal layer 8 specifically serves as the main electrode of the source.

[0089] In this embodiment, a complete metal layer structure is achieved by setting a barrier metal layer 6, a tungsten metal layer 7, and a source metal layer 8.

[0090] Further, see Figure 9 In the sixth embodiment of the transistor fabrication method of the present invention based on the first embodiment, the step S10 includes the following steps: Step S50: The gate layer 3 is prepared on the front side of the silicon carbide substrate 2. The gate layer 3 includes a gate oxide layer and a polysilicon layer.

[0091] Polycrystalline silicon is the main material used as the gate electrode in transistors.

[0092] The gate oxide layer is a critical insulating dielectric layer located between the gate and the channel in a transistor.

[0093] Isolation between the gate and the channel can be achieved by setting a gate oxide layer.

[0094] The drain metal layer 1 is a metal electrode formed on the back side of the silicon carbide wafer, used to lead out the terminal of the main current path, i.e., the drain.

[0095] The specific fabrication process of the drain metal layer 1 can be set according to actual needs, such as by deposition and annealing.

[0096] The overall preparation process of this application is described below: 1. After completing the deposition and etching processes of the front-end silicon carbide substrate layer, gate oxide layer and polysilicon layer, first deposit an oxide layer by chemical vapor deposition. This oxide layer can be SiO2 without boron and phosphorus doping, such as LPETOS, PETEOS or PEOX. The oxide layer has a thickness of 2000-6000 Å. Compared with borosilicate glass, the oxide layer has better leakage current prevention and breakdown resistance. At the same time, it can protect the gate from boron and phosphorus penetrating into the gate and affecting the device performance. 2. See Figure 6 Based on the above, a layer of borophosphosilicate glass with a thickness of 4000-8000 Å is deposited by chemical vapor deposition; the borophosphosilicate glass film is made flatter and denser by reflow process, with a reflow temperature of about 900℃; the boron and phosphorus precipitated on the surface of the borophosphosilicate glass is removed by wet cleaning process to obtain dielectric layer 4. 3. See Figure 7 After the pattern is created by photolithography, the source region metal contact hole H is exposed. After a dry etching process, the source region metal contact hole H is etched open. The etching stop layer is the SiC substrate. Then the photoresist is removed. 4. See Figure 8The conventional ohmic contact process involves sequentially depositing Ni metal, rapid thermal annealing, removing Ni metal, and a second rapid thermal annealing to form an ohmic contact.

[0097] The secondary rapid thermal annealing process can reach a temperature of 800-1000℃. After rapid thermal annealing, the borosilicate glass at the top of the source region metal contact hole H shrinks to form a large opening. The size of the opening at the top of the source region metal contact hole H and the shrinkage performance of the borosilicate glass are optimized. By adjusting the boron content in the borosilicate glass, which varies from 1% to 4.5%, the shrinkage performance of the borosilicate glass can be adjusted, thereby controlling the size of the opening at the top of the source region metal contact hole H, which is beneficial to enhancing the filling performance of subsequent metal processes. 5. By adjusting the boron content in borosilicate glass, the effects of different boron contents on the top opening size of the metal contact hole H in the source region and the metal filling effect were explored. The boron content varied from 1% to 4.5%. (See [reference needed]). Figures 2-4 , Figure 2 This is a schematic diagram of metal pore filling when the boron content is 1%; Figure 3 This is a schematic diagram of metal pore filling when the boron content is 2.5%; Figure 4 This is a schematic diagram of metal via filling when the boron content is 4.5%. As shown in the figure, the higher the boron content, the larger the top opening. After subsequent Ti / TiN metal layer deposition, the thickness of the metal layer at the bottom and sidewalls of the source region metal contact hole H is greater, and the tungsten via filling and seam are smaller. For the variation of the top opening size of the source region metal contact hole H and the metal via filling effect, see [link to relevant documentation]. The variation of Ti / TiN metal thickness at the bottom and sidewalls of the source region metal contact hole H with the boron content in BPSG is also shown in [reference needed]. Figure 5 , combined Figures 2-3 The experimental results show that when the boron content in borosilicate glass is 2.5%-3%, the device morphology and metal filling effect are better. It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0098] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0099] This application also provides a transistor fabrication apparatus for implementing the above-described transistor fabrication method, the transistor fabrication apparatus comprising: The first acquisition module is used to acquire the size of the top opening of the metal contact hole in the target source region and match it with the target boron content corresponding to the metal contact hole H in the target source region; The first preparation module is used to prepare a dielectric layer 4 on the gate layer 3, wherein the dielectric layer 4 is prepared by using silicon dioxide and borosilicate glass, and the boron content of the borosilicate glass is the target boron content; The first opening module is used to open the dielectric layer 4 to obtain the source region metal contact hole H; The second preparation module is used to prepare a metal layer on the dielectric layer 4 after the annealing process.

[0100] This transistor fabrication apparatus determines the size of the target source region metal contact hole to be fabricated and matches it with the corresponding target boron content. This allows for a suitable flowability setting of borosilicate glass at the target boron content. After annealing, the dielectric layer 4 fabricated from borosilicate glass shrinks, causing the size of the source region metal contact hole H to reach the size of the target source region metal contact hole H. At the same time, since the top opening size of the source metal contact hole meets the requirements, there is no need for secondary etching, saving the subsequent process of increasing the opening size.

[0101] It should be noted that the first acquisition module in this embodiment can be used to execute step S10 in this application embodiment, the first preparation module in this embodiment can be used to execute step S20 in this application embodiment, the first opening module in this embodiment can be used to execute step S30 in this application embodiment, and the second preparation module in this embodiment can be used to execute step S40 in this application embodiment.

[0102] Further, the first preparation module includes: The first preparation unit is used to prepare an oxide layer on the gate layer 3, wherein the oxide layer is prepared using silicon dioxide; The second preparation unit is used to prepare the borosilicate glass on the oxide layer.

[0103] Further, the first preparation module includes: The first deposition unit is used to prepare an oxide layer on the gate layer 3 using silicon dioxide. Borophosphosilicate glass is deposited on the oxide layer to obtain a borophosphosilicate glass layer; The first reflow unit is used to reflow the borophosphosilicate glass layer to obtain a dense borophosphosilicate glass layer. The first cleaning unit is used to clean the boron and phosphorus on the surface of the dense boron-phosphorus-silicon glass layer to obtain the dielectric layer 4.

[0104] Furthermore, the first opening module includes: The first coating unit is used to coat photoresist at a location other than the source region metal contact hole H on the dielectric layer 4. The first execution unit is used to perform a dry etching process to remove the corresponding portion of the dielectric layer 4 that is not coated with photoresist and expose the silicon carbide substrate layer 2 under the gate layer 3. The first removal unit is used to remove the photoresist.

[0105] Furthermore, the second preparation module includes: The third preparation unit is used to prepare an ohmic contact layer 5 at the bottom of the metal contact hole H in the source region; The fourth preparation unit is used to prepare the metal layer on the ohmic contact layer 5.

[0106] Furthermore, the fourth preparation unit includes: The first fabrication subunit is used to fabricate the barrier metal layer 6 on the ohmic contact layer 5; The first filling subunit is used to fill the source region metal contact hole H by preparing a tungsten metal layer 7 on the barrier metal layer 6. The second preparation subunit is used to prepare the source metal layer 8 on the tungsten metal layer 7.

[0107] Furthermore, the device also includes: The third fabrication module is used to fabricate the gate layer 3 on the front side of the silicon carbide substrate layer 2, wherein the gate layer 3 includes a gate oxide layer and a polysilicon layer.

[0108] To achieve the above objectives, the present invention also provides a transistor, which is prepared by the transistor preparation method described above.

[0109] Reference Figure 10In terms of hardware structure, the electronic device may include components such as a communication module 10, a memory 20, and a processor 30. In the electronic device, the processor 30 is connected to both the memory 20 and the communication module 10. The memory 20 stores a computer program, which is executed by the processor 30. When the computer program is executed, it implements the steps of the above-described method embodiments.

[0110] The communication module 10 can connect to external communication devices via a network. The communication module 10 can receive requests from the external communication devices and can also send requests, instructions, and information to the external communication devices. The external communication devices can be other electronic devices, servers, or IoT devices, such as televisions, etc.

[0111] The memory 20 can be used to store software programs and various data. The memory 20 may primarily include a program storage area and a data storage area. The program storage area may store the operating system, at least one application program required for a function (such as obtaining the size of the metal contact hole in the target source area), etc.; the data storage area may include a database, and may store data or information created based on system usage. Furthermore, the memory 20 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other volatile solid-state storage device.

[0112] The processor 30 is the control center of the electronic device. It connects various parts of the electronic device via various interfaces and lines. By running or executing software programs and / or modules stored in the memory 20, and by calling data stored in the memory 20, it performs various functions and processes data, thereby providing overall monitoring of the electronic device. The processor 30 may include one or more processing units; optionally, the processor 30 may integrate an application processor and a modem processor. The application processor mainly handles the operating system, user interface, and applications, while the modem processor mainly handles wireless communication. It is understood that the modem processor may not be integrated into the processor 30.

[0113] although Figure 10 Not shown, but the above-described electronic device may further include a circuit control module for connecting to a power supply to ensure the normal operation of other components. Those skilled in the art will understand that... Figure 10 The electronic device structure shown does not constitute a limitation on the electronic device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0114] The present invention also proposes a computer-readable storage medium having a computer program stored thereon. The computer-readable storage medium may be... Figure 10 The memory 20 in the electronic device may also be at least one of ROM (Read-Only Memory) / RAM (Random Access Memory), magnetic disk, optical disk, etc. The computer-readable storage medium includes a number of instructions to cause a terminal device with a processor (which may be a television, automobile, mobile phone, computer, server, terminal, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0115] In this invention, the terms "first," "second," "third," "fourth," and "fifth" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0116] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0117] Although embodiments of the present invention have been shown and described above, the scope of protection of the present invention is not limited thereto. It is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, and substitutions to the above embodiments within the scope of the present invention, and such changes, modifications, and substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a transistor, characterized in that, The transistor fabrication method includes: Obtain the top opening size of the metal contact hole in the target source region and match it with the target boron content corresponding to the metal contact hole in the target source region; A dielectric layer is prepared on the gate layer, wherein the dielectric layer is prepared by silicon dioxide and borosilicate glass, and the boron content of the borosilicate glass is the target boron content; The dielectric layer is perforated to obtain source region metal contact holes; After the annealing process, a metal layer is prepared on the dielectric layer.

2. The transistor fabrication method according to claim 1, characterized in that, The step of fabricating a dielectric layer on the gate layer includes: An oxide layer is prepared on the gate layer, and the oxide layer is prepared using silicon dioxide. The borosilicate glass is prepared on the oxide layer.

3. The transistor fabrication method according to claim 1, characterized in that, The fabrication of the dielectric layer on the gate layer includes: An oxide layer is prepared on the gate layer using silicon dioxide; Borophosphosilicate glass is deposited on the oxide layer to obtain a borophosphosilicate glass layer; The borophosphosilicate glass layer is reflowed to obtain a dense borophosphosilicate glass layer; The boron and phosphorus on the surface of the dense borophosphorus silicon glass layer are cleaned to obtain the dielectric layer.

4. The transistor fabrication method according to claim 1, characterized in that, The step of creating a source region metal contact hole by opening a hole in the dielectric layer includes: Photoresist is applied to the dielectric layer at a location other than the metal contact hole location in the source region; A dry etching process is performed to remove the corresponding portion of the dielectric layer that is not coated with photoresist, thereby exposing the silicon carbide substrate layer under the gate layer. Remove the photoresist.

5. The transistor fabrication method according to claim 1, characterized in that, The step of preparing a metal layer on the dielectric layer after the annealing process includes: An ohmic contact layer is prepared at the bottom of the metal contact hole in the source region; The metal layer is prepared on the ohmic contact layer.

6. The transistor fabrication method according to claim 5, characterized in that, The process of preparing the metal layer on the ohmic contact layer includes: A barrier metal layer is prepared on the ohmic contact layer; A tungsten metal layer is prepared in the barrier metal layer to fill the metal contact hole in the source region; A source metal layer is prepared on the tungsten metal layer.

7. The transistor fabrication method according to claim 1, characterized in that, The process prior to fabricating the dielectric layer on the gate layer includes: The gate layer is formed on the front side of the silicon carbide substrate, and the gate layer includes a gate oxide layer and a polysilicon layer.

8. A transistor fabrication apparatus, characterized in that, The transistor fabrication apparatus includes: The first acquisition module is used to acquire the size of the top opening of the metal contact hole in the target source region and match it with the target boron content corresponding to the metal contact hole in the target source region. The first preparation module is used to prepare a dielectric layer on the gate layer, wherein the dielectric layer is prepared using silicon dioxide and borosilicate glass, and the boron content of the borosilicate glass is the target boron content; The first aperture module is used to create apertures in the dielectric layer to obtain source region metal contact holes; The second preparation module is used to prepare a metal layer on the dielectric layer after the annealing process.

9. A transistor, characterized in that, The transistor is prepared by the transistor preparation method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the transistor fabrication method as described in any one of claims 1 to 7.

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