Preparation method of transistor and SRAM (Static Random Access Memory) unit
By introducing an oxide amorphous layer during transistor fabrication and disrupting the ion implantation direction, the static power consumption problem caused by static leakage current in SRAM cells was solved, resulting in reduced static power consumption and improved reliability.
Patent Information
- Application Number
- CN202610042723.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-01-13
- Publication Date
- 2026-04-10
AI Technical Summary
As semiconductor processes advance to nanometer and even sub-nanometer nodes, static power consumption caused by static leakage current of SRAM cells has gradually become a core issue limiting their reliability. Especially in advanced processes below 7nm, static power consumption can account for more than 70% of the total standby power consumption. Furthermore, random fluctuations in the threshold voltage of transistors and channel doping concentration lead to uneven distribution of static leakage current, increasing the uncertainty of overall static power consumption.
By introducing an oxide amorphous layer during transistor fabrication, its amorphous structure disrupts the ion implantation direction, suppressing the channel effect, reducing static leakage current, and applying this transistor in SRAM cells to reduce static power consumption.
This effectively reduces the static leakage current of transistors, thereby reducing the static power consumption of SRAM cells and improving the reliability and stability of SRAM cells.
Smart Images
Figure CN121843155A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor, and in particular to a transistor manufacturing method and SRAM cell. BACKGROUND
[0002] With the semiconductor process entering nanometer level or even sub-nanometer level node, integrated circuits have an increasingly urgent demand for low-power memory. SRAM (Static Random-Access Memory, SRAM) is widely used in processor cache and Internet of Things terminals due to its high-speed access characteristics and high compatibility with logic processes. However, as the process size continues to shrink, the static power consumption of SRAM, i.e., the power consumption generated by the static leakage current (Istandby) in standby state, gradually becomes a core problem that limits its reliability. Since SRAM usually needs to maintain data for a long time, its static power consumption accounts for a significant proportion of the total power consumption as the process advances. Studies have shown that in advanced processes below 7nm, the static power consumption of SRAM can account for more than 70% of the total standby power consumption, becoming a major challenge for high-density storage system design. In nanometer processes, random fluctuations (Random Variations) in parameters such as threshold voltage (Vth) and channel doping concentration of transistors in SRAM cells can cause uneven distribution of static leakage current of the transistors, and some SRAM cells may form an abnormally high leakage path due to process deviation, significantly increasing the uncertainty of the overall static power consumption. SUMMARY
[0003] Therefore, the present application provides a transistor manufacturing method and SRAM cell, which can reduce the static leakage current of the transistor and thus reduce the static power consumption of the SRAM cell.
[0004] In a first aspect, an embodiment of the present application provides a transistor manufacturing method, which includes:
[0005] providing a substrate, the substrate including an active region therein, a gate structure being formed on part of the active region, an offset sidewall being formed on a sidewall surface of the gate structure, and a shallow doped region being formed in the active region on both sides of the gate structure and the offset sidewall;
[0006] forming a main sidewall on a surface of the offset sidewall, and forming an oxide amorphous layer on a surface of the active region on both sides of the gate structure and the offset sidewall when the main sidewall is formed or after the main sidewall is formed;
[0007] after the oxide amorphous layer is formed, performing an ion implantation process to form a source region and a drain region in the active region on both sides of the main sidewall.
[0008] In some embodiments of the present application, the material of the oxide amorphous layer includes silicon oxide.
[0009] In some embodiments of the present application, the thickness of the oxide amorphization layer is less than the thickness of the main spacer, and the thickness of the oxide amorphization layer is 50-180 angstroms.
[0010] In some embodiments of the present application, the main spacer is formed on the surface of the offset spacer, and the process of forming the oxide amorphization layer on the surface of the active region on both sides of the gate structure and the offset spacer after forming the main spacer includes:
[0011] forming a main spacer material layer on the surface of the offset spacer, the top surface of the gate structure, and the surface of the active region;
[0012] etching the main spacer material layer using a dry etching process to remove a portion of the thickness of the main spacer material layer;
[0013] continuing to etch the main spacer material layer using a wet etching process to remove the main spacer material layer on the top surface of the gate structure and the surface of the active region, and to retain a portion of the thickness of the main spacer material layer on the surface of the offset spacer, thereby forming the main spacer on the surface of the offset spacer and the oxide amorphization layer on the surface of the active region on both sides of the gate structure and the offset spacer.
[0014] In some embodiments of the present application, the material of the main spacer material layer includes silicon oxide.
[0015] In some embodiments of the present application, the main spacer is formed on the surface of the offset spacer, and the process of forming the oxide amorphization layer on the surface of the active region on both sides of the gate structure and the offset spacer after forming the main spacer includes:
[0016] forming a main spacer material layer on the surface of the offset spacer, the top surface of the gate structure, and the surface of the active region;
[0017] etching the main spacer material layer using a dry etching process to remove a portion of the thickness of the main spacer material layer;
[0018] continuing to etch the main spacer material layer using a wet etching process to remove the main spacer material layer on the top surface of the gate structure and the surface of the active region, and to retain a portion of the thickness of the main spacer material layer on the surface of the offset spacer, thereby forming the main spacer on the surface of the offset spacer and the oxide amorphization layer on the surface of the active region on both sides of the gate structure and the offset spacer.
[0019] performing an oxygen-containing plasma treatment on the surface of the active region on both sides of the main spacer to form an oxide amorphization layer on the surface of the active region, and the oxygen-containing plasma is electrically neutral.
[0020] In some embodiments of the present application, the oxygen source gas used in the oxygen-containing plasma treatment includes O2 or O3.
[0021] In some embodiments of the present application, the depth of the source region and the drain region is greater than the depth of the shallow doped region.
[0022] In some embodiments of the present application, when performing the ion implantation process to form the source region and the drain region, the energy range of the ion implantation includes 2KeV~6KeV, and the dose range of the ion implantation includes 2E14atom / cm 2 ~2E15atom / cm 2 , and the implantation angle is 0 degree-8 degrees.
[0023] In a second aspect, the embodiments of the present application further provide an SRAM cell, comprising the transistor prepared by the preparation method.
[0024] The embodiments of the present application can have / at least have the following advantages:
[0025] The preparation method of the transistor in the embodiments of the present application includes: providing a substrate, the substrate includes an active region, a gate structure is formed on part of the active region, an offset side wall is formed on the sidewall surface of the gate structure, and a shallow doped region is formed in the active region on both sides of the gate structure and the offset side wall; a main side wall is formed on the surface of the offset side wall, and an oxide amorphous layer is formed on the surface of the active region on both sides of the gate structure and the offset side wall when the main side wall is formed or after the main side wall is formed; after the oxide amorphous layer is formed, an ion implantation process is performed to form a source region and a drain region in the active region on both sides of the main side wall. Since the material of the oxide amorphous layer is a non-crystalline substance, the material of the oxide amorphous layer does not have a fixed crystal structure, and when the ion implantation process is used to form the source region and the drain region in the active region, the oxide amorphous layer effectively "destroys" or changes the direction of the incident ions. When the ions pass through the oxide amorphous layer, they will experience random collisions, so that their direction becomes random when they enter the substrate, thereby inhibiting the channeling effect during ion implantation, reducing the projected range (Rp) of the implanted ions, and thus improving and reducing the static leakage current of the formed transistor. Channeling effect refers to the physical phenomenon that when charged particles are incident along the main crystal axis or crystal plane direction of the crystal, the penetration depth increases significantly due to the reduction of collisions with lattice atoms. When the transistor prepared by the method of the present application is applied to an SRAM (Static Random-Access Memory, SRAM) cell, the static leakage current of the transistor is reduced, thereby reducing the static power consumption of the SRAM cell. In addition, the oxide amorphous layer can also protect the surface of the substrate and reduce lattice damage.
[0026] The details of one or more embodiments of the present application are presented in the following drawings and description. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF DRAWINGS
[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0028] Figure 1 This is a schematic diagram of the structure after forming a gate structure and offset sidewalls on a substrate in a method for fabricating a transistor according to some embodiments of this application;
[0029] Figure 2 This application provides a schematic diagram of the structure after forming the main sidewall material layer in a method for fabricating a transistor, according to some embodiments;
[0030] Figure 3 This application provides schematic diagrams of the structure after forming the main sidewall and the oxide amorphous layer in a method for fabricating a transistor, according to some embodiments;
[0031] Figure 4 This is a schematic diagram of the structure after the source and drain regions are formed in a method for fabricating a transistor according to some embodiments of this application;
[0032] Figure 5 A schematic diagram of the structure after forming the main sidewall in a method for fabricating a transistor according to other embodiments of this application;
[0033] Figure 6 This is a schematic diagram of the structure after forming an oxide amorphous layer in a method for fabricating a transistor according to other embodiments of this application;
[0034] Figure 7 This is a schematic diagram of the structure after the source and drain regions are formed in a method for fabricating a transistor according to other embodiments of this application;
[0035] Figure 8 This is a schematic diagram comparing the static leakage current of a transistor fabricated using the method described in this application with that of a conventional transistor.
[0036] Explanation of reference numerals in the attached figures:
[0037] Substrate 100; Well region 102; Gate dielectric layer 103; Gate electrode 104; Offset sidewall 105; Shallow doped region 106; Main sidewall material layer 107; Main sidewall 108; Oxide amorphous layer 109; Source region 110; Drain region 111; Ion implantation process 10. Detailed Implementation
[0038] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be more thorough and complete.
[0039] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this application's specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0040] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, part, region, layer, doping type, or portion discussed below may be referred to as a second element, part, region, layer, or portion.
[0041] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0042] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0043] The structure of the embodiments of this application should not be limited to the specific shape shown in the accompanying drawings, but includes shape deviations due to, for example, manufacturing techniques.
[0044] This application first provides a method for fabricating a transistor. Figures 1-7 The accompanying drawings are schematic diagrams illustrating the various stages of a transistor fabrication method according to some embodiments of this application. The transistor fabrication method will now be described in detail with reference to the accompanying drawings.
[0045] First, refer to Figure 1 A substrate 100 is provided, which includes an active region. A gate structure (including a gate dielectric layer 103 and a gate electrode 104) is formed on a portion of the active region. An offset sidewall 105 is formed on the sidewall surface of the gate structure. Shallow doped regions 106 are formed in the active regions on both sides of the gate structure and the offset sidewall 105.
[0046] The substrate 100 may be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate 100 may be a layered substrate comprising Si / SiGe, Si / SiC, silicon-on-insulator (SOI), germanium-on-insulator (SOI), or silicon-germanium-on-insulator.
[0047] The substrate 100 includes active regions, on which transistors are subsequently formed. In some embodiments, there may be multiple active regions, and adjacent active regions may be electrically isolated by shallow trench isolation (STI) structures formed in the substrate 100. The materials of the shallow trench isolation structures may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride.
[0048] In some embodiments, a transistor well region 102 may also be formed within the substrate 100. The well region 102 is formed by an ion implantation process, and the well region 102 has different doping types depending on the type of transistor formed. In one specific example, when the formed transistor is an NMOS transistor, the well region 102 is a P-well, and the well region 102 is doped with P-type impurity ions, including one or more of boron ions, aluminum ions, gallium ions, or indium ions. In another specific example, when the formed transistor is a PMOS transistor, the well region 102 is an N-well, and the well region 102 is doped with N-type impurity ions, including one or more of nitrogen ions, phosphorus ions, arsenic ions, or antimony ions.
[0049] The gate structure includes a gate dielectric layer 103 located on the surface of the active region and a gate electrode 104 located on the gate dielectric layer. In a specific example, the gate dielectric layer 103 is made of silicon oxide, and the gate electrode 104 is made of polysilicon.
[0050] Offset sidewalls 105 are formed on the sidewalls of the gate structure, serving as a mask when shallowly doped regions 106 are formed in the active regions on both sides of the gate structure using an ion implantation process. In one example, the material of the offset sidewalls 105 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, and silicon carbonitride.
[0051] The lightly doped region 106, also known as the lightly doped region (LDD), is used to prevent hot carrier effects and suppress short-channel effects. The lightly doped region 106 is formed through an ion implantation process, and the doping type varies depending on the type of transistor being formed. In one specific example, when the transistor being formed is an NMOS transistor, the lightly doped region 106 is doped with N-type impurity ions, which include one or more of nitrogen, phosphorus, arsenic, or antimony ions. In another specific example, when the transistor being formed is a PMOS transistor, the lightly doped region 106 is doped with P-type impurity ions, which include one or more of boron, aluminum, gallium, or indium ions.
[0052] Next, refer to Figure 2 and Figure 3 A main sidewall 108 is formed on the surface of the offset sidewall 105. When forming the main sidewall 108, an oxide amorphous layer 109 is formed on the surface of the active region on both sides of the gate structure and the offset sidewall 105.
[0053] The main sidewall 108 serves as a mask for the subsequent formation of source and drain regions in the active region using ion implantation technology.
[0054] The oxide amorphous layer 109 is made of an amorphous material and does not have a fixed crystal structure. Subsequently, ion implantation is used to form source and drain regions in the active region. The oxide amorphous layer 109 effectively "disrupts" or changes the direction of incident ions. When ions pass through this oxide amorphous layer 109, they undergo random collisions, causing their direction to become random when entering the substrate 100. This suppresses the channeling effect during ion implantation, reduces the projected range (Rp) of the implanted ions, and thus improves and reduces the static leakage current of the formed transistor. The channeling effect refers to the physical phenomenon where charged particles, when incident along the main crystal axis or crystal plane, experience a significant increase in penetration depth due to reduced collisions with lattice atoms. When the transistors fabricated using this method are applied to SRAM (Static Random-Access Memory) cells, the reduced static leakage current of the transistors lowers the static power consumption of the SRAM cells. In addition, the oxide amorphous layer 109 can also protect the surface of the substrate 100 and reduce lattice damage.
[0055] In some embodiments, the material of the oxide amorphous layer 109 includes silicon oxide. The thickness of the oxide amorphous layer 109 cannot be too thick. If it is too thick, during ion implantation, the implanted impurity ions will be retained in the oxide amorphous layer 109, affecting the concentration and depth of the implanted impurity ions implanted into the active region, thereby affecting the impurity ion concentration in the source and drain regions and the formation depth of the source and drain regions. The thickness of the oxide amorphous layer 109 cannot be too thin either. If it is too thin, the oxide amorphous layer 109 cannot effectively "disrupt" or change the direction of the incident ions, which is prone to channing and cannot effectively reduce the projected range (Rp) of the implanted ions, thereby failing to effectively improve and reduce the static leakage current of the formed transistor. Therefore, in a specific example, the thickness of the oxide amorphous layer 109 is less than the thickness of the main sidewall 108, and the thickness of the oxide amorphous layer 109 is 50 angstroms to 180 angstroms, which can be 50 angstroms, 60 angstroms, 70 angstroms, 80 angstroms, 90 angstroms, 100 angstroms, 110 angstroms, 120 angstroms, 130 angstroms, 140 angstroms, 150 angstroms, 160 angstroms, 170 angstroms, or 180 angstroms.
[0056] In some embodiments, forming a main sidewall 108 on the surface of the offset sidewall 105, and forming an oxide amorphous layer 109 on the active region surface on both sides of the gate structure and the offset sidewall 105 during the formation of the main sidewall 108 includes:
[0057] refer to Figure 2 A main sidewall material layer 107 is formed on the surface of the offset sidewall 105, the top surface of the gate structure, and the surface of the active region.
[0058] refer to Figure 3 The main sidewall material layer 107 is etched using a dry etching process to remove part of the thickness of the main sidewall material layer 107.
[0059] Continue to refer to Figure 3 The main sidewall material layer 107 is further etched using a wet etching process, retaining a portion of the thickness of the main sidewall material layer 107 located on the sidewall of the offset sidewall 105 and the surface of the active region. A main sidewall 108 is formed on the surface of the offset sidewall 105, and an oxide amorphous layer 109 is formed on the surface of the active region on both sides of the gate structure and the offset sidewall 105.
[0060] The aforementioned steps enable the simultaneous formation of the main sidewall 108 and the oxide amorphous layer 109, simplifying the process. Furthermore, the thickness of the formed oxide amorphous layer 109 can be less than the thickness of the main sidewall 108. In addition, performing dry etching first, followed by wet etching, reduces plasma damage caused by dry etching and allows for precise control of the thickness of the remaining main sidewall material layer on the active region surfaces on both sides of the gate structure and the offset sidewall 105, i.e., the thickness of the oxide amorphous layer 109.
[0061] In some embodiments, the material of the main sidewall material layer 107 includes silicon oxide. The main sidewall material layer 107 can be formed using high-pressure chemical vapor deposition (HPCVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma-enhanced chemical vapor deposition (HDPCVD), or atomic layer chemical vapor deposition (ALCVD). Dry etching uses etching gases including CF4, CHF3, C4F8, or C4F6, while wet etching uses etching solutions including diluted hydrofluoric acid (DHF).
[0062] In other embodiments, reference is made to... Figure 6 The oxide amorphous layer 109 can be formed after the main sidewall 108 is formed.
[0063] In one specific embodiment, a main sidewall 108 is formed on the surface of the offset sidewall 105. After forming the main sidewall 108, the process of forming an oxide amorphous layer 109 on the active region surface on both sides of the gate structure and the offset sidewall 105 includes:
[0064] refer to Figure 5 A main sidewall material layer is formed on the surface of the offset sidewall 105, the top surface of the gate structure, and the surface of the active region. The main sidewall material layer is etched using a dry etching process to remove a portion of the thickness of the main sidewall material layer 107. The main sidewall material layer is then etched using a wet etching process to remove the main sidewall material layer on the top surface of the gate structure and the surface of the active region, while retaining a portion of the thickness of the main sidewall material layer 107 on the surface of the offset sidewall 105 to form the main sidewall 108.
[0065] refer to Figure 6 The active region surfaces on both sides of the main sidewall 108 are treated with oxygen-containing plasma to form an oxide amorphous layer 109 on the surface of the active region, and the oxygen-containing plasma is electrically neutral.
[0066] The difference between this embodiment and the previous embodiment is that when forming the main sidewall 108, the main sidewall material layer on the surface of the active region is removed, leaving no thickness. Then, oxygen-containing plasma treatment is performed on the surface of the active region on both sides of the main sidewall 108 to form an oxide amorphous layer 109 on the surface of the active region. In addition to the effects described above, the oxide amorphous layer 109 formed in this way has the following advantages: In the method of the previous embodiment, due to the influence of dry etching plasma, the remaining main sidewall material layer on the surface of the active region may exhibit charging phenomenon when it becomes the oxide amorphous layer 109. This may lead to changes in saturation current and threshold voltage. However, in this embodiment, this possible situation can be completely avoided. When oxygen-containing plasma treatment is performed on the surface of the active region on both sides of the main sidewall 108, since the oxygen-containing plasma is electrically neutral, there will be no charging phenomenon when the oxide amorphous layer 109 is formed on the surface of the active region, thus preventing changes in saturation current and threshold voltage.
[0067] In some embodiments, the oxygen source gas used in oxygen-containing plasma treatment includes O2 or O3.
[0068] Finally, refer to Figure 4 or Figure 7 After forming the oxide amorphous layer 109, an ion implantation process 10 is performed to form a source region 110 and a drain region 111 in the active regions on both sides of the main sidewall 108.
[0069] The depths of the source region 110 and the drain region 111 are greater than the depth of the shallow doped region 106, and the concentrations of impurity ions implanted in the source region 110 and the drain region 111 are greater than the concentrations of impurity ions implanted in the shallow doped region 106.
[0070] Depending on the type of transistor formed, the source region 110 and drain region 111 have different doping types. In one specific example, when the formed transistor is an NMOS transistor, the source region 110 and drain region 111 are doped with N-type impurity ions, which include one or more of nitrogen ions, phosphorus ions, arsenic ions, or antimony ions. In another specific example, when the formed transistor is a PMOS transistor, the source region 110 and drain region 111 are doped with P-type impurity ions, which include one or more of boron ions, aluminum ions, gallium ions, or indium ions.
[0071] In some embodiments, when performing ion implantation process 10 to form source region 110 and drain region 111, the ion implantation energy range includes 2 keV to 6 keV, and the ion implantation dose range includes 2E14 atom / cm². 2 ~2E15atom / cm 2 The injection angle is 0 degrees to 8 degrees.
[0072] refer to Figure 8 , Figure 8 This is a comparative schematic diagram of a transistor fabricated using the method of this application (with an oxide amorphous layer 109 of 60-100 angstroms on the surface of the active region) and a conventional transistor (without an oxide amorphous layer or silicon oxide layer on the surface of the active region). The horizontal axis represents different wafer numbers, on which several transistors are fabricated, and the vertical axis represents the order of magnitude of the static leakage current. It can be clearly seen from the figure that the static leakage current of the transistor fabricated using the method of this application is one order of magnitude smaller than that of the conventional transistor.
[0073] This application also provides an SRAM cell, including a transistor prepared by the aforementioned preparation method.
[0074] In some embodiments, the SRAM cell includes a 6T-SRAM cell, which includes a latch / cross-coupled inverter and a transmission gate.
[0075] The latch / cross-coupled inverter consists of two inverters composed of four transistors: Inverter 1 (INV1): composed of one PMOS transistor (pull-up) and one NMOS transistor (pull-down). Inverter 2 (INV2): also composed of one PMOS transistor (pull-up) and one NMOS transistor (pull-down). The inputs and outputs of these two inverters (INV1 and INV2) are cross-connected (the output of INV1 is connected to the input of INV2, and the output of INV2 is connected to the input of INV1). This structure forms a bistable circuit, which can stably exist in one of two states (state 0 and state 1). Once the power is turned on, the circuit will "latch" in one of the states, thereby achieving non-volatile data storage (the data will not be lost as long as power is supplied).
[0076] The transmission gate is the interface between the SRAM cell and the outside world (bit line). It consists of two NMOS transistors: Transmission gate 1 (PG1): an NMOS transistor whose gate is connected to the word line, one end of its source / drain is connected to a memory node (Q) of the latch / cross-coupled inverter, and the other end is connected to the bit line; Transmission gate 2 (PG2): an NMOS transistor whose gate is connected to the word line, one end of its source / drain is connected to another memory node (Q_bar) of the latch / cross-coupled inverter, and the other end is connected to the complementary bit line.
[0077] When the memory cell needs to be read or written: a high voltage is applied to the word line, the two transmission gate NMOS transistors are turned on, and the memory nodes Q and Q_bar are connected to the bit line and complementary bit line respectively.
[0078] In the 6T-SRAM cell itself, the four transistors of the latch / cross-coupled inverter (including two pull-up PMOS transistors and two pull-down NMOS transistors) and the two transistors in the transmission gate (including two transmission gate NMOS transistors) are all fabricated by the aforementioned fabrication method of this application. The transistors fabricated by the aforementioned method of this application have low static leakage current, and when applied to the 6T-SRAM cell, the static power consumption of the 6T-SRAM cell is reduced.
[0079] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0080] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0081] The above embodiments merely illustrate several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method for fabricating a transistor, characterized in that, include: A substrate is provided, the substrate including an active region, a gate structure is formed on a portion of the active region, an offset sidewall is formed on the sidewall surface of the gate structure, and a shallow doped region is formed in the active region on both sides of the gate structure and the offset sidewall. A main sidewall is formed on the surface of the offset sidewall. During or after the formation of the main sidewall, an oxide amorphous layer is formed on the surface of the active region on both sides of the gate structure and the offset sidewall. After the oxide amorphous layer is formed, an ion implantation process is performed to form source and drain regions in the active regions on both sides of the main sidewall.
2. The method for fabricating a transistor according to claim 1, characterized in that, The material of the oxide amorphous layer includes silicon oxide.
3. The method for fabricating a transistor according to claim 1 or 2, characterized in that, The thickness of the oxide amorphous layer is less than the thickness of the main sidewall, and the thickness of the oxide amorphous layer is 50 angstroms to 180 angstroms.
4. The method for fabricating a transistor according to claim 3, characterized in that, The process of forming a main sidewall on the surface of the offset sidewall, and forming an oxide amorphous layer on the surface of the active region on both sides of the gate structure and the offset sidewall during the formation of the main sidewall, includes: A main sidewall material layer is formed on the surface of the offset sidewall, the top surface of the gate structure, and the surface of the active region; The main sidewall material layer is etched using a dry etching process to remove a portion of the thickness of the main sidewall material layer. The main sidewall material layer is further etched using a wet etching process, retaining a portion of the thickness of the main sidewall material layer located on the sidewall of the offset sidewall and the surface of the active region. The main sidewall is formed on the surface of the offset sidewall, and an oxide amorphous layer is formed on the surface of the active region on both sides of the gate structure and the offset sidewall.
5. The method for fabricating a transistor according to claim 4, characterized in that, The material of the main sidewall material layer includes silicon dioxide.
6. The method for fabricating a transistor according to claim 3, characterized in that, The process of forming a main sidewall on the surface of the offset sidewall, and then forming an oxide amorphous layer on the surface of the active region on both sides of the gate structure and the offset sidewall after forming the main sidewall, includes: A main sidewall material layer is formed on the surface of the offset sidewall, the top surface of the gate structure, and the surface of the active region; The main sidewall material layer is etched using a dry etching process to remove a portion of the thickness of the main sidewall material layer. The main sidewall material layer is further etched using a wet etching process to remove the main sidewall material layer on the top surface of the gate structure and the surface of the active region, while retaining a portion of the thickness of the main sidewall material layer on the surface of the offset sidewall to form the main sidewall. The active area surfaces on both sides of the main sidewall are subjected to oxygen-containing plasma treatment to form an oxide amorphous layer on the surface of the active area, and the oxygen-containing plasma is electrically neutral.
7. The method for fabricating a transistor according to claim 6, characterized in that, The oxygen source gas used in the oxygen-containing plasma treatment includes O2 or O3.
8. The method for fabricating a transistor according to claim 1, characterized in that, The depths of the source region and the drain region are greater than the depth of the shallow doped region.
9. The method for fabricating a transistor according to claim 8, characterized in that, When performing ion implantation to form source and drain regions, the ion implantation energy range is 2 keV to 6 keV, and the ion implantation dose range is 2E14 atom / cm². 2 ~2E15atom / cm 2 The injection angle is 0 degrees to 8 degrees.
10. An SRAM cell, characterized in that, include: The transistor prepared by the preparation method according to any one of claims 1-9.