Semiconductor structure and method for forming the same

Abstract

In one embodiment, a method for forming a semiconductor structure includes forming a plurality of nanostructures, forming a gate structure on the nanostructures, forming a source / drain feature adjacent the gate structure, forming a source / source contact feature on the source / drain feature, forming a dielectric layer on the gate structure and the source / drain contact feature, etching the dielectric layer to form a first opening on the gate structure and a second opening on the source / drain contact feature, forming a metal liner layer in the first opening and the second opening, removing a portion of the metal liner layer to form a metal liner on a bottom of the first opening and the second opening, and removing the metal liner layer from the metal liner layer. And depositing a conductive material layer on the metal liner to fill the first opening and the second opening to form a first via contact feature in the first opening and a second via contact feature in the second opening. The embodiment of the invention also relates to a semiconductor structure.

Description

Technical Field

[0001] Embodiments of this disclosure relate to semiconductor structures and methods of forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. While scaling down improves production efficiency and reduces costs, it also introduces greater complexity in the handling and manufacturing of ICs. Summary of the Invention

[0003] Embodiments of this application provide a method for forming a semiconductor structure, comprising: forming a plurality of nanostructures; forming a gate structure on the nanostructures; forming source / drain components adjacent to the gate structure; forming source / drain contact components on the source / drain components; forming a dielectric layer on the gate structure and the source / drain contact components; etching the dielectric layer to form a first opening on the gate structure and a second opening on the source / drain contact components; forming a metal liner layer in the first opening and the second opening; removing a portion of the metal liner layer to form a metal liner at the bottom of the first opening and the second opening; and depositing a conductive material layer on the metal liner to fill the first opening and the second opening, and forming a first via contact component in the first opening and a second via contact component in the second opening.

[0004] Another embodiment of this application provides a method for forming a semiconductor structure, comprising: forming a vertically stacked nanostructure above a substrate; forming a gate structure around and above the nanostructure; forming a source / drain component above the substrate, wherein the source / drain component is adjacent to the nanostructure; forming a source / drain contact component in contact with the source / drain component, wherein the source / drain contact component has a top surface coplanar with the top surface of the gate structure, and wherein the source / drain contact component and the gate structure are laterally surrounded by a first dielectric layer; and in the first dielectric layer, the source / drain contact component and the gate structure are laterally surrounded by a first dielectric layer; An etch stop layer is formed over the drain contact and the gate structure; a second dielectric layer is formed over the etch stop layer; a first opening and a second opening are formed extending through the second dielectric layer and the first dielectric layer, wherein the first opening exposes the gate structure and the second opening exposes the source / drain contact; a metal liner is formed only on the bottom surfaces of the first opening and the second opening; and a first via contact is formed in the first opening to be electrically coupled to the gate structure, and a second via contact is formed in the second opening to be electrically coupled to the source / drain contact.

[0005] Another embodiment of this application provides a semiconductor structure, including: a vertically stacked nanostructure located above a substrate; a gate structure enclosing the nanostructure; a source / drain component adjacent to the nanostructure; a source / drain contact component located above the source / drain component; an etch stop layer located above the gate structure and the source / drain contact component; a dielectric layer located above the etch stop layer; a gate via contact component extending through the dielectric layer and the etch stop layer and electrically coupled to the gate structure via a first metal liner; and a source / drain via contact component extending through the dielectric layer and the etch stop layer and electrically coupled to the source / drain contact component via a second metal liner, wherein the dielectric layer contacts the sidewalls of the gate via contact component and the source / drain via contact component, and the etch stop layer contacts the sidewalls of the first metal liner and the second metal liner. Attached Figure Description

[0006] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the individual components may be arbitrarily increased or decreased.

[0007] Figure 1 This is a flowchart of a method for manufacturing a gate-all-around (GAA) device according to some embodiments of the present disclosure.

[0008] Figures 2 to 25Some embodiments according to this disclosure are shown. Figure 1 Various views of GAA devices during the manufacturing process of the method. Detailed Implementation

[0009] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0010] Additionally, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Besides the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0011] In FET fabrication, source / drain via contacts (VDs) are typically formed vertically to electrically couple the source / drain contact structure to the upper-level interconnect structure. Similarly, gate via contacts (VGs) extend vertically to establish an electrical connection between the metal gate and the upper-level interconnect structure. In some embodiments, forming these via contacts includes forming openings in a dielectric layer, filling the openings with a conductive material, and performing planarization processes (such as chemical mechanical polishing (CMP)) to refine the conductive material.

[0012] In the prior art, source / drain via contacts (VD) and gate via contacts (VG) are typically made of different metals and require separate fabrication processes. Therefore, different contact masks are needed to define their respective formation areas and / or accommodate different metal depositions. However, as transistor dimensions continue to shrink, the spacing between the metal gate and source / drain contacts becomes increasingly limited. Misalignment between contact masks during separate etching processes can lead to unintended short circuits between the gate via contacts and the source / drain via contacts. Furthermore, the additional steps required to separately form the gate via contacts and source / drain via contacts increase manufacturing costs.

[0013] In embodiments of this disclosure, the same metal is used to form both the gate via contact and the source / drain via contact. As a result, the same mask or mask set can be used to form both the gate via contact and the source / drain via contact simultaneously, which reduces the number of masks required and thus lowers manufacturing costs.

[0014] The disclosed methods and structures can be applied to ICs having FinFETs, gate-all-around (GAA) transistors, or other types of transistors. A GAA transistor is a transistor having a gate stack (including the gate electrode and the gate dielectric) surrounding a channel nanostructure (such as vertically stacked horizontal nanowires or nanosheets).

[0015] The gate-all-around (GAA) transistor structure described below can be patterned using any suitable method. For example, the structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0016] Figure 1 This is a flowchart of a method 100 for forming a GAA device 200 according to some embodiments of the present disclosure. Figures 2 to 25 These are various views of the GAA device 200 at various stages of method 100 according to some embodiments. The following reference is made to the GAA device 200 in conjunction with... Figures 2 to 25 Some embodiments of method 100 are described. Method 100 is merely an example and is not intended to limit this disclosure beyond the scope expressly referenced in the claims. Additional operations may be provided before, during, and after method 100, and some of the described operations may be replaced, eliminated, or rearranged for additional embodiments of the method.

[0017] refer to Figure 1 and Figure 2 Method 100 includes operation 102, in which an initial structure of GAA device 200 is provided. The initial structure includes a substrate 202 and a stack of alternating epitaxial semiconductor layers 204 located above the substrate 202. Figure 2 This is a cross-sectional view of the GAA device 200 after the stack of alternating epitaxial semiconductor layers 204 is formed on the substrate 202.

[0018] Substrate 202 can be any suitable substrate and can be processed to have various components. In some embodiments, substrate 202 can be a semiconductor substrate, such as a silicon substrate. In some embodiments, substrate 202 includes various layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 202 can include various doping configurations. For example, different doping profiles (e.g., n-wells, p-wells) can be formed on substrate 202 in regions designed for different device types (e.g., n-type FETs, p-type FETs). Suitable doping can include ion implantation and / or diffusion processes of dopants. Even if not shown, substrate 202 includes isolation components (e.g., shallow trench isolation (STI) components) between regions providing different device types. Substrate 202 includes other semiconductors, such as germanium or diamond. Optionally, substrate 202 includes compound semiconductors, such as silicon carbide (SiC), gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, GaInAsP, and / or other suitable materials. Additionally, the substrate 202 may optionally include an epitaxial layer, which may be strained for performance enhancement, may include a silicon-on-insulator structure, and / or may have other suitable enhancement components.

[0019] A stack 204 of alternating epitaxial semiconductor layers is blanket-deposited on a substrate 202. The stack 204 includes alternating sacrificial semiconductor layers 206 and channel semiconductor layers 208, wherein the channel semiconductor layer 208 forms the top layer and the sacrificial semiconductor layer 206 forms the bottom layer. In some embodiments, the sacrificial semiconductor layer 206 comprises a first semiconductor material, and the channel semiconductor layer 208 comprises a second semiconductor material different from the first semiconductor material. The materials of the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 can be selected based on providing different etch selectivity. For example, in some embodiments, the first semiconductor material may comprise germanium (Ge) or silicon germanium (SiGe), while the second semiconductor material may comprise silicon (Si). In some alternative embodiments, the first semiconductor material comprises SiGe having a first Ge content, and the second semiconductor material comprises SiGe having a second Ge content lower than the first Ge content. In various embodiments, the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 are substantially dopant-free (i.e., having less than about 1 × 10⁻⁶ dopants). 17 cm -3 (exogenous dopant concentration).

[0020] In some embodiments, the sacrificial semiconductor layer 206 can be removed in a later process, leaving a channel semiconductor layer 208 that defines a channel nanostructure for the GAA device 200 (e.g., Figure 11(208C). Therefore, the thickness of the sacrificial semiconductor layer 206 determines the spacing between adjacent channel nanostructures. In some embodiments, the thickness of the sacrificial semiconductor layer 206 can range from about 8 nm to about 15 nm. The thickness of the channel semiconductor layer 208 is selected based on, for example, manufacturing considerations, transistor performance considerations, etc. In some embodiments, the thickness of the channel semiconductor layer 208 can range from about 4 nm to about 10 nm.

[0021] The number of sacrificial semiconductor layer 206 and channel semiconductor layer 208 depends on the desired number of channel nanostructures in the GAA device 200. In some embodiments, the number of channel semiconductor layers 208 is, for example, from 2 to 10, to form a stack of 2 to 10 vertically spaced channel nanostructures. In some embodiments, and as... Figure 2 As shown, the stack 204 includes four (4) sacrificial semiconductor layers 206 and three (3) channel semiconductor layers 208.

[0022] The sacrificial semiconductor layer 206 and the channel semiconductor layer 208 are epitaxially grown layer by layer from the top surface of the substrate 202. In some embodiments, the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 are grown using molecular beam epitaxy (MBE), chemical vapor deposition (CVD) processes (such as metal-organic CVD (MOCVD)), or other suitable epitaxial growth processes. The epitaxial growth results in the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 having the same crystal orientation as the substrate 202.

[0023] refer to Figure 1 and Figure 3 Method 100 proceeds to operation 104, wherein, according to some embodiments, at least one fin structure 210 is formed from the stack 204. Figure 3 This is a cross-sectional view of the GAA device 200 after at least one fin structure 210 has been formed.

[0024] In some embodiments, portions of the stack 204 and the substrate 202 are patterned to form at least one fin structure 210. Each fin structure 210 extends perpendicularly from the substrate 202 along the Z direction and has a length dimension along the X direction and a width dimension along the Y direction. The width of each fin structure 210 can range from about 10 nm to about 90 nm. Each fin structure 210 includes a base portion 210B and a fin stack portion 210S. The base portion 210B is formed by the substrate 202, while the fin stack portion 210S is formed by the stack 204 and includes a portion of a sacrificial semiconductor layer 206 (hereinafter referred to as sacrificial semiconductor portion 206P) and a portion of a channel semiconductor layer 208 (hereinafter referred to as channel semiconductor portion 208P).

[0025] In some embodiments, at least one fin structure 210 may be formed using photolithography and etching processes. During the photolithography process, a hard mask layer (not shown) may first be formed over the topmost surface of the stack 204. In some embodiments, the hard mask layer comprises a dielectric material, such as, for example, silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbide (SiOC), silicon carbonitride oxynitride (SiOCN), or combinations thereof. In some embodiments, the hard mask layer is formed by chemical CVD, plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition processes. In some embodiments, the hard mask layer may have a bilayer structure, comprising a pad oxide layer and a pad nitride layer formed over the pad oxide layer. In some embodiments, the pad oxide layer comprises silicon oxide, which may be formed by thermal oxidation. The pad nitride layer comprises SiN, which may be formed by CVD, PECVD, PVD, ALD, or other suitable deposition processes.

[0026] Subsequently, a photoresist layer is applied to a hard mask layer, for example, by spin coating. The photoresist layer is then exposed according to a patterned mask and developed to form a pattern within it. The patterned photoresist layer can be used as an etching mask to pattern other layers. In some embodiments, the patterned photoresist layer is performed using extreme ultraviolet (EUV) lithography. The patterned photoresist layer is then used to protect regions of substrate 202 and the sacrificial semiconductor layer 206 and channel semiconductor layer 208 formed thereon, while the etching process forms the fin structure 210. In some embodiments, the etching process can be a dry etching process (such as plasma etching or reactive ion etching (RIE)), a wet etching process, or a combination thereof.

[0027] In various other embodiments, the fin structure 210 can be formed using suitable processes, including dual-patterning or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, allowing the creation of patterns with, for example, smaller pitches than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. A mandrel is formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining mandrel is used as an etch mask to pattern the stack 204 and the substrate 202 to provide the fin structure 210.

[0028] Subsequently, isolation components (not shown) can be formed over the substrate 202 and on the opposite sides of the fin structure 210. In some embodiments, the isolation components may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, fluorine-doped silicate glass (FSG), low-k dielectric, and / or other suitable dielectric materials. In an example process, the isolation components can be formed by first depositing a dielectric layer over the substrate 202 to fill the trenches between the fin structures 210. In various examples, the dielectric layer can be deposited using CVD processes, subatmospheric pressure CVD (SACVD) processes, flowable CVD processes, atomic layer deposition (ALD) processes, physical vapor deposition (PVD) processes, spin coating, and / or other suitable processes. The deposited dielectric material is then planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed using a suitable anisotropic etching process to expose at least one fin stack portion 210S of the fin structure 210. In some embodiments, the anisotropic etching process is a dry etching process, a wet etching process, or a combination thereof. In some embodiments, the top surface of the isolation member is substantially flush with or lower than the bottom surface of the bottommost sacrificial semiconductor portion 206P, such that the fin stack portion 210S rises above the isolation member.

[0029] Next, if the hard mask layer was not removed during the formation of the isolation component, the hard mask layer is removed from the topmost surface of the fin structure 210. The removal of the hard mask layer can be performed using an anisotropic etching process. The etching process can be a dry etching process (such as RIE), a wet etching process, or a combination thereof.

[0030] refer to Figure 1 and Figure 4 Method 100 continues to operation 106, wherein, according to some embodiments, a sacrificial gate structure 220 is formed over at least one fin structure 210. Figure 4 This is a cross-sectional view of the GAA device 200 after the sacrificial gate structure 220 has been formed. The sacrificial gate structure 220 is formed across the fin structure 210, along the sidewalls of the fin structure 210, and at the top surface.

[0031] The sacrificial gate structure 220 includes sacrificial gate stacks (222, 224) and gate spacers 226. In embodiments of this disclosure, the sacrificial gate stacks (222, 224) are replaced with metal gate stacks.

[0032] In some embodiments, the sacrificial gate stack (222, 224) includes a sacrificial gate dielectric 222 and a sacrificial gate electrode 224 located on the sacrificial gate dielectric 222. In some embodiments, the sacrificial gate stack (222, 224) may further include a sacrificial gate cap (not shown) located on top of the sacrificial gate electrode 224.

[0033] In some embodiments, the sacrificial gate dielectric 222 may be made of silicon oxide, silicon nitride, or silicon oxynitride. The sacrificial gate electrode 224 may be made of silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the sacrificial gate stack (222, 224) may be formed by first conformally depositing a sacrificial gate dielectric layer over the fin structure 210 and the isolation member. Then, a sacrificial gate electrode layer is blanket-deposited on the sacrificial gate dielectric layer such that the fin structure 210 is fully embedded in the sacrificial gate electrode layer. In some embodiments, the thickness of the sacrificial gate dielectric layer may be in the range of about 1 nm to about 5 nm. In some embodiments, the thickness of the sacrificial gate electrode layer may be in the range of about 100 nm to about 200 nm. In some embodiments, the sacrificial gate electrode layer undergoes a planarization operation, such as CMP. The sacrificial gate dielectric layer and the sacrificial gate electrode layer may be deposited using CVD, PECVD, PVD, ALD, or other suitable deposition processes. Subsequently, the sacrificial gate dielectric layer and the sacrificial gate electrode layer are patterned using photolithography and etching processes. For example, a photoresist layer (not shown) is applied over a sacrificial gate electrode layer, and the photoresist layer is photolithographically patterned by photolithographic exposure and development. The pattern in the photoresist layer is sequentially transferred to the sacrificial gate electrode layer and the sacrificial gate dielectric layer via at least one anisotropic etching process, thereby forming a sacrificial gate stack (222, 224) comprising the remaining portions of the sacrificial gate dielectric layer and the sacrificial gate electrode layer. The anisotropic etching process can be a dry etching process (e.g., RIE), a wet etching process, or a combination thereof. If not completely consumed, the remaining photoresist layer after forming the sacrificial gate stack (222, 224) is removed by, for example, ashing.

[0034] Gate spacer 226 is disposed on the sidewalls of the sacrificial gate stack (222, 224). In some embodiments, gate spacer 226 may comprise a dielectric material, such as, for example, an oxide, a nitride, an oxide oxynitride, or a combination thereof. In some embodiments, gate spacer 226 is made of silicon nitride. In some embodiments, gate spacer 226 may be formed by first depositing a conformal gate spacer material layer on the exposed surfaces of the sacrificial gate stack (222, 224), the fin structure 210, and the isolation member, and then etching the gate spacer material layer to remove the horizontal portion of the gate spacer material layer. In some embodiments, the gate spacer material layer may be deposited, for example, by CVD, PECVD, or ALD. In some embodiments, the gate spacer material layer may be etched by dry etching, such as, for example, plasma etching or RIE. Vertical portions of the gate spacer material layer present on the sidewalls of the sacrificial gate stack (222, 224) constitute gate spacer 226.

[0035] refer to Figure 1 and Figure 5 Method 100 proceeds to operation 108, wherein, according to some embodiments, a source / drain trench 230 is formed in at least one fin structure 210. Figure 5 This is a cross-sectional view of the GAA device 200 after the source / drain trench 230 has been formed.

[0036] The source / drain trench 230 may extend through the fin stack portion 210S. In some embodiments, the sacrificial semiconductor portion 206P and the channel semiconductor portion 208P in the source / drain region or the region not covered by the sacrificial gate structure 200 are etched using the sacrificial gate structure 220 as an etching mask to form the source / drain trench 230. The etching may be performed by a dry etching process, such as plasma etching or RIE. Exemplary dry etching processes may employ oxygen-containing gases, hydrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma and / or combinations thereof. Alternatively, etching can be performed using a wet etching process that employs an etchant such as a mixture of ammonium hydroxide, hydrogen peroxide, and water (APM), tetramethylammonium hydroxide (TMAH), or ammonium hydroxide (NH4OH). Figure 5 As shown, the sidewalls of the sacrificial semiconductor portion 206P and the channel semiconductor portion 208P are exposed in the source / drain trench 230. In some embodiments, the substrate portion 210B may also be partially etched such that the source / drain trench 230 extends into the substrate portion 210B. Therefore, the bottom surface of the source / drain trench 230 may be coplanar with or lower than the top surface of the substrate portion 210B.

[0037] refer to Figure 1 and Figure 6 Method 100 proceeds to operation 110, wherein, according to some embodiments, the sacrificial semiconductor portion 206P is recessed to form a lateral opening 232. Figure 6 This is a cross-sectional view of the GAA device 200 after the sacrificial semiconductor portion 206P is recessed to form a lateral opening 232.

[0038] The end portion of the sacrificial semiconductor portion 206P exposed in the source / drain trench 230 is selectively and laterally recessed to form a lateral opening 232 between the channel semiconductor portions 208P, while the exposed channel semiconductor portions 208P are substantially unetched.

[0039] In some embodiments, a wet etching process may be performed to selectively remove a portion of the sacrificial semiconductor portion 206P located below the gate spacer 226. In some embodiments, the amount of sacrificial semiconductor portion 206P etched is controlled such that the lateral etch distance is no greater than the width of the gate spacer 226. Depending on the materials forming the sacrificial semiconductor portion 206P and the channel semiconductor portion 208P, the wet etching process may use etchants such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), and potassium hydroxide (KOH) solutions. Optionally, operation 110 may first selectively oxidize the lateral ends of the sacrificial semiconductor portion 206P exposed in the source / drain trench 230 to improve the etch selectivity between the sacrificial semiconductor portion 206P and the channel semiconductor portion 208P. In some embodiments, an oxidation process may be performed by exposing the GAA device 200 to a wet oxidation process, a dry oxidation process, or a combination thereof. The remaining portion of the sacrificial semiconductor portion 206P is referred to herein as the recessed sacrificial semiconductor portion 206R.

[0040] refer to Figure 1 and Figure 7 Method 100 proceeds to operation 112, wherein, according to some embodiments, an internal spacer 234 is formed in the transverse opening 232. Figure 7 This is a cross-sectional view of the GAA device 200 after the internal spacer 234 has been formed.

[0041] To form the internal spacer 234, an internal spacer material layer is deposited over the various components of the GAA device 200 and in the lateral opening 232. In some embodiments, the internal spacer material layer may include a dielectric nitride, such as silicon nitride, silicon carbonitride, silicon carbonitride, or any suitable dielectric material. In some embodiments, the internal spacer material layer may be formed by CVD, ALD, or any other suitable conformal deposition process. In some embodiments, the internal spacer material layer may be formed to a thickness such that the lateral opening 232 is completely filled by the internal spacer material layer, such that the resulting internal spacer 234 contacts the sidewall of the recessed sacrificial semiconductor portion 206R.

[0042] An etching process (such as an anisotropic etching process) is then performed to remove a portion of the internal spacer material layer disposed outside the transverse opening 232. The remaining portion of the internal spacer material layer (i.e., the portion disposed within the internal spacer recess) forms the internal spacer 234. In some embodiments, the anisotropic etching process may be a wet etching process, which includes using an etchant such as, for example, buffered hydrofluoric acid (BHF), hydrofluoric acid (HF), hydrofluoric acid diluted with nitric acid (HNA), phosphoric acid, HF diluted with ethylene glycol (HFEG), hydrochloric acid (HCl), or any combination thereof. In some embodiments, the anisotropic etching process may be a dry etching process, which includes using oxygen-containing gas, hydrogen, nitrogen, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas (e.g., CF3I), other suitable gases and / or plasma and / or combinations thereof.

[0043] refer to Figure 1 and Figure 8 Method 100 proceeds to operation 114, wherein, according to some embodiments, a source / drain component 240 is formed in a source / drain trench 230. Figure 8 This is a cross-sectional view of the GAA device 200 after the source / drain components 240 have been formed.

[0044] The source / drain component 240 is disposed on the opposite side of the sacrificial gate structure 220, the channel semiconductor portion 208P and the recessed sacrificial semiconductor portion 206R, such that the source / drain component 240 is in contact with the channel semiconductor portion 208P, but is separated from the recessed sacrificial semiconductor portion 206R by the internal spacer 234.

[0045] Source / drain components 240 are epitaxially grown in source / drain trench 230. The epitaxial process may include CVD deposition (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD)), molecular beam epitaxy (MBE), other suitable selective epitaxial growth (SEG) processes, or combinations thereof. During the epitaxial process, the source / drain components 240 are grown from exposed semiconductor surfaces, including the sidewall surfaces of the channel semiconductor portion 208P and the sidewall surfaces of the substrate portion 210B.

[0046] The source / drain component 240 may comprise any suitable material for an n-type or p-type FET device. For example, when forming an n-type FET device, the source / drain component 240 may comprise a material for applying tensile strain in the channel region, such as Si, SiC, etc., and may be in-situ doped during the epitaxial process by introducing an n-type dopant (such as phosphorus (P) or arsenic (As)), or ex-situ doped using an implantation process (i.e., a junction implantation process). The concentration of the n-type dopant can range from 5 x 10⁻⁶. 19 / cm 3 Up to 5x10 21 / cm 3 Similarly, when forming a p-type FET device, the source / drain components 240 may include a material to which compressive strain is applied in the channel region, such as Si, SiGe, etc., and may be in-situ doped during the epitaxial process by introducing p-type dopants (such as boron (B), aluminum (Al), gallium (Ga), and indium (In)), or ex-situ doped using an implantation process (i.e., a junction implantation process). The concentration of the p-type dopant can range from 5 x 10⁻⁶. 19 / cm 3 Up to 5x10 21 / cm 3 Within the range. The source / drain component 240 may have a surface protruding from a corresponding surface of the channel semiconductor portion 208P, and may have a small plane. In some embodiments, the source / drain component 240 is a p-type source / drain component and comprises boron-doped SiGe or SiGe with a germanium (Ge) concentration in the range of 10% to 50%. In some embodiments, the source / drain component 240 is an n-type source / drain component and comprises phosphorus- or arsenic-doped Si.

[0047] In some embodiments, an annealing process, such as rapid thermal annealing (RTA) or laser annealing, may be performed to activate the dopants in the source / drain components 240.

[0048] refer to Figure 1 and Figure 9 Method 100 proceeds to operation 116, wherein, according to some embodiments, an interlayer dielectric (ILD) layer 250 is formed over the source / drain component 240. Figure 9 This is a cross-sectional view of the GAA device 200 after the formation of the ILD layer 250.

[0049] In some embodiments, the ILD layer 250 may include a low-k dielectric material having a dielectric constant lower than that of silicon dioxide (approximately 3.9). The low-k dielectric material may include an oxide formed from tetraethyl orthosilicate (TEOS) (e.g., by reacting TEOS with oxygen using CVD to deposit silicon dioxide), undoped silicate glass, or doped silicon dioxide such as borosilicate glass (BPSG), fluoride-doped silicon glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), other suitable low-k dielectric materials, or combinations thereof. The ILD layer 250 may include a multilayer structure having a variety of dielectric materials and may be formed by CVD, flowable CVD (FCVD), spin coating, or other suitable deposition processes. In some embodiments, forming the ILD layer 250 further includes performing a CMP process to planarize the top surface of the ILD layer 250, such that the topmost surface of the sacrificial gate structure 220 is exposed. In some embodiments, the top surface of the ILD layer 250 is coplanar with the top surface of the gate spacer 226.

[0050] refer to Figure 1 and Figure 10 Method 100 proceeds to operation 118, wherein, according to some embodiments, the sacrificial gate stack (222, 224) is removed. Figure 10 This is a cross-sectional view of the GAA device 200 after the sacrificial gate stack (222, 224) has been removed.

[0051] One or more etching processes are performed to selectively remove various components of each sacrificial gate stack (222, 224), including the sacrificial gate dielectric 222 and the sacrificial gate electrode 224. Removal of the sacrificial gate stack (222, 224) forms a gate trench 252, which exposes a channel semiconductor portion 208P and a recessed sacrificial semiconductor portion 206R in the channel region of the fin structure 210. An ILD layer 250 protects the source / drain components 240 during the etching process. The etching process can be a dry etching process, a wet etching process, or a combination thereof. The etching process can be tailored such that the sacrificial gate dielectric 222 and the sacrificial gate electrode 224 are removed without (or with minimal) etching of other elements in the GAA device 200, including the ILD layer 250 and the gate spacer 226. For example, in the case where the sacrificial gate electrode 224 is made of polysilicon and the ILD layer 250 is made of silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the sacrificial gate electrode 224. Subsequently, plasma dry etching and / or wet etching are used to remove the sacrificial gate dielectric 222.

[0052] refer to Figure 1 and Figure 11Method 100 proceeds to operation 120, wherein, according to some embodiments, the recessed sacrificial semiconductor portion 206R is removed. Figure 11 This is a cross-sectional view of the GAA device 200 after the recessed sacrificial semiconductor portion 206R has been removed.

[0053] Selectively removing the recessed sacrificial semiconductor portion 206R releases the channel semiconductor portion 208P, thereby forming a channel nanostructure 208C. The channel nanostructure 208C can be a nanowire or a nanosheet.

[0054] In some embodiments, the recessed sacrificial semiconductor portion 206R can be removed by a selective etching process using an etchant selective for the sacrificial semiconductor material, such that the recessed sacrificial semiconductor portion 206R is removed without substantially damaging the channel semiconductor portion 208P. In some embodiments, the etching process is an isotropic etching process, which can be a dry etching process or a wet etching process. In some embodiments, the selective etching process may include oxidizing the recessed sacrificial semiconductor portion 206R using a suitable oxidant (such as ozone). Thereafter, the oxidized recessed sacrificial semiconductor portion 206R can be selectively removed. In some embodiments, when the channel semiconductor portion 208P comprises Si and the recessed sacrificial semiconductor portion 206R comprises SiGe, the recessed sacrificial semiconductor portion 206R can be selectively removed by applying HCl gas or a gas mixture of CF4, SF6, and CHF3 at a temperature of about 500°C to about 700°C. The internal spacer 234 serves as an etch stop layer to protect the source / drain component 240 during the removal of the recessed sacrificial semiconductor portion 206R in the gate trench 252. As a result, the remaining channel semiconductor portion 208P forms the channel nanostructure 208C.

[0055] After removing the recessed sacrificial semiconductor portion 206R, a trimming operation can be performed to reduce the thickness of the channel nanostructure 208C, thereby improving the gate fill window. The trimming operation can utilize any suitable etching process, such as dry etching, wet etching, or a combination thereof. In some embodiments, the channel nanostructure 208C can have a thickness ranging from 3 nm to 8 nm.

[0056] like Figure 11 As shown, due to the removal of the recessed sacrificial semiconductor portion 206R and nanosheet trimming, gaps 254 (e.g., blanking spaces) are formed between adjacent channel nanostructures 208C and between the bottommost channel nanostructure 208C and the substrate portion 210B. Gap 254 defines the spacing between adjacent channel nanostructures 208C. In some embodiments, the spacing between adjacent channel nanostructures 208C (also referred to as inter-chip spacing) can range from about 8 nm to about 15 nm.

[0057] refer to Figure 1 and Figure 12 Method 100 proceeds to operation 122, wherein, according to some embodiments, gate stacks (262, 264, 266) are formed in gate trench 252 and gap 254. Figure 12 This is a cross-sectional view of the GAA device 200 after the gate stack (262, 264, 266) has been formed.

[0058] Each gate stack (262, 264, 266) is disposed above and between vertically spaced channel nanostructures 208C, and above a substrate portion 210B, respectively. In some embodiments, the gate stack (262, 264, 266) includes an interface layer 262, a gate dielectric 264, and a gate electrode 266.

[0059] Gate stacks (262, 264, 266) are formed by first forming an interface layer 262 on the exposed surfaces of the channel nanostructure 208C and the substrate portion 210B. The interface layer facilitates adhesion of the gate dielectric 264 to the channel nanostructure 208C. In some embodiments, the interface layer 262 may include a dielectric material, such as silicon oxide. In some embodiments, the interface layer 262 may be formed by chemical oxidation or thermal oxidation of the surface portions of the channel nanostructure 208C and the substrate portion 210B. For example, in some embodiments, ozonated deionized water including ozone is used to form the interface layer 262. The thickness of the interface layer 262 is in the range of about 0.5 nm to about 1.5 nm. In some embodiments, the interface layer 262 is about 1 nm thick, achieved by oxidizing about 1 nm of the channel nanostructure 208C.

[0060] Subsequently, a gate dielectric layer is conformally deposited over the interface layer 262. The gate dielectric layer encapsulates the channel nanostructure 208C and is located on the bottom and sidewalls of the gate trench 252. In some embodiments, the gate dielectric layer may comprise a high-k dielectric material with a dielectric constant greater than that of silicon dioxide. Examples of high-k dielectric materials include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), and hafnium oxide-aluminum oxide (HfO2-Al2O3) alloys. The gate dielectric 264 may be formed by CVD, ALD, or other suitable conformal deposition methods. In some embodiments, a conformal deposition process (such as ALD) is used to form the gate dielectric layer to ensure that the gate dielectric layer has a uniform thickness around each channel nanostructure 208C. The gate dielectric layer may be formed to have a thickness ranging from about 1 nm to about 2.5 nm. In some embodiments, the gate dielectric layer may be formed to have a thickness of about 1.5 nm.

[0061] Next, a gate electrode layer is formed on the gate dielectric layer to fill the gate trench 252 and the gap 254. For an n-type FET, the gate electrode layer may include an n-type work function material suitable for adjusting the threshold voltage of the n-type FET. Suitable n-type work function materials include, but are not limited to, titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum silicon nitride (TaSiN), tantalum aluminum carbide (TaAlC), tantalum aluminum nitride (TiAlN), and combinations thereof. For a p-type FET, the gate electrode layer may include a p-type work function material suitable for adjusting the threshold voltage of the p-type FET. Suitable p-type work function materials include, but are not limited to, titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum nitride (TaN), tungsten (W), tungsten carbon nitride (WCN), molybdenum nitride (MoN), titanium tungsten nitride (TiWN), and combinations thereof. The gate electrode layer can be formed by any suitable deposition process, such as CVD, PECVD, PVD, or electrochemical plating.

[0062] Next, in a planarization process such as CMP, excess portions of the gate dielectric layer and gate electrode layer deposited on the top surface of the ILD layer 250 and the gate spacer 226 are removed to form gate stacks (262, 264, 266). The remaining portions of the gate dielectric layer in each gate trench 252 and the corresponding underlying gap 254 constitute the gate dielectric 264, and the remaining portions of the gate electrode layer in each gate trench 252 and the corresponding underlying gap 254 constitute the gate electrode 266. The top surface of the gate stacks (262, 264, 266) may be coplanar with the top surface of the ILD layer 250 and the gate spacer 226. In some embodiments, the gate stacks (262, 264, 266) may have a height ranging from 5 nm to 40 nm and a lateral dimension (i.e., width) ranging from 5 nm to 30 nm.

[0063] The resulting gate stacks (262, 264, 266) surround the channel nanostructure 208C and fill the gaps 254 between the channel nanostructures 208C and between the bottommost channel nanostructure 208C and the substrate portion 201B. Between the channel nanostructures 208C, the gate electrode 266 is circumferentially surrounded by a gate dielectric 264 (in the cross-sectional view). In the portions of the gate stacks (262, 264, 266) formed above the topmost channel nanostructure 208C, the gate electrode 266 is formed above the gate dielectric 264, wherein the gate dielectric 264 encloses the gate electrode 266. Each gate stack (262, 264, 266) and the corresponding gate spacers 226 located on the sidewalls of the gate stacks (262, 264, 266) constitute a gate structure 260.

[0064] refer to Figure 1 and Figure 13 Method 100 proceeds to operation 124, wherein, according to some embodiments, a source / drain contact opening 270 is formed to expose the source / drain component 240. Figure 13 This is a cross-sectional view of the GAA device 200 after the source / drain contact opening 270 is formed to expose the source / drain components 240.

[0065] Source / drain contact openings 270 extend through the ILD layer 250 to expose portions of the source / drain components 240. In some embodiments, the source / drain contact openings 270 are formed by removing corresponding portions of the ILD layer 250 using an etching process. For example, the formation of the source / drain contact openings 270 includes applying a photoresist layer (not shown) over the ILD layer 250 and the gate structure 260 by a suitable deposition process (such as spin coating), patterning the photoresist layer by a photolithography method to form a patterned photoresist layer, and etching the ILD layer 250 to remove portions of the ILD layer 250 exposed by the patterned photoresist layer. In some embodiments, the ILD layer 250 is etched using a dry etching process (such as, for example, RIE or plasma etching). In some embodiments, the ILD layer 250 is etched using a wet etching process. The gate spacer 226 is protected by the patterned photoresist layer and remains intact during the etching of the ILD layer 250.

[0066] After forming the source / drain contact openings 270 through the ILD layer 250, the patterned photoresist layer is removed, for example, by ashing. Optionally, in some embodiments, a hard mask is used such that the source / drain contact opening pattern is transferred from the patterned photoresist layer to the hard mask by a first etching, and then transferred to the ILD layer 250 by a second etching.

[0067] In some embodiments, and as Figure 13 As shown, etching can also remove a portion of each source / drain component 240, so that the bottom surface of each source / drain contact opening 270 is located below the top surface of the corresponding source / drain component 240. In some embodiments, each source / drain contact opening 270 has a rounded bottom corner.

[0068] refer to Figure 1 and Figure 14 Method 100 proceeds to operation 126, wherein, according to some embodiments, a silicide component 272 and a source / drain contact component 274 are sequentially formed in a source / source contact opening 270. Figure 14 This is a cross-sectional view of the GAA device 200 after the silicide component 272 and the source / drain contact component 274 are sequentially formed in the source / drain contact opening 270.

[0069] The silicide component 272 and the source / drain contact component 274 are formed such that the conductivity of the silicide component 274 is between the conductivity of the source / drain component 240 and the conductivity of the source / drain contact structure 274, wherein the conductivity of the source / drain contact component 274 is the highest.

[0070] In some embodiments, the silicide component 272 is first formed to contact the source / drain component 240. To form the silicide component 272, one or more metals may be deposited over a portion of the source / drain component 240 exposed by the source / drain contact opening 270. The GAA device 200 is then annealed to allow the one or more metals to react with the semiconductor material of the source / drain component 240. Thereafter, unreacted portions of the one or more metals are removed, leaving the silicide component 272 over the source / drain component 240. The one or more metals may include chromium (Cr), titanium (Ti), tantalum (Ta), molybdenum (Mo), zirconium (Zr), hafnium (Hf), scandium (Sc), yttrium (Y), holmium, terbium (Tb), gadolinium (Gd), lutetium (Lu), dysprosium (Dy), erbium (Er), ytterbium (Yb), other noble metals, other refractory metals, rare earth metals, or alloys thereof, and may be deposited using CVD, PVD, ALD, or other suitable methods. The resulting silicide component 272 may include TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, YSi, HoSi, TbSi, GdSi, LuSi, DySi, ErSi, or YbSi. In some embodiments, the silicide component 272 has a curved profile.

[0071] After forming the silicide component 272, operation 126 deposits a metal layer (not shown) into the source / drain contact opening 270 and over the top surface of the ILD layer 250 and gate structure 260. The metal layer completely fills the source / drain contact opening 270 and is in direct contact with the silicide component 272. In some embodiments, the metal layer may include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), nickel (Ni), titanium (Ti), tantalum (Ta), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or other metals, and may be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the metal layer includes W, Mo, Ru, alloys thereof, or combinations thereof. Subsequently, a planarization process (e.g., CMP) is performed to remove excess material from the metal layer above the top surface of the ILD layer 250 and gate structure 260, thereby forming the source / drain contact component 274. In some embodiments, the source / drain contact component 274 has a height ranging from 5 nm to 40 nm and a lateral dimension (i.e., width) ranging from 5 nm to 30 nm.

[0072] refer to Figure 1 and Figure 15Method 100 proceeds to operation 128, wherein, according to some embodiments, a contact etch stop layer 278 is formed over the ILD layer 250, the gate structure 260 and the source / drain contact component 274, and subsequently a contact layer dielectric layer 280 is formed over the contact etch stop layer 278. Figure 15 This is a cross-sectional view of the GAA device 200 after the formation of the contact etch stop layer 278 and the contact level dielectric layer 280.

[0073] A contact etch stop layer 278 is disposed on the top surface of the ILD layer 250, the gate structure 260, and the source / drain contact component 274. In some embodiments, the contact etch stop layer 278 may comprise silicon nitride (SiN), silicon nitride carbon (SiCN), silicon carbonitride, or silicon carbon oxynitride; and may be formed by CVD, PVD, ALD, or other suitable deposition methods. In some embodiments, the contact etch stop layer 278 may have a thickness ranging from 1 nm to 10 nm.

[0074] The contact-level dielectric layer 280 may include the same or different low-k material as the ILD layer 250. In some embodiments, the contact-level dielectric layer 280 may include an oxide formed of tetraethyl orthosilicate (TEOS) (e.g., by reacting TEOS with oxygen using CVD to deposit silicon oxide), undoped silicate glass, or doped silicon oxide such as borosilicate glass (BPSG), fluoride-doped silicon glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), other suitable low-k dielectric materials, or combinations thereof. The contact-level dielectric layer 280 may be formed by PECVD, FCVD, or other suitable deposition methods.

[0075] refer to Figure 1 and Figure 16 Method 100 proceeds to operation 129, wherein, according to some embodiments, a gate via opening 282A and a trench 284 are formed through the contact level dielectric layer 280 and the contact etch stop layer 278. Figure 16 This is a cross-sectional view of a GAA device 200 after the formation of gate via opening 282A and trench 284, according to some embodiments.

[0076] A gate via opening 282A is disposed on the gate structure 260. The gate via opening 282A extends through the contact-level dielectric layer 280 and the contact etch stop layer 278 to expose a portion of the gate electrode 266 in a corresponding one of the gate structures 260. A trench 284 extends through the contact-level dielectric layer 280 and the contact etch stop layer 278 to expose a portion of the gate electrode in a corresponding one of the gate structures 260 and a source / drain contact 274 adjacent to one of the gate structures 260.

[0077] In some embodiments, the gate via opening 282A and trench 284 can be formed by forming a patterned mask (not shown) on the contact-level dielectric layer 280 to partially expose the contact-level dielectric layer 280, etching the contact-level dielectric layer 280 and contact etch stop layer 278 through the patterned mask, and removing the patterned mask. Etching can be performed using dry etching, wet etching, or a combination thereof. The patterned mask may include a photoresist material or other suitable mask material and can be formed by applying a photoresist layer, soft baking, exposing the photoresist layer through the photomask, post-exposure baking and developing the photoresist layer, followed by hard baking.

[0078] refer to Figure 1 and Figure 17 Method 100 proceeds to operation 130, wherein, according to some embodiments, a source / drain contact via opening 282B is formed through the contact level dielectric layer 280 and the contact etch stop layer 278. Figure 17 This is a cross-sectional view of a GAA device 200 after the formation of the source / drain contact via opening 282B, according to some embodiments.

[0079] A source / drain contact via opening 282B is provided on the source / drain contact component 274. The source / drain contact via opening 282B extends through the contact level dielectric layer 280 and the contact etch stop layer 278 to expose a portion of a corresponding one of the source / drain contact components 274.

[0080] In some embodiments, the source / drain contact via opening 282B can be formed by first forming a patterned mask (not shown) on the contact-level dielectric layer 280 to cover the areas where the gate via opening 282A and trench 284 are located, while exposing the contact-level dielectric layer 280 in the area located above the corresponding source / drain contact member 274. Subsequently, the contact-level dielectric layer 280 and the contact etch stop layer 278 are etched through the patterned mask. After etching, the patterned mask is removed. Etching can be performed using dry etching, wet etching, or a combination thereof. The patterned mask can include a photoresist material or other suitable mask material, and can be formed by coating a photoresist layer, soft baking, exposing the photoresist layer through a photomask, post-exposure baking and developing the photoresist layer, followed by hard baking.

[0081] Although in the embodiments shown in this disclosure, the source / drain contact via opening 282B is formed in a separate manufacturing step from the gate via opening 282A and the trench 284, in some embodiments, all three openings, namely the gate via opening 282A, the source / drain contact via opening 282B, and the trench 284, can be formed simultaneously using a single mask, thereby simplifying the manufacturing process and improving alignment accuracy.

[0082] refer to Figure 1 and Figure 18 Method 100 proceeds to operation 132, wherein, according to some embodiments, a conformal metal liner layer 286 is formed in the gate via opening 282A, the source / drain contact via opening 282B, and the trench 284, and above the top surface of the contact level dielectric layer 280. Figure 18 This is a cross-sectional view of the GAA device 200 after the metal liner layer 286 has been formed.

[0083] A metal liner layer 286 is formed along the sidewalls and bottom surface of the gate via opening 282A, the source / drain contact via opening 282B, and the trench 284. The metal liner layer 286 is disposed on the gate structure 260 and the source / drain contact member 274 and serves as a seed layer to facilitate the deposition of contact metal for forming the via contacts and trench contacts. Furthermore, the metal liner layer 286 can serve as a capping layer to protect the metal in the underlying source / drain contact member 274 and the gate electrode 266 of the gate structure 260 from oxidation. In some embodiments, the metal liner layer 286 comprises W, Mo, Ru, alloys thereof, or combinations thereof. The metal liner layer 286 can be formed by a conformal deposition process such as CVD or ALD. The thickness of the metal liner layer 286 can vary relative to the contact etch stop layer 278; the metal liner layer 286 can be thinner than, equal to, or thicker than the contact etch stop layer 278. In some embodiments, the metal liner layer 286 has a thickness ranging from 0.5 nm to 5 nm. If the metal liner layer is too thin, it is difficult to form contact metal on it. Conversely, if the metal liner layer is too thick, it may coalesce within the via opening, making it difficult to remove.

[0084] In some embodiments, a pre-cleaning process may be performed to remove native oxides from the gate electrode 266 and the source / drain contact portion 274. This removal can be achieved using a suitable surface cleaning process, such as a nitrogen plasma process. In some embodiments, the pre-cleaning process and the metal liner deposition process are performed in situ.

[0085] refer to Figure 1 and Figure 19Method 100 proceeds to operation 134, wherein, according to some embodiments, a dielectric structure 288 is formed over a metal liner layer 286 and filled with a gate via opening 282A, a source / drain contact via opening 282B, and a trench 284. Figure 19 This is a cross-sectional view of the GAA device 200 after the dielectric structure 288 has been formed.

[0086] The dielectric structure 288 protects a portion of the underlying metal liner layer 286 and may include a material as a bottom anti-reflective coating. In some embodiments, the dielectric structure 288 may include a BARC polymer containing C, H, and O. Examples of BARC polymers may include, but are not limited to, polyhydroxystyrene (PHS), methacrylates, acrylates, polyamic acid, and polyimide. In some embodiments, the dielectric structure 288 is formed by spin coating. Any excess BARC polymer outside the gate via opening 282A, source / drain contact via opening 282B, and trench 284 is removed such that the top surface of the dielectric structure 288 is coplanar with the topmost surface of the metal liner layer.

[0087] refer to Figure 1 and Figure 20 Method 100 proceeds to operation 136, wherein, according to some embodiments, the dielectric structure 288 is recessed to form a groove 290 on the recessed dielectric structure 288R. Figure 20 This is a cross-sectional view of the GAA device 200 after the dielectric structure 288 has been recessed.

[0088] In some embodiments, the dielectric structure 288 is recessed by an etch-back process that selectively etches the dielectric structure 288 without etching the metal liner layer 286. The etch-back process removes the top portion of the dielectric structure 288, creating a groove 290 over the dielectric structure 288. As a result of the etching, the top surface of the dielectric structure 288 lies below the topmost surface of the metal liner layer 286, such that the upper sidewall portion of the metal liner layer 286 along the sidewalls of the respective gate via opening 282A, source / drain contact via opening 282B, and trench 284 is exposed within the groove 290. In some embodiments, an etching gas comprising fluorine may be used to etch the dielectric structure 288. After recessing, the remaining portion of the dielectric structure 288 in the lower portion of the respective gate via opening 282A, source / drain contact via opening 282B, and trench 284 is referred to herein as the recessed dielectric structure 288R.

[0089] refer to Figure 1 and Figure 21Method 100 proceeds to operation 138, wherein, according to some embodiments, a portion of the metal liner layer 286 above the contact level dielectric layer 280 exposed by the groove 290 and above the upper sidewalls of the corresponding gate via opening 282A, source / drain contact via opening 282B and trench 284 is removed. Figure 21 This is a cross-sectional view of the GAA device 200 after removing a portion of the metal liner layer 286 above the contact-level dielectric layer 280 exposed by the groove 290 and above the corresponding gate via opening 282A, source / drain contact via opening 282B and the upper sidewall of the trench 284.

[0090] In some embodiments, the metal liner layer 286 is etched isotropically until it is completely removed from the top surface of the contact-level dielectric layer 280 and the sidewall surfaces of the recess 290. Etching may include a dry etching process using an etching gas comprising Cl and O or a wet etching process using a wet etchant comprising S. In some embodiments, an SPM (sulfuric acid and hydrogen peroxide mixture) solution is used. The remaining portion of the metal liner layer 286 is referred to herein as the metal liner portion 286P. The topmost surface of the metal liner portion 286P may be coplanar with the top surface of the recessed dielectric structure 288R or located below the top surface of the recessed dielectric structure 288R.

[0091] refer to Figure 1 and Figures 22A to 22C Method 100 proceeds to operation 140, wherein, according to some embodiments, the vertical portion of the metal lining portion 286P and the recessed dielectric structure 288R are removed. Figures 22A to 22C This is a cross-sectional view of the GAA device 200 after removing the vertical portion of the metal liner portion 286P and the recessed dielectric structure 288R.

[0092] A sidewall pull-back process is performed to selectively remove the vertical portions of the metal liner portion 286P and the recessed dielectric structure 288R on the sidewalls of the gate via opening 282A, the source / drain contact via opening 282B, and the trench 284, while substantially not etching the contact-level dielectric layer 280 and the contact etch stop layer 278. The sidewall pull-back process is a timed etching process that continues until the recessed dielectric structure 288R is completely removed, exposing portions of the metal liner portion 286P on the bottom surfaces of the gate via opening 282A, the source / drain contact via opening 282B, and the trench 284. In some embodiments, the sidewall pull-back process is an anisotropic etching process, such as reactive ion etching (RIE). In some embodiments, the etching process also recesses the top surface of the bottom portion of the metal liner portion 286P, such that the remaining metal liner portion 286P (referred to herein as metal liner 286L) has a concave top surface. Figure 22A , Figure 22B and Figure 22C As shown, the top surface of the metal liner 286L can be lower than, coplanar with, or higher than the top surface of the contact etch stop layer.

[0093] In some embodiments, the vertical portion of the metal liner portion 286P and the recessed dielectric structure 288R can be removed by a separate etching process. First, the etching process removes the vertical portion of the metal liner portion 286P. Then, a second etching process removes the recessed dielectric structure 288R, leaving the bottom portion of the metal liner portion 286P in the structure.

[0094] refer to Figure 1 and Figure 23 Method 100 proceeds to operation 142, wherein, according to some embodiments, a conductive material layer 292 is deposited over the metal liner 286L and the contact-level dielectric layer 280. Figure 23 This is a cross-sectional view of the GAA device 200 after the deposition of the conductive material layer 292.

[0095] A conductive material layer 292 is deposited in the gate via opening 282A, the source / drain contact via opening 282B, and the trench 284. The conductive material layer 292 may comprise the same or different material as the material providing the metal liner layer 286. In some embodiments, the conductive material layer 292 comprises W, Mo, Ru, alloys thereof, or combinations thereof. The conductive material layer 292 may be formed, for example, by CVD, PVD, or ALD. The deposition process continues until the conductive material layer 292 fills the gate via opening 282A, the source / drain contact via opening 282B, and the trench 284, and extends over the contact-level dielectric layer 280. In some embodiments, the conductive material layer 292 is formed of a metal with a grain size larger than the grain size of the metal in the metal liner layer 286.

[0096] refer to Figure 1 and Figure 24 Method 100 proceeds to operation 144, wherein, according to some embodiments, contact components 292A, 292B and 292C are formed. Figure 24 This is a cross-sectional view of the GAA device 200 after the contact parts 292A, 292B and 292C are formed, according to some embodiments.

[0097] Contacts 292A, 292B, and 292C are formed by removing excess portions of the conductive material layer 292 outside the gate via opening 282A, the source / drain contact via opening 282B, and the trench 284. In some embodiments, excess conductive material above the top surface of the contact-level dielectric layer 280 is removed by a planarization process (such as CMP). As a result, the top surfaces of contacts 292A, 292B, and 292C are coplanar with the top surface of the contact-level dielectric layer 280. The remaining portion of the conductive material layer 292 within the gate via opening 282A forms the gate via contact 292A for providing electrical connection to the gate structure 260. Similarly, the remaining portion of the conductive material layer 292 within the source / drain contact via opening 282B forms the source / drain via contact 292B for providing electrical connection to the source / drain component 240 via the source / drain contact 274. Furthermore, the remaining portion of the conductive material layer 292 within the trench 284 forms a gate-to-source / drain contact 292C, serving as a trench contact for interconnecting the gate structure 260 with adjacent source / drain components 240. In some embodiments, the gate via contact 292A and the source / drain via contact 292B have a height ranging from 5 nm to 20 nm and a lateral dimension (i.e., width) ranging from 5 nm to 100 nm.

[0098] In embodiments where the metal liner 286L and the contact components 292A-292C are made of the same metal, an interface is formed between the metal liner 286L and the corresponding contact components 292A-292C due to the difference in grain size (the metal in the metal liner 286L has a smaller grain size compared to the metal in the contact components 292A-192C).

[0099] In embodiments of this disclosure, at the mid-process (MOL) contact level, the gate via contact 292A and the source / drain via contact 292B are formed of the same material. Therefore, the gate and source / drain via contacts 292A and 292B can be formed simultaneously without requiring separate masking steps. Compared to prior art that requires separate masking steps to form the gate via and source / drain via contacts using different metals, this disclosure reduces the use of masks, which helps to reduce manufacturing costs and improve yield.

[0100] refer to Figure 1 and Figure 25 Method 100 proceeds to operation 146, wherein, according to some embodiments, contact components 294A, 294B and 294C are formed. Figure 25 This is a cross-sectional view of the GAA device 200 after the contact parts 294C, 294B and 294C are formed, according to some embodiments.

[0101] Contact components 294A, 294B, and 294C are embedded in the contact-level dielectric layer 296 and provide electrical connections to the underlying contact components 292A, 292B, and 292C, respectively. In some embodiments, each of the contact components 294A, 294B, and 294C includes a diffusion barrier 297 and a conductive plug 299.

[0102] In some embodiments, contact components 294A, 294B, and 294C can be formed by first depositing a contact-level dielectric layer 296 over a contact-level dielectric layer 280. The contact-level dielectric layer 296 comprises a low-k dielectric material that may be the same as or different from the low-k dielectric material of the contact-level dielectric layer 280. In some embodiments, the contact-level dielectric layer 296 comprises an oxide formed from tetraethyl orthosilicate (TEOS) (e.g., by reacting TEOS with oxygen using CVD to deposit silicon oxide), undoped silicate glass, or doped silicon oxide such as borosilicate glass (BPSG), fluorine-doped silicon glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), other suitable low-k dielectric materials, or combinations thereof. The contact-level dielectric layer 296 can be formed by PECVD, FCVD, or other suitable deposition methods.

[0103] Subsequently, the contact-level dielectric layer 296 is etched to form a plurality of openings (not shown). In some embodiments, the plurality of openings include a first opening exposing the top surface of the contact member 292A, a second opening exposing the top surface of the contact member 292B, and a third opening exposing the top surface of the contact member 292C.

[0104] Next, a diffusion barrier layer (not shown) is conformally deposited along the sidewalls and bottom surface of the opening and above the top surface of the contact-level dielectric layer 296. In some embodiments, the diffusion barrier layer comprises Ti, TiN, Ta, TaN, Ru, RuN, or other suitable diffusion barrier materials. In some embodiments, the diffusion barrier layer comprises a stack of the aforementioned diffusion barrier materials, such as, for example, Ti / TiN or Ta / TaN. In some embodiments, the diffusion barrier layer is deposited using a conformal deposition process (such as CVD, PECVD, PVD, or ALD).

[0105] Next, a conductive material layer (not shown) is deposited over the diffusion barrier layer to fill the opening. The conductive material layer may include Cu, Al, W, Co, alloys thereof, or other suitable conductive metals. In some embodiments, the conductive material layer is deposited by a suitable deposition process, such as, for example, CVD, PECVD, sputtering, or plating. The deposition process continues until the conductive material layer fills the opening and extends over the contact-level dielectric layer 296.

[0106] Next, a planarization process is used to remove portions of the conductive material layer and diffusion barrier layer located above the contact-level dielectric layer 296. In some embodiments, a CMP process is performed. After planarization, the portion of the diffusion barrier layer remaining in each opening constitutes a diffusion barrier 297, and the portion of the conductive material layer remaining in each opening constitutes a conductive plug 299. The top surfaces of contact members 294A, 294B, and 294C are coplanar with the top surface of the contact-level dielectric layer 296.

[0107] One aspect of this specification relates to a method for forming a semiconductor structure. The method includes: forming a plurality of nanostructures; forming a gate structure on the nanostructures; forming source / drain components adjacent to the gate structure; forming source / drain contact components on the source / drain components; forming a dielectric layer on the gate structure and the source / drain contact components; etching the dielectric layer to form a first opening on the gate structure and a second opening on the source / drain contact components; forming a metal liner layer in the first and second openings; removing a portion of the metal liner layer to form a metal liner at the bottom of the first and second openings; and depositing a conductive material layer on the metal liner to fill the first and second openings, forming a first via contact component in the first opening and a second via contact component in the second opening.

[0108] In some embodiments, the first through-hole contact component and the second through-hole contact component are laterally surrounded by the dielectric layer, and the first through-hole contact component and the second through-hole contact component have sidewalls that contact the dielectric layer and bottom surfaces that contact the metal liner.

[0109] In some embodiments, etching the dielectric layer to form the first opening on the gate structure and the second opening on the source / drain contact includes: forming a patterned photoresist layer over the dielectric layer; and removing portions of the dielectric layer not covered by the patterned photoresist layer.

[0110] In some embodiments, forming the metal liner layer in the first opening and the second opening includes conformally depositing the metal liner layer along the sidewalls and bottom surfaces of the first opening and the second opening and over the top surface of the dielectric layer.

[0111] In some embodiments, the method further includes forming a dielectric structure on the metal liner layer and filling the first opening and the second opening.

[0112] In some embodiments, the dielectric structure comprises a polymer containing carbon (C), hydrogen (H) and oxygen (O).

[0113] In some embodiments, removing the portion of the metal liner layer to form a metal liner at the bottom of the first opening and the second opening includes: recessing the dielectric structure to expose an upper vertical portion of the metal liner layer on the sidewalls of the first opening and the second opening; removing the metal liner layer from the top surface of the dielectric layer and the exposed upper vertical portion of the metal liner layer; and removing the remaining portion of the dielectric structure and the remaining vertical portion of the metal liner layer, wherein the horizontal portion of the dielectric layer remaining at the bottom of the first opening and the second opening forms the metal liner.

[0114] In some embodiments, the metal liner layer and the conductive material layer independently comprise tungsten (W), molybdenum (Mo), or ruthenium (W).

[0115] In some embodiments, the grain size of the metal liner layer is smaller than the grain size of the conductive material layer.

[0116] In some embodiments, the metal liner has a flat or concave top surface.

[0117] Another aspect of this specification relates to a method for forming a semiconductor structure. The method includes: forming a vertically stacked nanostructure over a substrate; forming a gate structure around and over the nanostructure; forming source / drain components over the substrate, with the source / drain components adjacent to the nanostructure; forming source / drain contact components that contact the source / drain components, wherein the source / drain contact components have a top surface coplanar with the top surface of the gate structure, and wherein the drain / source contact components and the gate structure are laterally surrounded by a first dielectric layer; forming an etch stop layer over the first dielectric layer, the source / drain contact components, and the gate structure; forming a second dielectric layer over the etch stop layer; forming a first opening and a second opening extending through the second dielectric layer and the first dielectric layer, wherein the first opening exposes the gate structure and the second opening exposes the source / drain contact components; forming a metal liner only on the bottom surfaces of the first and second openings; and forming a first via contact component in the first opening for electrical coupling to the gate structure, and forming a second via contact component in the second opening for electrical coupling to the source / drain contact components.

[0118] In some embodiments, the method further includes forming a silicide component between the source / drain component and the source / drain contact component.

[0119] In some embodiments, forming the metal liner includes: depositing a metal liner layer along the sidewalls and bottom surfaces of the first and second openings and over the second dielectric layer; forming a first dielectric structure over the metal liner layer and filling the first opening; and forming a second dielectric structure over the metal liner layer to fill the second opening; recessing the first and second dielectric structures to expose the upper vertical portion of the metal liner layer in each of the first and second openings; removing the metal liner layer from the top surface of the second dielectric layer and from the upper sidewalls of each of the first and second openings; and removing the remaining vertical portion of the metal liner layer and the remaining portion of each of the first and second dielectric structures.

[0120] In some embodiments, recessing the first dielectric structure and the second dielectric structure includes performing an etching process using an etching gas comprising F.

[0121] In some embodiments, removing the remaining vertical portion of the metal liner layer and the remaining portion of each of the first dielectric structure and the second dielectric structure comprises performing an etching process using an etching gas comprising chlorine (Cl) and oxygen (O).

[0122] Another aspect of this specification relates to a semiconductor structure. The semiconductor structure includes: a vertically stacked nanostructure above a substrate; a gate structure enclosing the nanostructure; source / drain components adjacent to the nanostructure; source / drain contact components above the source / drain components; an etch stop layer above the gate structure and the source / drain contact components; a dielectric layer above the etch stop layer; a gate via contact component extending through the dielectric layer and the etch stop layer and electrically coupled to the gate structure via a first metal liner; and a source / drain via contact component extending through the dielectric layer and the etch stop layer and electrically coupled to the source / drain contact components via a second metal liner. The dielectric layer contacts the sidewalls of the gate via contact component and the source / drain via contact component, and the etch stop layer contacts the sidewalls of the first and second metal liners.

[0123] In some embodiments, the gate via contact and the source / drain via contact are made of the same metal.

[0124] In some embodiments, the first metal liner and the second metal liner have a top surface located above the top surface of the etch stop layer, coplanar with the top surface of the etch stop layer, or located below the top surface of the etch stop layer.

[0125] In some embodiments, the first metal liner and the second metal liner have concave top surfaces.

[0126] In some embodiments, the grain size of the first metal liner is smaller than the grain size of the gate via contact, and the grain size of the second metal liner is smaller than the grain size of the source / drain via contact. Features of several embodiments have been summarized above to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: Multiple nanostructures are formed; A gate structure is formed on the nanostructure; Form source / drain components adjacent to the gate structure; Source / drain contact components are formed on the source / drain components; A dielectric layer is formed on the gate structure and the source / drain contact components; The dielectric layer is etched to form a first opening in the gate structure and a second opening in the source / drain contact component; A metal liner layer is formed in the first opening and the second opening; Remove a portion of the metal liner layer to form a metal liner at the bottom of the first opening and the second opening; as well as A conductive material layer is deposited on the metal liner to fill the first opening and the second opening, and a first through-hole contact component is formed in the first opening and a second through-hole contact component is formed in the second opening.

2. The method according to claim 1, wherein, The first through-hole contact component and the second through-hole contact component are laterally surrounded by the dielectric layer, and the first through-hole contact component and the second through-hole contact component have sidewalls that contact the dielectric layer and bottom surfaces that contact the metal liner.

3. The method according to claim 1, wherein, Etching the dielectric layer to form the first opening on the gate structure and forming the second opening on the source / drain contact includes: A patterned photoresist layer is formed above the dielectric layer; and Remove portions of the dielectric layer not covered by the patterned photoresist layer.

4. The method of claim 1, wherein forming the metal liner layer in the first opening and the second opening comprises: The metal liner layer is conformally deposited along the sidewalls and bottom surfaces of the first and second openings and above the top surface of the dielectric layer.

5. The method of claim 4, further comprising forming a dielectric structure on the metal liner layer and filling the first opening and the second opening.

6. The method according to claim 5, wherein, The dielectric structure comprises a polymer containing carbon (C), hydrogen (H) and oxygen (O).

7. The method according to claim 5, wherein, Removing the portion of the metal liner layer to form a metal liner at the bottom of the first opening and the second opening includes: The dielectric structure is recessed to expose the upper vertical portion of the metal liner layer on the sidewalls of the first and second openings; Remove the metal liner from the top surface of the dielectric layer and the exposed upper vertical portion of the metal liner; and Remove the remaining portion of the dielectric structure and the remaining vertical portion of the metal liner. The horizontal portion of the dielectric layer retained at the bottom of the first and second openings forms the metal liner.

8. The method according to claim 1, wherein, The metal lining layer and the conductive material layer independently comprise tungsten (W), molybdenum (Mo), or ruthenium (W).

9. A method for forming a semiconductor structure, comprising: A vertically stacked nanostructure is formed above a substrate; A gate structure is formed around and above the nanostructure; A source / drain component is formed above the substrate, and the source / drain component is adjacent to the nanostructure; A source / drain contact component is formed to contact the source / drain component, wherein the source / drain contact component has a top surface that is coplanar with the top surface of the gate structure, and wherein the source / drain contact component and the gate structure are laterally surrounded by a first dielectric layer; An etch stop layer is formed above the first dielectric layer, the source / drain contact components, and the gate structure; A second dielectric layer is formed above the etch stop layer; A first opening and a second opening are formed extending through the second dielectric layer and the first dielectric layer, wherein the first opening exposes the gate structure and the second opening exposes the source / drain contact components; Metal linings are formed only on the bottom surfaces of the first and second openings; and A first via contact is formed in the first opening to electrically couple to the gate structure, and a second via contact is formed in the second opening to electrically couple to the source / drain contact.

10. A semiconductor structure, comprising: Vertically stacked nanostructures are positioned above a substrate; A gate structure encapsulates the nanostructure; Source / drain components are adjacent to the nanostructure; Source / drain contact components are located above the source / drain components; An etch stop layer is located above the gate structure and the source / drain contact components; A dielectric layer is located above the etch stop layer; A gate via contact component extends through the dielectric layer and the etch stop layer and is electrically coupled to the gate structure via a first metal liner; as well as Source / drain via contact components extend through the dielectric layer and the etch stop layer and are electrically coupled to the source / drain contact components via a second metal liner. The dielectric layer contacts the sidewalls of the gate via contact and the source / drain via contact, and the etch stop layer contacts the sidewalls of the first metal liner and the second metal liner.

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