Stacked transistor and preparation method thereof, semiconductor device and electronic equipment

Abstract

The invention provides a stacked transistor and a preparation method thereof, a semiconductor device and electronic equipment. The method comprises the following steps: forming a stacked structure on a substrate; forming a first source-drain epitaxy of the first transistor based on the first active structure; reversing the wafer and thinning the substrate; forming a second source-drain epitaxy of the second transistor based on the second active structure; forming an outer wrapping sacrificial layer on the epitaxial surface of the second source drain; forming a second interlayer dielectric layer, second source-drain metal, a second gate structure and a second back-end interconnection layer of a second transistor based on the second active structure; pouring the sheet; forming a first interlayer dielectric layer and a first gate structure of the first transistor based on the first active structure; forming a first groove through graphical etching; forming a source-drain outer wrapping layer, a source-drain interconnection through hole and first source-drain metal which are electrically connected in the first groove; wherein the source-drain interconnection through hole penetrates through the first source-drain epitaxy and the source-drain isolation layer; and forming a first back-end interconnection layer of the first transistor.

Description

Technical Field

[0001] This application relates to semiconductor device manufacturing technology, and more particularly to a stacked transistor and its fabrication method, semiconductor devices, and electronic devices. Background Technology

[0002] With Moore's Law continuously evolving, and beyond the gate-all-around (GAA) technology node, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, through three-dimensional transistor stacking, can integrate two or more layers of transistors in vertical space, helping to further increase transistor integration density and improve circuit performance. This is considered one of the key technologies for continuing the miniaturization of integrated circuits. However, how to achieve efficient metal interconnects in stacked transistors remains a problem that needs to be solved. Summary of the Invention

[0003] This application provides a stacked transistor and its fabrication method, a semiconductor device, and an electronic device, which can reduce the parasitic capacitance inside the stacked transistor and the resistance between interconnect metals.

[0004] The technical solution of this application embodiment is implemented as follows:

[0005] This application provides a method for fabricating a stacked transistor, comprising: forming a stacked structure on a substrate; the stacked structure including a first active structure and a second active structure stacked in a first direction; forming a first source-drain epitaxial layer of the first transistor based on the first active structure; washing and thinning the substrate; forming a second source-drain epitaxial layer of the second transistor based on the second active structure; wherein a source-drain isolation layer is disposed between the first source-drain epitaxial layer and the second source-drain epitaxial layer; forming an outer sacrificial layer on the surface of the second source-drain epitaxial layer; the outer sacrificial layer encapsulating the second source-drain epitaxial layer; and forming a second interlayer dielectric layer of the second transistor based on the second active structure. A second source / drain metal, a second gate structure, and a second back-end interconnect layer; wafer flipping; forming a first interlayer dielectric layer and a first gate structure of a first transistor based on a first active structure; patterning and etching the first interlayer dielectric layer, the first source / drain epitaxial layer, and the source / drain isolation layer, and removing the outer sacrificial layer to form a first groove; filling the first groove with metal material to form an electrically connected source / drain encapsulation layer, a source / drain interconnect via, and a first source / drain metal; wherein the source / drain interconnect via penetrates the first source / drain epitaxial layer and the source / drain isolation layer; the source / drain encapsulation layer wraps around the second source / drain epitaxial layer and contacts the second source / drain metal; forming the first back-end interconnect layer of the first transistor.

[0006] In some possible implementations, patterning the first interlayer dielectric layer, the first source / drain epitaxial layer, and the source / drain isolation layer, and removing the outer sacrificial layer to form a first groove, includes: forming a patterned first hard mask on the first interlayer dielectric layer; the first hard mask does not block the source / drain region of the first transistor; under the etching blocking effect of the first hard mask, sequentially etching the first interlayer dielectric layer, the first source / drain epitaxial layer, and the source / drain isolation layer until the outer sacrificial layer is exposed; removing the outer sacrificial layer; and etching a portion of the first interlayer dielectric layer above the first source / drain epitaxial layer to form the first groove.

[0007] In some possible implementations, the first source-drain epitaxial layer includes a first source epitaxial layer and a first drain epitaxial layer; the first source epitaxial layer and / or the first drain epitaxial layer in the source-drain region not covered by the first hard mask.

[0008] In some possible implementations, the first source-drain epitaxial layer includes a first source epitaxial layer and a first drain epitaxial layer; the source-drain interconnect via extends through the first source epitaxial layer and / or the first drain epitaxial layer.

[0009] In some possible implementations, the stacked structure includes a first active structure, a first sacrificial layer, and a second active structure stacked sequentially in a first direction; a first source-drain epitaxial layer of a first transistor is formed based on the first active structure; the process includes: etching the first active structure, the first sacrificial layer, and the second active structure located in the source-drain region to form a first source-drain trench, a source-drain isolation trench, and a second source-drain trench; depositing an insulating material in the second source-drain trench to form a second sacrificial layer; depositing an insulating material in the source-drain isolation trench to form a source-drain isolation layer; and performing source-drain epitaxial growth in the first source-drain trench to form the first source-drain epitaxial layer.

[0010] In some possible implementations, forming a second source-drain epitaxial layer of a second transistor based on a second active structure includes: removing a second sacrificial layer and depositing an insulating material at the bottom of the exposed second source-drain trench to form a third sacrificial layer; and performing source-drain epitaxial growth in the second source-drain trench to form the second source-drain epitaxial layer.

[0011] In some possible implementations, forming an outer sacrificial layer on the surface of the second source / drain epitaxial layer includes: removing the third sacrificial layer to form a first gap between the source / drain isolation layer and the second source / drain epitaxial layer; depositing an insulating material in the first gap and on the surface of the second source / drain epitaxial layer to form an outer sacrificial layer; and filling the first gap and encapsulating the second source / drain epitaxial layer with the outer sacrificial layer.

[0012] This application provides a stacked transistor, fabricated using the method described above. The stacked transistor includes: a first transistor; the first transistor includes a first source-drain epitaxial layer and a first source-drain metal; a second transistor; the second transistor includes a second source-drain epitaxial layer and a second source-drain metal; the first transistor and the second transistor are stacked in a first direction; a source-drain interconnect via; the source-drain interconnect via penetrates the first source-drain epitaxial layer and is electrically connected to the first source-drain metal and the second source-drain metal, respectively.

[0013] This application provides a semiconductor device, including: a plurality of semiconductor structures as described above; wherein the plurality of semiconductor structures are electrically connected through a back-end interconnect layer to form a functional circuit.

[0014] This application provides an electronic device, including: a system motherboard; a semiconductor device as described above; the semiconductor device is mounted on the system motherboard and electrically connected to the system motherboard.

[0015] The technical solutions provided by the embodiments of this application may include the following beneficial effects:

[0016] By setting a source-drain interconnect via that penetrates the epitaxial layer of the first source-drain transistor inside the active region, the source-drain interconnect between the first transistor and the second transistor can be realized inside the active region; in this way, the parasitic capacitance inside the stacked transistor and the resistance between the interconnect metals can be reduced.

[0017] Furthermore, by forming a source-drain outer coating layer that wraps around the second source-drain epitaxial surface, and by simultaneously achieving electrical connection through contact with the second source-drain metal, the contact area between the second source-drain metal and the second source-drain epitaxial layer can be increased, greatly reducing the contact resistance and further reducing the resistance between interconnect metals inside the stacked transistor.

[0018] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] Figure 1 This is a schematic diagram of one implementation process of the method for fabricating stacked transistors in this application.

[0021] Figure 2 This is a design layout of stacked transistors in an embodiment of this application;

[0022] Figures 3 to 40 This is a schematic flowchart of a method for fabricating stacked transistors in an embodiment of this application;

[0023] Figure 41 This is a schematic diagram of a stacked transistor structure in an embodiment of this application.

[0024] The reference numerals and names in the figure are as follows:

[0025] 11-First transistor; 111-First active structure; 112-First source / drain epitaxial layer; 113-First interlayer dielectric layer; 114-First gate metal layer; 115-First gate cut-off structure; 116-First source / drain metal; 117-First back-channel interconnect layer; 12-Second transistor; 121-Second active structure; 122-Second source / drain epitaxial layer; 123-Second interlayer dielectric layer; 124-Second gate metal layer; 125-Second gate cut-off structure; 126-Second source / drain metal; 127-Second back-channel interconnect layer; 21-Substrate; 22-Bottom sacrificial layer; 231-First stack; 232-Second stack; 24- 25 - First sacrificial layer; 261 - First pseudo-gate structure; 262 - Second pseudo-gate structure; 27 - Gate isolation layer; 28 - Sidewall; 29 - Second gap; 30 - Intermediate isolation layer; 311 - First inner sidewall; 312 - Second inner sidewall; 32 - Second sacrificial layer; 33 - Third sacrificial layer; 34 - First gap; 351 - First hard mask; 352 - Second hard mask; 36 - Source / drain isolation layer; 37 - Outer sacrificial layer; 38 - First groove; 41 - First insulating layer; 42 - First carrier wafer; 43 - Second insulating layer; 44 - Second carrier wafer; 45 - Source / drain outer layer; 46 - Source / drain interconnect via. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0028] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0029] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0030] As integrated circuit technology continues to advance towards higher integration levels and smaller dimensions, traditional planar transistor structures are gradually encountering physical limits in terms of performance improvement. To continue the trend of Moore's Law, the industry has begun to explore three-dimensional integration solutions, among which stacked transistor technology has attracted widespread attention due to its ability to integrate multiple layers of transistors in the vertical direction. This technology significantly improves device density and circuit performance within a limited chip area by vertically stacking multiple active layers and constructing independent transistor devices.

[0031] In some embodiments, the interconnection between the source and drain of the stacked transistors is performed outside the active region. This requires creating deep vias aligned with the metal vias on the top layer, followed by metal filling to complete the direct connection between the source and drain of the upper and lower transistors. This interconnection scheme requires forming deep vias, which are difficult to etch, and the narrow width results in high resistance at the contact metal. Furthermore, forming metal outside the active region also limits the width and location of the active region; simultaneously, the large overlap area between the metal formed outside the active region and the gate leads to a large parasitic capacitance, which is detrimental to circuit performance.

[0032] To address the aforementioned technical problems, this application provides a method for fabricating stacked transistors, which can reduce the parasitic capacitance inside the stacked transistors and the resistance between interconnecting metals.

[0033] Figure 1 This is a schematic diagram illustrating one implementation process of the stacked transistor fabrication method in this application. See also... Figure 1 As shown, the fabrication method of the above-mentioned stacked transistors includes:

[0034] In step 101, a stacked structure is formed on the substrate. The stacked structure includes a first active structure and a second active structure stacked in a first direction.

[0035] In some embodiments, a substrate is first provided, and photolithography and etching processes are performed on the substrate to form a patterned first active structure and a second active structure.

[0036] In some embodiments, the first active structure is located above the second active structure in the vertical direction (i.e., the first direction).

[0037] In some embodiments, the first active structure is a portion of the channel region of a first transistor, used to carry a current path, and is the core region for the operation of the first transistor. The second active structure is a portion of the channel region of a second transistor, used to carry a current path, and is the core region for the operation of the second transistor.

[0038] In the embodiments of this application, the first active structure and the second active structure are formed in the same etching process, so that the first active structure and the second active structure are self-aligned; the active regions of the first transistor and the second transistor prepared based on the self-aligned first active structure and the second active structure are also self-aligned.

[0039] In the embodiments of this application, the active region is the area in which the transistor can amplify and control the signal during operation.

[0040] In some embodiments, the stacked transistors include a first transistor and a second transistor, and the first transistor and the second transistor can be of one of the following types: gate-all-around field-effect transistor (GAAFET), planar transistor, and complementary field-effect transistor (CFET), etc.

[0041] In some embodiments, the shape of the active structure (i.e., the first active structure and the second active structure) is related to the type of transistor. When the transistor is a fully all-around gate field-effect transistor, the active structure is a nanosheet structure; when the transistor is a planar transistor, the active structure is a block structure; but when the transistor is a complementary field-effect transistor, the active structure can be a fin structure.

[0042] In one example, where the transistor is a full-around-gate field-effect transistor, the first and second active structures on the substrate are stacks of two semiconductor materials stacked alternately. For example, silicon (Si) and silicon germanium (SiGe) are deposited alternately, wherein silicon germanium serves as a sacrificial layer and is removed during the channel release process.

[0043] In some embodiments, the material layers stacked on the substrate include not only the first active structure and the second active structure, but also, in the vertical direction, the structure stacked from top to bottom as follows: the first active structure, the first sacrificial layer, the second active structure, and the bottom sacrificial layer. The first sacrificial layer and the bottom sacrificial layer are temporary structures that will be removed in subsequent processes to support the structures of the upper and lower layers.

[0044] In step 102, a first source-drain epitaxial layer of the first transistor is formed based on the first active structure.

[0045] In some embodiments, a semiconductor material is epitaxially grown in the source and drain regions of the first transistor to form a first source and drain epitaxial layer.

[0046] In some embodiments, the formation of the first source / drain epitaxial layer can be accomplished by chemical vapor deposition (CVD), and the thickness and doping concentration of the first source / drain epitaxial layer can be adjusted according to specific application requirements.

[0047] It should be noted that in the embodiments of this application, "source and drain" is an abbreviation for "source and / or drain".

[0048] In some possible implementations, step 102 may include: etching the first active structure, the first sacrificial layer, and the second active structure located in the source-drain region to form a first source-drain groove, a source-drain isolation groove, and a second source-drain groove; depositing insulating material in the second source-drain groove to form a second sacrificial layer; depositing insulating material in the source-drain isolation groove to form a source-drain isolation layer; and performing source-drain epitaxial growth in the first source-drain groove to form a first source-drain epitaxial layer.

[0049] In some embodiments, by etching the first active structure, the first sacrificial layer, and the second active structure respectively, a plurality of grooves can be formed, including a first source-drain groove (corresponding to the first active structure), a source-drain isolation groove (corresponding to the sacrificial layer), and a second source-drain groove (corresponding to the second active structure).

[0050] In some embodiments, the second sacrificial layer is an insulating material deposited in the second source / drain trench for use as support or isolation in subsequent processes. In one example, the insulating material forming the second sacrificial layer may include, but is not limited to, silicon oxide, silicon nitride, etc.

[0051] In some embodiments, the source-drain isolation layer is another layer of insulating material deposited in the source-drain isolation groove to isolate the source-drain regions of the upper and lower transistors and prevent current crosstalk. The source-drain isolation layer not only improves the stability and reliability of the circuit but also reduces parasitic capacitance and enhances overall performance.

[0052] In some embodiments, the source / drain epitaxial growth process typically employs a selective epitaxial growth process, in which a single crystal material, such as silicon or silicon-germanium, is directionally grown in the first source / drain groove to form the first source / drain epitaxial layer.

[0053] In step 103, the wafer is poured and the substrate is thinned.

[0054] Understandably, wafer flipping refers to flipping a wafer so that the surface that was originally facing down is now facing up, so that subsequent processing operations (such as fabricating a second transistor) can be carried out on the back side.

[0055] In some embodiments, before performing step 103, an insulating material can be deposited on the unformed first transistor to form a first insulating layer; the first carrier wafer is then bonded to the first insulating layer. Thus, the first insulating layer and the first carrier wafer can protect the structure in the first transistor after wafer flipping, preventing damage to the structure due to external forces.

[0056] In some embodiments, after the initial fabrication of the first transistor is completed, a wafer flipping operation is performed to thin the substrate, preparing it for the subsequent fabrication of the second transistor on the back side. In one example, the thinning process can be achieved through chemical mechanical planarization (CMP).

[0057] In step 104, a second source-drain epitaxial layer of the second transistor is formed based on the second active structure. A source-drain isolation layer is disposed between the first and second source-drain epitaxial layers.

[0058] Understandably, the fabrication process of the second source-drain epitaxy is the same as that of the first source-drain epitaxy. The second source-drain epitaxy is formed based on the second active structure and is located in the source-drain region of the second transistor.

[0059] In some embodiments, the source-drain isolation layer is an insulating material layer used to isolate the first source-drain epitaxial layer and the second source-drain epitaxial layer to prevent current cross-interference. The source-drain isolation layer is formed before the second source-drain epitaxial layer.

[0060] In one example, silicon germanium can be used as the material for preparing the second source / drain epitaxy. To distinguish it from SiGe in the active structure, the silicon germanium for the second source / drain epitaxy is SiGe2, in which Ge atoms account for 30% of the total number of atoms.

[0061] In some possible implementations, step 104 may include: removing the second sacrificial layer and depositing an insulating material at the bottom of the exposed second source / drain groove to form a third sacrificial layer; and performing source / drain epitaxial growth in the second source / drain groove to form a second source / drain epitaxial layer.

[0062] In some embodiments, an etching process is used to remove the insulating material that was originally filled in the second source-drain groove, thereby exposing the second source-drain groove.

[0063] In some embodiments, after removing the second sacrificial layer, an insulating material is deposited at the bottom of the second source / drain recess to form a third sacrificial layer. The third sacrificial layer can be selectively removed in subsequent manufacturing steps without affecting the electrical performance of the final device.

[0064] In some embodiments, the source-drain epitaxial growth process typically employs a selective epitaxial growth process, in which single-crystal materials, such as silicon or silicon-germanium, are directionally grown in the second source-drain groove to form the second source-drain epitaxial layer.

[0065] In step 105, an outer sacrificial layer is formed on the surface of the second source / drain epitaxial layer. The outer sacrificial layer encapsulates the second source / drain epitaxial layer.

[0066] In some embodiments, the outer sacrificial layer is a temporary insulating material layer. The outer sacrificial layer is deposited on the surface of the second source / drain epitaxial layer and forms a wrapping structure around it.

[0067] In one example, the material for the outer sacrificial layer can be SiGe3, in which Ge atoms account for 90% of the total number of atoms.

[0068] In some possible implementations, step 105 may include: removing the third sacrificial layer to form a first gap between the source / drain isolation layer and the second source / drain epitaxial layer; depositing an insulating material in the first gap and on the surface of the second source / drain epitaxial layer to form an outer sacrificial layer; and filling the first gap and wrapping the second source / drain epitaxial layer with the outer sacrificial layer.

[0069] In some embodiments, removing the third sacrificial layer leaves a gap (i.e., a first gap) between the source / drain isolation layer and the second source / drain epitaxial layer. The first gap provides space for subsequent deposition of insulating material.

[0070] In some embodiments, an insulating material with a high dielectric constant (such as silicon oxide, silicon nitride, silicon carbide, etc.) is deposited inside the first gap and on the surface of the second source / drain epitaxial layer to form an outer sacrificial layer.

[0071] In some embodiments, the outer sacrificial layer not only fills the first gap but also surrounds the surface of the second source / drain epitaxial layer to form an encapsulation structure.

[0072] In step 106, based on the second active structure, a second inter-layer dielectric (ILD) layer, a second source / drain metal, a second gate structure, and a second back-end interconnect layer are formed for the second transistor.

[0073] Understandably, based on the core structure (i.e., the second active structure), front-end and back-end processes are performed separately to form the second front-end layer and the second back-end interconnect layer in the second transistor. The second front-end layer may include: a second interlayer dielectric layer, a second source / drain metal, a second gate structure, etc.

[0074] In some embodiments, the second interlayer dielectric layer is an insulating material layer used to isolate different structures in the second transistor (such as the second gate structure and the second source / drain metal) to prevent short circuits.

[0075] In some embodiments, the second source / drain metal refers to a metal layer formed in the source / drain region of the second transistor, used to connect the second source / drain epitaxial layer and an external circuit.

[0076] In some embodiments, the second gate structure includes a second gate dielectric layer and a second gate metal layer for controlling the conduction state of the second transistor.

[0077] In some embodiments, the second back-end interconnect layer refers to the metal interconnect network in the second transistor, which is used to connect various functional modules to form a complete circuit network.

[0078] In step 107, the film is reversed.

[0079] In some embodiments, after the initial construction of the second transistor is completed, a wafer flipping operation is performed again to facilitate subsequent processes based on the first active structure.

[0080] In some embodiments, before performing step 107, an insulating material can be deposited on the initially constructed second transistor to form a second insulating layer; the second carrier wafer is then bonded to the second insulating layer. Thus, the second insulating layer and the second carrier wafer can protect the structure in the second transistor after wafer flipping, preventing damage to the structure from external forces.

[0081] In step 108, a first interlayer dielectric layer and a first gate structure of the first transistor are formed based on the first active structure.

[0082] In some embodiments, the first interlayer dielectric layer is an insulating material layer used to isolate different structures in the first transistor (such as the first gate structure and the first source / drain metal) to prevent short circuits.

[0083] In some embodiments, the first gate structure includes a first gate dielectric layer and a first gate metal layer for controlling the conduction state of the first transistor.

[0084] In step 109, the first interlayer dielectric layer, the first source / drain epitaxial layer, and the source / drain isolation layer are patterned and etched, and the outer sacrificial layer is removed to form the first groove.

[0085] In some embodiments, a through-hole structure (i.e., a first groove) is formed by patterning and etching the first interlayer dielectric layer, the first source / drain epitaxial layer, and the source / drain isolation layer; simultaneously, the outer sacrificial layer is removed to expose the surface of the second source / drain epitaxial layer. The formation of the first groove provides a channel for subsequent filling metal material, thereby realizing the source / drain interconnection of the upper and lower transistors (i.e., the first transistor and the second transistor).

[0086] In one example, when the material of the second source drain epitaxial layer is SiGe2 and the material of the outer sacrificial layer is SiGe3, the SiGe3 can be selectively and isotropically etched by taking advantage of the different Ge contents to remove the outer sacrificial layer.

[0087] In some possible implementations, step 109 may include: forming a patterned first hard mask on the first interlayer dielectric layer; the first hard mask does not block the source / drain region of the first transistor; under the etch blocking effect of the first hard mask, sequentially etching the first interlayer dielectric layer, the first source / drain epitaxial layer, and the source / drain isolation layer until the outer sacrificial layer is exposed; removing the outer sacrificial layer; etching a portion of the first interlayer dielectric layer above the first source / drain epitaxial layer to form a first groove.

[0088] In some embodiments, the first hard mask is a patterned masking material, such as silicon nitride (SiN) or silicon dioxide (SiO2), used in the etching process. The patterned first hard mask defines the areas to be preserved through photolithography, thereby enabling selective etching of the underlying material. In the embodiments of this application, the first hard mask does not cover the source / drain regions of the first transistor, indicating that subsequent etching will occur in the source / drain regions.

[0089] In some embodiments, a first hard mask is used as a protective layer to prevent non-target areas from being accidentally etched during the etching process. The first interlayer dielectric layer, the first source / drain epitaxial layer, and the source / drain isolation layer are etched sequentially until the outer sacrificial layer is exposed. The outer sacrificial layer is removed by selective etching to form the first groove.

[0090] In some possible implementations, the first source-drain epitaxial layer includes a first source epitaxial layer and a first drain epitaxial layer. The region not covered by the first hard mask can be the first source epitaxial layer and / or the first drain epitaxial layer in the source-drain region.

[0091] In some embodiments, the pattern of the first hard mask can be designed according to actual process requirements to define the etching regions. The pattern can be designed to expose the first source region corresponding to the first source epitaxial layer and / or the first drain region corresponding to the first drain epitaxial layer; these exposed regions are the target regions for subsequent etching.

[0092] In step 110, a metallic material is filled into the first groove to form an electrically connected source / drain outer coating, a source / drain interconnect via, and a first source / drain metal. The source / drain interconnect via penetrates the first source / drain epitaxial layer and the source / drain isolation layer; the source / drain outer coating wraps around the second source / drain epitaxial layer and contacts the second source / drain metal.

[0093] In some embodiments, the source-drain interconnect via is a metal via used to connect the source-drain structures of upper and lower transistors. In this embodiment, the source-drain interconnect via penetrates the first source-drain epitaxial layer and the source-drain isolation layer, reaching the source-drain outer coating layer on the surface of the second source-drain epitaxial layer; the two ends of the source-drain interconnect via are respectively connected to the second source-drain metal and the source-drain outer coating layer, and the source-drain outer coating layer is connected to the first source-drain metal, thereby realizing the source-drain interconnection of the upper and lower transistors within the active region.

[0094] In some possible implementations, the source-drain interconnect via extends through the first source epitaxial layer and / or the first drain epitaxial layer.

[0095] In some embodiments, when the etched area of ​​the first hard mask is aligned with the first source region, the number of source-drain interconnect vias is 1, and the source-drain interconnect vias penetrate the first source epitaxial layer and the source-drain isolation layer, reaching the source-drain outer coating layer on the surface of the second source epitaxial layer.

[0096] In some embodiments, when the etched area of ​​the first hard mask is aligned with the first drain region, the number of source-drain interconnect vias is 1. The source-drain interconnect vias penetrate the first drain epitaxial layer and the source-drain isolation layer, reaching the source-drain outer coating layer on the surface of the second drain epitaxial layer.

[0097] In some embodiments, when the etched area of ​​the first hard mask is aligned with the first source region and the first drain region, the number of source-drain interconnect vias is 2. These two source-drain interconnect vias penetrate the first source epitaxial layer and the first drain epitaxial layer, respectively, and continue to extend to the source-drain isolation layer. The source-drain interconnect vias penetrating the first source epitaxial layer reach the source-drain outer coating layer on the surface of the second source epitaxial layer, and the source-drain interconnect vias penetrating the first drain epitaxial layer reach the source-drain outer coating layer on the surface of the second drain epitaxial layer.

[0098] In step 111, the first back-end interconnect layer of the first transistor is formed.

[0099] In some embodiments, the first back-end interconnect layer refers to the metal interconnect network in the first transistor, which is used to connect various functional modules to form a complete circuit network.

[0100] In this embodiment of the application, by providing a source-drain interconnect via that penetrates the epitaxial layer of the first source-drain region inside the active region, the source-drain interconnect between the first transistor and the second transistor can be realized inside the active region; thus, the parasitic capacitance inside the stacked transistor and the resistance between the interconnect metals can be reduced.

[0101] Furthermore, by forming a source-drain outer coating layer that wraps around the second source-drain epitaxial surface, and by simultaneously achieving electrical connection through contact with the second source-drain metal, the contact area between the second source-drain metal and the second source-drain epitaxial layer can be increased, greatly reducing the contact resistance and further reducing the resistance between interconnect metals inside the stacked transistor.

[0102] Furthermore, in the stacked transistors obtained according to the fabrication method of this application embodiment, self-alignment is achieved between the active regions of the first transistor and the second transistor, and the consistency of the active regions is maintained.

[0103] In some examples, Figure 2 This is a design layout of stacked transistors in an embodiment of this application; Figures 3 to 40 This is a schematic flowchart illustrating a method for fabricating stacked transistors according to an embodiment of this application. Below, in conjunction with... Figure 2 , Figures 3 to 40 The method for fabricating stacked transistors provided in the embodiments of this application will be described.

[0104] It should be noted that in this example, the first transistor and the second transistor in the stacked transistors are both all-around gate field-effect transistors; and the first transistor and the second transistor are interconnected through a source-drain interconnect via that penetrates the first drain epitaxial layer, with the first drain epitaxial layer located on the right side of the CC' section.

[0105] Step 1: Provide a substrate 21, on which a bottom sacrificial layer 22, a second stacked layer 232, a first sacrificial layer 24, and a first stacked layer 231 are sequentially stacked (see...). Figure 3 ).

[0106] The first stack 231 and the second stack 232 are both stacked structures formed by alternating deposition of silicon (Si) and silicon germanium (SiGe).

[0107] Step 2: Etch the first stacked layer 231, the first sacrificial layer 24, the second stacked layer 232, and the bottom sacrificial layer 22 to form the first active structure 111 and the second active structure 121 (see...). Figure 4 ).

[0108] Step 3: Deposit insulating material on substrate 21 and etch back to form shallow trench isolation (STI) layer 25 (see Figure 5 ).

[0109] Step 4: Deposit semiconductor material (such as polysilicon) in the gate region to form a second dummy gate structure 262; deposit insulating material on the second dummy gate structure 262 to form a gate isolation layer 27; deposit semiconductor material on the gate isolation layer to form a first dummy gate structure 261; deposit insulating material to form a sidewall 28 (see...). Figure 6 ).

[0110] Step 5: Etch sidewalls 28 until the first active structure 111 and the first sacrificial layer 24 are exposed (see...) Figure 7 ).

[0111] Step 6: Remove the first active structure 111 in the source / drain region by etching to form the first source / drain groove (see...). Figure 8 ).

[0112] Step 7: Remove the first sacrificial layer 24 to form the second gap 29 (see...) Figure 9 ).

[0113] Step 8: Deposit insulating dielectric material in the second gap 29 to form the intermediate isolation layer 30 (see...) Figure 10 ).

[0114] Step 9: Laterally etch the silicon and germanium in the first active structure 111, and fill the etched grooves with insulating material (such as SiN) to form the first inner sidewall 311 (see...). Figure 11 ).

[0115] Step 10: Remove the sidewalls 28 on the surface of the second active structure 121 by anisotropic etching; and remove the second active structure 121 in the source / drain region by etching to form the second source / drain groove (see...). Figure 12 ).

[0116] Step 11: Remove the first sacrificial layer 24 and the shallow trench isolation layer 25 at the bottom of the source / drain region by anisotropic etching (see...). Figure 13 ).

[0117] Step 12: Fill the second source / drain groove with insulating material (such as SiCN) to form the second sacrificial layer 32 (see...). Figure 14 ).

[0118] Step 13: Deposit insulating material in the source / drain region on the second sacrificial layer to form the source / drain isolation layer 36 (see...). Figure 15 ).

[0119] Step 14: Perform source / drain epitaxial growth in the first source / drain groove to form the first source / drain epitaxial layer 112 (see...). Figure 16 ).

[0120] Step 15: Form the first interlayer dielectric layer 113 in the source / drain region of the first transistor 11 (see...) Figure 17 ).

[0121] Step 16: Deposit insulating material on the first interlayer dielectric layer 113 and the first dummy gate structure 261 to form a first insulating layer 41; bond the first insulating layer 41 to the first carrier wafer 42; flip the first transistor 11 and thin the substrate 21 until the shallow trench isolation layer 25 is exposed (see...). Figure 18 ).

[0122] Step 17: Selectively etch the shallow trench isolation layer 25 (see...) Figure 19 ).

[0123] Step 18: In the groove left after etching the shallow trench isolation layer 25, semiconductor material is deposited. The deposited semiconductor material combines with the second pseudo-gate structure 262 to form a new second pseudo-gate structure 262 (see...). Figure 20 ).

[0124] Step 19: Remove the second sacrificial layer 32 (see...) Figure 21 ).

[0125] Step 20: Laterally etch the silicon and germanium in the second active structure 121, and fill the grooves formed by the etching with insulating material to form the second inner sidewall 312 (see...). Figure 22 ).

[0126] Step 21: Deposit insulating material at the bottom of the second source-drain groove to form the third sacrificial layer 33 (see...) Figure 23 ).

[0127] Step 22: Perform source / drain epitaxial growth in the second source / drain groove to form the second source / drain epitaxial layer 122 (see...). Figure 24 ).

[0128] Step 23: Remove the third sacrificial layer 33 by anisotropic etching to form the first gap 34 (see...). Figure 25 ).

[0129] Step 24: Deposit insulating material (such as silicon-germanium) on the surface of the second source / drain epitaxial layer 122 and in the first gap 34 to form an outer sacrificial layer 37 (see...). Figure 26 ).

[0130] It should be noted that the germanium content in the silicon-germanium outer sacrificial layer is different from the germanium content in the silicon-germanium active structure.

[0131] Step 25: Form a second interlayer dielectric layer 123 in the source and drain regions of the second transistor 12 (see...) Figure 27 ).

[0132] Step 26: Remove the second pseudo-gate structure 262 to expose the second gate region in the second transistor 12 (see...). Figure 28 ).

[0133] Step 27: Remove silicon and germanium from the second active structure 121, deposit dielectric material to form a second gate dielectric layer, and deposit metal in the second gate region to form a second gate metal layer 124 (see...). Figure 29 ).

[0134] Step 28: Perform gate cut processing to form the second gate cut structure 125 (see...) Figure 30 ).

[0135] Step 29: Form the second source / drain metal 126; through subsequent processing, form the second post-processing interconnect layer 127 (see...). Figure 31 ).

[0136] Step 30: Deposit insulating material on the second back-end interconnect layer 127 to form a second insulating layer 43; bond the second insulating layer 43 to the second carrier wafer 44; flip the second transistor 12 so that the first transistor faces upward, and remove the first carrier wafer 42 and the first insulating layer 41 until the first dummy gate structure 261 is exposed (see...). Figure 32 ).

[0137] Step 31: Remove the first pseudo-gate structure 261 (see...) Figure 33 ).

[0138] Step 32: Form the first gate dielectric layer and the first gate metal layer 114 in the first transistor 11 (see...) Figure 34 ).

[0139] Step 33: Form the first gate cutoff structure 115 in the first transistor 11 (see...) Figure 35 ).

[0140] Step 34: Form a patterned first hard mask 351 on the first interlayer dielectric layer 113 and the first gate metal layer 114 (see...) Figure 36 ).

[0141] Step 35: Under the blocking etching effect of the first hard mask 351, etch the first interlayer dielectric layer 113, the first source / drain epitaxial layer 112, and the source / drain isolation layer 36 (see...). Figure 37 ).

[0142] Step 36: Remove the outer sacrificial layer 37 by selective isotropic etching (see...) Figure 38 ).

[0143] Step 37: Remove the first hard mask 351, form a patterned second hard mask 352 on the first interlayer dielectric layer 113 and the first gate metal layer 114, and etch a portion of the first interlayer dielectric layer 113 under the blocking etching effect of the second hard mask 352 (see...). Figure 39 It should be noted that the etching in steps thirty-five to thirty-seven forms the final first groove 38.

[0144] Step 38: Deposit metal in the first groove to form the source / drain outer coating 45, the source / drain interconnect via 46, and the first source / drain metal 116 (see...). Figure 40 The two ends of the source-drain interconnect via 46 are connected to the first source-drain metal 116 and the source-drain outer coating layer 45, respectively. At the same time, the source-drain outer coating layer 45 is connected to the second source-drain metal 126. In this way, the source-drain interconnect of the first transistor and the second transistor is realized in the active region.

[0145] Step 39: Form the first back-channel interconnect layer 117 in the first transistor (see...) Figure 41 ).

[0146] This completes the fabrication of the stacked transistor.

[0147] In some embodiments, the first transistor and the second transistor can be transistors with different polarities (i.e., different channel doping types). For example, the first transistor is an N-channel metal oxide-semiconductor field-effect transistor (NMOS), and the second transistor is a P-channel metal oxide-semiconductor field-effect transistor (PMOS); or the first transistor is a PMOS and the second transistor is an NMOS.

[0148] This application provides a stacked transistor, which can be fabricated using the aforementioned stacked transistor fabrication method. The stacked transistor includes: a first transistor; the first transistor includes a first source-drain epitaxial layer and a first source-drain metal; a second transistor; the second transistor includes a second source-drain epitaxial layer and a second source-drain metal; the first transistor and the second transistor are stacked in a first direction; a source-drain interconnect via; the source-drain interconnect via passes through the first source-drain epitaxial layer and is electrically connected to the first source-drain metal and the second source-drain metal, respectively.

[0149] In some embodiments, Figure 41 This is a schematic diagram of a stacked transistor structure in an embodiment of this application; see also Figure 41As shown, the first transistor 11 and the second transistor 12 are stacked back to back, and the first transistor 11 and the second transistor 12 are interconnected in the active region through the source-drain interconnect via 46 that penetrates the first source-drain epitaxial layer 112.

[0150] The stacked transistors provided in this application embodiment can be inspected using analytical instruments such as scanning electron microscopes (SEM), transmission electron microscopes (TEM), and scanning transmission electron microscopy (STEM). For example, using TEM, it can be observed in TEM slices that the source-drain interconnect vias in the stacked transistors are located inside the active region.

[0151] This application provides a semiconductor device, which may include multiple such semiconductor devices. Figure 41 The stacked transistors shown are electrically connected through a back-end interconnect layer, which transmits signals to form a functional circuit.

[0152] This application provides an electronic device, including: a system motherboard and a semiconductor device as described above, wherein the semiconductor device is mounted on the system motherboard and electrically connected to the system motherboard.

[0153] In some embodiments, an electronic device refers to a device composed of a variety of electronic components capable of performing a specific function. Once semiconductor devices are mounted on the system motherboard, they can be used as main memory or cache, and can support high-speed data read / write and complex computational tasks.

[0154] In some embodiments, the electronic device may include, but is not limited to: mobile communication devices, such as mobile phones, tablets, 5G / 6G base stations; computing devices, such as personal computers, laptops, servers, data center computing units; consumer electronics products, such as smart wearable devices, digital cameras, game consoles; Internet of Things devices or automotive electronic systems.

[0155] The above are merely embodiments of this application and are not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A method for fabricating stacked transistors, characterized in that, include: A stacked structure is formed on a substrate; the stacked structure includes a first active structure and a second active structure stacked in a first direction; Based on the first active structure, a first source-drain epitaxial layer is formed for the first transistor; The substrate is then poured and thinned. Based on the second active structure, a second source-drain epitaxial layer is formed for the second transistor; wherein, a source-drain isolation layer is disposed between the first source-drain epitaxial layer and the second source-drain epitaxial layer; An outer sacrificial layer is formed on the outer surface of the second source / drain epitaxial layer; the outer sacrificial layer encapsulates the second source / drain epitaxial layer; Based on the second active structure, a second interlayer dielectric layer, a second source / drain metal, a second gate structure, and a second back-channel interconnect layer are formed for the second transistor. rewind film; Based on the first active structure, a first interlayer dielectric layer and a first gate structure are formed for the first transistor; The first interlayer dielectric layer, the first source / drain epitaxial layer, and the source / drain isolation layer are patterned and etched, and the outer sacrificial layer is removed to form a first groove; The first groove is filled with metal material to form an electrically connected source / drain outer wrapping layer, a source / drain interconnect via, and a first source / drain metal; wherein the source / drain interconnect via penetrates the first source / drain epitaxial layer and the source / drain isolation layer; the source / drain outer wrapping layer wraps around the second source / drain epitaxial layer and contacts the second source / drain metal. The first back-end interconnect layer of the first transistor is formed.

2. The method according to claim 1, characterized in that, The process of patterning and etching the first interlayer dielectric layer, the first source / drain epitaxial layer, and the source / drain isolation layer, and removing the outer sacrificial layer to form a first groove, includes: A patterned first hard mask is formed on the first interlayer dielectric layer; the first hard mask does not obscure the source and drain regions of the first transistor; Under the etch blocking effect of the first hard mask, the first interlayer dielectric layer, the first source / drain epitaxial layer, and the source / drain isolation layer are etched sequentially until the outer sacrificial layer is exposed; Remove the outer sacrificial layer; A portion of the first interlayer dielectric layer located above the first source / drain epitaxial layer is etched to form the first groove.

3. The method according to claim 2, characterized in that, The first source-drain epitaxial layer includes a first source epitaxial layer and a first drain epitaxial layer; The first hard mask does not obscure the first source epitaxial layer and / or the first drain epitaxial layer in the source-drain region.

4. The method according to claim 2, characterized in that, The first source-drain epitaxial layer includes a first source epitaxial layer and a first drain epitaxial layer; The source-drain interconnect via extends through the first source epitaxial layer and / or the first drain epitaxial layer.

5. The method according to claim 1, characterized in that, The stacked structure includes a first active structure, a first sacrificial layer, and a second active structure stacked sequentially in a first direction; The first source-drain epitaxial layer forming the first transistor based on the first active structure includes: The first active structure, the first sacrificial layer, and the second active structure located in the source and drain regions are etched respectively to form a first source and drain groove, a source and drain isolation groove, and a second source and drain groove. An insulating material is deposited in the second source-drain groove to form a second sacrificial layer; An insulating material is deposited in the source-drain isolation groove to form the source-drain isolation layer; Source-drain epitaxial growth is performed in the first source-drain groove to form the first source-drain epitaxial layer.

6. The method according to claim 5, characterized in that, The second source-drain epitaxial layer forming the second transistor based on the second active structure includes: Remove the second sacrificial layer and deposit insulating material at the bottom of the exposed second source drain groove to form a third sacrificial layer; Source-drain epitaxial growth is performed in the second source-drain groove to form the second source-drain epitaxial layer.

7. The method according to claim 6, characterized in that, An outer sacrificial layer is formed on the epitaxial surface of the second source / drain, including: Remove the third sacrificial layer to form a first gap between the source / drain isolation layer and the second source / drain epitaxial layer; An insulating material is deposited in the first gap and on the surface of the second source / drain epitaxial layer to form an outer sacrificial layer; the outer sacrificial layer fills the first gap and wraps the second source / drain epitaxial layer.

8. A stacked transistor, characterized in that, The stacked transistor is prepared by the method according to any one of claims 1 to 7, wherein the stacked transistor comprises: A first transistor; the first transistor includes a first source / drain epitaxial layer and a first source / drain metal layer; A second transistor; the second transistor includes a second source / drain epitaxial layer and a second source / drain metal; the first transistor and the second transistor are stacked in a first direction; Source-drain interconnect via; the source-drain interconnect via penetrates the first source-drain epitaxial layer and is electrically connected to the first source-drain metal and the second source-drain metal, respectively.

9. A semiconductor device, characterized in that, include: Multiple stacked transistors as described in claim 8; Multiple stacked transistors are electrically connected through a back-end interconnect layer to form a functional circuit.

10. An electronic device, characterized in that, include: System motherboard; The semiconductor device as described in claim 9; The semiconductor device is mounted on the system motherboard and electrically connected to the system motherboard.

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