Integrated circuit device and method of forming same

Abstract

An integrated circuit device and a method of manufacturing the integrated circuit device are provided. An integrated circuit device includes a transistor structure having one or more channel patterns extending between source / drain regions in a first direction and alternately stacked with one or more gate patterns. A hollow inner spacer is provided between the one or more gate patterns and the source / drain region. The hollow inner spacer includes a respective void between a side surface of the one or more gate patterns and a first side surface of the source / drain region in a first direction, and a first liner on the side surface of the one or more gate patterns and on the first side surface of the source / drain region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to integrated circuit devices. BACKGROUND

[0002] Transistor sizes in integrated circuit devices continue to decrease in order to maintain miniaturization of logic elements. Techniques to increase transistor density and integrate more transistors in the same area continue to evolve. As a result, three-dimensional (3D) device structures are being considered, and 3D stacking processes have been proposed.

[0003] One 3D device structure is a stacked transistor. Integrated circuit devices can utilize stacked transistors to increase density and improve performance. In some examples, the stacked transistors can be complementary to one another (e.g., complementary metal-oxide-semiconductor (CMOS) transistors). For example, a complementary FET (CFET) layout can include a plurality of vertically stacked all-around gate field effect transistor (GAAFET) pairs, with P-type GAAFETs on one level and N-type GAAFETs on another level (i.e., above or below the one level), and shared gates, with each shared gate extending between and wrapped around channel patterns of the stacked N-type and P-type GAAFET pairs. In such a structure, source / drain regions of a lower GAAFET are electrically isolated from source / drain regions of an upper GAAFET by a dielectric layer.

[0004] Parasitic capacitance is a phenomenon that can occur in integrated circuit devices, in which there is unintended capacitance between components. Parasitic capacitance can arise due to the proximity of conductive components, and can adversely affect device performance by increasing power consumption, compromising signal integrity, and the like. SUMMARY

[0005] According to some embodiments, an integrated circuit device includes a transistor structure including one or more channel patterns extending between source / drain regions in a first direction and stacked alternately with one or more gate patterns, and a hollow inner spacer between the one or more gate patterns and the source / drain regions. The hollow inner spacer includes respective voids between side surfaces of the one or more gate patterns and first side surfaces of the source / drain regions in the first direction, and first liners on the side surfaces of the one or more gate patterns and on the first side surfaces of the source / drain regions.

[0006] In some embodiments, the first liners extend conformally on the side surfaces of the one or more gate patterns and the first side surfaces of the source / drain regions, and the respective voids are bounded by the first liners in the first direction.

[0007] In some embodiments, the hollow inner spacer further comprises a second liner on second side surfaces of the source / drain regions, the second side surfaces being opposite to each other in a second direction intersecting the first direction, wherein the second liner and the first liner collectively enclose the respective voids.

[0008] In some embodiments, the second liner extends non-conformally on the second side surfaces of the source / drain regions, and the respective voids are bounded by the second liner in the second direction.

[0009] In some embodiments, the second liner extends at least partially between the side surfaces of the gate pattern and the respective portions of the first liner on the first side surfaces of the source / drain regions.

[0010] In some embodiments, the hollow inner spacer comprises a first portion having a first thickness and having the respective voids in a first cross-section along the first direction, and a second portion having a second thickness and having no respective voids in a second cross-section along the first direction.

[0011] In some embodiments, the first liner and / or the second liner comprises a respective material having a dielectric constant less than or equal to that of silicon nitride.

[0012] In some embodiments, the transistor structure comprises a stacked transistor structure on a substrate, the stacked transistor structure comprising a first transistor on the substrate and a second transistor stacked thereon

[0013] In some embodiments, the one or more channel patterns comprise a lower nanosheet of the first transistor and an upper nanosheet of the second transistor; the one or more gate patterns comprise a lower gate pattern of the first transistor and an upper gate pattern of the second transistor; the source / drain regions comprise a lower source / drain region of the first transistor and an upper source / drain region of the second transistor.

[0014] In some embodiments, the lower source / drain region has a first conductivity type, and the upper source / drain region has a second conductivity type opposite to the first conductivity type.

[0015] According to some embodiments, a method of fabricating an integrated circuit device includes forming a plurality of channel patterns and a plurality of sacrificial gate patterns, the channel patterns and the sacrificial gate patterns extending in a first direction and being alternately stacked on a substrate. The sacrificial gate patterns are selectively recessed at opposite ends thereof in the first direction to expose side surfaces of the sacrificial gate patterns. Preliminary inner spacers are formed on the exposed side surfaces; source / drain regions are formed at opposite ends of the channel patterns such that the preliminary inner spacers are located between the side surfaces of the sacrificial gate patterns and first side surfaces of the source / drain regions, the side surfaces of the sacrificial gate patterns and the first side surfaces of the source / drain regions facing each other in the first direction. An etching process is subsequently performed to remove the preliminary inner spacers; and first liners are formed on the side surfaces of the sacrificial gate patterns and on the first side surfaces of the source / drain regions, thereby providing respective voids between the side surfaces of the sacrificial gate patterns and the first side surfaces of the source / drain regions in the first direction.

[0016] In some embodiments, the first liners are formed on the side surfaces of the sacrificial gate patterns and the first side surfaces of the source / drain regions in a conformal manner such that the respective voids are bounded by the first liners in the first direction.

[0017] In some embodiments, second liners are formed on second side surfaces of the source / drain regions, the second side surfaces being opposite to each other in a second direction intersecting the first direction. The second liners collectively form, together with the first liners, hollow inner spacers enclosing the respective voids.

[0018] In some embodiments, the second liners extend non-conformally on the second side surfaces of the source / drain regions such that the respective voids are bounded by the second liners in the second direction.

[0019] In some embodiments, the second liners extend at least partially between portions of the first liners located on the side surfaces of the sacrificial gate patterns and the first side surfaces of the source / drain regions.

[0020] In some embodiments, the hollow inner spacers include a first portion having a first thickness and including the respective voids in a first cross-section along the first direction, and a second portion having a second thickness and being void of the respective voids in a second cross-section along the first direction.

[0021] In some embodiments, the first liners and / or the second liners include respective materials having a dielectric constant less than or equal to that of silicon nitride.

[0022] In some embodiments, after the formation of the spacers, the sacrificial gate patterns between the respective voids are removed; and gate patterns are formed to replace the sacrificial gate patterns. The first spacers extend along side surfaces of the gate patterns and along first side surfaces of the source / drain regions, with the respective voids being between the side surfaces of the sacrificial gate patterns and the first side surfaces of the source / drain regions.

[0023] According to some embodiments, a method of fabricating an integrated circuit device includes forming a channel pattern extending between source / drain regions in a first direction and alternatingly stacked with sacrificial gate patterns. Hollow inner spacers are formed between the sacrificial gate patterns and the source / drain regions by forming first spacers conformally extending over side surfaces of the sacrificial gate patterns and first side surfaces of the source / drain regions, with respective voids between the side surfaces of the sacrificial gate patterns and the first side surfaces of the source / drain regions in the first direction; and forming second spacers non-conformally extending over second side surfaces of the source / drain regions opposite to each other in a second direction intersecting the first direction. The respective voids are bounded by the first spacers in the first direction and by the second spacers in the second direction.

[0024] In some embodiments, the second spacers extend at least partially between the side surfaces of the sacrificial gate patterns and respective portions of the first spacers on the first side surfaces of the source / drain regions to collectively enclose the respective voids.

[0025] In some embodiments, the hollow inner spacers include first portions having a first thickness and the respective voids in first cross-sections along the first direction, and second portions having a second thickness and no respective voids in second cross-sections along the first direction.

[0026] In some embodiments, before the formation of the hollow inner spacers, the sacrificial gate patterns are selectively recessed at opposite ends of the sacrificial gate patterns in the first direction to expose side surfaces of the sacrificial gate patterns. Preliminary inner spacers are formed on the side surfaces of the sacrificial gate patterns; and the source / drain regions are formed at the opposite ends of the channel pattern such that the preliminary inner spacers are between the side surfaces of the sacrificial gate patterns and first side surfaces of the source / drain regions facing each other in the first direction. An etching process is performed to remove the preliminary inner spacers between the sacrificial gate patterns and the source / drain regions.

[0027] Other devices, apparatus, and / or methods according to some embodiments will be apparent to those skilled in the art upon review of the following drawings and detailed description. All such additional embodiments are intended to be included within the scope of this description and are contemplated to be within the scope of the inventors’ invention as defined by the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a plan view or layout view showing a semiconductor integrated circuit device according to some embodiments.

[0029] Figure 2A is Figure 1 is an enlarged cross-sectional view of the transistor structure TS, showing a transistor unit cell including a gate pattern between source / drain regions of a semiconductor integrated circuit device according to some embodiments of the present disclosure.

[0030] Figure 2B and Figure 2C are cross-sectional views taken along lines X1-X1 and X2-X2, respectively, of Figure 2A showing an example configuration of a semiconductor integrated circuit device according to some embodiments of the present disclosure.

[0031] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 are schematic cross-sectional views showing a method of manufacturing a semiconductor integrated circuit device according to some embodiments of the present disclosure.

[0032] Figure 11A , Figure 12A and Figure 13A are schematic cross-sectional views showing a method of manufacturing a semiconductor integrated circuit device according to some embodiments of the present disclosure.

[0033] Figure 11B , Figure 12B and Figure 13B correspond to Figure 2A .

[0034] Figure 14A , Figure 14B , Figure 15A and Figure 15B are schematic cross-sectional views showing a method of manufacturing a semiconductor integrated circuit device according to some embodiments of the present disclosure.

[0035] Figure 14C and Figure 15C correspond to Figure 2A .

[0036] Figure 16 and Figure 17 is a flowchart illustrating a method of manufacturing a semiconductor integrated circuit device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0037] In embodiments described herein, a stacked transistor structure can include a first transistor and a second transistor. The first transistor can be a first type of transistor (e.g., an n-type field effect transistor (nFET), such as an n-type metal oxide semiconductor (NMOS) transistor), and the second transistor can be a second type of transistor (e.g., a p-type field effect transistor (pFET), such as a p-type metal oxide semiconductor (PMOS) transistor). The first transistor and the second transistor can be stacked in any order (e.g., the first transistor on top of the second transistor, or the second transistor on top of the first transistor), resulting in a stacked structure (e.g., a stacked FET structure, such as a 3D stacked FET (3DSFET)) that includes a top device (also referred to herein as an upper device or upper transistor with respect to an underlying substrate) and a bottom device (also referred to herein as a lower device or lower transistor with respect to an overlying substrate). In some stacked transistors, nanosheets or nanowires can be vertically stacked and at least partially surrounded by a gate to improve channel control.

[0038] Some embodiments of the present disclosure can stem from the recognition that the presence of an inner spacer proximate to a source / drain region in a semiconductor device (e.g., a 3DSFET) can help reduce parasitic capacitance. For example, the inner spacer can be between a gate structure and a source / drain region.

[0039] Embodiments of the present disclosure are directed to methods of forming an air pocket within an inner spacer that is provided between a source / drain region and a gate of an integrated circuit device, such as a 3DSFET. As used herein, an air pocket or air gap can also be referred to as a cavity or void, and can include gases other than those included in air (e.g., gases other than oxygen and nitrogen) (or can include gases in different ratios than those included in air). Thus, an inner spacer as described herein can reduce parasitic capacitance by trapping air therein, as air has a lower dielectric constant than silicon oxide or other dielectric materials commonly used in semiconductor manufacturing. Thus, example embodiments of the present disclosure can provide an integrated circuit device (e.g., a 3DSFET) having an inner spacer that includes an air pocket or air gap, also referred to as a hollow inner spacer.

[0040] Figure 1 is a plan view or layout view of an integrated circuit device 100 according to some embodiments of the present disclosure. Figure 2A isFigure 1 an enlarged cross-sectional view of a transistor structure TS showing a transistor unit cell including a gate pattern between source / drain regions. Figure 2B and Figure 2C are cross-sectional views taken along lines X1-X1 and X2-X2, respectively, of Figure 2A

[0041] Referring to Figure 1 and Figures 2A-2C , the integrated circuit device 100 can include a substrate 101 (also referred to as a backside insulating layer) and a plurality of transistor structures TS (also referred to as transistors) on a first side (or front side) S1 of the substrate 101. The substrate 101 can extend in a first direction D1 (also referred to as a first horizontal direction or X direction) and a second direction D2 (also referred to as a second horizontal direction or Y direction) that intersects the first direction D1. The first direction D1 and the second direction D2 can be parallel to a surface (e.g., the front side S1) of the substrate 101. In some embodiments, the first direction D1 can be perpendicular to the second direction D2.

[0042] In some embodiments, the substrate 101 can include or can be a semiconductor material, such as Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP. For example, the substrate 101 can be an insulating layer, a bulk substrate (e.g., a bulk silicon wafer), and / or a semiconductor-on-insulator (SOI) substrate. In some embodiments, the substrate 101 can include or can be formed of an insulating material, such as silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, silicon boron nitride, and / or a low-k dielectric material. The low-k dielectric material can include, for example, fluorine-doped silicon oxide, organosilicate glass, carbon-doped oxide, porous silicon dioxide, porous organosilicate glass, spin-on organic polymer dielectric, and / or spin-on silicon-based polymer dielectric. A thickness of the substrate 101 in a third direction D3 (also referred to as a vertical direction or Z direction) can be, for example, in a range of (about) 50 nm to 100 nm. In some embodiments, the third direction D3 can be perpendicular to the first direction D1 and / or the second direction D2. The third direction D3 can be perpendicular to a surface (e.g., the front side S1) of the substrate 101.

[0043] ​Each transistor structure TS can include a gate structure and a channel structure, the gate structure including a gate pattern 102, the channel structure including a channel pattern 104 extending between source / drain regions 108 (in a first direction Dl). The gate pattern 102 can overlap the channel pattern 104 in a third direction D3. The channel pattern 104 can extend between the source / drain regions 108 in the first direction Dl, and the gate pattern 102 can extend in a second direction D2. In some implementations, each transistor structure TS can include a plurality of channel patterns 104 stacked in the third direction D3, the channel patterns 104 can be spaced apart from one another in the third direction D3. For example, the transistor structure TS can be a nanosheet transistor including a stack of nanosheet layers provided by the channel patterns 104.

[0044] Each transistor structure TS can also include a pair of source / drain regions 108 spaced apart from one another in the first direction Dl. The source / drain regions 108 can include a semiconductor layer (e.g., a silicon (Si) layer and / or a silicon germanium (SiGe) layer), and can additionally include a dopant in the semiconductor layer. The gate pattern 102 can be provided between the pair of source / drain regions 108. The source / drain regions 108 can contact opposite side surfaces of the channel pattern 104 that are spaced apart from one another in the first direction Dl. The transistor structure TS can further include a hollow inner spacer 110 between the gate pattern 102 and the source / drain regions 108 (in the first direction Dl), as described in more detail below.

[0045] The channel pattern 104 can include a semiconductor material (e.g., Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, and / or InP). In some implementations, the channel pattern 104 can include a nanosheet that can have a thickness in the third direction D3 of, for example, in a range from (about) 1 nanometer (nm) to 100 nm, or can be a nanowire having a circular cross-section with a diameter in a range from (about) 1 nm to 100 nm. When the channel pattern 104 includes a nanosheet or a nanowire, the gate pattern 102 can extend on multiple sides around the channel pattern 104 (e.g., at least partially surround the channel pattern 104).

[0046] The integrated circuit device 100 can include a plurality of gate patterns 102 extending in the second direction D2 (i.e., longitudinally) and spaced apart from each other in the first direction Dl. Each gate pattern 102 can include a single layer or multiple layers. In some implementations, each gate pattern 102 can include a metal layer or metal material including, for example, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), cobalt (Co), and / or ruthenium (Ru), and can additionally include a work function layer (e.g., a TiN layer, a TaN layer, a TiAl layer, a TiC layer, a TiAlC layer, a TiAlN layer, and / or a WN layer). In some implementations, each gate pattern 102 can include the same material.

[0047] The gate insulating layer 106 (also referred to as a gate insulator) can extend between the gate patterns 102 and the channel patterns 104. More specifically, the gate insulator 106 can contact and physically separate the gate patterns 102 and the channel patterns 104 (including their nanosheets). The gate insulator 106 can include a single layer or multiple layers (e.g., a silicon oxide layer and / or a high-k dielectric material layer). For example, the high-k dielectric material layer can include Al2O3, HfO2, ZrO2, HfZrO4, TiO2, Sc2O3, Y2O3, La2O3, Lu2O3, Nb2O5, and / or Ta2O5.

[0048] In some implementations, the transistor structure TS can be a three-dimensional (3D) field effect transistor (FET), such as a multi-bridge-channel FET (MBCFET). In some implementations, the transistor structure TS can have a different structure than the illustrated structure. For example, the transistor structure TS can be a gate-all-around FET (GAAFET) or a fin FET (FinFET) including a single channel structure.

[0049] As shown in FIGS. 1A and IB, the integrated circuit device 100 includes a plurality of gate patterns 102 extending in the second direction D2 (i.e., longitudinally) and spaced apart from each other in the first direction Dl. Each gate pattern 102 can include a single layer or multiple layers. In some implementations, each gate pattern 102 can include a metal layer or metal material including, for example, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), cobalt (Co), and / or ruthenium (Ru), and can additionally include a work function layer (e.g., a TiN layer, a TaN layer, a TiAl layer, a TiC layer, a TiAlC layer, a TiAlN layer, and / or a WN layer). In some implementations, each gate pattern 102 can include the same material. Figure 2A Figure 2B Figure 2C As shown in FIGS. 1A and IB, the integrated circuit device 100 includes a plurality of gate patterns 102 extending in the second direction D2 (i.e., longitudinally) and spaced apart from each other in the first direction Dl. Each gate pattern 102 can include a single layer or multiple layers. In some implementations, each gate pattern 102 can include a metal layer or metal material including, for example, tungsten (W), aluminum (Al), copper (Cu), molybdenum (Mo), cobalt (Co), and / or ruthenium (Ru), and can additionally include a work function layer (e.g., a TiN layer, a TaN layer, a TiAl layer, a TiC layer, a TiAlC layer, a TiAlN layer, and / or a WN layer). In some implementations, each gate pattern 102 can include the same material. Figures 2A-C ​​In the example of FIG. 1, multiple upper channel patterns 104b are stacked on multiple lower channel patterns 104a, and gate patterns 102 are alternately stacked between the channel patterns 104a, 104b, although embodiments of the present disclosure can include fewer or more channel patterns than shown. In some embodiments, the channel patterns 104 can include a lower channel pattern 104a (e.g., a lower nanosheet) of the first transistor 202a and an upper channel pattern 104b (e.g., an upper nanosheet) of the second transistor 202b, while the gate patterns 102 can include a lower gate pattern 102a of the first transistor 202a and an upper gate pattern 102b of the second transistor 202b. The channel patterns 104 can be provided by a semiconductor material, such as silicon (Si).

[0050] The source / drain regions 108 can include a lower source / drain region 108a of the first transistor 202a and an upper source / drain region 108b of the second transistor 202b. The lower source / drain region 108a of the first transistor 202a is provided on opposite sides (also referred to herein as opposite ends) of the lower channel pattern 104a, and the upper source / drain region 108b of the second transistor 202b is provided on opposite sides or opposite ends of the upper channel pattern 104b. In some embodiments, the lower source / drain region 108a can include the same material or material composition as the lower channel pattern 104a and the substrate 101. For example, the lower channel pattern 104a and the lower source / drain region 108a can be implemented as a silicon layer. In some embodiments, the upper source / drain region 108b can include a different material or material composition than the lower source / drain region 108a. For example, the upper source / drain region 108b can be implemented as a silicon germanium (SiGe) layer, while the lower source / drain region 108a can be implemented as a silicon (Si) layer.

[0051] The isolation patterns 118 and 122 provide electrical isolation between the first transistor 202a and the second transistor 202b. In particular, the isolation pattern 122 is provided between a lower surface of the upper source / drain region 108b and an upper surface of the lower source / drain region 108a (and between the gate patterns 102), while the isolation pattern 118 (also referred to as a middle dielectric isolation (MDI)) is provided between the lower gate pattern 102a of the first transistor 202a and the upper gate pattern 102b of the second transistor 202b. A gate insulating layer 106 (e.g., a gate oxide pattern) can extend around the gate patterns 102 and between the gate patterns 102 and the channel patterns 104. The gate insulating layer 106 can also be provided between the gate patterns 102.

[0052] In some embodiments, the first (lower) transistor 202a and the second (upper) transistor 202b can have complementary conductivity types, e.g., to provide a CMOS device. In particular, the first transistor 202a can have a first conductivity type (e.g., n-type), while the second transistor 202b can have a second conductivity type opposite the first conductivity type (e.g., p-type), or vice versa. That is, the stacked transistor structure TS according to embodiments of the present disclosure is not limited to a particular orientation of transistors having different conductivity types. Moreover, in some embodiments, the first transistor 202a and the second transistor 202b can have the same conductivity type (e.g., both the first transistor 202a and the second transistor 202b can be n-type, or both the first transistor 202a and the second transistor 202b can be p-type). Furthermore, while illustrated with reference to first and second transistors 202a, 202b, it will be appreciated that the stacked transistor structure TS according to embodiments of the present disclosure is not limited to a two-transistor arrangement, and can include additional transistors (e.g., third, fourth, etc.) vertically stacked on the substrate 101.

[0053] Accordingly, the stacked transistor structure TS includes a channel pattern 104 extending between the source / drain regions 108 in the first direction D1 and a gate pattern 102 extending in the second direction D2, with the channel pattern 104 and the gate pattern 102 alternatingly stacked in the third direction D3. The stacked transistor structure TS further includes a hollow inner spacer 110 providing a void 114 between the gate pattern 102 and the source / drain regions 108 (specifically, between the side surfaces 102s of the gate pattern 102 and the first side surfaces 108sl of the source / drain regions 108) in the first direction D1. As noted above, the void 114 can be implemented by air pockets or air gaps between portions of the hollow inner spacer 110, or by air pockets or air gaps enclosed within the hollow inner spacer 110.

[0054] As Figure 2A , Figure 2B and Figure 2CAs shown, the hollow interior spacer 110 includes a first insulative liner (here generally referred to as a first liner) 111 on the side surfaces 102s of the gate pattern 102 and on the first side surfaces 108sl of the source / drain regions 108, with respective voids 114 between the side surfaces 102s of the gate pattern 102 and the first side surfaces 108sl of the source / drain regions 108. More specifically, the first insulative liner 111 extends conformally over the side surfaces 102s of the gate pattern 102 and the first side surfaces 108sl of the source / drain regions 108, such that the respective voids 114 are bounded by the first insulative liner 111 in the first direction Dl. The first insulative liner 111 can be formed of a dielectric material (e.g., silicon nitride (SiN) and / or a low-k material having a lower dielectric constant than silicon oxide (SiO)). Further example materials for the first insulative liner 111 can include, but are not limited to, SiOC, SiCN, SiC, SiBCN, and SiOCN. The first insulative liner 111 can be a relatively thin layer. For example, the first insulative liner 111 can be deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, etc., such that the first insulative liner 111 extends conformally over the side surfaces 102s of the gate pattern 102 and the first side surfaces 108sl of the source / drain regions 108.

[0055] The hollow interior spacer 110 further includes a second insulative liner (here generally referred to as a second liner) 112 on the second side surfaces 108s2 of the source / drain regions 108, the second side surfaces 108s2 being opposite one another in the second direction D2. The second insulative liner 112 extends non-conformally over the second side surfaces 108s2 of the source / drain regions 108, such that the respective voids 114 are bounded by the second insulative liner 112 in the second direction D2. The second insulative liner 112 can be formed of a dielectric material (e.g., SiN) and / or a low-k material having a lower dielectric constant than SiO, for example, using a CVD process, a PVD process, an ALD process, etc. Further example materials for the second insulative liner 112 can include, but are not limited to, SiOC, SiCN, SiC, SiBCN, and SiOCN.

[0056] As shown in more detail, Figure 2A The second insulative liner 112 can extend at least partially between respective portions 111p of the first insulative liner 111 on the side surfaces 102s of the gate pattern 102 and the first side surfaces 108sl of the source / drain regions 108, for example. The second insulative liner 112 can be deposited using a liner overhang technique, for example, such that it overhangs the respective portions 111p of the first insulative liner 111 on the side surfaces 102s of the gate pattern 102 and the first side surfaces 108sl of the source / drain regions 108. Figure 2AThe portions of the block P indicated areas overlap with portions 111p of the first insulating liner 111 at the edges of the hollow inner spacers 110. The second insulating liner 112 can have or can be deposited with a thickness greater than the thickness of the first insulating liner 111. Thus, the central portions of the hollow inner spacers 110 have a first thickness T1 (corresponding to the conformal first insulating liner 111) with respective voids 114 between the central portions in a first cross-section XI along the first direction D1, while the edge portions of the hollow inner spacers 110 have a second thickness T2 (corresponding to the combined thickness of the second insulating liner 112 and the first insulating liner 111) without respective voids 114 between the edge portions in a second cross-section X2 along the first direction. That is, the hollow inner spacers 110 can have different profiles (hollow vs. filled) depending on whether the cross-section is taken at the central portions (along line X1-X1) or the edge portions (along line X2-X2).

[0057] The second insulating liner 112 and the first insulating liner 111 thereby extend over the side surfaces 102s of the gate pattern 102 and over the side surfaces 108sl, 108s2 of the source / drain regions 108 so as to collectively close the respective voids 114. As noted above, the closed voids 114 can have a lower dielectric constant than silicon oxide or other dielectric materials typically used to form inner spacers between gate patterns and source / drain regions, thereby allowing for reduced parasitic capacitance. In some embodiments, the first insulating liner 111 and / or the second insulating liner 112 of the hollow inner spacers 110 can be formed of a different insulating material than the gate insulating layer 106.

[0058] Although Figure 2B and Figure 2C While the first transistor 202a is shown as including two channel patterns 104a and the second transistor 202b is shown as including three channel patterns 104b, in some embodiments fewer or more channel layers 104 can be included in each transistor 202a, 202b. Further, while not shown, the integrated circuit device 100 can also include middle-of-line (MOL) structures and back-end-of-line (BEOL) structures. Each of the MOL and BEOL structures can include interlayer insulating layers in which conductive lines (e.g., metal lines) and conductive via plugs (e.g., metal via plugs) are provided. Various elements of the first transistor 202a and / or the second transistor 202b can be electrically connected to one or more of the conductive lines of the MOL and BEOL structures.

[0059] Furthermore, in some embodiments, a backside power distribution network structure (BSPDNS) and associated conductive structures can be provided below or within the substrate 101. The BSPDNS can include a backside insulating layer in which conductive backside wires (e.g., metal power rails) and conductive backside contacts (e.g., backside metal contacts) are provided. Various elements of the first transistor 202a and / or the second transistor 202b can be electrically connected to one of the conductive backside wires.

[0060] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 14B , Figure 15A and Figure 15B are schematic cross-sectional views illustrating methods of manufacturing a semiconductor integrated circuit device according to some embodiments of the present disclosure. Figure 11B , Figure 12B and Figure 13B correspond to Figure 2A . Figure 14C and Figure 15C correspond to Figure 2A . Figure 16 and Figure 17 are flowcharts illustrating methods of manufacturing a semiconductor integrated circuit device according to some embodiments of the present disclosure. The methods are described below by way of example only with reference to forming a hollow inner spacer 110 including a void or air pocket 114 in a 3D SFET, but the methods can also be used to similarly form a hollow inner spacer 110 in other transistor configurations. Also, it will be understood that certain steps can not be performed in various embodiments, and that the order of steps used to form a semiconductor integrated circuit device according to embodiments of the present disclosure is not limited to the examples shown and described herein.

[0061] Reference is made to Figure 3The method can include forming a plurality of channel layers 104L5alternately stacked on the substrate 101. In some embodiments, the method can further include forming an intermediate sacrificial layer 318L between the pair of sacrificial layers 302L, which can correspond to the first transistor 202a and the second transistor 202b. In some embodiments, the intermediate sacrificial layer 318L can have a greater thickness than the sacrificial layers 302L. The plurality of channel layers 104L can include a semiconductor material, such as silicon (Si), and the sacrificial layers 302L, 318L can include a material having etch selectivity with respect to the material of the channel layers 104L, such as silicon germanium (SiGe).

[0062] Referring to Figure 4 The method can further include performing one or more etching processes on the channel layers 104L, the sacrificial layers 302L, the intermediate sacrificial layer 318L, and a portion of the substrate 101 to form recesses 410. The recesses 410 can extend into at least a portion of the substrate 101 at opposite sides of the channel layers 104L, the sacrificial layers 302L, the intermediate sacrificial layer 318L. The etching processes can include wet etching processes and / or dry etching processes, such as plasma enhanced etching, and one or more mask patterns. In some embodiments, the etching processes include performing a dry or wet etching process and controlling parameters thereof to form sidewalls of the recesses 410 having a desired slope. As Figure 5 illustrated, the method can further include forming mask structures 530, 532, which can include one or more cover patterns or other protective patterns, and a spacer structure 534 in the recesses 410 and on a portion of the remaining alternating stack.

[0063] Referring to Figure 6 and Figure 16 the flowchart, the method can include forming a plurality of channel patterns 104 and a sacrificial gate pattern 302 alternately stacked on the substrate 101 (block 1602). For example, as Figure 6 illustrated, the etching processes can be performed using the structures 530, 532, and 534 as etching masks to form recesses 614 defining the channel patterns 104 from the channel layers 104L, the intermediate sacrificial patterns 318 from the intermediate sacrificial layer 318L, and the sacrificial gate pattern 302 from the sacrificial layers 302L. The recesses 614 can extend into portions of the substrate 101 such that the substrate 101 can include recessed surfaces adjacent to opposite sides of the channel patterns 104 and the sacrificial gate pattern 302.

[0064] Referring to Figure 7 the selective etching process is performed to remove the intermediate sacrificial patterns 318. As Figure 8As shown, isolation patterns 118 (also referred to as middle dielectric isolation (MDI)) are formed by filling the areas from which the intermediate sacrificial patterns 318 are removed with an insulating material, such as but not limited to SiN, SiOx, SiBCN, SiCN, SiON, SiOCN, or other insulating material. For example, the recesses 614 and the areas from which the intermediate sacrificial patterns 318 are removed can be filled with MDI insulating material, which can then be substantially removed from the recesses 614 to form the isolation patterns 118. Portions of the insulating material can remain at the bottoms of the recesses 614 to form preliminary insulating regions 126'.

[0065] Referring to Figure 9 and Figure 16 , edges of the sacrificial gate patterns 302 at their opposite ends in the first direction Dl are selectively recessed to expose their side surfaces 302s (block 1604), and preliminary inner spacers 910 are formed on the exposed side surfaces 302s at the opposite ends of the sacrificial gate patterns 302 (block 1606). For example, the edges or side surfaces of the sacrificial gate patterns 302 exposed by the recesses 614 can be recessed using a selective etching process, and an oxide or nitride layer can be formed on the recessed ends of the sacrificial gate patterns 302 to form the preliminary inner spacers 910. In some embodiments, the selective etching process can recess the edges or side surfaces of the sacrificial gate patterns 302 by substantially similar amounts, such that two or more of the preliminary inner spacers 910 can have substantially similar lengths in the first direction Dl. In some embodiments, the selective etching process can recess the edges or side surfaces of the sacrificial gate patterns 302 by different amounts, such that two or more of the preliminary inner spacers 910 can have different lengths in the first direction Dl. The preliminary inner spacers 910 can be formed of an insulating or dielectric material (e.g., an oxide or nitride material), which can be the same as or different from the material of the isolation patterns 118 and / or 122 (e.g., to provide etching selectivity with respect to the material of the isolation patterns 118 and / or 122).

[0066] As shown in Figure 10 , one or more insulating patterns can be formed in or on portions of the substrate 101 to at least partially fill the recesses 614, thereby forming insulating regions 126. In some embodiments, the insulating regions 126 can be oxide (e.g., silicon oxide)-based patterns or nitride (e.g., silicon nitride)-based patterns, which can be formed by filling the recesses 614 with an oxide-based material or a nitride-based material and etching the material to provide the insulating regions 126. The insulating regions 126 can be different from the material of the preliminary inner spacers 910 (e.g., to provide etching selectivity with respect to the material of the preliminary inner spacers 910).

[0067] With reference to Figure 11A and Figure 11B ( Figure 11B corresponding to Figure 2A ) and Figure 16 , the method can further include forming source / drain regions 108 in the recesses 614 at opposite ends of the channel pattern 104 (block 1608). In particular, a first (lower) source / drain region 108a can be formed in the recess 614 at the opposite end of the first channel pattern 104a. For example, the first source / drain region 108a can be formed by selective epitaxy growth at the opposite side of the first channel pattern 104a. In some embodiments, the first source / drain region 108a can include a first semiconductor material that is the same as the material of the first channel pattern 104a. For example, the first channel pattern 104a and the first source / drain region 108a can be silicon (Si). After growing the first source / drain region 108a, the method includes forming an isolation pattern 122 on the first source / drain region 108a. For example, an oxidation process (e.g., plasma oxidation or thermal oxidation) can be performed to oxidize the upper surface of the first source / drain region 108a to form the isolation pattern 122.

[0068] Still referring to Figures 11A-B and Figure 16 , a second (upper) source / drain region 108b can be formed in the recess 614 at the opposite end of the second channel pattern 104b. The isolation pattern 122 electrically separates the second source / drain region 108b from the first source / drain region 108a. For example, the second source / drain region 108b can be formed by selective epitaxy growth at the opposite side of the second channel pattern 104b. In some embodiments, the second source / drain region 108b can include a second semiconductor material that is different from the first semiconductor material of the second channel pattern 104b. For example, the second channel pattern 104b can be silicon (Si), while the second source / drain region 108b can be silicon germanium (SiGe). It will be understood that the first source / drain region 108a and the second source / drain region 108b can be formed in any order, not limited to the order described above. In response to the formation of the first source / drain region 108a and the second source / drain region 108b, the preliminary inner spacers 910 are located between the side surfaces 302s of the sacrificial gate pattern 302 and the first side surfaces 108s1 of the source / drain regions 108, which face each other in the first direction D1.

[0069] As Figure 12A and Figure 12B ( Figure 12B corresponding to Figure 2A ) and Figure 16As shown, the method can further include removing the preliminary inner spacers 910 between the side surfaces 302s of the sacrificial gate pattern 302 and the first side surfaces 108sl of the source / drain regions 108, e.g., using a selective etching process such as a wet cleaning process (block 1610). In some embodiments, the isolation patterns 118 and / or 122 (and / or the mask structures 530, 532 and spacer structures 534) can be formed of the same material as the preliminary inner spacers 910, and thus, can also be removed in the operations shown in Figure 12A and Figure 12B As shown in the operations shown in

[0070] Referring to Figure 13A and Figure 13B , Figure 14A and Figure 14C , Figure 15A and Figure 15C and Figure 16 the method can further include forming the hollow inner spacers 110 between the sacrificial gate pattern 302 and the source / drain regions 108 (block 1612). Figure 17 is a flowchart illustrating an example method of forming the hollow inner spacers 110 at block 1612 of Figure 16

[0071] In particular, Figure 13A and Figure 13B illustrate an example method of forming conformal first insulating liners 111 for the hollow inner spacers 110. As Figures 13A-B ( Figure 13B corresponding to Figure 2A ) and Figure 17 As shown, the first insulating liners 111 are formed on the side surfaces 302s of the sacrificial gate pattern 302 and on the first side surfaces 108sl of the source / drain regions 108, thereby providing respective voids 114 between the side surfaces 302s of the sacrificial gate pattern 302 and the first side surfaces 108sl of the source / drain regions 108 in the first direction Dl (block 1702).

[0072] ​The first insulative liner 111 is formed in a conformal manner on the side surfaces 302s of the sacrificial gate pattern 302 and the first side surfaces 108sl of the source / drain regions 108. For example, the first insulative liner 111 can be deposited (e.g., by performing a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, etc.) so as to extend conformally over the channel pattern 104, the sacrificial gate pattern 302, and the portions or surfaces of the source / drain regions 108 that are exposed (e.g., in the recesses 614) by the removal of the preliminary underliner 910 at block 1612.

[0073] The first insulative liner 111 can comprise an insulative or dielectric material (e.g., silicon nitride (SiN) and / or a low-k material having a lower dielectric constant than silicon oxide (SiO)). In some embodiments, the first insulative liner 111 can be a relatively thin layer, that is, have a thickness Tl sufficient to extend along the side surfaces 302s of the sacrificial gate pattern 302 and along the first side surfaces 108sl of the source / drain regions 108 without completely filling the space therebetween, such that respective voids 114 are bounded by the first insulative liner 111 in the first direction Dl. The first insulative liner 111 can also be formed to extend conformally over the second side surfaces 108s2 of the source / drain regions 108, which are opposite one another in a second direction D2 that intersects the first direction Dl.

[0074] Figure 14A and Figure 14B An example method for forming the non-conformal second insulative liner 112 of the hollow underliner 110 is shown. Figure 14C Corresponding to Figure 2A and Figure 14A and Figure 14B are taken along lines X1-X1 and X2-X2 of Figure 14C .

[0075] As shown in Figures 14A-C and Figure 17 , the second insulative liner 112 is formed to extend non-conformally over the second side surfaces 108s2 of the source / drain regions 108 (block 1704). For example, the second insulative liner 112 can be deposited (e.g., by performing a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, etc.) so as to extend non-conformally over the portions or surfaces of the channel pattern 104, the sacrificial gate pattern 302, and the source / drain regions 108 having the first insulative liner 111 thereon, thereby sealing or at least partially surrounding the channel pattern 104, the sacrificial gate pattern 302, and the source / drain regions 108.

[0076] In some embodiments, the second insulating liner 112 can be formed using a liner overhang technique so as to extend at least partially between the side surface 302s of the sacrificial gate pattern 302 and the respective portion 111p of the first insulating liner 111 on the first side surface 108sl of the source / drain region 108, thereby collectively enclosing the respective void 114. That is, the second insulating liner 112 collectively with the first insulating liner 111 forms the hollow in- spacer 110 enclosing the respective void 114.

[0077] The second insulating liner 112 can comprise an insulating material or a dielectric material (e.g., silicon nitride (SiN) and / or a low-k material having a dielectric constant lower than that of silicon oxide (SiO)), which can be the same or different from that of the first insulating liner 111. For example, the second insulating liner 112 can be formed of a second material that can be deposited with less conformality than the first material of the first insulating liner 111. In some embodiments, the second insulating liner 112 can be a relatively thick layer compared to the thickness Tl of the first insulating liner 111. The second insulating liner 112 can have a thickness T2 sufficient to fill the gap between the side surface 302s of the sacrificial gate pattern 302 and the portion 111p of the first insulating liner 111 on the first side surface 108sl of the source / drain region 108, such that the respective void 114 is bounded by the second insulating liner 112 in the second direction D2. That is, in response to depositing the second insulating liner 112, an air pocket 114 (i.e., a cavity or void comprising air) can be formed within the hollow in- spacer 110.

[0078] Accordingly, the integrated circuit device 100 can have a hollow in- spacer 110 comprising an air pocket or void 114, which can have a desired profile capable of reducing parasitic capacitance in the integrated circuit device 100. In particular, as shown in FIGS. 1A-1C, the hollow in- spacer 110 can have a first portion with a first thickness Tl and a respective void 114 in a first cross-section Xl-Xl along the first direction Dl, and a second portion with a second thickness T2 and no respective void 114 in a second cross-section X2-X2 along the first direction Dl. That is, the hollow in- spacer 110 can have different cross-sectional profiles at a central portion (which can be hollow) and an edge portion (which can be filled by the liner 111 and / or 112). In some embodiments, both the first insulating liner 111 and the second insulating liner 112 of the hollow in- spacer 110 can be formed of a low-k material (i.e., a respective material having a dielectric constant less than or equal to that of silicon nitride) so as to further reduce capacitive effects. Figure 14A 、 Figure 14B and Figure 14C

[0079] Figure 15A and Figure 15B ​An example method for forming a replacement metal gate (RMG) is shown. Figure 15C Corresponding to Figure 2A And Figure 15A The cross-section of Figure 15B is taken along lines X1-X1 and X2-X2. Figure 15C

[0080] As shown in Figures 15A-C , a replacement metal gate process is performed in which the sacrificial gate pattern 302 is selectively removed, and the gate pattern 102 is formed to replace the sacrificial gate pattern 302. In particular, after the insulating spacers 111 and 112 are formed as described above, the sacrificial gate pattern 302 between the respective voids 114 can be selectively etched, and the gate pattern 102 can be formed in the areas from which the sacrificial gate pattern 302 is removed. Thus, the first insulating spacer 111 extends conformally along the side surface 102s of the gate pattern 102 and along the first side surface 108sl of the source / drain region 108 with the respective void 114 therebetween, while the second insulating spacer 112 extends non-conformally along the second side surface 108s2 of the source / drain region 108 and at least partially on the respective portion 111p of the first insulating spacer 111 between the side surface 102s of the gate pattern 102 and the first side surface 108sl of the source / drain region 108. That is, the method can further include replacing the sacrificial gate pattern 302 with the conductive gate pattern 102 between the first source / drain region 108a and the second source / drain region 108b with the hollow inner spacer 110 between the conductive gate pattern 102 and the first source / drain region 108a and the second source / drain region 108b, thereby forming Figures 2B-C the first transistor 202a and the second transistor 202b of the integrated circuit device 100 shown in

[0081] Thus, Figures 3-17 ​The illustrated method forms a channel pattern 104 extending between source / drain regions 108 in a first direction Dl and alternatingly stacked with sacrificial gate patterns 302. The sacrificial gate patterns 302 are selectively recessed at opposite ends thereof in the first direction to expose side surfaces 302s, preliminary inner spacers 910 are formed on the side surfaces 302s of the sacrificial gate patterns 302, and the source / drain regions 108 are formed at opposite ends of the channel pattern 104 such that the preliminary inner spacers 910 are located between the side surfaces 302s of the sacrificial gate patterns 302 and first side surfaces 108sl of the source / drain regions 108, the side surfaces 302s of the sacrificial gate patterns 302 and the first side surfaces 108sl of the source / drain regions 108 facing each other in the first direction Dl. An etching process is performed to remove the preliminary inner spacers 910 between the sacrificial gate patterns 302 and the source / drain regions 108. A hollow inner spacer 110 is formed between the sacrificial gate patterns 302 and the source / drain regions 108 by forming a first insulating liner 111 extending conformally on the side surfaces 302s of the sacrificial gate patterns 302 and the first side surfaces 108sl of the source / drain regions 108, thereby providing a void 114 between the side surfaces 302s of the sacrificial gate patterns 302 and the first side surfaces 108sl of the source / drain regions 108 in the first direction; and forming a second insulating liner 112 extending non-conformally on second side surfaces 108s2 of the source / drain regions 108, the second side surfaces 108s2 opposite each other in a second direction D2 intersecting the first direction Dl. The respective voids 114 are thereby bounded in the first direction Dl by the first insulating liner 111 and in the second direction D2 by the second insulating liner 112.

[0082] Accordingly, embodiments of the disclosure can provide methods for fabricating 3D stacked transistor structures (e.g., 3DSFETs) with improved device performance and reliability by forming air pockets within inner spacers of 3DSFETs, thereby reducing parasitic capacitance and providing increased flexibility for desired profiles of inner spacers by using air. Further, advantages of the structures, features, or operations disclosed herein can include, for example, improved device performance and reliability of integrated circuit devices (e.g., 3DSFETs) by depositing liners (e.g., the first conformal insulating liner 111 and the second non-conformal insulating liner 112) including low-k materials, thereby reducing parasitic capacitance. However, it will be understood that embodiments of the disclosure are not limited to the above advantages.

[0083] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Further, all terms are to be interpreted in the same manner as they would be by a person of ordinary skill in the art and in the context in which they are used, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. For example, as referred to herein, an "insulating" layer or liner can include a dielectric material (which can be polarizable by an applied electric field).

[0084] In the above description, each example embodiment is described with reference to regions of a particular conductivity type. It will be understood that devices of the opposite conductivity type can be formed by simply reversing the conductivity of the n-type and p-type layers in each of the above embodiments. Thus, it will be understood that the present application encompasses both n-channel and p-channel devices for each different device structure.

[0085] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of embodiments. As used herein, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "including" and / or "having" specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0086] It will be understood that, although the terms "first," "second," etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present application. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0087] It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0088] Spatial terms such as "beneath" or "below" or "on" or "under" or "top" or "bottom" can be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0089] Example embodiments are described herein with reference to the accompanying figures, which can include schematic illustrations of idealized embodiments (and intermediate structures) of the present disclosure. Many specific details of the present disclosure are described herein in order to provide a thorough understanding of the present disclosure. It will be understood by those skilled in the art, however, that the present disclosure can be practiced without many of the specific details. In other instances, well-known methods, procedures and training have not been described in detail so as not to unnecessarily obscure aspects of the present disclosure. Accordingly, the present disclosure is not to be limited by the above-described example embodiments.

[0090] Embodiments of the present disclosure are also described with reference to manufacturing operations and flow diagrams. It will be understood that the steps shown in the manufacturing operations and flow diagrams need not be performed in the order shown.

[0091] The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the scope of the present disclosure. Thus, to the maximum extent allowed by law, the scope of the present disclosure is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited to the foregoing detailed description. The foregoing detailed description is to be understood as being in all aspects illustrative only and not restrictive.

[0092] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 704,658, filed October 8, 2024, entitled "Integrated circuit devices and methods of forming the same," the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An integrated circuit device, comprising: Transistor structure, including: One or more channel patterns, extending in a first direction between the source / drain regions and stacked alternately with one or more gate patterns; and A hollow spacer between the one or more gate patterns and the source / drain regions, wherein the hollow spacer comprises: The corresponding gap between the side surface of the one or more gate patterns and the first side surface of the source / drain region in the first direction; and The first pad on the side surface of the one or more gate patterns and on the first side surface of the source / drain region.

2. The integrated circuit device according to claim 1, wherein, The first pad extends conformally on the side surface of the one or more gate patterns and the first side surface of the source / drain region, and the corresponding gap is defined by the first pad in the first direction.

3. The integrated circuit device according to claim 2, wherein, The hollow internal spacer further includes: The second pad, on the second side surface of the source / drain region, has second side surfaces that are opposite to each other in a second direction intersecting the first direction. The second liner and the first liner together seal the corresponding gap.

4. The integrated circuit device according to claim 3, wherein, The second pad extends nonconformally on the second side surface of the source / drain region, and the corresponding gap is defined by the second pad in the second direction.

5. The integrated circuit device according to claim 3, wherein, The second pad extends at least partially between the corresponding portions of the first pad on the side surface of the one or more gate patterns and the first side surface of the source / drain region.

6. The integrated circuit device according to claim 3, wherein, The hollow spacer includes a first part and a second part. The first part has a first thickness and has the corresponding gap in a first cross section along the first direction. The second part has a second thickness and does not have the corresponding gap in a second cross section along the first direction.

7. The integrated circuit device according to claim 3, wherein, The first pad or the second pad comprises a material having a dielectric constant less than or equal to that of silicon nitride.

8. The integrated circuit device according to claim 1, wherein: The one or more channel patterns include a lower nanosheet of a first transistor and an upper nanosheet of a second transistor. The one or more gate patterns include the lower gate pattern of the first transistor and the upper gate pattern of the second transistor. as well as The source / drain region includes the lower source / drain region of the first transistor and the upper source / drain region of the second transistor.

9. The integrated circuit device according to claim 8, wherein, The lower source / drain region has a first conductivity type, and the upper source / drain region has a second conductivity type opposite to the first conductivity type.

10. A method for manufacturing an integrated circuit device, the method comprising: Multiple channel patterns and sacrificial gate patterns are formed, the channel patterns and sacrificial gate patterns extending in a first direction and being alternately stacked on the substrate; The sacrificial gate pattern is selectively recessed at opposite ends in the first direction to expose the side surface of the sacrificial gate pattern; Preliminary inner spacers are formed on the side surface of the sacrificial gate pattern; A source / drain region is formed at opposite ends of the channel pattern, wherein the initial inner spacer is between the side surface of the sacrificial gate pattern and the first side surface of the source / drain region, the side surface of the sacrificial gate pattern and the first side surface of the source / drain region facing each other in the first direction; An etching process is performed to remove the initial internal spacers; as well as A first pad is formed on the side surface of the sacrificial gate pattern and the first side surface of the source / drain region, wherein there is a corresponding gap between the side surface of the sacrificial gate pattern and the first side surface of the source / drain region in the first direction.

11. The method according to claim 10, wherein, The first pad extends conformally on the side surface of the sacrificial gate pattern and the first side surface of the source / drain region, and the corresponding gap is defined by the first pad in the first direction.

12. The method of claim 11, further comprising: A second pad is formed on the second side surface of the source / drain region, the second side surfaces being opposite to each other in a second direction intersecting the first direction. The second liner and the first liner together provide a hollow internal spacer to seal the corresponding gap.

13. The method according to claim 12, wherein, The second pad extends nonconformally on the second side surface of the source / drain region, and the corresponding gap is defined by the second pad in the second direction.

14. The method according to claim 12, wherein, The second pad extends at least partially between corresponding portions of the first pad on the side surface of the sacrificial gate pattern and on the first side surface of the source / drain region.

15. The method according to claim 12, wherein, The hollow internal spacer includes a first part and a second part, the first part having a first thickness and having the corresponding gap in a first cross section along the first direction, and the second part having a second thickness and not having the corresponding gap in a second cross section along the first direction.

16. The method according to claim 12, wherein, The first pad or the second pad comprises a material having a dielectric constant less than or equal to that of silicon nitride.

17. The method of claim 11, further comprising: Remove the sacrificial gate pattern between the corresponding gaps; as well as A gate pattern is formed to replace the sacrificial gate pattern, wherein the first pad extends on the side surface of the gate pattern and the first side surface of the source / drain region, wherein the corresponding gap is between the side surface of the sacrificial gate pattern and the first side surface of the source / drain region.

18. A method for manufacturing an integrated circuit device, the method comprising: A channel pattern is formed, the channel pattern extending between the source / drain regions in a first direction and the channel pattern being stacked alternately with the sacrificial gate pattern therebetween; as well as A hollow spacer is formed between the sacrificial gate pattern and the source / drain region, wherein forming the hollow spacer includes: A first pad is formed, the first pad extending conformally on the side surface of the sacrificial gate pattern and the first side surface of the source / drain region, having a corresponding gap between the side surface of the sacrificial gate pattern and the first side surface of the source / drain region in the first direction; and A second pad is formed, which extends nonconformally on a second side surface of the source / drain region, the second side surfaces being opposite to each other in a second direction intersecting the first direction. The corresponding gap is defined by the first pad in the first direction and by the second pad in the second direction.

19. The method of claim 18, wherein: The second pad extends at least partially between a corresponding portion of the first pad on the side surface of the sacrificial gate pattern and the first side surface of the source / drain region to jointly close the corresponding gap; as well as The hollow internal spacer includes a first part and a second part, the first part having a first thickness and having the corresponding gap in a first cross section along a first direction, and the second part having a second thickness and not having the corresponding gap in a second cross section along the first direction.

20. The method of claim 18, further comprising, prior to forming the hollow internal spacer: The sacrificial gate pattern is selectively recessed at opposite ends in the first direction to expose the side surface of the sacrificial gate pattern; Preliminary inner spacers are formed on the side surface of the sacrificial gate pattern; The source / drain region is formed at opposite ends of the channel pattern, wherein the initial inner spacer is between the side surface of the sacrificial gate pattern and the first side surface of the source / drain region, the side surface of the sacrificial gate pattern and the first side surface of the source / drain region facing each other in the first direction; as well as An etching process is performed to remove the initial internal spacer between the sacrificial gate pattern and the source / drain regions.

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