Electronic device

Abstract

An electronic device includes: an intermediate insulating layer disposed on a substrate; a pixel unit including a light emitting element; pixel defining patterns each having an opening defined therein, and disposed on the intermediate insulating layer; and a partition wall disposed between the pixel defining patterns close to (adjacent to) each other on the intermediate insulating layer. The partition wall includes first to third layers disposed on the intermediate insulating layer, a groove in which at least a portion of the intermediate insulating layer is recessed is defined in the intermediate insulating layer defined in a recessed region between the pixel defining pattern and the partition wall, and the common layer and the second electrode extend from the light emitting region to the recessed region and contact the first layer.

Description

[0001] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0136805, filed on October 8, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This disclosure relates to electronic devices, and more specifically, to electronic devices having improved display quality. Background Technology

[0003] Typically, electronic devices that provide images to users, such as smartphones, digital cameras, laptops, navigation devices, and smart TVs, include electronic devices for displaying images. These electronic devices generate images and then display the generated images to the user via a screen.

[0004] The electronic device includes multiple pixels for generating images and multiple lines connected to the pixels. The pixels are driven by receiving drive signals through the lines.

[0005] In small to medium-sized electronic devices such as tablet PCs with small area sizes or medium to large-sized electronic devices such as smart TVs with large area sizes, variations may occur in the driving voltage transmitted to each of the multiple pixels, and therefore designs are desired to compensate for variations in driving voltage. Summary of the Invention

[0006] This disclosure provides an electronic device capable of providing a consistent driving voltage to multiple pixels.

[0007] An embodiment of the present invention provides an electronic device comprising: a substrate including: a display area including a plurality of light-emitting areas; and a non-light-emitting area disposed between the plurality of light-emitting areas; an intervening insulating layer disposed on the substrate; a pixel unit disposed on the substrate and including light-emitting elements, each light-emitting element including: a first electrode and a second electrode overlapping with one of the light-emitting areas and disposed on the intervening insulating layer; and a common layer disposed between the first electrode and the second electrode; and a pixel defining pattern disposed on the intervening insulating layer, each defining a pixel corresponding to a light-emitting area and exposing the first electrode therein. A small portion of the opening; and a partition wall, overlapping the non-light-emitting area, and disposed on an intercalary insulating layer between pixel-defined patterns that are close to each other (adjacent), wherein the partition wall comprises: a first layer disposed on the intercalary insulating layer; a second layer disposed on the first layer; and a third layer disposed on the second layer, wherein a groove is defined in an intercalary insulating layer in a recessed area between the pixel-defined patterns and the partition wall, wherein at least a portion of the intercalary insulating layer is recessed in a direction from the upper surface to the lower surface of the intercalary insulating layer, and a common layer and a second electrode extend from the light-emitting area to the recessed area and contact the first layer.

[0008] In one embodiment, the groove may expose a portion of the lower surface of the first layer facing the intervening insulation layer.

[0009] In one embodiment, the common layer may contact a portion of the lower surface of the first layer.

[0010] In one embodiment, the second electrode may contact the side surface of the first layer.

[0011] In one embodiment, the second electrode may contact a portion of the lower surface of the first layer and expose the side surface of the first layer.

[0012] In one embodiment, the second electrode may contact the side surface of the first layer and the portion of the top surface of the first layer exposed from the second layer.

[0013] In an embodiment, the groove may have a concave shape in the cross-sectional view.

[0014] In an embodiment, the electronic device may further include an interlayer insulation layer disposed below the interlayer insulation layer, wherein the groove can penetrate the interlayer insulation layer from the upper surface to the lower surface and expose a portion of the upper surface of the interlayer insulation layer.

[0015] In one embodiment, the common layer may contact the side surface of the defined groove of the interlayer insulating layer, a portion of the upper surface of the interlayer insulating layer, and a portion of the lower surface of the first layer.

[0016] In an embodiment, the electronic device may further include: a transistor disposed on a substrate; a first connection electrode covered with an interlayer insulating layer and connected to the transistor; and a second connection electrode covered with an interlayer insulating layer and connected to the first connection electrode through a first contact hole defined in the interlayer insulating layer, wherein the first electrode can be connected to the second connection electrode through a second contact hole defined in the interlayer insulating layer.

[0017] In this embodiment, the first and third layers may include titanium, and the second layer may include aluminum.

[0018] In an embodiment, in a cross-sectional view, the width of the first layer and the width of the third layer may each be greater than the width of the second layer, and the thickness of the first layer and the thickness of the third layer may each be less than the thickness of the second layer.

[0019] In an embodiment, the electronic device may further include a first dummy pattern disposed on a third layer and a second dummy pattern disposed on the first dummy pattern, wherein the first dummy pattern may include the same material as the common layer, and the second dummy pattern may include the same material as the second electrode.

[0020] In an embodiment, the partition wall may further include a fourth layer disposed on the third layer and comprising a material different from that of the first and third layers.

[0021] In the embodiments, the first and third layers may comprise either titanium or a molybdenum-titanium alloy, and the second and fourth layers may comprise either aluminum or copper.

[0022] In an embodiment, the side surface of the second layer may be oxidized and may not be conductive.

[0023] In one embodiment, multiple second electrodes that are disconnected and have a partition wall between them can be connected via the partition wall.

[0024] In this embodiment, the intervening insulation layer may include any of inorganic and organic materials.

[0025] In an embodiment, the electronic device may further include an encapsulation layer covering the light-emitting element.

[0026] In an embodiment, a plurality of pixel units may be provided in the display area in such a manner as follows: each of the plurality of pixel units may include a first-1 pixel providing a first color light, a first-2 pixel providing the first color light and spaced apart from the first-1 pixel along a first direction, a second pixel providing a second color light different from the first color light and spaced apart from the first-1 pixel along a first diagonal direction, a third pixel providing a third color light different from the first color light and the second color light, and a third pixel spaced apart from the second pixel along a second direction intersecting the first direction and spaced apart from the first-1 pixel along a second diagonal direction intersecting the first diagonal direction. Attached Figure Description

[0027] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of the inventive concept. In the drawings:

[0028] Figure 1A This is a perspective view of an embodiment of an electronic device conceived according to the present invention;

[0029] Figure 1B This is a block diagram of an embodiment of an electronic device based on the present invention;

[0030] Figure 2 This is a cross-sectional view of an embodiment of an electronic device conceived according to the present invention;

[0031] Figure 3 This is a cross-sectional view of an embodiment of a display panel according to the present invention;

[0032] Figure 4A This is a block diagram of an embodiment of a display module according to the present invention;

[0033] Figure 4B yes Figure 4A The equivalent circuit of one pixel in the diagram;

[0034] Figure 5A This is a plan view of an embodiment of a pixel unit according to the present invention;

[0035] Figure 5B This is a plan view of an embodiment of a pixel unit according to the present invention;

[0036] Figure 6 It is along Figure 5A A cross-sectional view taken from line I-I';

[0037] Figure 7 It is along Figure 5A A cross-sectional view taken from line II-II';

[0038] Figure 8 This is a cross-sectional view of an embodiment of a display panel according to the present invention;

[0039] Figure 9 This is a cross-sectional view of an embodiment of a display panel according to the present invention;

[0040] Figure 10 This is a cross-sectional view of an embodiment of a display panel according to the present invention; and

[0041] Figure 11 This is a cross-sectional view of an embodiment of a display panel according to the present invention. Detailed Implementation

[0042] In this specification, it will be understood that when an element (or area, layer, or part, etc.) is referred to as being "on" another element, "connected to" or "attached to" another element, it may be directly disposed on, connected to or attached to that other element, or may be disposed therein with other elements.

[0043] The same reference numerals or symbols always refer to the same elements. In the drawings, the thickness, ratios, and dimensions of elements are exaggerated for the purpose of effectively describing the technical content. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed elements.

[0044] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, the elements are not limited by these terms. These terms are used only to distinguish one element from another. For example, the first element discussed below may be referred to as the second element without departing from the scope of the inventive concept. Similarly, the second element may be referred to as the first element. In this specification, unless the context clearly indicates otherwise, the singular expressions “a” and “the” are intended to include the plural forms as well.

[0045] Additionally, terms such as "below," "under," "on the lower side," "above," "on top," or "on the upper side" can be used to describe the relationships between the elements illustrated in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0046] It will be further understood that, when used in this specification, the terms “comprising,” “including,” “having,” and / or variations thereof indicate the presence of a stated feature, quantity, step, operation, element, component, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements, components, and / or combinations thereof.

[0047] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “approximately” or “about” as used herein include stated values ​​and mean within an acceptable range of deviation from a particular value as determined by one of ordinary skill in the art. For example, the term “approximately” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0048] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (such as those defined in commonly used dictionaries) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless so explicitly defined herein.

[0049] In the following description, embodiments of the inventive concept are illustrated with reference to the accompanying drawings.

[0050] Figure 1A This is a perspective view of an embodiment of an electronic device conceived according to the present invention. Figure 1B This is a block diagram of an embodiment of an electronic device conceived according to the present invention. Figure 2 This is a cross-sectional view of an embodiment of an electronic device conceived according to the present invention. Figure 3 This is a cross-sectional view of an embodiment of a display panel according to the present invention. Figure 4A This is a block diagram of an embodiment of a display module according to the present invention. Figure 4B yes Figure 4A The equivalent circuit of one pixel in the diagram.

[0051] Reference Figure 1A In an embodiment of the present invention, the electronic device DD may have a long side extending parallel to a first direction DR1 and a short side extending parallel to a second direction DR2 intersecting the first direction DR1. The corner connecting the long and short sides of the electronic device DD may have a curved shape. The curved corner of the electronic device DD may be defined as a rounded corner. The planar shape of such an electronic device DD may be defined as a rounded quadrilateral. However, this is one embodiment of the planar shape of the electronic device DD, and the planar shape of the electronic device DD is not limited to a rounded quadrilateral.

[0052] In the following text, the direction that intersects substantially perpendicularly with the plane defined by the first direction DR1 and the second direction DR2 is defined as the third direction DR3. Furthermore, in the specification, the phrase "in a plan view" is defined as the state viewed from the third direction DR3.

[0053] The front surface of the electronic device DD can be defined as a display surface DS, and has a plane defined by a first direction DR1 and a second direction DR2. An image IM generated in the electronic device DD can be provided to the user through the display surface DS.

[0054] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. An image IM may be displayed in the display area DA, and an image IM may not be displayed in the non-display area NDA. The non-display area NDA may surround the display area DA and define an edge of the electronic device DD printed in a predetermined color.

[0055] Depending on the shape of the electronic device DD, the display area DA can have a rounded quadrilateral shape. In an embodiment, for example, the display area DA may include sides of a quadrilateral extending in a first direction DR1 and a second direction DR2, and rounded corners connecting the sides. Of the four sides, the side extending in the first direction DR1 may be defined as the longer side, and the side extending in the second direction DR2 may be defined as the shorter side.

[0056] The electronic device DD can sense input applied from outside the electronic device DD. In an embodiment, for example, the electronic device DD can sense a first input from the stylus PEN and a second input from the touch TC. The stylus PEN can be defined as an input device.

[0057] The stylus (PEN) can be an active pen that outputs signals. A second input from the touch TC can include various forms of external input, such as a part of the user's body, light, heat, or pressure.

[0058] The electronic device DD and the stylus PEN can communicate bidirectionally. The electronic device DD can provide uplink signals to the stylus PEN. In embodiments, for example, the uplink signals may include information such as panel information and protocol version, but are not particularly limited thereto.

[0059] The stylus PEN can provide downlink signals to the electronic device DD. The downlink signals may include synchronization signals or status information about the stylus PEN. In embodiments, for example, the downlink signals may include coordinate information about the stylus PEN, battery information about the stylus PEN, tilt information about the stylus PEN, and / or various information stored in the stylus PEN, but are not particularly limited thereto.

[0060] The electronic device DD can be used in large electronic devices such as televisions, monitors, or outdoor billboards. Additionally, the electronic device DD can be used in small to medium-sized electronic devices such as personal computers (e.g., laptop computers, tablet computers), personal digital terminals, car navigation units, game consoles, smartphones, or cameras. However, these are merely examples, and the electronic device DD can also be used in other electronic devices, provided that the electronic device DD does not depart from the inventive concept.

[0061] Figure 1B An embodiment of a block diagram of the electronic device DD is shown. (Refer to...) Figure 1B The electronic device DD outputs various information through the display module DM in the operating system. When the processor 110 executes the application stored in the memory 120, the display module DM provides the application information to the user through the display panel DP.

[0062] Processor 110 receives external input via input module 130 or sensor module 161 and executes an application corresponding to the external input. In an embodiment, for example, when a user selects a camera icon displayed on display panel DP, processor 110 receives user input via input sensor 161-2 and activates camera module 171. Processor 110 transmits image data corresponding to the captured image obtained by camera module 171 to display module DM. Display module DM can display the image corresponding to the captured image via display panel DP.

[0063] In another embodiment, when personal information authentication is performed in the display module DM, the fingerprint sensor 161-1 obtains the input fingerprint information as input data. The processor 110 compares the input data obtained by the fingerprint sensor 161-1 with the authentication data stored in the memory 120, and executes the application based on the comparison result. The display module DM can display the information executed according to the application logic via the display panel DP.

[0064] In another embodiment, when a music stream icon displayed on the display module DM is selected, the processor 110 obtains user input through the input sensor 161-2 and activates the music stream application stored in the memory 120. When a music execution command is input into the music stream application, the processor 110 activates the sound output module 163 and provides the user with the sound information corresponding to the music execution command.

[0065] The operation of the electronic device DD has been briefly described above. The construction of the electronic device DD is described in detail below. Some of the components of the electronic device DD, which will be described later, can be integrated and provided as a single component, and a single component can be separated and provided as two or more components.

[0066] Reference Figure 1B The electronic device DD can communicate with the external electronic device 102 via a network (e.g., a short-range wireless communication network or a long-range wireless communication network). In an embodiment, the electronic device DD may include a processor 110, a memory 120, an input module 130, a display module DM, a power module 150, an internal module 160, and an external module 170. In an embodiment, at least one of the above-mentioned components may be omitted in the electronic device DD, or one or more other components may be added. In an embodiment, some of the above-mentioned components (e.g., sensor module 161, antenna module 162, or audio output module 163) may be integrated into another component (e.g., display module DM).

[0067] Processor 110 can execute software to control at least one other component (e.g., hardware or software component) connected to electronic device DD and perform various data processing or operations. In an embodiment, as at least part of the data processing or operation, processor 110 can store data or commands received from another component (e.g., input module 130, sensor module 161, or communication module 173) in volatile memory 121 and process the data or commands stored in volatile memory 121, and the resulting data can be stored in non-volatile memory 122.

[0068] Processor 110 may include a main processor 111 and an auxiliary processor 112. Main processor 111 may include one or more of a central processing unit (“CPU”) 111-1 and an application processor (“AP”). Main processor 111 may further include one or more of a graphics processing unit (“GPU”) 111-2, a communication processor (“CP”), and an image signal processor (“ISP”). Main processor 111 may further include a neural processing unit (“NPU”) 111-3. The neural processing unit is a processor specifically designed to process artificial intelligence models, which can be generated through machine learning. The artificial intelligence model may include multiple layers of artificial neural networks. The artificial neural network may be one of a deep neural network (“DNN”), a convolutional neural network (“CNN”), a recurrent neural network (“RNN”), a restricted Boltzmann machine (“RBM”), a deep belief network (“DBN”), a bidirectional recurrent deep neural network (“BRDNN”), and a deep Q-network, or a combination of two or more of the above networks, but is not limited to the examples above. In addition to or in place of a hardware architecture, the artificial intelligence model may include a software architecture. At least two of the aforementioned processing units and processors can be implemented as an integrated component (e.g., a single chip), or they can each be implemented as independent components (e.g., multiple chips).

[0069] The auxiliary processor 112 may include a controller 112-1. The controller 112-1 may include an interface conversion circuit and a timing control circuit. The controller 112-1 receives image signals from the main processor 111, converts the data format of the image signals to conform to the specifications of the interface with the display module DM, and outputs the image data. The controller 112-1 can output various control signals required to drive the display module DM.

[0070] The auxiliary processor 112 may further include a data conversion circuit 112-2, a gamma correction circuit 112-3, a rendering circuit 112-4, etc. The data conversion circuit 112-2 can receive image data from the controller 112-1 and can compensate the image data to display an image with the desired brightness according to the characteristics of the electronic device DD or user settings, or it can convert the image data to reduce power consumption or compensate for afterimages, etc. The gamma correction circuit 112-3 can convert image data or gamma reference voltage, etc., so that the image displayed on the electronic device DD has the desired gamma characteristics. The rendering circuit 112-4 can receive image data from the controller 112-1 and render the image data taking into account the pixel arrangement of the display panel DP applied to the electronic device DD, etc. At least one of the data conversion circuit 112-2, gamma correction circuit 112-3, and rendering circuit 112-4 can be integrated into another component (e.g., the main processor 111 or the controller 112-1). At least one of the data conversion circuit 112-2, the gamma correction circuit 112-3, and the rendering circuit 112-4 can be integrated into the data driver DDV, which will be described later.

[0071] Memory 120 may store various data slices used by at least one component of the electronic device DD (e.g., processor 110 or sensor module 161), as well as output or input data regarding commands associated therewith. Memory 120 may include at least one of volatile memory 121 and non-volatile memory 122.

[0072] The input module 130 can receive data or commands from outside the electronic device DD (e.g., from a user or external electronic device 102) that are to be used in components of the electronic device DD (e.g., processor 110, sensor module 161, or sound output module 163).

[0073] Input module 130 may include a first input module 131 for inputting commands or data from a user and a second input module 132 for inputting commands or data from an external electronic device 102. The first input module 131 may include a microphone, mouse, keyboard, keys (e.g., buttons), or pen (e.g., a passive or active pen). The second input module 132 may support a specified protocol for wired or wireless connectivity to the external electronic device 102. In embodiments, the second input module 132 may include a High Definition Multimedia Interface (“HDMI”), a Universal Serial Bus (“USB”) interface, a Secure Digital (“SD”) card interface, or an audio interface. The second input module 132 may include a connector for physical connectivity to the external electronic device 102, such as an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0074] The display module (DM) visually presents information to the user. The display module (DM) may include a display panel (DP), a scan driver (SDC), and a data driver (DDV). The display module (DM) may further include a base, support, and window for protecting the display panel (DP).

[0075] The display panel (DP) can include a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel, and the type of display panel (DP) is not particularly limited. The display panel (DP) can be a rigid display panel or a flexible display panel that can be rolled up or folded. The display module (DM) may further include support members, brackets, or heat dissipation components that support the display panel (DP).

[0076] The scan driver SDC can be configured (e.g., mounted) as a driver chip on the display panel DP. Alternatively, the scan driver SDC can be integrated into the display panel DP. In embodiments, for example, the scan driver SDC may include an amorphous silicon TFT gate driver circuit (“ASG”), a low-temperature polycrystalline silicon (“LTPS”) TFT gate driver circuit, or an oxide semiconductor TFT gate driver circuit (“OSG”) built into the display panel DP. The scan driver SDC receives control signals from the controller 112-1 and outputs scan signals to the display panel DP in response to the control signals.

[0077] The display panel DP may further include a light-emitting driver. The light-emitting driver outputs a light-emitting control signal to the display panel DP in response to a control signal received from the controller 112-1. The light-emitting driver may be formed separately from the scan driver SDC, or it may be integrated into the scan driver SDC.

[0078] The data driver DDV receives a control signal from the controller 112-1, converts the image data into an analog voltage (e.g., a data voltage) in response to the control signal, and then outputs the data voltage to the display panel DP.

[0079] The data driver DDV can be integrated into another component (e.g., controller 112-1). The functions of the timing control circuitry and interface conversion circuitry of the aforementioned controller 112-1 can be integrated into the data driver DDV.

[0080] The display module DM may further include a light-emitting driver or a voltage generation circuit, etc. The voltage generation circuit can output various voltages required to drive the display panel DP.

[0081] Power module 150 supplies power to components of electronic device DD. Power module 150 may include a battery charged with electrical voltage. The battery may include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. Power module 150 may include a power management integrated circuit (“PMIC”). The PMIC provides optimized power supply to each of the modules described above and later. Power module 150 may include wireless power transmitting / receiving components electrically connected to the battery. The wireless power transmitting / receiving components may include multiple antenna radiators in the form of coils.

[0082] The electronic device DD may further include an internal module 160 and an external module 170. The internal module 160 may include a sensor module 161, an antenna module 162, and a sound output module 163. The external module 170 may include a camera module 171, an optical module 172, and a communication module 173.

[0083] The sensor module 161 can sense input from the user's body or from a pen into the first input module 131 and generate data values ​​or electrical signals corresponding to the input. The sensor module 161 may include at least one of a fingerprint sensor 161-1, an input sensor 161-2, and a digitizer 161-3.

[0084] The fingerprint sensor 161-1 can generate data values ​​corresponding to a user's fingerprint. The fingerprint sensor 161-1 may include one of an optical fingerprint sensor and a capacitive fingerprint sensor.

[0085] Input sensor 161-2 can generate data values ​​corresponding to coordinate information about input from the user's body or from a pen. Input sensor 161-2 generates the amount of capacitance change caused by the input as a data value. Input sensor 161-2 can sense input from a passive pen, or can send data to / receive data from an active pen.

[0086] Input sensor 161-2 can measure biosignals related to biological information such as blood pressure, water content, or body fat. In an embodiment, for example, when a user touches the sensor layer or sensor panel with a part of their body and does not move for a certain period of time, input sensor 161-2 can sense the biosignals based on the change in the electric field caused by that part of the user's body and output the information desired by the user to the display module DM.

[0087] The digitizer 161-3 can generate data values ​​corresponding to coordinate information about input from the pen. The digitizer 161-3 generates the amount of electromagnetic change caused by the input as a data value. The digitizer 161-3 can sense input from a passive pen, or can send data to / receive data from an active pen.

[0088] At least one of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be implemented as a sensor layer formed on the display panel DP by a continuous process. The fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be disposed above the display panel DP. However, the inventive concept is not limited thereto, and any one of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 (e.g., digitizer 161-3) can be disposed below the display panel DP.

[0089] At least two of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 can be integrated into a single sensing panel using the same process. When at least two of the fingerprint sensor 161-1, input sensor 161-2, and digitizer 161-3 are integrated into a single sensing panel, the sensing panel can be positioned between the display panel DP and a window positioned above the display panel DP. In this embodiment, the sensing panel can be positioned on the window, and the position of the sensing panel is not particularly limited.

[0090] At least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 can be integrated into the display panel DP. That is, at least one of the fingerprint sensor 161-1, the input sensor 161-2, and the digitizer 161-3 can be formed simultaneously by a process for forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel DP.

[0091] Additionally, sensor module 161 can generate electrical signals or data values ​​corresponding to the internal or external states of the electronic device DD. For example, sensor module 161 may further include a gesture sensor, a gyroscope sensor, a barometric pressure sensor, a magnetic sensor, an accelerometer, a grip sensor, a proximity sensor, a color sensor, an infrared (“IR”) sensor, a biosensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0092] Antenna module 162 may include one or more antennas for transmitting or receiving signals or power to or from an external source. In an embodiment, communication module 173 may transmit signals to or receive signals from an external electronic device via an antenna suitable for a communication method. The antenna configuration of antenna module 162 may be integrated into a component of display module DM (e.g., display panel DP) or input sensor 161-2, etc.

[0093] For example, the sound output module 163 may be a device for outputting sound signals to the outside of the electronic device DD, and includes a speaker for general purposes such as playing multimedia or playing recordings, and a receiver for receiving calls only. In embodiments, the receiver may be integrally formed with the speaker, or it may be formed separately from the speaker. The sound output mode of the sound output module 163 may be integrated into the display module DM.

[0094] Camera module 171 can capture still images and moving images. In embodiments, camera module 171 may include one or more lenses, image sensors, or image signal processors. Camera module 171 may further include an IR camera capable of measuring the presence / absence of a user, the user's position, the user's gaze, etc.

[0095] The optical module 172 can provide light. The optical module 172 may include a light-emitting diode or a xenon lamp. The optical module 172 can operate in conjunction with the camera module 171 or operate independently.

[0096] Communication module 173 can support the establishment of wired or wireless communication channels between electronic device DD and external electronic device 102, and the performance of communication via the established communication channels. Communication module 173 may include any one or both of the following: wireless communication modules such as cellular communication modules, short-range wireless communication modules, or Global Navigation Satellite System (“GNSS”) communication modules; and wired communication modules such as local area network (“LAN”) communication modules or power line communication modules. Communication module 173 can communicate with external electronic device 102 via short-range communication networks such as Bluetooth, Wi-Fi Direct, or IR Data Association (“IrDA”) or long-range communication networks such as cellular networks, the Internet, or computer networks (e.g., LAN or WAN). The various types of communication modules 173 described above can be implemented as a single chip, or each can be implemented as a separate chip.

[0097] The input module 130, sensor module 161, camera module 171, etc., can be used to control the operation of the display module DM in association with the processor 110.

[0098] Based on the input data received from the input module 130, the processor 110 outputs commands or data to the display module DM, the sound output module 163, the camera module 171, or the optical module 172. In embodiments, for example, the processor 110 may generate image data corresponding to input data applied via a mouse or active pen and output the image data to the display module DM, or it may generate command data corresponding to the input data and output the command data to the camera module 171 or the optical module 172. When no input data is received from the input module 130 within a predetermined time, the processor 110 may change the operating mode of the electronic device DD to a relatively low-power mode or a sleep mode, thereby reducing the power consumption of the electronic device DD.

[0099] The processor 110 outputs commands or data to the display module DM, the sound output module 163, the camera module 171, or the optical module 172 based on sensing data received from the sensor module 161. In an embodiment, for example, the processor 110 can compare authentication data applied by the fingerprint sensor 161-1 with authentication data stored in the memory 120, and then execute an application based on the comparison result. Based on sensing data sensed by the input sensor 161-2 or the digitizer 161-3, the processor 110 can execute commands or output corresponding image data to the display module DM. Where a temperature sensor is included in the sensor module 161, the processor 110 can receive temperature data about the measured temperature from the sensor module 161 and further perform brightness correction on image data, etc., based on the temperature data.

[0100] Processor 110 can receive measurement data from camera module 171 regarding the presence / absence of a user, the user's location, the user's gaze, etc. Processor 110 can further perform brightness correction on image data, etc., based on the measurement data. In an embodiment, for example, processor 110 determines the presence / absence of a user based on input from camera module 171, and can then output image data with its brightness corrected by data conversion circuit 112-2 or gamma correction circuit 112-3 to display module DM.

[0101] Some of the aforementioned components can be connected to each other via communication methods between peripheral devices, such as buses, general purpose input / output (“GPIO”), serial peripheral interfaces (“SPI”), mobile industrial processor interfaces (“MIPI”), or ultrapath interconnects (“UPI”) links, and can exchange signals (e.g., commands or data). Processor 110 can communicate with display module DM via a mutually agreed interface, and can use, for example, any of the aforementioned communication methods, but is not limited to them.

[0102] The electronic device DD according to the various embodiments disclosed herein can be of various forms. For example, the electronic device DD may include at least one of portable communication devices (e.g., smartphones), computer devices, portable multimedia devices, portable medical devices, cameras, wearable devices, and home appliances. The electronic device DD in the embodiments herein is not limited to the devices described above.

[0103] Figure 2 The illustrations serve as illustrative examples. Figure 1A The diagram shows a cross-section of the electronic device. Figure 2 The illustration shows a cross-section of the electronic device DD as viewed in the second direction DR2, as an illustrative embodiment. Figure 2 References not shown in the image. Figure 1B Some of the components of the described electronic device DD.

[0104] Reference Figure 2 The electronic device DD may include a display panel DP, an input sensor ISP, an anti-reflective layer RPL, a window WIN, a panel protective film PPF, and a first adhesive layer AL1 and a second adhesive layer AL2. Figure 2 The input sensor ISP shown in the diagram can be related to the reference sensor. Figure 1B The input sensor 161-2 described is the same component.

[0105] In embodiments of the present invention, the display panel DP can be an emitting display panel. In embodiments, for example, the display panel DP can be an organic light-emitting display panel or an inorganic light-emitting display panel. The emitting layer of an organic light-emitting display panel may include organic light-emitting materials. The emitting layer of an inorganic light-emitting display panel may include quantum dots or quantum rods, etc. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0106] An input sensor ISP can be disposed on a display panel DP. The input sensor ISP may include multiple sensing portions (not shown) for sensing external input using capacitive methods. When manufacturing the electronic device DD, the input sensor ISP can be directly fabricated on the display panel DP. Accordingly, the input sensor ISP in the embodiment can be directly disposed on the display panel DP. However, the inventive concept is not limited thereto, and the input sensor ISP can be manufactured as a panel separate from the display panel DP, and can be attached to the display panel DP via an adhesive layer.

[0107] The anti-reflective layer RPL can be disposed on the input sensor ISP. When manufacturing the electronic device DD, the anti-reflective layer RPL can be directly fabricated on the input sensor ISP. However, the inventive concept is not limited thereto, and the anti-reflective layer RPL can be fabricated as a separate panel and attached to the input sensor ISP via an adhesive layer.

[0108] The anti-reflective layer RPL can be defined as an external light anti-reflective film. The anti-reflective layer RPL reduces the reflectivity of external light incident from above the electronic device DD towards the display panel DP. Because of the anti-reflective layer RPL, external light is not visible to the user.

[0109] When external light propagating toward the display panel DP is reflected off the display panel DP and returned to an external user, the user can view the external light as if it were light reflected from a mirror. To prevent this phenomenon, as one embodiment, the anti-reflective layer RPL may include multiple color filters that display the same color as the pixels of the display panel DP.

[0110] A color filter can filter external light to the same color as the pixel. In this case, the external light may not be visible to the user. However, the inventive concept is not limited to this, and the anti-reflective layer RPL may include a retarder and / or a polarizer for reducing the reflectivity of external light.

[0111] The WIN window can be placed on the anti-reflective layer RPL. The WIN window can protect the display panel DP, input sensor ISP, and anti-reflective layer RPL from external scratches and impacts.

[0112] A panel protective film (PPF) can be placed below the display panel (DP). The panel protective film (PPF) protects the lower part of the display panel (DP). The panel protective film (PPF) can include flexible plastic materials such as polyethylene terephthalate (“PET”).

[0113] The first adhesive layer AL1 can be disposed between the display panel DP and the panel protective film PPF, and the display panel DP and the panel protective film PPF can be connected to each other through the first adhesive layer AL1. The second adhesive layer AL2 can be disposed between the window WIN and the anti-reflective layer RPL, and the window WIN and the anti-reflective layer RPL can be connected to each other through the second adhesive layer AL2.

[0114] Figure 3 The illustrations serve as illustrative examples. Figure 2 The diagram shows a cross-sectional view of the display panel. As one embodiment, Figure 3 The illustration shows a cross-section of the display panel DP as viewed from the second direction DR2.

[0115] Reference Figure 3 The display panel DP may include a substrate SUB, a circuit element layer DP-CL disposed on the substrate SUB, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and a thin film encapsulation layer (also known as an encapsulation layer) TFE disposed on the display element layer DP-OLED.

[0116] The substrate SUB can have a display area DA and a non-display area NDA surrounding the display area DA. The substrate SUB can include glass or a flexible plastic material such as polyimide. The display element layer DP-OLED can be disposed in the display area DA.

[0117] Multiple pixels can be disposed in the circuit element layer DP-CL and the display element layer DP-OLED. Each pixel may include a transistor disposed in the circuit element layer DP-CL and a light-emitting element disposed in the display element layer DP-OLED and connected to the transistor.

[0118] A thin-film encapsulation layer (TFE) can be disposed on the circuit element layer (DP-CL) to cover the display element layer (DP-OLED). The TFE protects the pixels from external moisture, oxygen, and foreign matter. The TFE may include inorganic and organic layers. The organic layer may be disposed between the inorganic layers, encapsulated by the inorganic layers, and provides a flat surface. In embodiments, the organic layer may be disposed on the inorganic layers or omitted, and is not limited to specific embodiments.

[0119] Figure 4A yes Figure 1B The diagram shows the block diagram of the display module.

[0120] Reference Figure 4A The display module DM may include a display panel DP, a timing controller TC, a scan driver SDC, a data driver DDV, a light-emitting driver EDV, and a voltage generator VG.

[0121] The display panel (DP) may include multiple scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm and GBL1 to GBLm, multiple light-emitting lines EML1 to EMLm, multiple data lines DL1 to DLn, and multiple pixels (PX). Here, m and n are natural numbers greater than 0.

[0122] Pixel PX can be electrically connected to scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm and GBL1 to GBLm, light emission lines EML1 to EMLm, and data lines DL1 to DLn. Each pixel PX can be electrically connected to four corresponding scan lines, one corresponding data line, and one corresponding light emission line.

[0123] Scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm may include multiple initialization scan lines GIL1 to GILm, multiple compensation scan lines GCL1 to GCLm, multiple write scan lines GWL1 to GWLm, and multiple bias scan lines GBL1 to GBLm.

[0124] Each pixel PX can be connected to a corresponding initialization scan line GIL1 to GILm, a corresponding compensation scan line GCL1 to GCLm, a corresponding write scan line GWL1 to GWLm, and a corresponding bias scan line GBL1 to GBLm.

[0125] Scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm can be connected to the scan driver SDC, extending in the first direction DR1, and can be arranged in the second direction DR2. Emission lines EML1 to EMLm can be connected to the emission driver EDV, extending in the first direction DR1, and can be arranged in the second direction DR2. Data lines DL1 to DLn can be connected to the data driver DDV, extending in the second direction DR2, and can be arranged in the first direction DR1.

[0126] The scan driver SDC, the light emission driver EDV, and the data driver DDV can be substantially mounted on the display panel DP, although such a configuration is not illustrated in the accompanying drawings.

[0127] The timing controller TC can receive image signals RGB and control signals CTRL. The timing controller TC can generate an image data signal DAS obtained by converting the data format of the image signals RGB to conform to the interface specification with the data driver DDV. The timing controller TC can output a scan control signal SCS, a data control signal DCS, and an illumination control signal ECS in response to the control signal CTRL.

[0128] The voltage generator VG generates the voltages required for the operation of the display panel DP. The voltage generator VG generates a first driving voltage ELVDD, a second driving voltage ELVSS, a first initialization voltage VINT, and a second initialization voltage VAINT. These voltages can be applied to pixels PX.

[0129] The scan driver SDC can receive scan control signals SCS from the timing controller TC. In response to the scan control signals SCS, the scan driver SDC can output scan signals to scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm. The scan signals can be applied to pixels PX through scan lines GIL1 to GILm, GCL1 to GCLm, GWL1 to GWLm, and GBL1 to GBLm.

[0130] The data driver DDV receives data control signals DCS and image data signals DAS from the timing controller TC. The data driver DDV converts the image data signals DAS into data signals and outputs them. The data signals can be defined as analog voltages corresponding to the gray levels of the image data signals DAS. The data signals can be applied to pixels PX via data lines DL1 to DLn.

[0131] The EDV (Emitting Driver) can receive the ECS (Emitting Control Signal) from the timing controller TC. In response to the ECS, the EDV can output an emitting signal to the emitting lines EML1 to EMLm. The emitting signal can then be applied to the pixel PX via the emitting lines EML1 to EMLm.

[0132] A pixel PX can be supplied with a data voltage in response to a scan signal. A pixel PX can display an image by emitting light with a brightness corresponding to the data voltage in response to a light emission signal.

[0133] Figure 4B It is a diagram. Figure 4A The diagram shows the equivalent circuit of one pixel among the pixels shown in the figure.

[0134] As one of the embodiments, Figure 4BThe diagram shows pixel PXij connected to the j-th data line DLj, the i-th scan lines GWLi, GCLi, GILi, and GBLi, and the i-th emission line EMLi. Here, i and j are natural numbers equal to or less than m and n, respectively, and greater than 0.

[0135] Reference Figure 4B A pixel PXij may include a pixel circuit PC and a light-emitting element OLED connected to the pixel circuit PC. The pixel circuit PC can drive the light-emitting element OLED.

[0136] The pixel circuit PC may include multiple transistors T1 to T8 and a capacitor CST. Transistors T1 to T8 and capacitor CST control the amount of current flowing through the light-emitting element OLED. The light-emitting element OLED can generate light with a predetermined brightness according to the amount of current supplied.

[0137] The i-th write scan line GWLi can receive the i-th write scan signal GWi, and the i-th compensation scan line GCLi can receive the i-th compensation scan signal GCI. The i-th initialization scan line GILi can receive the i-th initialization scan signal GIi, and the i-th bias scan line GBLi can receive the i-th bias scan signal GBi. The i-th emission line EMLi can receive the i-th emission signal EMi.

[0138] Pixel PXij can be connected to the j-th data line DLj, the i-th write scan line GWLi, the i-th compensation scan line GCLi, the i-th initialization scan line GILi, the i-th bias scan line GBLi, the i-th emission line EMLi, the first initialization line VIL1, the second initialization line VIL2, the bias line VBL, and the first power line PL1 and the second power line PL2.

[0139] The first initialization line VIL1 can receive the first initialization voltage VINT, and the second initialization line VIL2 can receive the second initialization voltage VAINT. The bias line VBL can receive the bias voltage VBIAS. The first power line PL1 can receive the first drive voltage ELVDD, and the second power line PL2 can receive the second drive voltage ELVSS.

[0140] Transistors T1 through T8 may each include a source electrode, a drain electrode, and a gate electrode. In the following text, in... Figure 4B In this design, for convenience, either the source electrode or the drain electrode is defined as the first electrode, and the remaining one (or the other) is defined as the second electrode. Additionally, the gate electrode is defined as the control electrode.

[0141] Transistors T1 to T8 may include first transistor T1 to eighth transistor T8. First transistor T1, second transistor T2, and fifth transistor T5 to eighth transistor T8 may be P-type metal-oxide-semiconductor (“PMOS”) transistors. Third transistor T3 and fourth transistor T4 may be N-type metal-oxide-semiconductor (“NMOS”) transistors.

[0142] The first transistor T1 can be defined as a driving transistor, and the second transistor T2 can be defined as a switching transistor. The third transistor T3 can be defined as a compensation transistor. The fourth transistor T4 and the seventh transistor T7 can be defined as initialization transistors. The fifth transistor T5 and the sixth transistor T6 can be defined as light-emitting control transistors. The eighth transistor T8 can be defined as a bias transistor.

[0143] The light-emitting element (OLED) can be defined as an organic light-emitting element. The OLED may include a first electrode AE ​​and a second electrode CE. The first electrode AE ​​can receive a first driving voltage ELVDD through a sixth transistor T6, a first transistor T1, and a fifth transistor T5. The first driving voltage ELVDD can be applied to the pixel circuit PC through a first power line PL1.

[0144] The second electrode CE can receive a second driving voltage ELVSS, which has a lower level than the first driving voltage ELVDD. The second driving voltage ELVSS can be applied to the pixel circuit PC via the second power line PL2.

[0145] The first transistor T1 can be disposed between the fifth transistor T5 and the sixth transistor T6, and connected to both the fifth transistor T5 and the sixth transistor T6. The first transistor T1 can be connected to the first power line PL1 through the fifth transistor T5, and can be connected to the first electrode AE ​​through the sixth transistor T6.

[0146] The first transistor T1 may include a first electrode connected to the first power line PL1 via a fifth transistor T5, a second electrode connected to the first electrode AE ​​via a sixth transistor T6, and a control electrode connected to the first node N1.

[0147] The first electrode of the first transistor T1 can be connected to the fifth transistor T5, and the second electrode of the first transistor T1 can be connected to the sixth transistor T6. The first transistor T1 can control the amount of current flowing through the light-emitting element OLED according to the voltage applied to the control electrode of the first transistor T1, the first node N1.

[0148] The second transistor T2 can be disposed between the first transistor T1 and the j-th data line DLj, and connected to the first transistor T1 and the j-th data line DLj. The second transistor T2 may include a first electrode connected to the j-th data line DLj, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th write scan line GWLi.

[0149] The second transistor T2 can be turned on by the i-th write scan signal GWi applied through the i-th write scan line GWLi, and can electrically connect the j-th data line DLj to the first electrode of the first transistor T1. The second transistor T2 can perform a switching operation to provide the data voltage VD (corresponding to the aforementioned data signal) applied through the j-th data line DLj to the first electrode of the first transistor T1.

[0150] The third transistor T3 can be connected to the second electrode of the first transistor T1 and the first node N1. The third transistor T3 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first node N1, and a control electrode connected to the i-th compensation scan line GCLi.

[0151] The third transistor T3 can be turned on by the i-th compensation scan signal GCI applied through the i-th compensation scan line GCLi, and can electrically connect the second electrode of the first transistor T1 and the control electrode of the first transistor T1. When the third transistor T3 is turned on, the first transistor T1 can be connected to a diode via the third transistor T3.

[0152] The fourth transistor T4 can be connected to the first node N1. The fourth transistor T4 may include a first electrode connected to the first node N1, a second electrode connected to the first initialization line VIL1, and a control electrode connected to the i-th initialization scan line GILi. The fourth transistor T4 can be turned on by the i-th initialization scan signal GIi applied through the i-th initialization scan line GILi, and can provide the first initialization voltage VINT applied through the first initialization line VIL1 to the first node N1.

[0153] The fifth transistor T5 may include a first electrode connected to the first power line PL1, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th light-emitting line EMLi.

[0154] The sixth transistor T6 may include a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the first electrode AE, and a control electrode connected to the i-th light-emitting line EMLi.

[0155] The fifth transistor T5 and the sixth transistor T6 can be turned on by the i-th emission signal EMi applied through the i-th emission line EMi. The first driving voltage ELVDD can be provided to the light-emitting element OLED through the turned-on fifth transistor T5 and sixth transistor T6, and the driving current Id can flow through the light-emitting element OLED. Therefore, the light-emitting element OLED can emit light.

[0156] The seventh transistor T7 may include a first electrode connected to the first electrode AE, a second electrode connected to the second initialization line VIL2, and a control electrode connected to the i-th bias scan line GBLi. The seventh transistor T7 may be turned on by the i-th bias scan signal GBi applied through the i-th bias scan line GBLi, and may provide the second initialization voltage VAINT received through the second initialization line VIL2 to the first electrode AE ​​of the light-emitting element OLED.

[0157] In an embodiment of the present invention, the second initialization voltage VAINT may have a different level than the first initialization voltage VINT, but is not limited thereto, and may have the same level as the first initialization voltage VINT.

[0158] The seventh transistor T7 improves the black level performance of pixel PXij. When the seventh transistor T7 is turned on, the parasitic capacitor (not shown) of the OLED light-emitting element can be discharged. Therefore, when achieving black brightness, the OLED light-emitting element will not emit light due to the leakage current of the first transistor T1, and thus the black level performance can be improved.

[0159] The capacitor CST may include a first electrode connected to the first power line PL1 and a second electrode connected to the first node N1. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 can be determined based on the voltage stored in the capacitor CST.

[0160] The eighth transistor T8 may include a first electrode connected to the bias line VBL, a second electrode connected to the first electrode of the first transistor T1, and a control electrode connected to the i-th bias scan line GBLi.

[0161] The eighth transistor T8 can be turned on by the i-th bias scan signal GBi applied through the i-th bias scan line GBLi, and can provide the bias voltage VBIAS applied through the bias line VBL to the first electrode of the first transistor T1. However, the transistors included in the pixel PXij are not limited to this.

[0162] Figure 5A This is a plan view of an embodiment of a pixel unit according to the present invention. Figure 5B This is a plan view of an embodiment of a pixel unit according to the present invention.

[0163] Reference Figure 5A In the illustrated embodiment, a pixel unit PXU may include a reference Figure 4A and Figure 4B The described pixel. Multiple pixel units (PXUs) can be provided, such that multiple pixel units (PXUs) can be referenced. Figure 1A The display area DA is arranged along the first diagonal direction CDR1 and the second diagonal direction CDR2.

[0164] The pixel unit PXU in this embodiment may include pixels 1-1 to 3, PX-G1, PX-G2, PX-R, and PX-B. Pixel 1-1, PX-G1, can provide green light. The light generated in pixel 1-1, PX-G1, can be provided to the display area DA (see reference 1-1) through the first emitting area PXA-G1. Figure 1A In the illustrated embodiment, the first-1 light-emitting region PXA-G1 can have a rhomboid shape.

[0165] Pixels 1-2 (PX-G2) can provide green light just like pixel 1-1 (PX-G1). The light generated in pixels 1-2 (PX-G2) can be provided to the display area DA (see reference 1-2) through the first and second emitting areas (PXA-G2). Figure 1A The first-second light-emitting region PXA-G2 can be spaced apart from the first-first light-emitting region PXA-G1 along the first direction DR1. In the illustrated embodiment, the first-second light-emitting region PXA-G2 can have a rhomboid shape.

[0166] The second pixel, PX-R, can provide red light. The light generated in the second pixel, PX-R, can be provided to the display area, DA, through the second emitting area, PXA-R (see reference). Figure 1A The second light-emitting region PXA-R can be spaced apart from the third light-emitting region PXA-B along the second direction DR2. The second light-emitting region PXA-R can be spaced apart from the first-1 light-emitting region PXA-G1 along the first oblique direction CDR1, and can be spaced apart from the first-2 light-emitting region PXA-G2 along the second oblique direction CDR2. In the illustrated embodiment, the second light-emitting region PXA-R can have a rhomboid shape.

[0167] The third pixel PX-B can provide blue light. The light generated in the third pixel PX-B can be provided to the display area DA through the third emitting area PXA-B (see reference). Figure 1A The third light-emitting region PXA-B can be spaced apart from the first-second light-emitting region PXA-G2 along the first oblique direction CDR1, and can be spaced apart from the first-first light-emitting region PXA-G1 along the second oblique direction CDR2. In the illustrated embodiment, the third light-emitting region PXA-B can have a rhomboid shape.

[0168] In an embodiment, the area of ​​the second light-emitting region PXA-R can be larger than the areas of the first-1 light-emitting regions PXA-G1 and the first-2 light-emitting regions PXA-G2, and smaller than the area of ​​the third light-emitting region PXA-B.

[0169] The area between the first luminescent region and the third luminescent regions PXA-G1, PXA-G2, PXA-R and PXA-B can be defined as the non-luminescent region NPXA.

[0170] A pixel-defined pattern (PDL) can be disposed within a non-emitting area (NPXA). The first to third emitting areas (PXA-G1, PXA-G2, PXA-R, and PXA-B) can correspond to openings defined in the pixel-defined pattern (PDL). Each pixel-defined pattern (PDL) can surround a corresponding emitting element. Each pixel-defined pattern (PDL) can have a closed-line shape. In embodiments, the widths of the pixel-defined patterns (PDLs) surrounding emitting elements providing different colors of light can be different from each other. However, the inventive concept is not limited to this, and the widths of the pixel-defined patterns (PDLs) can be the same.

[0171] According to the present invention, a partition wall WL can be disposed between pixel-defined patterns PDL. A partition wall opening W-OP overlapping the first to third light-emitting regions PXA-G1, PXA-G2, PXA-R, and PXA-B can be defined within the partition wall WL. In the illustrated embodiment, each of the partition wall openings W-OP can have a rhomboid shape. The partition wall WL can include multiple conductive layers. Since the multiple conductive layers each have a different width, the multiple conductive layers can have an undercut shape in a cross-sectional view. This will be described later.

[0172] Figure 5A The second electrode CE of the light-emitting element included in each of pixels PX-G1, PX-G2, PX-R, and PX-B is illustrated in dashed lines. The second electrode CE, included in the light-emitting element, is distributed across the light-emitting region PXA and the non-light-emitting region NPXA, but the second electrode CE can be disconnected by an undercut partition wall WL. However, since the partition wall WL comprises multiple conductive layers, the second electrode CE disconnected by the partition wall WL can contact any one of the conductive layers included in the partition wall WL, and the second electrodes CE can be connected to each other through any one of these conductive layers. Accordingly, the second electrodes CE can receive the same voltage. This will be described later.

[0173] According to the present invention, the non-light-emitting area NPXA may include a pattern area PA, a recessed area HA, and a partition wall area NA disposed between the recessed areas HA. The pattern area PA may be defined as an area in which a pixel-defined pattern PDL is disposed. The partition wall area NA may be defined as an area in which a partition wall WL is disposed. The recessed area HA may be defined as the area between the pixel-defined pattern PDL and the partition wall WL. In a cross-sectional view, the two recessed areas HA may be close to each other (adjacent) and a partition wall area NA may be located between them.

[0174] Reference Figure 5B In the illustrated embodiment, a pixel unit PXU-a may include a reference Figure 4A and Figure 4B The described pixel. Multiple pixel units PXU-a can be provided, such that multiple pixel units PXU-a can be referenced. Figure 1A The display area DA is set along the first direction DR1 and the second direction DR2.

[0175] The pixel unit PXU-a in the embodiment may include first pixels to third pixels PX-R, PX-B, and PX-G. The first pixel PX-R can provide red light. The light generated in the first pixel PX-R can be provided to the display area DA (see reference) through the first light-emitting area PXA-R. Figure 1A In the illustrated embodiment, the first light-emitting area PXA-R can have a rounded quadrilateral shape.

[0176] The second pixel, PX-B, can provide blue light. The light generated in the second pixel, PX-B, can be provided to the display area, DA, through the second light-emitting area, PXA-B (see reference). Figure 1A The second luminescent region PXA-B may be spaced apart from the first luminescent region PXA-R along the first direction DR1. When viewed in the first direction DR1, the second luminescent region PXA-B may overlap with the first luminescent region PXA-R and the third luminescent region PXA-G. The second luminescent region PXA-B may have a rounded quadrilateral shape extending along the second direction DR2.

[0177] The third pixel, PX-G, can provide green light. The light generated in the third pixel, PX-G, can be provided to the display area, DA, through the third emitting area, PXA-G (see reference). Figure 1A The third luminescent region PXA-G can be spaced apart from the first luminescent region PXA-R along the second direction DR2. The third luminescent region PXA-G can have a rounded quadrilateral shape.

[0178] In an embodiment, the area of ​​the first light-emitting region PXA-R can be larger than the area of ​​the third light-emitting region PXA-G, and smaller than the area of ​​the second light-emitting region PXA-B.

[0179] The area between the first luminescent region and the third luminescent regions PXA-R, PXA-B, and PXA-G can be defined as the non-luminescent region NPXA.

[0180] A pixel-defined pattern (PDL) can be set in the non-emitting area NPXA. The first to third emitting areas PXA-R, PXA-B, and PXA-G can correspond to the openings defined in the pixel-defined pattern (PDL). Each pixel-defined pattern (PDL) can surround its corresponding emitting element. Each pixel-defined pattern (PDL) can have a closed-line shape.

[0181] According to the present invention, a partition wall WL can be disposed between pixel-defined patterns PDL. A partition wall opening W-OP overlapping the first to third light-emitting regions PXA-R, PXA-B, and PXA-G can be defined within the partition wall WL. In the illustrated embodiment, each partition wall opening W-OP can have a quadrilateral shape. The partition wall WL can include multiple conductive layers. Since the multiple conductive layers each have different widths, they can have an undercut shape in a cross-sectional view. This will be described later.

[0182] Figure 5B The second electrode CE is illustrated in dashed lines in the light-emitting element included in each of the first to third pixels PX-R, PX-B, and PX-G. The second electrode CE is distributed throughout the light-emitting area PXA and the non-light-emitting area NPXA, but it can be disconnected by an undercut partition wall WL. However, since the partition wall WL comprises multiple conductive layers, the second electrode CE disconnected by the partition wall WL can contact any of the conductive layers included in the partition wall WL, and the second electrodes CE can be connected to each other through these conductive layers. Accordingly, the second electrodes CE can receive the same voltage. This will be described later.

[0183] According to the present invention, the non-light-emitting area NPXA may include a pattern area PA, a recessed area HA, and a partition wall area NA disposed between the recessed areas HA. The pattern area PA may be defined as an area in which a pixel-defined pattern PDL is disposed. The partition wall area NA may be defined as an area in which a partition wall WL is disposed. The recessed area HA may be defined as the area between the pixel-defined pattern PDL and the partition wall WL.

[0184] Figure 6 It is along Figure 5A The cross-sectional view taken from line I-I'. Figure 7 It is along Figure 5A The cross-sectional view taken from line II-II'.

[0185] Figure 6 Illustration Figure 5A A cross-sectional view of pixel 1-1, PX-G1. (Refer to...) Figure 6 The light-emitting element OLED-G1 in the embodiment may include a first electrode AE-G1, a second electrode CE, and a first common layer CL-G1. The first common layer CL-G1 may include a hole control layer, an electron control layer, and an emission layer, etc.

[0186] The second electrode CE can be disposed on the first electrode AE-G1, and the first common layer CL-G1 can be disposed between the first electrode AE-G1 and the second electrode CE. The light-emitting element OLED-G1 in the embodiment may further include a protective layer disposed on the second electrode CE. The protective layer may include an organic material and prevent components disposed beneath the protective layer from being damaged in subsequent processes. In the embodiment, the protective layer may be omitted.

[0187] The first transistor T1, the fourth transistor T4, the sixth transistor T6, and the light-emitting element OLED-G1 can be disposed on the substrate SUB. Display area DA (see reference) Figure 1A ) can include pixels PXij (refer to Figure 4B The corresponding luminescent region PXA-G1 and the non-luminescent region NPXA that is close to (adjacent to) the luminescent region PXA-G1.

[0188] The substrate SUB may include glass or a flexible plastic material such as polyimide. The circuit element layer DP-CL, the display element layer DP-OLED, and the thin-film encapsulation layer TFE may be disposed on the substrate SUB. The circuit element layer DP-CL may include an insulating layer and conductive patterns. The display element layer DP-OLED may include a light-emitting element OLED-G1 and a pixel-defining pattern PDL.

[0189] A barrier layer (BRL) can be disposed on a substrate (SUB). The barrier layer (BRL) prevents foreign objects from entering from the outside. The barrier layer (BRL) may include inorganic materials.

[0190] A metal layer BML can be disposed on a barrier layer BRL. The metal layer BML can overlap with a first transistor T1. In an embodiment, the metal layer BML can receive a constant voltage. When a constant voltage is applied to the metal layer BML, the value of the threshold voltage (Vth) of the first transistor T1 disposed on the metal layer BML can be maintained without being changed.

[0191] The metal layer BML can block light incident on the first transistor T1 from below the metal layer BML. The metal layer BML may include reflective metal. In an embodiment, the metal layer BML may be omitted.

[0192] A buffer layer (BFL) can be disposed on a barrier layer (BRL) and covered by a metal layer (BML). The buffer layer (BFL) can increase the adhesion between the semiconductor pattern included in the transistor and the substrate (SUB). The buffer layer (BFL) can include inorganic materials.

[0193] The semiconductor layers S1, A1, and Dr1 of the first transistor T1 and the semiconductor layers S6, A6, and Dr6 of the sixth transistor T6 can be disposed on the buffer layer BFL. The semiconductor layers S1, A1, Dr1, S6, A6, and Dr6 can comprise polycrystalline silicon. However, the inventive concept is not limited thereto, and the semiconductor layers S1, A1, Dr1, S6, A6, and Dr6 can comprise amorphous silicon.

[0194] Semiconductor layers S1, A1, Dr1, S6, A6, and Dr6 may be doped with N-type or P-type dopants. Semiconductor layers S1, A1, Dr1, S6, A6, and Dr6 may include heavily doped and lightly doped regions. Heavily doped regions may have higher conductivity than lightly doped regions and may substantially function as the source and drain of the first transistor T1 or the sixth transistor T6. Lightly doped regions may substantially correspond to the active region (or channel) of the first transistor T1 or the sixth transistor T6.

[0195] The first source region S1, the first channel region A1, and the first drain region Dr1 of the first transistor T1 can be formed by semiconductor layers S1, A1, and Dr1. The sixth source region S6, the sixth channel region A6, and the sixth drain region Dr6 of the sixth transistor T6 can be formed by semiconductor layers S6, A6, and Dr6. The first channel region A1 can be disposed between the first source region S1 and the first drain region Dr1. The sixth channel region A6 can be disposed between the sixth source region S6 and the sixth drain region Dr6.

[0196] The first insulating layer INS1 can be disposed on the buffer layer BFL to cover the semiconductor layers S1, A1, Dr1, S6, A6, and Dr6. The first gate electrode G1 (or control electrode) of the first transistor T1 and the sixth gate electrode G6 (or control electrode) of the sixth transistor T6 can be disposed on the first insulating layer INS1. In the plan view, the first gate electrode G1 can overlap with the first channel region A1, and the sixth gate electrode G6 can overlap with the sixth channel region A6.

[0197] Although not illustrated, the source, channel, drain, and gate electrode structures of each of the second transistor T2, the fifth transistor T5, and the seventh transistor T7 can be substantially the same as those of the first transistor T1 and the sixth transistor T6.

[0198] A second insulating layer INS2 can be disposed on the first insulating layer INS1 to cover the first gate electrode G1 and the sixth gate electrode G6. A dummy electrode DME can be disposed on the second insulating layer INS2. The dummy electrode DME can be disposed on the first gate electrode G1 and overlaps with the first gate electrode G1 in a plan view. The dummy electrode DME, together with the first gate electrode G1, can form the aforementioned capacitor CST (see reference). Figure 4B ).

[0199] The third insulating layer INS3 can be disposed on the second insulating layer INS2 to cover the dummy electrode DME. The semiconductor layers S4, A4, and Dr4 of the fourth transistor T4 can be disposed on the third insulating layer INS3. The semiconductor layers S4, A4, and Dr4 can include oxide semiconductors comprising metal oxides or composed of metal oxides. The oxide semiconductor can include crystalline or amorphous oxide semiconductors.

[0200] Semiconductor layers S4, A4, and Dr4 may include multiple regions divided according to whether the metal oxide is reduced. Regions where the metal oxide is reduced (hereinafter, reduced regions) may have higher conductivity than regions where the metal oxide is not reduced (hereinafter, non-reduced regions). Reduced regions may substantially act as the source or drain electrode of the fourth transistor T4. Non-reduced regions may substantially correspond to the active region (or channel) of the fourth transistor T4.

[0201] The fourth source region S4, the fourth channel region A4, and the fourth drain region Dr4 of the fourth transistor T4 can be formed by semiconductor layers S4, A4, and Dr4. The fourth channel region A4 can be disposed between the fourth source region S4 and the fourth drain region Dr4.

[0202] A fourth insulating layer INS4 can be disposed on the third insulating layer INS3 to cover semiconductor layers S4, A4, and Dr4. The fourth gate electrode G4 of the fourth transistor T4 can be disposed on the fourth insulating layer INS4. In a planar view, the fourth gate electrode G4 can overlap with the fourth channel region A4.

[0203] The fifth insulating layer INS5 can be disposed on the fourth insulating layer INS4 to cover the fourth gate electrode G4. Although not shown, the structure of the source region, channel region, drain region and gate electrode of the third transistor T3 can be substantially the same as the structure of the source region, channel region, drain region and gate electrode of the fourth transistor T4.

[0204] The barrier layer BRL, buffer layer BFL, and first insulating layers INS1 to fifth insulating layers INS5 may comprise inorganic materials. As one embodiment, the barrier layer BRL, buffer layer BFL, and first insulating layers INS1 to fifth insulating layers INS5 may comprise any one of silicon oxide and silicon nitride, or may comprise multiple inorganic layers, and the inventive concept is not limited thereto. The multiple inorganic layers may have a structure in which layers comprising silicon nitride and silicon oxide are alternately stacked.

[0205] The connecting electrode CNE can be disposed between the sixth transistor T6 and the light-emitting element OLED-G1. The connecting electrode CNE can electrically connect the sixth transistor T6 and the light-emitting element OLED-G1. The connecting electrode CNE can include a first connecting electrode CNE1 and a second connecting electrode CNE2 disposed on the first connecting electrode CNE1.

[0206] The first connecting electrode CNE1 may be disposed on the fifth insulating layer INS5 and connected to the sixth drain region Dr6 through a first contact hole CH1 defined in the first insulating layer INS1 to the fifth insulating layer INS5. The sixth insulating layer INS6 (also referred to as the "interlayer insulating layer") may be disposed on the fifth insulating layer INS5 to cover the first connecting electrode CNE1.

[0207] The second connecting electrode CNE2 can be disposed on the sixth insulating layer INS6. The second connecting electrode CNE2 can be connected to the first connecting electrode CNE1 through the second contact hole CH2 defined in the sixth insulating layer INS6.

[0208] Despite Figure 6 It is not shown in the figure, but the second power line PL2 can be set on the sixth insulation layer INS6 and covered by the seventh insulation layer INS7 (also known as the "intermediate insulation layer").

[0209] The seventh insulating layer INS7 can be disposed on the sixth insulating layer INS6 to cover the second connecting electrode CNE2. The sixth insulating layer INS6 and the seventh insulating layer INS7 can comprise any of organic and inorganic materials.

[0210] A pixel-defined pattern (PDL) can be disposed on a seventh insulating layer (INS7). A first electrode AE-G1 can be disposed on the seventh insulating layer (INS7). An opening PDL-OP exposing at least a portion of the first electrode AE-G1 can be defined in each of the pixel-defined patterns (PDL). The opening PDL-OP can correspond to the aforementioned light-emitting area. In the illustrated embodiment, the pixel-defined pattern (PDL) can include an organic material. Furthermore, the pixel-defined pattern (PDL) can have a predetermined color and is not limited to a specific embodiment. The first electrode AE-G1 can be connected to the second connecting electrode CNE2 through a third contact hole CH3 defined in the seventh insulating layer (INS7).

[0211] The first common layer CL-G1 and the second electrode CE included in the light-emitting element OLED-G1 can be disposed on the pixel-defined pattern PDL.

[0212] The thin-film encapsulation layer TFE can be disposed on and cover the light-emitting element OLED-G1. The thin-film encapsulation layer TFE can be disposed throughout the entire display area DA. The thin-film encapsulation layer TFE may include an inorganic film and an organic film disposed between the inorganic films, and is not limited to a specific embodiment.

[0213] Figures 7 to 11 The figure shows a cross-sectional view between two adjacent light-emitting elements OLED-G1 and OLED-R. A first electrode AE-G1 may be included in the first light-emitting element OLED-G1, and a first electrode AE-R may be included in the second light-emitting element OLED-R.

[0214] exist Figure 7 References not shown in the image. Figure 6 The components described extend from the substrate SUB up to the fifth insulating layer INS5.

[0215] The display panel DP may include luminescent areas PXA-G1 and PXA-R and a non-luminescent area NPXA. The non-luminescent area NPXA may include a pattern area PA, a recessed area HA, and a partition wall area NA. The partition wall area NA may be located between the recessed areas HA.

[0216] A pixel-defined pattern (PDL) is set in each of the pattern areas (PA). A recessed area (HA) can be defined as the area between the pixel-defined pattern (PDL) and the partition wall (WL), and a partition wall area (NA) can be defined as the area in which the partition wall (WL) is set.

[0217] The pixel-defined pattern (PDL) can be set on the seventh insulating layer (INS7, also known as the "intermediate insulating layer"). The sixth insulating layer (INS6, also known as the "interlayer insulating layer") can be set below the seventh insulating layer (INS7).

[0218] According to the present invention, a partition wall WL can be disposed between pixel-defined patterns PDL that are close to each other (adjacent). The partition wall WL may comprise a first to a third layer W1, W2, and W3, each comprising a conductive material. The first layer W1 may contact a seventh insulating layer INS7. A second layer W2 may be disposed on the first layer W1, and a third layer W3 may be disposed on the second layer W2.

[0219] In the illustrated embodiment, the first layer W1 and the third layer W3 may include titanium, and the second layer W2 may include aluminum.

[0220] In the cross-sectional view, the width of the first layer W1 and the width of the third layer W3 can each be greater than the width of the second layer W2. Therefore, a portion of each of the first layer W1 and the third layer W3 can protrude from the second layer W2 to have an undercut structure. Due to the difference in etching rates relative to the etchant between the first layer W1 and the third layer W3 and the second layer W2, an undercut shape of the partition wall WL can be formed. The thickness of each of the first layer W1 and the third layer W3 can be less than the thickness of the second layer W2.

[0221] According to the present invention, the second layer W2 may comprise aluminum, and therefore the side surface W2-S of the second layer W2 may be oxidized and may not be conductive.

[0222] According to the present invention, a groove GR can be defined in a seventh insulating layer INS7 that overlaps with a recessed region HA. The groove GR can be defined by recessing or removing at least a portion of the seventh insulating layer INS7 in a direction from the upper surface to the lower surface. The groove GR can surround a corresponding pixel defining pattern PDL. The groove GR can be surrounded by a partition wall WL. Therefore, the groove GR can be formed between the pixel defining pattern PDL and the partition wall WL. In the illustrated embodiment, the groove GR can have a concave shape.

[0223] In the illustrated embodiment, a portion of the lower surface W1-B of the first layer W1 (hereinafter, "this portion") can be exposed from the seventh insulating layer INS7 by the recess GR. The common layer CL-G1 or CL-R and the second electrode CE included in each of the first-1 light-emitting elements OLED-G1 and OLED-R can extend from the light-emitting region PXA-G1 or PXA-R to the non-light-emitting region NPXA (specifically, the recessed region HA) and can contact a portion of the partition wall WL.

[0224] The common layers CL-G1 and CL-R, as well as the second electrode CE, can be disposed on the pixel-defined pattern PDL in the pattern area PA, and the common layers CL-G1 and CL-R, as well as the second electrode CE, can be disposed in the groove GR in the recess area HA.

[0225] In the illustrated embodiment, the ends of each of the common layers CL-G1 and CL-R disposed in the groove GR can contact that portion of the lower surface W1-B of the first layer W1. The common layers CL-G1 and CL-R can be spaced apart from the side surfaces W1-S and upper surfaces W1-U of the first layer W1 disposed at the lowest portion of the partition wall WL.

[0226] In the illustrated embodiment, the end of the second electrode CE can contact the side surface W1-S of the first layer W1. Contrary to the inventive concept, in the case where the common layers CL-G1 and CL-R cover the first layer W1 and the second electrode CE contacts the second layer W2, the side surface W2-S of the second layer W2 is oxidized and non-conductive, and therefore the second electrodes CE, disconnected by the partition wall WL, may not be able to connect to each other through the partition wall WL.

[0227] In the illustrated embodiment, the second electrode CE, which is physically disconnected due to the formation of the undercut of the partition wall WL, can be easily connected by forming a groove GR in the recessed region HA and by using the shape of the groove GR to make the second electrode CE contact the side surface W1-S of the first layer W1.

[0228] In the illustrated embodiment, a dummy pattern DMP may be further included on the partition wall WL. The dummy pattern DMP may include a first dummy pattern D1 disposed on the third layer W3 and a second dummy pattern D2 disposed on the first dummy pattern D1. The first dummy pattern D1 may include the same material as the common layers CL-G1 and CL-R, and the second dummy pattern D2 may include the same material as the second electrode CE.

[0229] In the process of forming a common layer CL-G1 and CL-R and a second electrode CE in the light-emitting areas PXA-G1 and PXA-R and the non-light-emitting area NPXA, the first dummy pattern D1 and the second dummy pattern D2 can be formed by the disconnection of the common layer CL-G1 and CL-R and the second electrode CE due to the partition wall WL.

[0230] According to the concept of the present invention, in the display area DA (refer to...) Figure 1A In this configuration, the second electrode CE can contact the side surface W1-S of the first layer W1 via the groove GR, and can prevent the second electrode CE from contacting the oxidized side surface W2-S of the second layer W2. Accordingly, voltage drop can be prevented by connecting the second electrode CE, which is easily disconnected by the partition wall WL, and a constant voltage can be provided to the pixel.

[0231] Figure 8 This is a cross-sectional view of an embodiment of a display panel according to the present invention. Figure 9This is a cross-sectional view of an embodiment of a display panel according to the present invention. Figure 10 This is a cross-sectional view of an embodiment of a display panel according to the present invention. Figure 11 This is a cross-sectional view of an embodiment of a display panel according to the present invention.

[0232] Figures 8 to 11 It is relative to Figure 7 An embodiment of a display panel in the same area as the display panel. Figures 8 to 11 References not shown in the image. Figure 6 The components described extend from the substrate SUB to the fifth insulating layer INS5. (With) Figure 7 Components that are identical or similar to those in the figures will be represented by the same or similar reference numerals or symbols, and no duplicate descriptions will be provided.

[0233] Reference Figure 8 The display panel DP-1 in the embodiment may include a pixel-defined pattern PDL disposed in the pattern area PA and a partition wall WL disposed in the partition wall area NA.

[0234] A separator wall (WL) can be disposed between pixel-defined patterns (PDLs) that are close to each other. The separator wall (WL) can comprise first to third layers (W1, W2, and W3) each comprising conductive material. The first layer (W1) can contact the seventh insulating layer (INS7). The second layer (W2) can be disposed on the first layer (W1), and the third layer (W3) can be disposed on the second layer (W2). A dummy pattern (DMP) can be disposed on the separator wall (WL).

[0235] According to the present invention, a groove GR-1 can be defined in a seventh insulating layer INS7 that overlaps with a recessed region HA. The groove GR-1 can be defined by recessing or removing at least a portion of the seventh insulating layer INS7 in a direction from the upper surface to the lower surface. The groove GR-1 can surround a corresponding pixel defining pattern PDL. The groove GR-1 can be surrounded by a partition wall WL. Therefore, the groove GR-1 can be formed between the pixel defining pattern PDL and the partition wall WL. In the illustrated embodiment, the groove GR-1 can have a concave shape.

[0236] In the illustrated embodiment, a portion of the lower surface W1-B of the first layer W1 (hereinafter, "this portion") can be exposed from the seventh insulating layer INS7 by the recess GR-1. The common layer CL-G1 or CL-R and the second electrode CE included in each of the first-1 light-emitting element OLED-G1 and the second light-emitting element OLED-R can extend from the light-emitting region PXA-G1 or PXA-R to the non-light-emitting region NPXA (specifically, the recessed region HA) and can contact a portion of the partition wall WL.

[0237] The common layers CL-G1 and CL-R, as well as the second electrode CE, can be disposed on the pixel-defined pattern PDL in the pattern area PA, and the common layers CL-G1 and CL-R, as well as the second electrode CE, can be disposed in the groove GR-1 in the recessed area HA.

[0238] In the illustrated embodiment, the end of each of the common layers CL-G1 and CL-R disposed in the groove GR-1 can contact that portion of the lower surface W1-B of the first layer W1. The common layers CL-G1 and CL-R can be spaced apart from the side surfaces W1-S and upper surfaces W1-U of the first layer W1 disposed at the lowest portion of the partition wall WL.

[0239] In the illustrated embodiment, the end of the second electrode CE can contact a portion of the lower surface W1-B of the first layer W1. That is, the ends of each of the common layers CL-G1 and CL-R and the second electrode CE can contact the lower surface W1-B of the first layer W1.

[0240] In the illustrated embodiment, the second electrode CE, which is physically disconnected due to the formation of the undercut of the partition wall WL, can be easily connected by forming a groove GR-1 in the recessed region HA and by using the shape of the groove GR-1 to make the second electrode CE contact the lower surface W1-B of the first layer W1.

[0241] Reference Figure 9 The display panel DP-2 in the embodiment may include a pixel-defined pattern PDL disposed in the pattern area PA and a partition wall WL disposed in the partition wall area NA.

[0242] A separator wall (WL) can be disposed between pixel-defined patterns (PDLs) that are close to each other. The separator wall (WL) can comprise first to third layers (W1, W2, and W3) each comprising conductive material. The first layer (W1) can contact the seventh insulating layer (INS7). The second layer (W2) can be disposed on the first layer (W1), and the third layer (W3) can be disposed on the second layer (W2). A dummy pattern (DMP) can be disposed on the separator wall (WL).

[0243] According to the present invention, the groove GR-2 can be defined in a seventh insulating layer INS7 that overlaps with the recessed region HA. The groove GR-2 can be defined by recessing or removing at least a portion of the seventh insulating layer INS7 in a direction from the upper surface to the lower surface. The groove GR-2 can surround a corresponding pixel defining pattern PDL. The groove GR-2 can be surrounded by a partition wall WL. Therefore, the groove GR-2 can be formed between the pixel defining pattern PDL and the partition wall WL. In the illustrated embodiment, the groove GR-2 can have a concave shape.

[0244] In the illustrated embodiment, a portion of the lower surface W1-B of the first layer W1 (hereinafter, "this portion") can be exposed from the seventh insulating layer INS7 by the recess GR-2. The common layer CL-G1 or CL-R and the second electrode CE included in each of the first-1 light-emitting element OLED-G1 and the second light-emitting element OLED-R can extend from the light-emitting region PXA-G1 or PXA-R to the non-light-emitting region NPXA (specifically, the recessed region HA) and can contact a portion of the partition wall WL.

[0245] The common layers CL-G1 and CL-R and the second electrode CE can be disposed on the pixel-defined pattern PDL in the pattern area PA, and the common layers CL-G1 and CL-R and the second electrode CE can be disposed in the groove GR-2 in the recessed area HA.

[0246] In the illustrated embodiment, the ends of each of the common layers CL-G1 and CL-R disposed in the groove GR-2 can contact a portion of the lower surface W1-B of the first layer W1. The common layers CL-G1 and CL-R can be spaced apart from the side surfaces W1-S and upper surfaces W1-U of the first layer W1 disposed at the lowest portion of the partition wall WL.

[0247] In the illustrated embodiment, the second electrode CE can contact the side surface W1-S and the top surface W1-U of the first layer W1. In the embodiment, the second electrode CE can expose a portion of the upper surface W1-U of the first layer W1 that is exposed by the second layer W2, or it can completely cover the portion of the upper surface W1-U of the first layer W1 that is exposed by the second layer W2 and contact a portion of the side surface W2-S of the second layer W2, and is not limited to the specific embodiment.

[0248] In the illustrated embodiment, the second electrode CE, which is physically disconnected due to the formation of the undercut of the partition wall WL, can be easily connected by forming a groove GR-2 in the recessed region HA and by using the shape of the groove GR-2 to make the second electrode CE contact the side surface W1-S and the top surface W1-U of the first layer W1.

[0249] Reference Figure 10 The display panel DP-3 in the embodiment may include a pixel-defined pattern PDL disposed in the pattern area PA and a partition wall WL disposed in the partition wall area NA.

[0250] A separator wall (WL) can be disposed between pixel-defined patterns (PDLs) that are close to each other. The separator wall (WL) can comprise first to third layers (W1, W2, and W3) each comprising conductive material. The first layer (W1) can contact the seventh insulating layer (INS7). The second layer (W2) can be disposed on the first layer (W1), and the third layer (W3) can be disposed on the second layer (W2). A dummy pattern (DMP) can be disposed on the separator wall (WL).

[0251] According to the present invention, the groove GR-3 can be defined within the seventh insulating layer INS7, which overlaps with the recessed region HA. The groove GR-3 can be defined by penetrating the seventh insulating layer INS7 from its upper surface to its lower surface. In the illustrated embodiment, the groove GR-3 can expose a portion of the upper surface I6-U of the sixth insulating layer INS6. The groove GR-3 can be defined from the side surface I7-S of the seventh insulating layer INS7.

[0252] In the illustrated embodiment, a portion of the lower surface W1-B of the first layer W1 (hereinafter, "this portion") can be exposed from the seventh insulating layer INS7 by the recess GR-3. The common layer CL-G1 or CL-R and the second electrode CE included in each of the first-1 light-emitting element OLED-G1 and the second light-emitting element OLED-R can extend from the light-emitting region PXA-G1 or PXA-R to the non-light-emitting region NPXA (specifically, the recessed region HA) and can contact a portion of the partition wall WL.

[0253] The common layers CL-G1 and CL-R, as well as the second electrode CE, can be disposed on the pixel-defined pattern PDL in the pattern area PA, and the common layers CL-G1 and CL-R, as well as the second electrode CE, can be disposed in the groove GR-3 in the recessed area HA.

[0254] In the illustrated embodiment, the end of each of the common layers CL-G1 and CL-R disposed in the groove GR-3 can contact a portion of the lower surface W1-B of the first layer W1. The common layers CL-G1 and CL-R can be spaced apart from the side surfaces W1-S and upper surfaces W1-U of the first layer W1 disposed at the lowest portion of the partition wall WL. Each of the common layers CL-G1 and CL-R can contact a portion of the side surface I7-S of the groove GR-3 defining the seventh insulating layer INS7 and the upper surface I6-U of the sixth insulating layer INS6.

[0255] In the illustrated embodiment, the end of the second electrode CE can contact the side surfaces W1-S of the first layer W1. In the embodiment, the second electrode CE can contact at least a portion of the upper surface W1-U of the first layer W1 exposed by the second layer W2, or it can completely cover the upper surface W1-U of the first layer W1 exposed by the second layer W2 and contact a portion of the side surfaces W2-S of the second layer W2, and is not limited to a particular embodiment.

[0256] In the illustrated embodiment, the second electrode CE, which is physically disconnected due to the formation of the undercut of the partition wall WL, can be easily connected by forming a groove GR-3 in the recessed region HA and by using the shape of the groove GR-3 to make the second electrode CE contact the side surface W1-S of the first layer W1.

[0257] The main focus will be on Figure 7 To describe the differences Figure 11 . Reference Figure 11 The display panel DP-4 in this embodiment may include a partition wall WL-4 disposed in the partition wall region NA of the non-light-emitting region NPXA. The partition wall WL-4 may surround the pixel-defining pattern PDL. The recessed region HA may be defined between the pixel-defining pattern PDL and the partition wall WL-4.

[0258] The partition wall WL-4 may comprise first to fourth layers W1, W2, W3, and W4, each comprising a conductive material. The first layer W1 may contact the seventh insulating layer INS7. A second layer W2 may be disposed on the first layer W1, a third layer W3 may be disposed on the second layer W2, and a fourth layer W4 may be disposed on the third layer W3. A dummy pattern DMP may be disposed on the partition wall WL-4.

[0259] In the illustrated embodiment, the first layer W1 and the third layer W3 may comprise the same material, and the second layer W2 and the fourth layer W4 may comprise the same material as each other. In this embodiment, for example, the first layer W1 and the third layer W3 may comprise either titanium or a molybdenum-titanium alloy. The second layer W2 and the fourth layer W4 may comprise either aluminum or copper.

[0260] In the cross-sectional view, the width of the first layer W1 and the width of the third layer W3 can each be greater than the width of the second layer W2 and the width of the fourth layer W4. Therefore, a portion of the first layer W1 and the third layer W3 can protrude from the second layer W2 to have an undercut structure. Due to the difference in etch rates relative to the etchant between the first layer W1 and the third layer W3 and the second layer W2 and the fourth layer W4, an undercut shape of the partition wall WL-4 can be formed. The thickness of the first layer W1 and the thickness of the third layer W3 can each be less than the thickness of the second layer W2 and the fourth layer W4. In an embodiment, the side surface W2-S of the second layer W2 can be oxidized and can be non-conductive.

[0261] In the illustrated embodiment, the second electrode CE can contact the side surfaces W1-S of the first layer W1. In the embodiment, the second electrode CE can expose a portion of the upper surface W1-U of the first layer W1 that is exposed by the second layer W2, or it can completely cover the portion of the upper surface W1-U of the first layer W1 that is exposed by the second layer W2 and contact a portion of the side surfaces W2-S of the second layer W2, and is not limited to the specific embodiment.

[0262] According to the present invention, in the display area, through the groove, the electrode included in the light-emitting element can contact the side surface of the lower layer included in the partition wall, and the electrode included in the light-emitting element can be prevented from contacting the oxidized side surface of the intermediate layer. Accordingly, voltage drop can be prevented by connecting a second electrode that is easily disconnected from the partition wall, and a constant voltage can be provided to the pixel.

[0263] The embodiments of the present invention have been described above with reference to the present invention concept. However, it will be understood by those skilled in the art or of ordinary skill that various modifications and variations can be made to the present invention concept, as long as such modifications and variations do not depart from the spirit and scope of the present invention concept set forth in the claims described later.

[0264] Therefore, the technical scope of the present invention should not be limited to the contents stated in the detailed description of the specification, but should be determined by the claims.

Claims

1. An electronic device comprising: A substrate includes: a display area, including a plurality of light-emitting areas; and a non-light-emitting area disposed between the plurality of light-emitting areas; An intermediate insulating layer is disposed on the substrate; A pixel unit is disposed on the substrate and includes light-emitting elements, each of the light-emitting elements including: a first electrode and a second electrode, which overlap with the light-emitting area of ​​the plurality of light-emitting areas and are disposed on the intervening insulating layer; and a common layer disposed between the first electrode and the second electrode; Pixel-defined patterns are disposed on the intervening insulating layer; and A partition wall, overlapping the non-light-emitting area and disposed on the intervening insulating layer between adjacent pixel-defined patterns, comprises: a first layer disposed on the intervening insulating layer; a second layer disposed on the first layer; and a third layer disposed on the second layer. The opening corresponding to the light-emitting area and exposing at least a portion of the first electrode is defined in each of the pixel-defined patterns. In the intervening insulating layer defined in a recessed area between the partition wall and one of the pixel-defined patterns, a groove is defined in which at least a portion of the intervening insulating layer is recessed in a direction from the upper surface to the lower surface of the intervening insulating layer. The common layer and the second electrode extend from the light-emitting area to the recessed area and contact the first layer.

2. The electronic device according to claim 1, wherein, The groove exposes a portion of the lower surface of the first layer facing the intervening insulation layer.

3. The electronic device according to claim 2, wherein, The common layer contacts a portion of the lower surface of the first layer.

4. The electronic device according to claim 3, wherein, The second electrode contacts the side surface of the first layer.

5. The electronic device according to claim 3, wherein, The second electrode contacts a portion of the lower surface of the first layer and exposes the side surface of the first layer.

6. The electronic device according to claim 3, wherein, The second electrode contacts the side surface of the first layer and the portion of the upper surface of the first layer exposed from the second layer.

7. The electronic device according to claim 4, wherein, In the cross-sectional view, the groove has a concave shape.

8. The electronic device according to claim 4, further comprising an interlayer insulating layer disposed beneath the intervening insulating layer. in, The groove penetrates the interlayer insulation layer from the upper surface to the lower surface and exposes a portion of the upper surface of the interlayer insulation layer.

9. The electronic device according to claim 8, wherein, The common layer contacts the side surface of the recess defining the interlayer insulation layer, a portion of the upper surface of the interlayer insulation layer, and a portion of the lower surface of the first layer.

10. The electronic device according to claim 8, further comprising: A transistor is disposed on the substrate; The first connecting electrode is covered by the interlayer insulating layer and connected to the transistor; as well as The second connecting electrode is covered by the intercalary insulating layer and is connected to the first connecting electrode through a first contact hole defined in the intercalary insulating layer. The first electrode is connected to the second connecting electrode through a second contact hole defined in the intervening insulating layer.

11. The electronic device according to claim 1, wherein, The first layer and the third layer comprise titanium, and The second layer comprises aluminum.

12. The electronic device according to claim 11, wherein, In the cross-sectional view, the width of the first layer and the width of the third layer are each greater than the width of the second layer, and The thickness of the first layer and the thickness of the third layer are each less than the thickness of the second layer.

13. The electronic device according to claim 12, further comprising a first dummy pattern disposed on the third layer and a second dummy pattern disposed on the first dummy pattern. in, The first dummy pattern includes the same material as the common layer, and The second dummy pattern comprises the same material as the second electrode.

14. The electronic device according to claim 1, wherein, The partition wall further includes a fourth layer disposed on the third layer and comprising a material different from that of the first layer and the third layer.

15. The electronic device according to claim 14, wherein, The first layer and the third layer comprise either titanium or a molybdenum-titanium alloy, and The second and fourth layers comprise either aluminum or copper.

16. The electronic device according to claim 1, wherein, The side surfaces of the second layer are oxidized and are not conductive.

17. The electronic device according to claim 1, wherein, A plurality of second electrodes, which are disconnected and have a partition wall located therebetween, are connected through the partition wall.

18. The electronic device according to claim 1, wherein, The intermediary insulation layer includes any one of inorganic and organic materials.

19. The electronic device of claim 1, further comprising an encapsulation layer covering the light-emitting element.

20. The electronic device according to any one of claims 1 to 19, wherein, The pixel units in the display area are provided as a plurality of pixels in such a manner that each of the plurality of pixel units includes a first-1 pixel that provides a first color light, a first-2 pixel that provides the first color light and is spaced apart from the first-1 pixel along a first direction, a second pixel that provides a second color light different from the first color light and is spaced apart from the first-1 pixel along a first diagonal direction, a third pixel that provides a third color light different from the first color light and the second color light, and a third pixel that is spaced apart from the second pixel along a second direction intersecting the first direction and spaced apart from the first-1 pixel along a second diagonal direction intersecting the first diagonal direction.

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