Adapter plate, preparation method of adapter plate, processor and preparation method of processor

Abstract

The invention provides an adapter plate and a preparation method thereof, and a processor and a preparation method thereof, and the preparation method of the adapter plate comprises the steps: preparing a first assembly based on a first substrate, the first assembly comprising a micro-channel structure and superconducting metal filled in the micro-channel structure; preparing a second assembly based on the second substrate, wherein the second assembly comprises a blind hole; the first assembly and the second assembly are bonded based on the corresponding relation between the micro-channel structures and the blind holes in a vacuum environment, the superconducting metal is melted, the corresponding blind holes are filled with the superconducting metal in the micro-channel structures through negative pressure, and an assembly is obtained; performing de-bonding on the assembly to obtain a third assembly; wherein the third assembly comprises a blind hole filled with superconducting metal; and the third assembly is thinned so that the blind hole becomes a through hole and the superconducting metal is exposed, and the adapter plate is formed. According to the adapter plate and the preparation method thereof, and the processor and the preparation method thereof provided by the embodiment of the invention, the preparation efficiency of the adapter plate is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to an adapter board and its preparation method, and a processor and its preparation method. Background Technology

[0002] Quantum computing has demonstrated exponential computing power superiority over classical computing in certain specific application scenarios and has shown great application potential in multiple fields.

[0003] In current technologies, superconducting quantum processors have reached the kilobitant scale. Traditional wire bonding interconnect technologies, due to crosstalk and mechanical reliability issues with high-density wires, are no longer sufficient for further scaling. Therefore, there is a need to develop a three-dimensional integrated architecture compatible with superconducting qubits. However, as a core element in constructing this architecture, superconducting adapters still lack effective superconducting filling processes. Thus, how to fabricate adapters with fully filled superconducting structures has become a crucial issue urgently needing to be addressed in this field. Summary of the Invention

[0004] To address the problems in the prior art, embodiments of the present invention provide an adapter board and its preparation method, and a processor and its preparation method, which can at least partially solve the problems existing in the prior art.

[0005] In a first aspect, the present invention provides a method for preparing an adapter plate, comprising: A first component is fabricated based on a first substrate, the first component comprising a microchannel structure and a superconducting metal filled in the microchannel structure; A second component is fabricated based on a second substrate, the second component including blind vias; In a vacuum environment, based on the correspondence between the microchannel structure and the blind holes, the first component and the second component are bonded, and the superconducting metal is melted and the superconducting metal in the microchannel structure is filled with the corresponding blind holes by negative pressure to obtain the assembly. The assembly is debonded to obtain a third component; wherein the third component includes blind holes filled with superconducting metal; The third component is thinned so that the blind hole becomes a through hole and exposes the superconducting metal, forming an adapter plate.

[0006] Secondly, the present invention provides a method for manufacturing a processor, wherein the adapter board described in any of the above embodiments comprises: Spacer pillars are fabricated based on the aforementioned adapter plate, and superconducting metal is exposed as bumps. Dielectric layers are deposited on both surfaces of the adapter plate and wiring is performed to obtain the adapter plate layer; A processor is obtained by integrating spacers and bumps on an adapter plate layer with a core and a packaging substrate.

[0007] Thirdly, the present invention provides an adapter plate, which is prepared by the adapter plate preparation method described in any of the above embodiments.

[0008] Fourthly, the present invention provides a processor manufactured using the processor manufacturing method described in any of the above embodiments.

[0009] The adapter plate and its fabrication method, and the processor and its fabrication method provided in this invention include: fabricating a first component based on a first substrate, the first component including a microchannel structure and a superconducting metal filled in the microchannel structure; fabricating a second component based on a second substrate, the second component including blind holes; bonding the first component and the second component in a vacuum environment based on the correspondence between the microchannel structure and the blind holes, melting the superconducting metal and filling the corresponding blind holes in the microchannel structure with the superconducting metal through negative pressure to obtain an assembly; debonding the assembly to obtain a third component; wherein the third component includes blind holes filled with superconducting metal; thinning the third component so that the blind holes become through holes and expose the superconducting metal to form an adapter plate, thereby reducing the complexity of adapter plate fabrication and improving the fabrication efficiency of adapter plate. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In the drawings: Figure 1 This is a schematic flowchart of the preparation method of the adapter plate provided in the first embodiment of the present invention.

[0011] Figure 2 This is a schematic flowchart of the preparation method of the first component provided in the second embodiment of the present invention.

[0012] Figure 3 This is a schematic flowchart of the preparation method of the microchannel structure provided in the third embodiment of the present invention.

[0013] Figure 4 This is a schematic flowchart of the preparation method of the microchannel structure provided in the fourth embodiment of the present invention.

[0014] Figure 5 This is a schematic flowchart of the preparation method of the assembly provided in the fifth embodiment of the present invention.

[0015] Figure 6A This is a schematic diagram of the structure after the formation of the dielectric layer provided in the sixth embodiment of the present invention.

[0016] Figure 6B This is a schematic diagram of the structure after the formation of the microchannel structure provided in the sixth embodiment of the present invention.

[0017] Figure 6C This is a schematic diagram of the structure after the first component is formed, provided in the sixth embodiment of the present invention.

[0018] Figure 6D This is a schematic diagram of the structure after the mask layer is formed, provided in the sixth embodiment of the present invention.

[0019] Figure 6E This is a schematic diagram of the structure after forming a blind hole according to the sixth embodiment of the present invention.

[0020] Figure 6F This is a schematic diagram of the structure after the second component is formed, provided in the sixth embodiment of the present invention.

[0021] Figure 6G This is a schematic diagram of a structure in a vacuum environment provided in the sixth embodiment of the present invention.

[0022] Figure 6H This is a schematic diagram of the bonded structure provided in the sixth embodiment of the present invention.

[0023] Figure 6I This is a schematic diagram of the structure of the superconducting metal after melting, provided in the sixth embodiment of the present invention.

[0024] Figure 6J This is a schematic diagram of the structure after the superconducting metal fills the blind hole according to the sixth embodiment of the present invention.

[0025] Figure 6K This is a schematic diagram of the debonded structure provided in the sixth embodiment of the present invention.

[0026] Figure 6L This is a schematic diagram of the structure after forming the adapter plate according to the sixth embodiment of the present invention.

[0027] Figure 7 This is a schematic flowchart of the processor fabrication method provided in the seventh embodiment of the present invention.

[0028] Figure 8 This is a schematic flowchart of the processor fabrication method provided in the eighth embodiment of the present invention.

[0029] Figure 9 This is a schematic flowchart of the processor fabrication method provided in the ninth embodiment of the present invention.

[0030] Figure 10 This is a schematic flowchart of the processor fabrication method provided in the tenth embodiment of the present invention.

[0031] Figure 11AThis is a schematic diagram of the adapter plate provided in the eleventh embodiment of the present invention.

[0032] Figure 11B This is a schematic diagram of the structure of the adapter plate after photolithography according to the eleventh embodiment of the present invention.

[0033] Figure 11C This is a schematic diagram of the structure of the adapter plate after etching, provided in the eleventh embodiment of the present invention.

[0034] Figure 11D This is a schematic diagram of the structure after the deposition of the medium layer provided in the eleventh embodiment of the present invention.

[0035] Figure 11E This is a schematic diagram of the integrated core provided in the eleventh embodiment of the present invention.

[0036] Figure 11F This is a schematic diagram of the processor provided in the eleventh embodiment of the present invention. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and descriptions of the present invention are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. The acquisition, storage, use, and processing of data in the technical solutions of this application all comply with the relevant provisions of laws and regulations. The user information in the embodiments of this application is obtained through legal and compliant means, and the acquisition, storage, use, and processing of user information have been agreed upon by the customer.

[0038] To facilitate understanding of the technical solution provided in this application, the relevant content of the technical solution in this application will be explained below.

[0039] In the existing technology, the transition plate technology for superconducting quantum devices mainly includes the following two technical routes: (1) Through-Silicon Via (TSV) with superconducting material on the sidewall: After deep silicon etching, superconducting materials such as TiN, Ti, Ta, and TaN are deposited on the sidewall of TSV using techniques such as atomic layer deposition (ALD) and physical vapor deposition (PVD) to achieve superconducting interconnection between the top and bottom surfaces within the layer; however, the main limitation of this method is that the hollow TSV transition plate cannot meet the requirements of the machine for vacuuming process without the addition of an auxiliary layer, which increases the complexity of the process; in addition, a large amount of chemical reagents and contaminants will remain in the TSV hole or on the sidewall of the hole, affecting the physical properties of the superconducting material layer on the sidewall; and may cause gas release or denaturation problems in the ultra-low temperature test, affecting the stability of the TSV transition plate test. (2) Fully filled TSV with superconducting material covering the sidewalls and copper plating inside the holes: The superconducting material on the sidewalls can form a parallel path with the internal copper plating. Electroplated copper TSV, through glass via (TGV) and other technologies are mature processes in the semiconductor industry. However, in the high-frequency measurement and control process of TSV adapters, the electromagnetic field distribution in non-superconducting copper may still cause the risk of Joule heating, which in turn affects the accuracy of temperature control and the stability of the superconducting state.

[0040] Therefore, this application proposes a method for fabricating an adapter plate based on differential pressure filling of superconducting metal. This method has few restrictions on the filling material (any superconducting metal will suffice) and the adapter plate substrate (any material that can be drilled) and has broad technology transfer characteristics. Furthermore, the differential pressure method can effectively fill the entire wafer at the wafer level in a short time, with high yield and consistency.

[0041] Figure 1 This is a schematic flowchart of the preparation method of the adapter plate provided in the first embodiment of the present invention, as shown below. Figure 1 As shown, the method for preparing the adapter plate provided in this embodiment of the invention includes: S101. Fabricate a first component based on a first substrate, the first component comprising a microchannel structure and a superconducting metal filled in the microchannel structure; Specifically, a dielectric layer is grown on a first substrate, then a microfluidic structure is fabricated on the dielectric layer, and a superconducting metal is filled within the structure to form a first component. The first substrate can be a silicon wafer, glass wafer, molded wafer, etc., selected according to actual needs; this embodiment of the invention does not limit the choice. The specific shape and number of the microfluidic structure are set according to actual needs; this embodiment of the invention does not limit the choice. The superconducting metal can be indium, etc.

[0042] Before use, the first substrate is cleaned. If the first substrate is a silicon wafer, the silicon wafer surface can be cleaned using the RCA standard process. If the first substrate is a glass wafer, the hydrofluoric acid (HF) in the RCA solution will corrode the glass, so the RCA standard process cannot be used for cleaning. Instead, a suitable organic solvent and deionized water (DI) can be used for cleaning. If the first substrate is a molded wafer, a suitable organic solvent and DI can be used for cleaning.

[0043] S102. Fabricate a second component based on the second substrate, the second component including blind vias; Specifically, blind vias are fabricated on the second substrate to obtain the second component. The positions of the blind vias correspond to the positions of the superconducting metal, facilitating subsequent filling of the corresponding blind vias by the superconducting metal. The second substrate can be a silicon wafer, glass wafer, molded wafer, etc., selected according to actual needs; this embodiment of the invention does not limit the choice. The number of blind vias is set according to actual needs; this embodiment of the invention does not limit the choice.

[0044] The second substrate is cleaned before use. If the second substrate is a silicon wafer, the silicon wafer surface can be cleaned using the standard RCA process. For silicon wafers, silicon blind vias can be fabricated, which will form TSVs after the adapter board is fabricated. If the second substrate is a glass wafer, the HF component in the RCA solution will corrode the glass, so the standard RCA process cannot be used for cleaning. Instead, suitable organic solvents and DI can be used for cleaning. For glass wafers, glass blind vias can be fabricated, which will form TGVs after the adapter board is fabricated. If the second substrate is a molded wafer, it can be cleaned using suitable organic solvents and DI. For molded wafers, molded blind vias can be fabricated, which will form through-molding vias (TMVs) after the adapter board is fabricated.

[0045] S103. Under vacuum conditions, based on the correspondence between the microchannel structure and the blind hole, the first component and the second component are bonded, and the superconducting metal is melted and the superconducting metal in the microchannel structure is filled with the corresponding blind hole by negative pressure to obtain the assembly. Specifically, the first component and the second component are bonded in a vacuum environment. During bonding, the microfluidic structure and the blind vias are aligned, allowing the superconducting metal in the microfluidic structure to fill the corresponding blind vias after melting. After the first component and the second component are bonded, the superconducting metal is melted, and negative pressure is used to force the superconducting metal in the microfluidic structure to fill the corresponding blind vias. After the superconducting metal cools, the assembly is obtained. The correspondence between the microfluidic structure and the blind vias is predetermined.

[0046] During bonding, the first component and the second component can be heated and pressurized to facilitate bonding. It is understood that the heating temperature during bonding should be lower than the melting point of the superconducting metal to prevent the superconducting metal from melting during the bonding process.

[0047] S104. Debond the assembly to obtain a third component; wherein the third component includes blind holes filled with superconducting metal; Specifically, after obtaining the assembly, the superconducting metal has been filled, shaped, and cooled. The assembly can then be debonded to separate the first and second components. The second component, filled with superconducting metal within the blind hole, constitutes the third component. Debonding can be performed using mechanical methods such as pulling or rotating, or chemical methods such as immersion in a specific chemical solvent, selected according to actual needs. This embodiment of the invention does not impose any limitations on the method.

[0048] S105. Thin the third component so that the blind hole becomes a through hole and exposes the superconducting metal to form an adapter plate.

[0049] Specifically, the blind hole of the third component is thinned, the bottom of the blind hole is removed, and the blind hole becomes a through hole, exposing the superconducting metal. That is, the superconducting metal will be exposed at both ends of the through hole to form an adapter plate.

[0050] Specifically, if the second substrate is a silicon wafer, silicon blind vias will be formed on the adapter board. If the second substrate is a glass wafer, glass blind vias will be formed on the adapter board. If the second substrate is a molded wafer, molded blind vias will be formed on the adapter board.

[0051] After thinning the third component, the adapter plate can be processed using Chemical Mechanical Polishing (CMP) to obtain a smooth surface. After debonding the assembly, the two debonded surfaces will have undesirable geometries, and there is a risk of superconducting metal contamination on the dielectric layer in the non-blind via regions; therefore, CMP is necessary. After CMP, the original dielectric layer of the third component will be removed, requiring redeposition and patterning of the dielectric layer to ensure insulation between the second substrate and the first substrate.

[0052] The two surfaces of the exposed superconducting metal in the third component can be used to deposit wiring layers and pattern them for the fabrication of related electrical structures.

[0053] The method for fabricating an adapter plate provided in this invention includes: fabricating a first component based on a first substrate, the first component comprising a microchannel structure and a superconducting metal filled in the microchannel structure; fabricating a second component based on a second substrate, the second component comprising blind vias; bonding the first component and the second component in a vacuum environment based on the correspondence between the microchannel structure and the blind vias, melting the superconducting metal and filling the corresponding blind vias in the microchannel structure with the superconducting metal through negative pressure to obtain an assembly; debonding the assembly to obtain a third component; wherein the third component comprises blind vias filled with superconducting metal; thinning the third component to make the blind vias become through-holes and expose the superconducting metal to form an adapter plate, thereby reducing the complexity of adapter plate fabrication and improving the fabrication efficiency of the adapter plate. Furthermore, it avoids chemical reagent contamination of the through-holes, improving the stability of the adapter plate during testing.

[0054] Figure 2 This is a schematic flowchart of the preparation method of the first component provided in the second embodiment of the present invention, as shown below. Figure 2 As shown, based on the above embodiments, the further step of fabricating the first component based on the first substrate includes: S201. Grow a dielectric layer on the first substrate; Specifically, a dielectric layer is grown on the first substrate. The dielectric layer can be made of materials such as silicon dioxide and silicon nitride, and the selection is made according to actual needs. This embodiment of the invention does not limit the choice.

[0055] S202. A microchannel structure is formed on the dielectric layer; Specifically, a microchannel structure can be fabricated on the dielectric layer. This microchannel structure is used to fill the superconducting metal and can accommodate the superconducting metal during subsequent melting. The microchannel structure has channels communicating with the outside world, so that when the superconducting metal is subsequently filled into the blind hole, pressure can be applied to the molten superconducting metal using an inert gas, pushing the superconducting metal towards the blind hole.

[0056] For example, microchannel patterns can be photolithographically etched onto the dielectric layer, and then the microchannel structure can be etched using dry or wet etching methods.

[0057] S203. Fill the microchannel structure with superconducting metal.

[0058] Specifically, a superconducting metal can be filled within the microchannel structure. The filled superconducting metal can be flush with the surface of the dielectric layer containing the microchannel structure.

[0059] For example, superconducting metal can be filled into microchannels by evaporation or electroplating, making the surface of the superconducting metal flush with the surface of the dielectric layer to ensure sufficient superconducting metal to fill the corresponding blind holes. It should be noted that if electroplating is used, necessary underlay materials, such as an adhesion layer and an electroplating seed layer, need to be deposited before step S203.

[0060] Because the superconducting metal within the microchannel structure and the dielectric layers on both sides of the microchannel structure are at the same height, a good sealing structure will be formed after the first and second components are bonded, maintaining the vacuum environment inside the blind hole.

[0061] Figure 3 This is a schematic flowchart of the method for preparing the microchannel structure provided in the third embodiment of the present invention, as shown below. Figure 3 As shown, based on the above embodiments, further, forming a microchannel structure on the dielectric layer includes: S301. Photolithography is performed on the dielectric layer to form a microchannel pattern; Specifically, microchannel patterns are photolithographically formed on the dielectric layer, and these microchannel patterns are used to fabricate microchannel structures. The microchannel patterns are configured according to actual needs, and this embodiment of the invention does not impose any limitations.

[0062] S302. Etch the dielectric layer based on the microchannel pattern to obtain the microchannel structure.

[0063] Specifically, the microchannel structure can be obtained by etching the dielectric layer based on the microchannel pattern. The etching can be performed using either dry or wet etching methods.

[0064] Figure 4 This is a schematic flowchart of the method for preparing the microchannel structure provided in the fourth embodiment of the present invention, as shown below. Figure 4 As shown, based on the above embodiments, the further step of fabricating the second component based on the second substrate includes: S401. Grow a mask layer on the second substrate; Specifically, a mask layer is grown on the second substrate. The mask layer can be made of materials such as silicon dioxide and silicon nitride, and the selection is made according to actual needs. This embodiment of the invention does not limit the choice.

[0065] S402. Photolithographically pattern blind holes on the mask layer; Specifically, blind hole patterns are photolithographically formed on the mask layer, and these blind hole patterns are used to fabricate blind holes. The blind hole patterns are configured according to actual needs, and this embodiment of the invention does not impose any limitations.

[0066] S403. Etch the second substrate based on the blind via pattern to form a blind via within the second substrate.

[0067] Specifically, by etching the second substrate based on the blind via pattern, blind vias can be formed within the second substrate. After obtaining the blind vias, the mask layer can be removed. The etching can be performed using either dry or wet etching methods.

[0068] For example, the second substrate is a silicon wafer, which can be etched using the DRIE dry etching method or the KOH solution wet etching method to form blind holes in the second substrate.

[0069] For example, if the second substrate is a glass wafer, laser-induced etching can be used to form blind holes within the second substrate.

[0070] For example, if the second substrate is a molded wafer, blind vias can be formed in the second substrate using methods such as laser drilling or mechanical drilling.

[0071] Based on the above embodiments, an adhesion layer is further deposited on the inner wall of the blind hole. The adhesion layer may be made of a superconducting metal such as Ti. The melting point of the adhesion layer material is higher than that of the superconducting metal used in the superconducting metal pillar.

[0072] An adhesion layer can be deposited on the insulating layer of the through-hole using a thin-film growth technique capable of filling deep-hole structures, thereby achieving good fixation between the superconducting metal and the hole structure. Atomic layer deposition, bias sputtering, chemical vapor deposition, and other processes can be used to deposit the adhesion layer. Furthermore, based on the above embodiments, when the second substrate is a conductor or semiconductor material, a dielectric layer is deposited inside the blind hole and on the second substrate as an insulating layer.

[0073] Figure 5 This is a schematic flowchart of the preparation method of the assembly provided in the fifth embodiment of the present invention, as shown below. Figure 5 As shown, based on the above embodiments, further, the step of bonding the first component and the second component in a vacuum environment based on the correspondence between the microchannel structure and the blind holes, melting the superconducting metal, and filling the corresponding blind holes with the superconducting metal in the microchannel structure through negative pressure to obtain the assembly includes: S501. Bond the first component and the second component in a vacuum environment so that the surfaces of the first component and the second component overlap, and the superconducting metal seals the corresponding blind holes. Specifically, the first component and the second component are placed in a vacuum environment and bonded together, i.e., bonded by van der Waals forces between the surfaces of the first and second components. During bonding, the side of the first component with the microfluidic structure and superconducting metal faces the second component, and the side of the second component with blind holes faces the first component. The superconducting metal filling the microfluidic structure corresponds to the blind holes so that the corresponding blind holes can be sealed after bonding. To facilitate bonding, the bonding surfaces of the first and second components can be heated, and pressure can be applied during the bonding process.

[0074] The vacuum environment can be achieved using a bonding device. The first and second components are clamped in the bonding device and brought into the main cavity of the device. A vacuum operation is then performed on the main cavity to remove the air, achieving a vacuum state and creating a vacuum environment.

[0075] S502. Melt the superconducting metal and fill the vacuum environment with inert gas, so that the inert gas pushes the molten superconducting metal through the microchannel structure to fill the corresponding blind holes; Specifically, the superconducting metal is heated above its melting point, causing it to melt. An inert gas is then introduced into the vacuum environment. Since the blind holes remain under vacuum, the inert gas enters the microchannel structure under negative pressure, propelling the molten superconducting metal into the corresponding blind holes until the entire blind hole is filled. The inert gas can be nitrogen or other gases, selected according to actual needs; this embodiment of the invention does not impose limitations.

[0076] Understandably, when a superconducting metal is heated above its melting point, the liquid superconducting metal can extend inward at the outlet of the blind hole due to surface tension, thus achieving a good liquid seal for the blind hole and preventing pressure leakage.

[0077] To ensure complete filling of the blind holes, the total amount of superconducting metal in the microchannel is greater than the total amount of superconducting metal required to fill the blind holes.

[0078] S503. After the superconducting metal cools and solidifies, the assembly is formed.

[0079] Specifically, after the superconducting metal fills the blind holes, it is cooled to below the melting point of the superconducting metal, allowing it to solidify within the blind holes, thus obtaining the assembly. To ensure the superconducting metal solidifies within the blind holes, an inert gas pressure is maintained on the superconducting metal throughout the cooling process; after the superconducting metal has solidified, the gas pressure is removed.

[0080] The following specific embodiment illustrates the detailed implementation process of the adapter plate preparation method provided by the present invention.

[0081] Step 1: Growing SiO2 on the first silicon wafer 1 to form dielectric layer 2, such as... Figure 6A As shown.

[0082] The second step involves photolithographically etching the microchannel pattern onto the dielectric layer 2, and then wet etching the dielectric layer 2 to form the microchannel structure 3, such as... Figure 6B As shown, microchannel structure 3 has a cavity to accommodate the superconducting metal.

[0083] The third step involves filling the microchannel structure 3 with superconducting indium 4 via evaporation, followed by removing the photoresist from the microchannel structure 3 to obtain the first component 5, as shown below. Figure 6C As shown.

[0084] Step 4: SiO2 is grown on the second silicon wafer 6 to form a mask layer 7, as shown below. Figure 6D As shown.

[0085] Step 5: Photolithographically pattern blind vias are formed on mask layer 7. Based on the blind via pattern, mask layer 7 and the second silicon wafer 6 are etched to form blind vias 8, as shown below. Figure 6E As shown.

[0086] Step 6: Remove the mask layer 7 and deposit a SiO2 thin film on the surface of the second silicon wafer 6 and in the blind vias 8 as an insulating layer 9 to form the second component 10, as shown below. Figure 6F As shown. Since the second silicon wafer 6 uses low-resistivity silicon, an insulating layer needs to be deposited; otherwise, if the second silicon wafer 6 uses high-resistivity silicon, such as intrinsic silicon or other non-conductive materials, then the mask layer 7 can be removed, and there is no need to deposit an insulating layer.

[0087] Step 7: Using wafer-level bonding equipment, clamp the first component 5 and the second component 10 into the main cavity of the wafer-level bonding equipment, and then perform a vacuum operation to place the first component 5 and the second component 10 in a vacuum environment. The gas in the blind via 8 of the second component 10 is emptied, and it is in a vacuum state. Figure 6G As shown.

[0088] Step 8: Bond the first component 5 and the second component 10 under temperature T and pressure P, so that the surface of the microchannel structure 3 of the first component 5 adheres tightly to the surface of the insulating layer 9 of the second component 10 under the action of van der Waals forces, as shown. Figure 6H As shown. The temperature T is less than the melting point of the superconducting metal indium 4; the pressure P is selected according to actual needs, and is not limited in this embodiment of the invention.

[0089] Step 9: Heat the superconducting indium 4 above its melting point, causing it to melt. Due to surface tension, the molten liquid indium 4 will form a seal with the insulating layer 9, maintaining the vacuum state of the blind hole 8. Figure 6I As shown.

[0090] Step 10: After the superconducting indium 4 is completely melted, nitrogen gas is introduced into the main cavity of the wafer-level bonding equipment to increase the pressure inside the main cavity. Due to the liquid seal of the superconducting indium 4, the blind hole 8 remains in a vacuum state. The external pressure of the blind hole 8 is high while the internal pressure is low. Nitrogen gas will enter the microfluidic structure 3 from the inlet of the microfluidic structure 3, pushing the liquid superconducting indium 4 into the blind hole 8. Over time, the liquid superconducting indium 4 will fill the blind hole 8. After the superconducting indium 4 fills the blind hole 8, the pressure inside the main cavity is kept constant, and the temperature is lowered to below the melting point of the superconducting indium 4, allowing the superconducting indium 4 inside the blind hole 8 to cool and solidify, resulting in assembly 11, as shown. Figure 6J As shown.

[0091] Step 11: Debond assembly 11. The second component, filled with superconducting metal in the blind hole, constitutes the third component 12, as shown below. Figure 6K As shown.

[0092] Step 12: Thin the third component 12 to make the blind via 8 a through-hole, exposing the superconducting indium 4; then perform CMP on the upper and lower surfaces of the third component 12 to obtain smooth upper and lower surfaces, and then deposit and pattern a dielectric layer 13 on the smooth upper and lower surfaces to ensure that the wiring layer is insulated from the second silicon wafer 6, forming the adapter plate 14, as shown. Figure 6L As shown.

[0093] After obtaining the adapter board 14, wiring layers can be redeposited and patterned on the upper and lower surfaces of the adapter board 14 to prepare the necessary electrical structure.

[0094] Figure 7 This is a schematic flowchart of the processor fabrication method provided in the seventh embodiment of the present invention, as shown below. Figure 7 As shown, the processor fabrication method provided in this embodiment of the invention, using the adapter board described in any of the above embodiments, includes: S701. Based on the adapter plate, spacer pillars are prepared and exposed superconducting metal is used as bumps; Specifically, spacers can be fabricated on the adapter plate, exposing superconducting metal as bumps. The spacers ensure that the tilt and spacing between the adapter plate and the chip meet requirements. The bumps are used to bond the chip or the packaging substrate. The number of spacers and bumps is set according to actual needs, and this embodiment of the invention does not limit this. The spacers and bumps can have the same height. Spacers and bumps can be fabricated on both surfaces of the adapter plate. The chip can be the smallest functional unit that implements computing, storage, and interface functions. Multiple chips can be integrated together to form a processor using packaging technology.

[0095] For example, the two surfaces of the adapter plate can be etched, and raised structures can be retained on both sides of the adapter plate as spacers; when etching the adapter plate, a portion of the superconducting metal is exposed as bumps.

[0096] S702. Deposit dielectric layers on both surfaces of the adapter plate and perform wiring to obtain the adapter plate layer; Specifically, after fabricating the spacers and bumps, a dielectric layer is deposited on the two surfaces of the adapter plate having the spacers and bumps, and then wiring is performed on the dielectric layer to obtain the adapter plate layer. The spacers and bumps protrude from the surface of the adapter plate layer.

[0097] The dielectric layer can be made of insulating materials such as silicon dioxide and silicon nitride to ensure insulation between the wiring layer and the adapter board.

[0098] Because the bumps protrude from the surface of the adapter board layer, they can have a good electrical connection with the wiring layer.

[0099] S703, a processor is obtained by integrating spacers and bumps on an adapter plate layer with a core and a packaging substrate.

[0100] Specifically, the processor can be obtained by integrating the chip and the packaging substrate through the spacers and bumps of the transition plate layer. The number of transition plate layers and the number of chips included in the processor are set according to actual needs, and this embodiment of the invention does not limit this. The chip can be a quantum chip, which can be the smallest unit including structures such as qubits and resonant cavities, capable of realizing functions such as computing, storage, and interface.

[0101] For example, the processor includes an adapter layer, the upper surface of which is based on spacer pillars and bumps integrated die, and the lower surface of which is based on spacer pillars and bumps integrated package substrate.

[0102] For example, a processor includes multiple interposer layers, and the multiple interposer layers, individual chips, and a packaging substrate form a stacked structure. In the stacked structure, chips are integrated between adjacent interposer layers, the packaging substrate is integrated in the bottom interposer layer, and the chip is integrated on the upper surface of the top interposer layer.

[0103] The processor fabrication method provided in this embodiment of the invention involves fabricating spacer pillars based on the adapter plate and exposing superconducting metal as bumps; depositing dielectric layers on the two surfaces of the adapter plate and performing wiring to obtain an adapter plate layer; integrating the chip and packaging substrate based on the spacer pillars and bumps of the adapter plate layer to obtain the processor. Since the fabrication complexity of the adapter plate is reduced, the fabrication efficiency of the processor is improved.

[0104] Figure 8 This is a schematic flowchart of the processor fabrication method provided in the eighth embodiment of the present invention, as shown below. Figure 8 As shown, based on the above embodiments, further comprising the step of fabricating spacer pillars based on the adapter plate and exposing superconducting metal as bumps includes: S801. Photolithography is performed on the two surfaces of the adapter plate to form a preset pattern; the preset pattern is used to form spacer pillars and bumps. Specifically, a preset pattern is photolithographically etched on both surfaces of the adapter plate. The preset pattern is then covered with spacer pillars and superconducting metal by photoresist so that spacer pillars and bumps are formed after the adapter plate is etched.

[0105] In order to facilitate photolithography, CMP can be performed on the upper and lower surfaces of the adapter plate before photolithography to make the upper and lower surfaces of the adapter plate planarize.

[0106] S802. Based on the preset pattern, etch the two surfaces of the adapter plate to obtain the spacer post and the protrusion.

[0107] Specifically, etching is performed on both surfaces of the adapter plate based on a preset pattern. The areas not protected by photoresist are etched away, leaving the protruding structures of the adapter plate as spacers and the retained superconducting metal as bumps. After removing the photoresist, the spacers and bumps are exposed, and the top surfaces of the spacers and bumps on the same surface of the adapter plate are in the same plane. The etching can be performed using either dry or wet etching. The etching depth is set according to actual needs and is not limited in this embodiment. For example, etching from several micrometers to tens of micrometers.

[0108] Figure 9 This is a schematic flowchart of the processor fabrication method provided in the ninth embodiment of the present invention, as shown below. Figure 9 As shown, based on the above embodiments, the spacer post and bump integrated core based on the transition plate layer further includes: S901. Place balls on the pads on the surface of the core to form microbumps on the pads; Specifically, ball-planting on the pads on the surface of the core chip can form microbumps on the pads, which are used to achieve bonding between the core chip and the adapter layer.

[0109] S902. Based on the microbumps of the core and the spacers and bumps of the transition plate layer, the transition plate layer and the core are bonded.

[0110] Specifically, the microbumps of the core particle are aligned with the bumps of the transition plate layer, and then pressure is applied for bonding at room temperature until the microbumps of the core particle and the bumps of the transition plate layer are pressed together and cannot be further deformed. The distance between the core particle and the transition plate layer, as well as the tilt of the core particle substrate and the transition plate layer, are maintained by the spacers of the transition plate layer. The pressure used during bonding is set according to actual needs, and this embodiment of the invention does not limit it.

[0111] Because bonding is achieved at room temperature, temperature interference during multilayer bonding is greatly reduced, improving the electrical reliability of the structure of the adapter layer and the core multilayer stack.

[0112] Based on the above embodiments, the spacer post and bump integrated packaging substrate based on the adapter plate layer further includes: The adapter layer and the packaging substrate are bonded based on the spacer pillars and bumps on the opposite side surface of the integrated core of the adapter layer.

[0113] Specifically, the surface of the interposer integrated chip opposite to each other has spacer posts and bumps. The bumps on the surface of the interposer integrated chip opposite to each other are bonded to the packaging substrate. The spacer posts on the surface of the interposer integrated chip opposite to each other can limit the distance between the interposer and the packaging substrate.

[0114] Among these methods, microbumps can be fabricated on the pads of the packaging substrate, and then bonded to the bumps of the adapter layer through the microbumps of the packaging substrate.

[0115] Figure 10 This is a schematic flowchart of the processor fabrication method provided in the tenth embodiment of the present invention, as shown below. Figure 10 As shown, based on the above embodiments, further, there are multiple transition board layers, and correspondingly, the spacer pillars and bumps integrated cores and packaging substrates based on the transition board layers include: S1001, Each transition board layer is stacked into a single unit through cores, and each transition board layer integrates cores based on spacer pillars and bumps to obtain a multi-chip module; Specifically, there are multiple adapter layers, each with spacer pillars and bumps on its first and second surfaces. The adapter layers and chips can be spaced apart, with each adapter layer integrating chips based on the spacer pillars and bumps, stacked to form a multi-chip module. The inner surface of the outermost adapter layer of the multi-chip module integrates the chip, while the outer surface of this adapter layer is used to integrate the packaging substrate. The inner surface of the adapter layer refers to the surface facing the chip. The integration order of the adapter layers and chips is set according to actual needs, and this embodiment of the invention does not limit it.

[0116] S1002. Integrate the packaging substrate through the spacer pillars and bumps on the outer surface of the outermost adapter board layer of the multi-chip module.

[0117] Specifically, the outermost adapter layer of the multi-chip module integrates a packaging substrate, which is integrated through spacers and bumps on the outer surface of the adapter layer. Chips are integrated on the two surfaces of the other outermost adapter layer of the multi-chip module.

[0118] For example, a processor includes n transition board layers, where n is greater than or equal to 2. The upper surface of the first transition board layer is integrated with a die based on spacers and bumps, and the lower surface of the first transition board layer is integrated with a die based on spacers and bumps. The upper surface of the second transition board layer is integrated with spacers and bumps on the die integrated in the first transition board layer, and the lower surface of the second transition board layer is integrated with spacers and bumps. The upper surface of the third transition board layer is integrated with spacers and bumps on the die integrated in the second transition board layer, and the lower surface of the third transition board layer is integrated with spacers and bumps. And so on, the upper surface of the nth transition board layer is integrated with spacers and bumps on the die integrated in the (n-1)th transition board layer, and the lower surface of the nth transition board layer is integrated with spacers and bumps on the package substrate.

[0119] An adapter board provided in this embodiment of the invention is prepared using the adapter board preparation method described in any of the above embodiments.

[0120] This invention provides a processor manufactured using the processor manufacturing method described in any of the above embodiments.

[0121] The following specific embodiment illustrates the detailed implementation process of the processor fabrication method provided by the present invention.

[0122] Step 1: Obtain three adapter plates 101. The first and second surfaces of each adapter plate 101 are treated with CMP. Each adapter plate 101 includes a TSV, which is filled with a superconducting metal 101-0. An insulating layer is disposed within the TSV, such as... Figure 11A As shown.

[0123] The second step involves photolithography on the first and second surfaces of each adapter plate 101, forming preset patterns on the first and second surfaces respectively, such as... Figure 11B As shown.

[0124] Step 3: Based on the preset pattern of the first surface of each adapter plate 101, the first surface of the adapter plate 101 is etched to obtain spacer pillars 101-1 and bumps 101-2; based on the preset pattern of the second surface of each adapter plate 101, the second surface of the adapter plate 101 is etched to obtain spacer pillars 101-3 and bumps 101-4. After removing the photoresist, the resulting structure is as follows: Figure 11C As shown.

[0125] Fourth step: Deposit dielectric layers 102 on the first and second surfaces of each adapter board 101, and then perform wiring on each dielectric layer 102 to obtain the corresponding adapter board layer 103, such as... Figure 11D As shown.

[0126] Step 5: The upper surface of the first transition plate layer 103-1 integrates a core 104 based on spacer pillars 101-1 and bumps 101-2. Microbumps 104-1 are formed by ball-planting on the pads of the core 104. The microbumps 104-1 of the core 104 are bonded to the bumps 101-2 of the transition plate layer 103-1. The spacing and tilt are controlled by the spacer pillars 101-1 of the transition plate layer 103-1 to achieve integration of the core 104 with the first transition plate layer 103-1. Multiple cores 104 can be integrated on the upper surface of the first transition plate layer 103-1.

[0127] A core 105 is integrated on the lower surface of the first transition layer 103-1 based on spacer pillars 101-3 and bumps 101-4. Microbumps 105-1 are formed by ball-planting on the pads on the upper surface of the core 105. The microbumps 105-1 of the core 105 are bonded to the bumps 101-4 of the first transition layer 103-1. The spacing and tilt are controlled by the spacer pillars 101-3 of the first transition layer 103-1, thus achieving integration between the core 105 and the first transition layer 103-1. Multiple cores 105 can be integrated on the lower surface of the first transition layer 103-1. Figure 11E As shown.

[0128] Step 6: The upper surface of the second transition plate layer 103-2 integrates a core 105 based on spacer pillars 101-1 and bumps 101-2. Microbumps 105-2 are formed by ball-planting on the pads on the lower surface of the core 105. The microbumps 105-2 of the core 105 are bonded to the bumps 101-2 of the second transition plate layer 103-2. The spacing and tilt are controlled by the spacer pillars 101-1 of the second transition plate layer 103-2 to achieve integration between the core 105 and the second transition plate layer 103-2. Multiple cores 105 can be integrated on the upper surface of the second transition plate layer 103-2.

[0129] The lower surface of the second transition layer 103-2 integrates a core 106 based on spacers 101-3 and bumps 101-4. Microbumps 106-1 are formed by ball-planting on the pads on the upper surface of the core 106. These microbumps 106-1 are bonded to the bumps 101-4 of the second transition layer 103-2, and the spacing is controlled by the spacers 101-3 of the second transition layer 103-2, thus achieving integration between the core 106 and the second transition layer 103-2. Multiple cores 106 can be integrated on the lower surface of the second transition layer 103-2.

[0130] The upper surface of the third transition layer 103-3 integrates a core 106 based on spacer pillars 101-1 and bumps 101-2. Microbumps 106-2 are formed by ball-planting on the pads of the lower surface of the core 106. The microbumps 106-2 of the core 106 are bonded to the bumps 101-2 of the third transition layer 103-3, and the spacing and tilt are controlled by the spacer pillars 101-1 of the third transition layer 103-3 to achieve integration between the core 106 and the third transition layer 103-3. Multiple cores 106 can be integrated on the upper surface of the third transition layer 103-2.

[0131] The lower surface of the third interposer layer 103-3 integrates a packaging substrate 107 based on spacers 101-3 and bumps 101-4. Microbumps 107-1 can be formed by ball-mounting on the pads of the packaging substrate 107. These microbumps 107-1 are bonded to the bumps 101-4 of the third interposer layer 103-3, and the spacing is controlled by the spacers 101-3 of the third interposer layer 103-3, thus achieving integration between the packaging substrate 107 and the third interposer layer 103-3. The final processor structure is as follows: Figure 11F As shown.

[0132] It should be noted that: (1) Various film preparations can be replaced by compatible common material growth technologies such as sputtering, CVD, PVD, ALD, electroplating, and electroless plating; (2) Various groove, hole, and protrusion structures can be replaced by compatible addition and subtraction processes, such as machining, dry etching, wet etching, the material growth process in (1), 3D printing, and other industry-standard technologies; (3) Various materials with superconducting properties can be interchanged, such as TiN, Al, Ti, W, In, Nb, Ta, NbN, and NbTiN-based materials. (4) All inter-chip interconnects can adopt various industry-standard technologies such as superconducting solder bumps, copper pillar bumps covered with superconducting materials, and nail head bumps covered with superconducting materials. The adapter board can be based on various industry-standard technologies such as silicon-based, glass-based, and molding compound-based. The through-hole structure can be based on various industry-standard technologies such as TSV, TGV, and TMV. (5) The insulating layer can include inorganic insulating materials, such as silicon oxide, silicon nitride, silicon oxynitride, and other silicon oxides, silicon nitrides, or silicon oxynitrides, or insulating materials including metal oxynitrides such as aluminum oxide and titanium nitride. The insulating layer can also include organic insulating materials such as polyimide (PI), acrylate, epoxy resin, and polymethyl methacrylate (PMMA). The insulating layer can be a single-layer structure or a multi-layer structure, for example, a multi-layer structure of alternating stacks of silicon oxide and silicon nitride.

[0133] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0134] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for preparing an adapter plate, characterized in that, include: A first component is fabricated based on a first substrate, the first component comprising a microchannel structure and a superconducting metal filled in the microchannel structure; A second component is fabricated based on a second substrate, the second component including blind vias; In a vacuum environment, based on the correspondence between the microchannel structure and the blind holes, the first component and the second component are bonded, and the superconducting metal is melted and the superconducting metal in the microchannel structure is filled with the corresponding blind holes by negative pressure to obtain the assembly. The assembly is debonded to obtain a third component; wherein the third component includes blind holes filled with superconducting metal; The third component is thinned so that the blind hole becomes a through hole and exposes the superconducting metal, forming an adapter plate.

2. The method according to claim 1, characterized in that, The fabrication of the first component based on the first substrate includes: A dielectric layer is grown on the first substrate; A microchannel structure is formed on the dielectric layer; The microchannel structure is filled with superconducting metal.

3. The method according to claim 2, characterized in that, The formation of the microchannel structure on the medium layer includes: Photolithography is performed on the dielectric layer to form a microchannel pattern; The microchannel structure is obtained by etching the dielectric layer based on the microchannel pattern.

4. The method according to claim 1, characterized in that, The fabrication of the second component based on the second substrate includes: A mask layer is grown on the second substrate; Blind hole patterns are photolithographically etched onto the mask layer; The second substrate is etched to form blind vias within the second substrate.

5. The method according to claim 1, characterized in that, The assembly is obtained by bonding the first component and the second component in a vacuum environment based on the correspondence between the microchannel structure and the blind holes, melting the superconducting metal, and filling the corresponding blind holes with the superconducting metal in the microchannel structure through negative pressure, thereby obtaining the following components: The first component and the second component are bonded in a vacuum environment so that the surfaces of the first component and the second component overlap, and the superconducting metal seals the corresponding blind holes; The superconducting metal is melted and an inert gas is introduced into the vacuum environment, so that the inert gas pushes the molten superconducting metal through the microchannel structure to fill the corresponding blind holes; The assembly is formed after the superconducting metal cools and solidifies.

6. A method for manufacturing a processor, characterized in that, The adapter plate according to any one of claims 1 to 5 includes: Spacer pillars are fabricated based on the aforementioned adapter plate, and superconducting metal is exposed as bumps. Dielectric layers are deposited on both surfaces of the adapter plate and wiring is performed to obtain the adapter plate layer; A processor is obtained by integrating spacers and bumps on an adapter plate layer with a core and a packaging substrate.

7. The method according to claim 6, characterized in that, The process of fabricating spacer pillars based on the adapter plate and exposing superconducting metal as bumps includes: Photolithography is performed on both surfaces of the adapter plate to form a preset pattern; the preset pattern is used to form spacer pillars and bumps. Based on the preset pattern, the two surfaces of the adapter plate are etched to obtain the spacer post and the protrusion.

8. The method according to claim 6, characterized in that, The spacer post and bump integrated core based on the transition plate layer includes: Balls are implanted on the pads on the surface of the core to form microbumps on the pads; The transition plate layer and the core are bonded based on the microbumps of the core and the spacers and bumps of the transition plate layer.

9. The method according to claim 8, characterized in that, The spacer post and bump integrated packaging substrate based on the adapter plate layer includes: The adapter layer and the packaging substrate are bonded based on the spacer pillars and bumps on the opposite side surface of the integrated core of the adapter layer.

10. The method according to any one of claims 6 to 9, characterized in that, The adapter plate layer has multiple layers, and correspondingly, the spacer pillars and bumps integrated cores and packaging substrates based on the adapter plate layer include: Each adapter board layer is stacked into a single unit using cores, and each adapter board layer integrates cores based on spacer pillars and bumps to obtain a multi-chip module. The packaging substrate is integrated through the spacers and bumps on the outer surface of the outermost adapter layer of the multi-chip module.

11. An adapter board, characterized in that, It is prepared by the method of any one of claims 1 to 5.

12. A processor, characterized in that, It is prepared by the method of preparation of the processor according to any one of claims 6 to 10.

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