Gold wire automatic paying-off method of semiconductor wire welding machine and related equipment of gold wire automatic paying-off method

Abstract

The invention discloses an automatic gold wire paying-off method of a semiconductor wire bonding machine and related equipment thereof, and the method comprises the steps: obtaining a first paying-off speed and a second paying-off speed within the continuous automatic paying-off time recorded by a controller; calculating a pay-off speed increment according to the first pay-off speed and the second pay-off speed; calculating an expected pay-off speed according to the initial pay-off speed and the pay-off speed increment; according to the expected pay-off speed change condition of each time period within the continuous automatic pay-off time, the change direction of the continuous pay-off speed is determined; according to the continuous paying-off speed change direction, a paying-off integral coefficient is calculated; and correcting the current paying-off speed according to the paying-off integral coefficient. The paying-off speed can be updated in real time based on the paying-off speed change rule, the gold wire paying-off speed can be accurately matched with the welding wire machining process by means of continuous change direction judgment and an integral coefficient adjustment mechanism, and the trend following capacity and stability are achieved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor wire bonding machine technology, and particularly relates to an automatic gold wire feeding method for a semiconductor wire bonding machine, a semiconductor wire bonding machine, processing equipment and storage medium. Background Technology

[0002] Semiconductor wire bonders are core equipment in semiconductor packaging processes, used to achieve electrical interconnection between chips and external circuits. Their performance directly affects the functionality and reliability of the chip. Semiconductor wire bonders use wire bonding technology to connect fine metal wires (such as gold wires, copper wires, and aluminum wires) to chip pads and substrate pads, forming a conductive path.

[0003] In semiconductor wire bonding machines, the wire feeding module is the core module responsible for feeding, positioning, and cutting the solder ribbon / wire. Its function is to achieve precise solder supply and process control through automated mechanisms, directly affecting welding quality and efficiency. The wire feeding module consists of a spool and a sensor. When the gold wire is in the dotted line area, the sensor cannot detect its presence and will continuously feed the spool within a set time until the gold wire is in the solid line position. At this point, the sensor detects the gold wire and the spool stops working. However, because the amount of gold wire used by the wire bonding machine's cutter is uncertain, while the amount of wire fed per unit time by the spool is fixed, inaccurate wire feeding can easily occur, making it impossible to accurately match the wire bonding process. For example, when the amount of gold wire used continuously exceeds the amount fed by the spool, wire breakage occurs. Conversely, when the amount of gold wire used continuously is less than the amount fed by the spool, the tension between the spool and the cutter is affected by the large amount of gold wire, impacting the wire bonding process and further affecting the quality of the wire bond. Summary of the Invention

[0004] The purpose of this application is to provide an automatic gold wire feeding method, apparatus, computer equipment, and storage medium for a semiconductor wire bonding machine, so as to solve the technical problems of inaccurate wire feeding and inability to accurately match the wire bonding process in existing semiconductor wire bonding machines.

[0005] Firstly, an automatic gold wire feeding method for a semiconductor wire bonding machine is provided, which adopts the following technical solution: An automatic gold wire feeding method for a semiconductor wire bonding machine includes: Within the continuous automatic wire feeding time recorded by the controller, the first wire feeding speed and the second wire feeding speed are obtained; Calculate the increment of the wire laying speed based on the first wire laying speed and the second wire laying speed; Calculate the desired casting speed based on the initial casting speed and the casting speed increment; The direction of change of continuous wire feeding speed is determined based on the expected changes in wire feeding speed during each time period within the continuous automatic wire feeding time. Calculate the integral coefficient of the continuous line laying speed based on the direction of change; The current laying speed is corrected based on the laying integral coefficient.

[0006] Furthermore, the steps of obtaining the first and second wire-feeding speeds within the continuous automatic wire-feeding time recorded by the controller specifically include: Retrieve the equipment operation logs recorded by the controller and parse the logs to obtain the line laying speed records; Based on a preset time period, a first time period and a second time period are extracted within the continuous automatic line laying time, wherein the first time period and the second time period are adjacent. The average casting speed corresponding to the first time period and the second time period is obtained from the casting speed record, thus obtaining the first casting speed and the second casting speed.

[0007] Furthermore, the increment of the line-laying speed is calculated based on the following formula:

[0008] In the formula, For the increment of the laying speed, The first laying speed, The second laying speed, It is a positive integer.

[0009] Furthermore, the desired line-laying speed is calculated based on the following formula:

[0010] In the formula, For the desired laying speed, The initial line-laying speed, For the increment of the laying speed, This is the coefficient of the rate of change of the laying speed.

[0011] Furthermore, the step of determining the direction of change of the continuous wire-laying speed based on the expected changes in wire-laying speed during each time period within the continuous automatic wire-laying time specifically includes: During the continuous automatic wire feeding time, the difference in expected wire feeding speed between adjacent time periods is calculated, and the speed change trend is determined based on the difference in expected wire feeding speed. Generate corresponding velocity change direction markers based on velocity change trends; The direction of change in continuous line laying speed is determined based on the sequence of directional markers in adjacent time periods.

[0012] Furthermore, the steps for calculating the integral coefficient of the continuous wire laying speed, based on the direction of change, specifically include: Obtain the direction of change of the expected laying speed in the current time period; Compare the direction of change of the expected laying speed in the current time period with the direction of change of the laying speed in the previous time period; When the direction of change of the expected laying speed in the current time period is the same as the direction of change of the laying speed in the previous time period, the integral increment is accumulated based on the preset initial integral coefficient. When the direction of change of the expected laying speed in the current time period is inconsistent with the direction of change of the laying speed in the previous time period, the integral coefficient will be cleared to zero.

[0013] Furthermore, the current line-laying speed is calculated based on the following formula:

[0014] In the formula, This is the current laying speed. The speed at which the line was laid out at the previous moment. For the desired laying speed, The integral coefficient for setting out lines, For the maximum line laying integral, This is the integral ratio coefficient for line laying.

[0015] Secondly, a semiconductor wire bonding machine is provided, which adopts the following technical solution: A semiconductor wire bonding machine includes a controller and a wire feeding module. The controller is a field-programmable gate array controller, and the wire feeding module performs the automatic gold wire feeding method of the semiconductor wire bonding machine as described above.

[0016] Thirdly, embodiments of this application provide a processing apparatus, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the automatic gold wire feeding method of the semiconductor wire bonding machine described in any of the first aspects above.

[0017] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the automatic gold wire laying method for a semiconductor wire bonding machine according to any one of the first aspects described above.

[0018] Fifthly, embodiments of this application provide a computer program product that, when running on a terminal device, causes the terminal device to execute the automatic gold wire laying method of the semiconductor wire bonding machine described in any of the first aspects above.

[0019] The beneficial effects of the embodiments of this application are: This application discloses an automatic gold wire feeding method and related equipment for a semiconductor wire bonding machine. The method involves acquiring a first feeding speed and a second feeding speed within a continuous automatic feeding time recorded by a controller; calculating the feeding speed increment based on the first and second feeding speeds; calculating the desired feeding speed based on the initial feeding speed and the feeding speed increment; determining the direction of continuous feeding speed change based on the changes in the desired feeding speed over different time periods within the continuous automatic feeding time; calculating the feeding integral coefficient based on the direction of continuous feeding speed change; and correcting the current feeding speed based on the feeding integral coefficient. This application can update the feeding speed in real time based on the feeding speed change pattern, and through the continuous change direction determination and integral coefficient adjustment mechanism, the gold wire feeding speed can accurately match the wire bonding process, exhibiting trend following capability and stability. Attached Figure Description

[0020] To more clearly illustrate the solutions in this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart illustrating the automatic gold wire feeding method for the semiconductor wire bonding machine provided in this application; Figure 2 This is a schematic diagram of the structure of a processing device provided in one embodiment of this application. Detailed Implementation

[0022] To make the technical problem to be solved, the technical solution and the beneficial effects of this application clearer, the following is in conjunction with the appendix. Figure 1-2 The present application will be further described in detail below with reference to embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

[0023] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0024] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0025] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0026] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0027] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0028] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0029] In a first aspect, an embodiment of this application provides an automatic gold wire feeding method for a semiconductor wire bonding machine. Figure 1 This is a schematic flowchart of an automatic gold wire feeding method for a semiconductor wire bonding machine according to an embodiment of this application. (Reference) Figure 1 The automatic gold wire feeding method for semiconductor wire bonding machines provided in the embodiments of this application includes steps S101 to S106.

[0030] S101, within the continuous automatic wire feeding time recorded by the controller, obtain the first wire feeding speed and the second wire feeding speed; Specifically, in implementation, the continuous wire-laying process is typically divided into several adjacent time periods using a fixed sampling period (e.g., 1 ms, 5 ms, or 10 ms, depending on the resolution of the motion controller and encoder). For each time period, a wire-laying speed sample is read from the equipment operation log or the real-time speed sampling buffer. The sample can be the linear velocity obtained from the encoder pulse count conversion, the stepper pulse frequency, or the speed feedback from the servo motor (the unit should be uniformly mm / s or µm / ms, etc.). Subsequently, the statistical speed values ​​of adjacent time periods (e.g., using the average speed within the segment as a representative value) are assigned as the first wire-laying speed and the second wire-laying speed, respectively, and the corresponding timestamps are recorded in the data structure for use in gain adjustment and anomaly detection.

[0031] To reduce transient errors, the original velocity samples within each segment should be denoised first, for example, by using an in-window arithmetic mean, weighted average, or median filter; if severely affected by impact noise, an impulse removal algorithm can be used.

[0032] Furthermore, the steps of obtaining the first and second wire-feeding speeds within the continuous automatic wire-feeding time recorded by the controller specifically include: Retrieve the equipment operation logs recorded by the controller and parse the logs to obtain the line laying speed records; Based on a preset time period, a first time period and a second time period are extracted within the continuous automatic line laying time, wherein the first time period and the second time period are adjacent. The average casting speed corresponding to the first time period and the second time period is obtained from the casting speed record, thus obtaining the first casting speed and the second casting speed.

[0033] Specifically, the selection of the preset time period needs to comprehensively consider equipment characteristics and process requirements. For example, for high-speed wire bonding scenarios, it can be set to 5ms to capture subtle speed fluctuations, while for low-speed scenarios, it can be extended to 20ms to reduce data processing volume. When obtaining the average wire laying speed, all speed sampling points in the first and second time periods need to be calculated with equal weights or dynamic weights. The dynamic weights can be allocated according to the distance between the sampling point and the midpoint of the time period to suppress endpoint effects. When there is missing data in the equipment operation log, linear interpolation or cubic spline interpolation methods should be used to fill in the missing values ​​to ensure the continuity of the average wire laying speed calculation.

[0034] In addition, to improve the robustness of the algorithm, the average wire-laying speed can be threshold-filtered to remove outliers that exceed the physical limits of the equipment. For example, data that exceeds the maximum wire-laying speed by 1.5 times or is less than the minimum wire-laying speed by 0.5 times can be marked as invalid and resampled.

[0035] S102, Calculate the wire laying speed increment based on the first wire laying speed and the second wire laying speed; Specifically, the increment of the line-laying speed is calculated based on the following formula:

[0036] In the formula, For the increment of the laying speed, The first laying speed, The second laying speed, It is a positive integer.

[0037] This is achieved by comparing the difference in average wire-laying velocity between adjacent time periods. For example, when the average velocity in the first time period is 1200 μm / ms and in the second time period is 1150 μm / ms, the increment is... =1200-1150=50μm / ms. This calculation needs to be completed synchronously in the FPGA (Field Programmable Gate Array) controller through the parallel computing unit to ensure that the speed difference calculation and storage are completed within each sampling period (e.g., 5ms).

[0038] To suppress sampling noise, a moving average filter can be applied to the incremental values ​​over three consecutive periods. For example, when sampling noise is detected... =50、 =48、 When =52, the final adoption is =(50+48+52) / 3=50μm / ms as the effective increment value.

[0039] In particular, when a sudden speed change occurs during the equipment startup or emergency stop phase, an abnormal handling process needs to be triggered by judging through a dynamic threshold (such as setting the sudden change threshold to 200μm / ms). At this time, the integral coefficient update is paused and the backup PID control unit is started.

[0040] This step allows for precise quantification of the variation in the wire-laying speed over adjacent time periods, enabling the calculation of the desired wire-laying speed based on this variation.

[0041] S103, Calculate the desired wire laying speed based on the initial wire laying speed and the wire laying speed increment; Specifically, the desired line-laying speed is calculated based on the following formula:

[0042] In the formula, For the desired laying speed, The initial line-laying speed, For the increment of the laying speed, This is the coefficient of the rate of change of the laying speed.

[0043] The expected wire release speed is a target value calculated by the algorithm. It reflects the speed at which the system should release gold wire to meet the cutting blade's demand for gold wire at the current moment. The expected wire release speed is dynamically adjusted according to the actual production situation. The expected wire release speed can be adjusted based on the real-time demand for gold wire from the cutting blade, ensuring the timeliness and accuracy of gold wire supply.

[0044] The calculation of the desired casting speed needs to combine the initial casting speed with the currently detected casting speed increment. For example, when the initial casting speed... The setting is 1000 μm / ms, and the increment of the wire release speed is calculated in step S102. When = 50 μm / ms, according to the formula (in, The coefficient for the rate of change of the wire feeding speed needs to be pre-calibrated based on the dynamic characteristics of the equipment (typically ranging from 0.8 to 1.2) to determine the desired wire feeding speed. If... If we take 1.0, then... =1000+50×1.0=1050μm / ms. This calculation process needs to be implemented in the FPGA controller through a fixed-point arithmetic unit to ensure real-time performance within a 1ms sampling period, while an overflow protection mechanism is used to prevent the value from exceeding the physical limits of the device (such as the maximum wire laying speed of 1500μm / ms).

[0045] Its main function is to dynamically adjust the current wire-laying speed based on the historical changes in wire-laying time (i.e., the increasing or decreasing trend of wire-laying speed) to achieve adaptive control. When the wire-laying time increases (i.e., the wire-laying speed decreases), and The product of will increase the current wire feeding speed; conversely, when the wire feeding time decreases (i.e., the wire feeding speed increases), the product will decrease the current wire feeding speed.

[0046] Specifically, when detected If the speed remains below a set threshold (e.g., 10 μm / ms) for three consecutive cycles, steady-state optimization logic needs to be triggered by reducing the speed. The value (e.g., adjusted to 0.9) suppresses the interference of small fluctuations on the system.

[0047] This step allows for the precise calculation of the desired wire-laying speed based on the initial wire-laying speed and the currently detected increment, combined with a pre-calibrated wire-laying speed change rate coefficient determined by the equipment's dynamic characteristics. This calculation process fully considers the real-time and stability requirements of the equipment operation, ensuring efficiency and accuracy through the fixed-point arithmetic unit and overflow protection mechanism of the FPGA controller. Furthermore, the introduction of steady-state optimization logic further enhances the system's anti-interference capability under minute fluctuations, making the calculation of the desired wire-laying speed more closely reflect actual needs.

[0048] S104, Determine the direction of change of continuous wire feeding speed based on the expected changes in wire feeding speed during each time period within the continuous automatic wire feeding time. Specifically, during the continuous automatic wire laying process, the expected wire laying speed for each time period needs to be continuously monitored. First, the expected wire laying speed value for each time period is recorded sequentially using the timer module built into the FPGA controller at preset sampling intervals (e.g., 5ms). Then, the difference between the expected wire laying speed of the current time period and the previous time period is calculated. For example, if the expected speed for the nth time period is 1050μm / ms and the expected speed for the (n-1)th time period is 1000μm / ms, the difference is calculated. =1050-1000=50μm / ms. The direction of velocity change is determined by the sign of the difference: if... If >0, then mark the current direction as "accelerate" (DIR[n]=1); if If <0, it is marked as "deceleration" (DIR[n]=0); if If the value is 0, then the previous direction mark is retained.

[0049] To improve noise immunity, majority voting filtering can be applied to the direction markers for three consecutive cycles. For example, when DIR[n-2]=1, DIR[n-1]=1, and DIR[n]=0, DIR=1 is ultimately used as the valid direction marker.

[0050] Specifically, when a sudden change in direction (such as from acceleration to deceleration) is detected and the absolute value of the difference exceeds the dynamic threshold (such as 200 μm / ms), the abnormal handling process needs to be triggered to suspend the integral coefficient update and switch to the backup PID control mode.

[0051] This step generates time series markers (such as DIR[1], DIR[2], DIR[3], ..., DIR[n]) for the direction of continuous wire laying speed change, so as to calculate the integral coefficients.

[0052] Furthermore, the step of determining the direction of change of the continuous wire-laying speed based on the expected changes in wire-laying speed during each time period within the continuous automatic wire-laying time specifically includes: During the continuous automatic wire feeding time, the difference in expected wire feeding speed between adjacent time periods is calculated, and the speed change trend is determined based on the difference in expected wire feeding speed. Generate corresponding velocity change direction markers based on velocity change trends; The direction of change in continuous line laying speed is determined based on the sequence of directional markers in adjacent time periods.

[0053] Specifically When calculating the difference in expected laying speed between adjacent time periods, it is necessary to ensure that the time period division is consistent with the sampling period. For example, the time periods should be divided into 5ms intervals, and the average expected laying speed within each time period should be calculated separately. Then, the difference is obtained by comparing the average expected laying speed of the current time period with that of the previous time period. .like If positive, the trend of speed change is acceleration; if... If it is negative, the trend of velocity change is deceleration; if If the value is zero, the speed remains unchanged. Based on this trend, a corresponding speed change direction marker DIR[n] is generated, where acceleration is marked as 1, deceleration as 0, and the previous marker is retained when there is no change.

[0054] Furthermore, to improve the accuracy of direction determination, a sliding window process can be applied to the direction markers for three consecutive time periods, and a majority voting mechanism can be used to determine the final direction marker. For example, when two or more of the three markers are 1, the final marker is 1. Simultaneously, special handling is required for sudden changes in direction. When a sudden change in the direction markers between adjacent time periods is detected (e.g., from 1 to 0) and the absolute value of the difference exceeds a preset threshold (e.g., 200 μm / ms), an exception handling procedure is triggered, pausing the integral coefficient update and switching to a backup PID control mode to ensure system stability.

[0055] This step generates a time series marker indicating the direction of change in the continuous wire feeding speed.

[0056] S105, Calculate the integral coefficient of the continuous line laying speed according to the direction of change; Specifically, the integral coefficient register is set within the FPGA controller. Its initial value is 0, and the integration increment is preset. (This value needs to be pre-calibrated based on the dynamic characteristics of the equipment, for example, a typical range of 0.01-0.1) and maximum value. (e.g., set to 1.0). When the expected direction of change of the casting speed DIR[n] is the same as DIR[n-1] for two consecutive time periods (i.e., the speed continues to accelerate or decelerate), the current integral coefficient will be adjusted. Increase the points increment (Right now + If the direction markings are different (i.e., the speed changes from acceleration to deceleration or from deceleration to acceleration), then the integral coefficient will be... Reset to 0. For example, when DIR[n]=1 and DIR[n-1]=1, Value accumulation When DIR[n]=0 and DIR[n-1]=1, The value is cleared to zero. This process must be completed within each sampling period (e.g., 5ms) and ensured through an overflow protection mechanism. Value not exceeding .

[0057] This step generates integral coefficients that are strongly correlated with the speed change trend, providing a basis for dynamic adjustment of speed compensation.

[0058] Furthermore, the steps for calculating the integral coefficient of the continuous wire laying speed, based on the direction of change, specifically include: Obtain the direction of change of the expected laying speed in the current time period; Compare the direction of change of the expected laying speed in the current time period with the direction of change of the laying speed in the previous time period; When the direction of change of the expected laying speed in the current time period is the same as the direction of change of the laying speed in the previous time period, the integral increment is accumulated based on the preset initial integral coefficient. When the direction of change of the expected laying speed in the current time period is inconsistent with the direction of change of the laying speed in the previous time period, the integral coefficient will be cleared to zero.

[0059] Specifically Pre-setting the integral coefficient register within the FPGA controller The initial value (e.g., 0) and the integral increment (Typical value 0.05), while setting an upper limit for the integral coefficient. (e.g., 1.0). Within each sampling period (5ms), the direction marker DIR[n] of the current time period is compared with DIR[n-1] of the previous time period: if they are the same (acceleration → acceleration or deceleration → deceleration), then execution is performed. + The accumulation operation is performed, and an overflow protection mechanism is used to ensure... ≤ If the direction markings are different (acceleration → deceleration or deceleration → acceleration), then... Reset to 0. For example, when DIR[1]=1, DIR[2]=1, and DIR[3]=0 are detected for three consecutive cycles, the first two cycles The value accumulates to 0.1, and the third cycle occurs due to a sudden change in direction. The value is reset to zero.

[0060] This mechanism enhances the system's compensation capability when the velocity continuously changes by dynamically adjusting the integral coefficient. Increase), while quickly eliminating accumulated error when the velocity direction reverses ( (Zeroing), thereby improving the stability and response speed of the wire feeding speed control.

[0061] S106, Correct the current wire laying speed according to the wire laying integral coefficient.

[0062] Specifically, the current line-laying speed is calculated based on the following formula:

[0063] In the formula, This is the current laying speed. The speed at which the line was laid out at the previous moment. For the desired laying speed, The integral coefficient for setting out lines, For the maximum line laying integral, This is the integral ratio coefficient for line laying.

[0064] This formula introduces an integral coefficient. This enables dynamic correction of the wire-laying speed. Specifically, the current wire-laying speed... It consists of three parts: the speed of laying the line at the previous moment. As a benchmark, the expected laying speed and The difference ( The integral coefficient reflects the speed adjustment requirements. With the maximum integral value The ratio ( This determines the adjustment range. For example, when =1000μm / ms =1050μm / ms =0.5、 When =1.0, the current laying speed =1000+(1050-1000)×0.5=1025μm / ms.

[0065] This calculation needs to be implemented within the FPGA controller using a floating-point arithmetic unit, and must be ensured through limiting processing. Not exceeding the physical limits of the device (e.g., 1500 μm / ms). Integral coefficient. Its function is to: when the speed continuously deviates from the expected value (such as continuous acceleration or deceleration). The value increases through accumulation, thereby strengthening the correction; when the velocity direction reverses, Set the value to zero to avoid over-correction.

[0066] Through this step, the system can dynamically adjust the wire feeding speed based on historical speed change trends and current expected values, achieving more precise control over the gold wire supply.

[0067] In the above embodiments, this application discloses an automatic gold wire feeding method for a semiconductor wire bonding machine. The method involves acquiring a first feeding speed and a second feeding speed within a continuous automatic feeding time recorded by the controller; calculating the feeding speed increment based on the first and second feeding speeds; calculating the desired feeding speed based on the initial feeding speed and the feeding speed increment; determining the direction of continuous feeding speed change based on the changes in the desired feeding speed over different time periods within the continuous automatic feeding time; calculating the feeding integral coefficient based on the direction of continuous feeding speed change; and correcting the current feeding speed based on the feeding integral coefficient. This application can update the feeding speed in real time based on the feeding speed change pattern, and through the continuous change direction determination and integral coefficient adjustment mechanism, the gold wire feeding speed can accurately match the wire bonding process, exhibiting trend following capability and stability.

[0068] Corresponding to the methods in the above embodiments, only the parts related to the embodiments of this application are shown for ease of explanation.

[0069] Secondly, this application provides a semiconductor wire bonding machine, which includes a controller and a wire feeding module. The controller is a field-programmable gate array controller, and the wire feeding module performs the automatic gold wire feeding method of the semiconductor wire bonding machine as described above.

[0070] FPGA (Field Programmable Gate Array) is an integrated chip primarily used for digital circuits. Internally, it consists of numerous programmable logic units (such as lookup tables (LUTs) and flip-flops (FFs). These logic units can be combined and connected like gate circuits to implement various digital logic functions. FPGAs can be customized and configured according to user needs to achieve different functions and applications.

[0071] FPGAs offer far greater flexibility than traditional Application-Specific Integrated Circuits (ASICs). Functionality can be rapidly adjusted via software programming without redesigning hardware circuits, making them particularly suitable for industrial control scenarios requiring frequent iterations or customized features. In semiconductor wire bonding machines, the FPGA controller undertakes the core computing tasks: it processes complex logic such as wire feeding speed calculations and integral coefficient updates in real time using its built-in fixed-point / floating-point arithmetic units, while simultaneously utilizing timer modules to achieve millisecond-level sampling cycle control, ensuring synchronization between wire supply and wire bonding processing. Its multi-channel parallel processing capability allows for simultaneous monitoring of the status of multiple wire feeding modules, and mechanisms such as overflow protection and amplitude limiting ensure system stability. Compared to traditional microcontrollers (MCUs), the hardware-level parallel computing architecture of FPGAs reduces speed correction response latency to the microsecond level, significantly improving the dynamic tracking accuracy of wire feeding, making it especially suitable for high-precision, high-speed semiconductor packaging scenarios.

[0072] Thirdly, this application provides a processing device. Figure 2 This is a schematic diagram of the structure of a processing device provided in one embodiment of this application. Figure 2 As shown, the processing equipment 2 in this embodiment includes: at least one processor 20 ( Figure 2 Only one is shown in the diagram), memory 21, and computer program 22 stored in memory 21 and executable on at least one processor 20; when processor 20 executes computer program 22, it implements the steps in the various method embodiments described above.

[0073] The processing equipment may include, but is not limited to, processor 20 and memory 21. Those skilled in the art will understand that... Figure 2 This is merely an example of processing equipment and does not constitute a limitation on the processing equipment. It may include more or fewer components than shown in the figure, or combinations of certain components, or different components. For example, it may also include input / output devices, network access devices, buses, etc.

[0074] The processor 20 can be a Central Processing Unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0075] In some embodiments, memory 21 may be an internal storage unit of the processing equipment 2, such as a hard drive or memory of the processing equipment. In other embodiments, memory 21 may be an external storage device of the processing equipment, such as a plug-in hard drive, smart media card (SMC), secure digital (SD) card, flash card, etc., provided on the processing equipment. Furthermore, memory 21 may include both internal and external storage units of the processing equipment. Memory 21 is used to store operating systems, applications, bootloaders, data, and other programs, such as program code for computer programs. Memory 21 may also be used to temporarily store data that has been output or will be output.

[0076] For example, computer program 22 may be divided into one or more modules / units, one or more of which are stored in memory 21 and executed by processor 20 to complete this application. One or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of computer program 22 in processing equipment 2.

[0077] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0078] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0079] If the aforementioned integrated units are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. This computer program can be stored in a computer-readable storage medium; when executed by a processor, the computer program can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. Computer-readable media include: any entity or device capable of carrying computer program code to a device / terminal equipment, recording media, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0080] Fourthly, embodiments of this application also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.

[0081] Fifthly, embodiments of this application provide a computer program product that, when run on a terminal device, enables the terminal device to implement the steps described in the various method embodiments above.

[0082] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0083] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0084] In the embodiments provided in this application, it should be understood that the disclosed apparatus / device and method can be implemented in other ways. For example, the apparatus / device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0085] The units described above as separate components may or may not be physically separate. Similarly, the components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0086] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A gold wire automatic pay-off method for a semiconductor wire bonder, characterized by, The method comprises the following steps: acquiring a first wire feeding speed and a second wire feeding speed within a continuous automatic wire feeding time recorded by a controller; calculating a wire feeding speed increment based on the first wire feeding speed and the second wire feeding speed; calculating an expected wire feeding speed based on an initial wire feeding speed and the wire feeding speed increment; determining a continuous wire feeding speed change direction based on a change of the expected wire feeding speed in each time period within the continuous automatic wire feeding time; calculating a wire feeding integral coefficient based on the continuous wire feeding speed change direction; and correcting a current wire feeding speed based on the wire feeding integral coefficient.

2. The gold wire automatic pay-off method of a semiconductor wire bonder according to claim 1, wherein The step of acquiring the first wire feeding speed and the second wire feeding speed within the continuous automatic wire feeding time recorded by the controller comprises the following steps: calling a device operation log recorded by the controller and parsing the device operation log to acquire a wire feeding speed record; acquiring a first time period and a second time period within the continuous automatic wire feeding time based on a preset time period length, wherein the first time period and the second time period are adjacent; and acquiring average wire feeding speeds corresponding to the first time period and the second time period from the wire feeding speed record to obtain the first wire feeding speed and the second wire feeding speed.

3. The gold wire automatic pay-off method of a semiconductor wire bonder according to claim 1, wherein The wire feeding speed increment is calculated based on the following formula: wherein is an increment of the payout speed, is a first payout speed, is a second payout speed, is a positive integer.

4. The gold wire automatic pay-off method of a semiconductor wire bonder according to claim 1, wherein The expected wire feeding speed is calculated based on the following formula: wherein is the desired pay-out speed, is the initial pay-out speed, is the pay-out speed increment, is the pay-out speed change rate coefficient.

5. The gold wire automatic pay-off method of a semiconductor wire bonder as recited in claim 2, wherein, The step of determining the continuous wire feeding speed change direction based on the change of the expected wire feeding speed in each time period within the continuous automatic wire feeding time comprises the following steps: calculating an expected wire feeding speed difference value of adjacent time periods within the continuous automatic wire feeding time and determining a speed change trend based on the expected wire feeding speed difference value; generating a corresponding speed change direction mark based on the speed change trend; and determining the continuous wire feeding speed change direction based on a sequence of direction marks of adjacent time periods.

6. The gold wire automatic pay-off method of a semiconductor wire bonder as recited in claim 1, wherein, The step of calculating the wire feeding integral coefficient based on the continuous wire feeding speed change direction comprises the following steps: acquiring an expected wire feeding speed change direction of a current time period; comparing the expected wire feeding speed change direction of the current time period with a wire feeding speed change direction of a previous time period; when the expected wire feeding speed change direction of the current time period is consistent with the wire feeding speed change direction of the previous time period, accumulating an integral increment on the basis of a preset initial integral coefficient; when the expected wire feeding speed change direction of the current time period is not consistent with the wire feeding speed change direction of the previous time period, performing zero processing on the integral coefficient.

7. The gold wire automatic pay-off method of a semiconductor wire bonder as claimed in claim 6, wherein The current wire feeding speed is calculated based on the following formula: wherein is the current pay-off speed, is the previous pay-off speed, is the desired pay-off speed, is the pay-off integral coefficient, is the maximum pay-off integral, is the pay-off integral proportionality coefficient.

8. A semiconductor wire bonder comprising a controller and a wire feed module, characterized by, The controller is a field programmable gate array controller, and the wire feeding module executes the gold wire automatic feeding method of the semiconductor wire bonding machine as described in any one of claims 1 to 7.

9. A processing apparatus characterized by comprising: The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the gold wire automatic feeding method of the semiconductor wire bonding machine as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, and the computer program is executed by the processor to implement the gold wire automatic feeding method of the semiconductor wire bonding machine as described in any one of claims 1 to 7.

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