Semiconductor element with dam structure covering substrate slot

Abstract

The invention provides a semiconductor element and a preparation method thereof. The semiconductor element comprises a substrate, an electronic element, a packaging piece and a dam structure. The substrate has a lower surface and an upper surface opposite to the lower surface. The electronic component is disposed on the upper surface of the substrate. The package is disposed on the upper surface of the substrate and has a portion penetrating the substrate. The dam structure vertically overlaps the portion of the package.

Description

[0001] Cross-referencing

[0002] This application claims priority to U.S. Patent Application No. 18 / 909,144 (i.e., priority date "October 8, 2024"), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device and a method for fabricating the same. In particular, it relates to a semiconductor device having a dam structure having a narrow groove covering a substrate. Background Technology

[0004] With the rapid development of the electronics industry, integrated circuits (ICs) have achieved high efficiency and miniaturization. Advances in integrated circuit materials and design technologies have led to the creation of generation after generation of integrated circuits, each generation becoming smaller and more complex.

[0005] Many technologies have been developed to improve the performance of semiconductor devices. For example, decoupling capacitor structures can be used to filter signals with a specific frequency. However, such decoupling capacitor structures may occupy additional area, thereby increasing the size of the semiconductor device. Therefore, there is a need for improved semiconductor devices and methods to address such problems.

[0006] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this disclosure. Summary of the Invention

[0007] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, an electronic component, a package, and a dam structure. The substrate has a lower surface and an upper surface opposite the lower surface. The electronic component is disposed on the upper surface of the substrate. The package is disposed on the upper surface of the substrate and has a portion extending through the substrate. The dam structure vertically overlaps with the portion of the package.

[0008] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, an electronic component, a package, and a dam structure. The substrate has a lower surface and an upper surface opposite the lower surface. The electronic component is disposed on the upper surface of the substrate. The package is disposed on the upper surface of the substrate and has a portion extending through the substrate. The substrate and the dam structure define a package injection groove. A first aperture of the package injection groove adjacent to the upper surface of the substrate and a second aperture of the package injection groove adjacent to the lower surface of the substrate are different.

[0009] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate having a lower surface and an upper surface opposite the lower surface, wherein the substrate defines a package injection groove penetrating the lower surface and the upper surface; forming an electronic device on the upper surface of the substrate; forming a dam structure on the substrate to reduce the aperture of an aperture in the package injection groove; and forming a package on the substrate.

[0010] When an encapsulant is formed on the substrate, a mold chase is used to accommodate the substrate with a slot. Next, molding material is filled into the mold and flows through the slot from the upper surface of the substrate (e.g., the surface on which an electronic component is disposed) to the lower surface of the substrate. In a comparative example component, the molding material may encroach on an undesired area of ​​the lower surface of the substrate (e.g., an area where solder balls are disposed), which can lead to electrical connection failure between components. One reason for molding material overflow is that the slot has a large aperture, especially a large dimension along the X direction. In this embodiment, a dam structure is provided to reduce the area (or aperture) of the slot to prevent the encapsulant from encroaching on the undesired area of ​​the substrate. This solves the problem of the comparative example component.

[0011] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0012] A more complete understanding of this disclosure can be obtained by referring to the embodiments and claims. This disclosure should also be understood to be associated with the element numbers in the drawings, which represent similar elements throughout the description.

[0013] Figure 1A This is a top view schematic diagram illustrating semiconductor elements of some embodiments of the present disclosure.

[0014] Figure 1B This is a cross-sectional schematic diagram illustrating some embodiments of this disclosure, for example. Figure 1A The semiconductor device shown is shown in cross section along line A-A'.

[0015] Figure 1C This is a cross-sectional schematic diagram illustrating some embodiments of this disclosure, for example. Figure 1A The semiconductor device shown is a cross-section along section line B-B'.

[0016] Figure 2A This is a top view schematic diagram illustrating semiconductor elements of some embodiments of the present disclosure.

[0017] Figure 2B This is a cross-sectional schematic diagram illustrating some embodiments of this disclosure, for example. Figure 2A The semiconductor device shown is shown in cross-section along section line C-C'.

[0018] Figure 2C This is a cross-sectional schematic diagram illustrating some embodiments of this disclosure, for example. Figure 2A The semiconductor device shown is shown in cross section along section line D-D'.

[0019] Figure 3A This is a top view schematic diagram illustrating semiconductor elements of some embodiments of the present disclosure.

[0020] Figure 3B This is a cross-sectional schematic diagram illustrating some embodiments of this disclosure, for example. Figure 3A The semiconductor device shown is shown in cross-section along section line E-E'.

[0021] Figure 3C This is a cross-sectional schematic diagram illustrating some embodiments of this disclosure, for example. Figure 3A The semiconductor device shown is a cross-section along section line F-F'.

[0022] Figure 4A This is a top view schematic diagram illustrating semiconductor elements of some embodiments of the present disclosure.

[0023] Figure 4B This is a cross-sectional schematic diagram illustrating some embodiments of this disclosure, for example. Figure 4A The semiconductor device shown is shown in cross-section along section line G-G'.

[0024] Figure 4C This is a cross-sectional schematic diagram illustrating some embodiments of this disclosure, for example. Figure 4A The semiconductor device shown is a cross-section along section line H-H'.

[0025] Figure 5 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0026] Figure 6A This is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0027] Figure 6B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 6A The section along line A-A'.

[0028] Figure 6C This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 6A The section along line B-B'.

[0029] Figure 7A This is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0030] Figure 7B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 7A The section along line A-A'.

[0031] Figure 7C This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 7A The section along line B-B'.

[0032] Figure 8A This is a cross-sectional schematic diagram illustrating one or more stages of an example of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0033] Figure 8B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 8A The section along line A-A'.

[0034] Figure 8C This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 8A The section along line B-B'.

[0035] Explanation of reference numerals in the attached figures:

[0036] 1a: Semiconductor element

[0037] 1b: Semiconductor components

[0038] 1c: Semiconductor components

[0039] 1d: Semiconductor element

[0040] 2: Preparation method

[0041] 10: Base

[0042] 10s1: Surface

[0043] 10s2: Surface

[0044] 20: Opening

[0045] 20p1: End

[0046] 20p2: Central Section

[0047] 20s1: Side

[0048] 20s2: Side

[0049] 30: Electronic components

[0050] 30s1: Surface

[0051] 32: Adhesive

[0052] 42: Dam Structure

[0053] 42s1: Surface

[0054] 42s2: Surface

[0055] 42s3: Surface

[0056] 44: Dam Structure

[0057] 46: Dam Structure

[0058] 46s1: Surface

[0059] 50: Package

[0060] 50p1: Partial

[0061] 50s1: Surface

[0062] 50s2: Surface

[0063] 60: Wire

[0064] 70: Electronic connector

[0065] 202: Steps

[0066] 204: Steps

[0067] 206: Steps

[0068] AR1: Area

[0069] AR2: Area

[0070] L1: First Length

[0071] L2: Second Length

[0072] L3: Third Length

[0073] L4: Fourth Length

[0074] T1: Thickness

[0075] T2: Thickness

[0076] W1: Width

[0077] X: Direction

[0078] Y: direction

[0079] Z: Direction Detailed Implementation

[0080] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0081] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0082] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include multiple forms unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0083] Figure 1A , Figure 1B and Figure 1C Semiconductor element 1a is illustrated in some embodiments of this disclosure. Figure 1A It is a top view. Figure 1B and Figure 1C They are along Figure 1AThe cross-sectional schematic diagrams along lines A-A' and B-B' are shown. In some embodiments, semiconductor element 1a may include a double data rate fifth-generation synchronous dynamic random-access memory (DDR5 SDRAM) or a derivative thereof.

[0084] In some embodiments, semiconductor element 1a may include a substrate 10. In some embodiments, for example, substrate 10 may be or include a printed circuit board (PCB), such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate.

[0085] In some embodiments, the substrate 10 may include a surface 10s1 and a surface 10s2 opposite to the surface 10s1. In some embodiments, the surface 10s1 may also be referred to as a lower surface. In some embodiments, the surface 10s2 may also be referred to as an upper surface.

[0086] In some embodiments, substrate 10 may include conductive pads, traces, vias, layers, or other interconnects adjacent to surfaces 10s1 and 10s2. For example, substrate 10 may include one or more transmission lines (e.g., communication wires) and one or more ground lines and / or ground planes.

[0087] In some embodiments, the substrate 10 may define an opening 20 (or slot or aperture). The opening 20 may have a plurality of longer edges extending in the Y direction and a plurality of shorter edges connecting the longer edges.

[0088] like Figure 1AAs shown, the opening 20 may have multiple terminal portions 20p1 located on opposite sides of the longer edge. The terminal portions 20p1 may have a curved profile (e.g., a hemispherical profile) or other suitable profile. The opening 20 may have a central portion 20p2 extending between the two terminal portions 20p1. In some embodiments, the central portion 20p2 may have a substantially uniform width along the X direction. In some embodiments, the width W1 of the central portion 20p2 of the opening 20 may be greater than 1100 μm, for example, 1100 μm, 1200 μm, 1300 μm, 1400 μm, 1500 μm, or greater. In some embodiments, the opening 20 may be configured to allow a molding material (or encapsulant material) to pass through during the formation of an encapsulant. In some embodiments, the opening 20 may also be referred to as an encapsulant-injection slot.

[0089] In some embodiments, semiconductor element 1a may include an electronic element 30. The electronic element 30 may be disposed on or above the surface 10s2 of substrate 10. In some embodiments, the electronic element 30 may cover a portion of opening 20. In some embodiments, an end 20p1 of opening 20 may be exposed from electronic element 30. In some embodiments, a portion of the central portion 20p2 of opening 20 may be covered by electronic element 30. In some embodiments, a portion of the central portion 20p2 of opening 20 may be exposed from electronic element 30.

[0090] Electronic component 30 may include a memory element, such as a dynamic random access memory (DRAM) element, an over-the-top (OTP) memory element, a static random access memory (SRAM) element, or other suitable memory element. In some embodiments, electronic component 30 may include logic elements (e.g., system-on-a-chip (SoC), central processing unit (CPU), graphics processing unit (GPU), application processor (AP), microcontroller, etc.), radio frequency (RF) elements, sensor elements, microelectromechanical systems (MEMS) elements, signal processor elements (e.g., digital signal processing (DSP) elements), front-end elements (e.g., analog front-end (AFE) elements), or other elements.

[0091] In some embodiments, the electronic component 30 may be attached to the substrate 10 by an adhesive 32. In some embodiments, the adhesive 32 may include a die-attach film (DAF) or other suitable material.

[0092] In some embodiments, the electronic component 30 may have an active surface facing the substrate 10 and a passive surface opposite to the active surface. However, this disclosure is not intended to be limiting.

[0093] In some embodiments, the semiconductor element 1a may include a dam structure 42 and a dam structure 44. In some embodiments, the dam structure 42 and the dam structure 44 may be disposed on opposite sides of the electronic element 30. In some embodiments, the dam structure 42 may be disposed on or above the surface 10s2 of the substrate 10. In some embodiments, the dam structure 44 may be disposed on or above the surface 10s2 of the substrate 10. In some embodiments, the dam structure 42 may cover or perpendicularly overlap the end portion 20p1 of the opening 20. In some embodiments, the dam structure 44 may cover or perpendicularly overlap the end portion 20p1 of the opening 20. The dam structure 42 (or 44) may be attached to the substrate 10 by means of an adhesive or other suitable material.

[0094] In some embodiments, dam structure 42 (or dam structure 44) may be configured to reduce the area of ​​opening 20 through which the package passes. In some embodiments, dam structure 42, dam structure 44, opening 20, and / or electronic component 30 may be configured to define a package injection groove to allow a package material to pass through. Figure 1C As shown, the opening 20 defined by the substrate 10, electronic component 30, dam structure 42, and dam structure 44 may have a first length L1 at the surface 10s2 of the substrate 10 along the Y direction and a second length L2 at the surface 10s1 of the substrate 10. In some embodiments, the first length L1 may be different from the second length L2. In some embodiments, the first length L1 may be smaller than the second length L2.

[0095] In some embodiments, dam structure 42 and dam structure 44 may include a dummy die, such as a silicon dummy die, a glass dummy die, a plastic dummy die, a ceramic dummy die, or other suitable material.

[0096] In some embodiments, semiconductor element 1a may include a package 50 (or a molding compound). In some embodiments, package 50 may be disposed on or below surface 10s1 of substrate 10. A portion of surface 10s1 may be exposed from package 50. In some embodiments, package 50 may be disposed on or above surface 10s2 of substrate 10. In some embodiments, package 50 may encapsulate electronic element 30. In some embodiments, package 50 may encapsulate dam structure 42 (or dam structure 44). In some embodiments, package 50 may contact a portion of surface 42s1 (or a lower surface) of dam structure 42. In some embodiments, package 50 may contact surface 42s2 (or an upper surface) of dam structure 42. In some embodiments, package 50 may contact surface 42s3 (or a side surface) of dam structure 42.

[0097] In some embodiments, a portion 50p1 may be disposed within the opening 20. In some embodiments, the portion 50p1 may extend through the substrate 10. In some embodiments, the dam structure 42 may cover or vertically overlap the portion 50p1 of the package 50. In some embodiments, the dam structure 44 may cover or vertically overlap the portion 50p1 of the package 50. In some embodiments, the electronic component 30 may cover or vertically overlap the portion 50p1 of the package 50.

[0098] In some embodiments, for example, the package 50 may include a molding material, which may include a novolac-based resin, an epoxy-based resin, a silicone-based resin, or other suitable encapsulant. It may also include a suitable filler, such as powdered SiO2.

[0099] In some embodiments, the semiconductor element 1a may include a plurality of wires 60. In some embodiments, the wires 60 may be configured to electrically connect the substrate 10 and the electronic element 30. In some embodiments, the wires 60 may pass through the opening 20. In some embodiments, each wire 60 may have a first end connected to a surface 10s1 of the substrate 10 and a second end connected to an active surface of the electronic element 30 (e.g., the lower surface of the electronic element 30).

[0100] In some embodiments, the wire 60 may be encapsulated by the package 50. In some embodiments, the wire 60 may include a metal, such as copper (Cu), silver (Ag), gold (Au), nickel (Ni), aluminum (Al), alloys thereof, combinations thereof, or other suitable materials.

[0101] In some embodiments, the semiconductor element 1a may include a plurality of electronic connectors 70. In some embodiments, the electronic connectors 70 may be disposed on or below the surface 10s1 of the substrate 10. The electronic connectors 70 may be configured to provide an external connection. The electronic connectors 70 may be electrically connected to an external component (e.g., a semiconductor die or a circuit board). The electronic connectors 70 may include a soldering material, such as an alloy of gold and tin solder or an alloy of silver and tin solder.

[0102] When a package is formed on a substrate, a mold is used to receive the substrate with a slot. Next, a molding material is filled into the mold and flows through the slot from the upper surface of the substrate (e.g., the surface on which an electronic component is disposed) to the lower surface of the substrate. In a comparative example component, the molding material may encroach on undesirable areas of the lower surface of the substrate (e.g., areas where solder is disposed), which can lead to electrical connection failures between components. One cause of molding material overflow is that the slot has a large aperture, particularly a large dimension along the X-direction. In this embodiment, a dam structure is provided to reduce the area (or aperture) of the slot to prevent the package from encroaching on undesirable areas of the substrate. This solves the problem of the comparative example component.

[0103] Figure 2A , Figure 2B and Figure 2C Semiconductor element 1b is illustrated in some embodiments of this disclosure. In some embodiments, semiconductor element 1b has a structure similar to that of semiconductor element 1a, one difference being that semiconductor element 1b does not include dam structure 44.

[0104] In some embodiments, the opening 20 may have a side edge 20s1 and a side edge 20s2 on two opposite sides of the longer edge. In some embodiments, a dam structure 42 is provided on or at side edge 20s1. In some embodiments, no dam structure is provided on or above side edge 20s2. In some embodiments, the surface roughness of a surface 50s1 (or lower surface) of the package 50 at side edge 20s1 may be less than the surface roughness of surface 50s1 (or lower surface) of the package 50 at side edge 20s2. In some embodiments, the package 50 may include an overflow portion located on surface 10s1 of the substrate 10 adjacent to side edge 20s2. In some embodiments, the number of electronic connectors located on or adjacent to side edge 20s2 may be less than the number of electronic connectors located on or adjacent to side edge 20s1.

[0105] Figure 3A , Figure 3B and Figure 3CSemiconductor element 1c is illustrated in some embodiments of this disclosure. In some embodiments, semiconductor element 1c has a structure similar to that of semiconductor element 1a, one difference being that semiconductor element 1c may include a dam structure 46.

[0106] In some embodiments, the dam structure 46 may also be configured to effectively transfer heat from the semiconductor element 1c to the surrounding environment. In some embodiments, the dam structure 46 may cover surface 30s1 (or upper surface) of the electronic element 30. In some embodiments, a surface 46s1 (or upper surface) of the dam structure 46 is substantially aligned with or coplanar with a surface 50s2 (or upper surface) of the package 50. In some embodiments, surface 46s1 is exposed from the package 50.

[0107] In some embodiments, the dam structure 46 may cover the center portion 20p2 of the opening 20. In some embodiments, a portion 50p1 of the encapsulation within the opening 20 may be completely covered by the dam structure 46.

[0108] In some embodiments, the dam structure 46 may include a thermally conductive material, such as copper (Cu), tungsten (W), silver (Ag), gold (Au), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, combinations thereof, or other suitable materials. In some embodiments, the dam structure 46 may include a radiator or other suitable heat dissipation element, such as a heat pipe including a steam chamber or other suitable element.

[0109] Electronic component 30 may have a thickness T1. Dam structure 46 may have a thickness T2. In some embodiments, thickness T2 may be greater than thickness T1.

[0110] In some embodiments, the dam structure 46 may include one or more openings (not shown) configured to allow molding material to pass through.

[0111] Figure 4A , Figure 4B and Figure 4C Semiconductor element 1d is illustrated in some embodiments of this disclosure. In some embodiments, semiconductor element 1d has a structure similar to semiconductor element 1a, one difference being that the dam structure 42 and dam structure 44 of semiconductor element 1d are located above or below the surface 10s1 of substrate 10.

[0112] like Figure 4CAs shown, dam structure 42 and dam structure 44 define an opening 20, which has a third length L3 along the Y direction on the surface 10s2 of the base 10 and a fourth length L4 on the surface 10s1 of the base 10. In some embodiments, the third length L3 may be greater than the fourth length L4.

[0113] Figure 5 This is a flowchart illustrating a method for fabricating a semiconductor element according to some embodiments of this disclosure.

[0114] Preparation method 2 begins at step 202, wherein a substrate is provided. The substrate may define an opening extending through it. An electronic component may be attached to an upper surface of the substrate. Multiple wires may be formed to electrically connect a lower surface of the substrate and the electronic component. The substrate and the electronic component may define a package injection groove having a first area.

[0115] Preparation method 2 continues to step 204, wherein at least one dam structure may be formed. The dam structure may be formed on the upper surface of the substrate 10. In some embodiments, the dam structure may be attached to the substrate by an adhesive material, such as glue or other suitable material. The substrate, the dam structure, and the electronic component may define a package injection groove having a second area smaller than the first area.

[0116] Preparation method 2 continues to step 206, wherein a package can be formed to encapsulate the electronic component, the dam structure, and the wires. Thus, a semiconductor component can be manufactured.

[0117] Preparation method 2 is merely an example and is not intended to limit the scope of this disclosure beyond what is expressly stated in the claims. Additional steps may be provided before, during, or after each step of preparation method 2, and some described steps may be replaced, eliminated, or reordered for additional embodiments of the preparation method. In some embodiments, preparation method 2 may include... Figure 5 Further steps not described herein. In some embodiments, preparation method 2 may include... Figure 5 One or more steps are shown.

[0118] Figures 6A to 8A This illustration shows one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure. Figures 6B to 8B , Figures 6C to 8C respectively along Figures 6A to 8A A schematic cross-sectional view along section lines A-A' and B-B'. In some embodiments, this can be achieved through... Figures 6A to 8A The steps described are used to manufacture semiconductor device 1a.

[0119] Please refer to Figure 6A , Figure 6B and Figure 6C A substrate 10 may be provided. The substrate 10 may define an opening 20 extending through the substrate 10. An electronic component 30 may be attached to a surface 10s2 of the substrate 10. A wire 60 may be formed to electrically connect the surface 10s1 of the substrate 10 and the electronic component 30. For example... Figure 6A As shown, the opening 20 exposed from the electronic component 30 may have an area AR1.

[0120] Please refer to Figure 7A , Figure 7B and Figure 7C Dam structures 42 and 44 can be formed. Dam structures 42 and 44 can be formed on the surface 10s2 of the substrate 10. In some embodiments, dam structures 42 and 44 can be attached to the substrate 10 using an adhesive material (e.g., glue or other suitable material). In some embodiments, the opening 20 exposed from the electronic component 30 and the dam structures 42 and 44 can have an area AR2. In some embodiments, the area AR2 can be smaller than the area AR1.

[0121] Please refer to Figure 8A , Figure 8B and Figure 8C This allows the formation of a package 50 to encapsulate electronic components 30, dam structures 42 and dam structures 44, and wires 60. This enables the manufacture of semiconductor devices (e.g., semiconductor device 1a).

[0122] At this stage, if the width of opening 20 (for example, Figure 1A If the width W1 shown is large, the molding material will encroach on the undesirable area of ​​the surface 10s1 of the substrate 10. In some embodiments, dam structures 42 and dam structures 44 can be used to reduce the area (or aperture) of the opening 20 to prevent the surface 10s1 of the substrate 10 from being encroached upon by the molding material. Therefore, the yield of the semiconductor device process can be improved.

[0123] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, an electronic component, a package, and a dam structure. The substrate has a lower surface and an upper surface opposite the lower surface. The electronic component is disposed on the upper surface of the substrate. The package is disposed on the upper surface of the substrate and has a portion extending through the substrate. The dam structure vertically overlaps with the portion of the package.

[0124] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a substrate, an electronic component, a package, and a dam structure. The substrate has a lower surface and an upper surface opposite the lower surface. The electronic component is disposed on the upper surface of the substrate. The package is disposed on the upper surface of the substrate and has a portion extending through the substrate. The substrate and the dam structure define a package injection groove. A first aperture of the package injection groove adjacent to the upper surface of the substrate and a second aperture of the package injection groove adjacent to the lower surface of the substrate are different.

[0125] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes providing a substrate having a lower surface and an upper surface opposite the lower surface, wherein the substrate defines a package injection groove penetrating the lower surface and the upper surface; forming an electronic device on the upper surface of the substrate; forming a dam structure on the substrate to reduce the aperture of an aperture in the package injection groove; and forming a package on the substrate.

[0126] When a package is formed on the substrate, a mold chase is used to receive the substrate with a slot. Next, a molding material is filled into the mold and flows through the slot from the upper surface of the substrate (e.g., the surface on which an electronic component is disposed) to the lower surface of the substrate. In a comparative example component, the molding material may encroach on an undesirable area of ​​the lower surface of the substrate (e.g., an area where solder balls are disposed), which can lead to electrical connection failure between components. One reason for molding material overflow is that the slot has a large aperture, particularly a large dimension along the X-direction. In this embodiment, a dam structure is provided to reduce the area (or aperture) of the slot to prevent the package from encroaching on the undesirable area of ​​the substrate. This solves the problem of the comparative example component.

[0127] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0128] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: A substrate having a lower surface and an upper surface opposite to the lower surface; An electronic component is disposed on the upper surface of the substrate; An encapsulation is disposed on the upper surface of the substrate and has a portion extending through the substrate; as well as A dam structure that overlaps perpendicularly with this portion of the encapsulation.

2. The semiconductor device of claim 1, wherein the dam structure is disposed on the upper surface of the substrate.

3. The semiconductor device of claim 1, wherein the dam structure is disposed on the lower surface of the substrate.

4. The semiconductor device of claim 1, wherein the dam structure includes a dummy die.

5. The semiconductor device of claim 1, wherein the dam structure includes a thermally conductive material.

6. The semiconductor device of claim 1, wherein the dam structure is exposed from the package.

7. The semiconductor device of claim 1, wherein the dam structure covers an upper surface of the electronic device.

8. The semiconductor element of claim 1, wherein an upper surface of the dam structure is substantially aligned with an upper surface of the package.

9. The semiconductor element of claim 1, wherein the substrate defines an opening that accommodates the portion of the package, and a shorter length of the opening is equal to or greater than about 1100 μm.

10. The semiconductor device of claim 9, further comprising: A wire electrically connects the substrate to the electronic component and passes through the opening in the substrate.

11. The semiconductor element of claim 1, wherein the package is further disposed on a first side of the lower surface of the substrate and on a second side opposite to the first side, and the roughness of the package on the first side of the lower surface of the substrate is different from the roughness of the package on the second side of the lower surface of the substrate.

12. A semiconductor element, comprising: A substrate having a lower surface and an upper surface opposite to the lower surface; An electronic component is disposed on the upper surface of the substrate; An encapsulation is disposed on the upper surface of the substrate and has a portion extending through the substrate; as well as A dam structure, wherein the base and the dam structure define an encapsulation injection groove, and a first aperture of the encapsulation injection groove adjacent to the upper surface of the base and a second aperture of the encapsulation injection groove adjacent to the lower surface of the base are different.

13. The semiconductor element of claim 12, wherein the dam structure is disposed on the upper surface of the substrate.

14. The semiconductor device of claim 12, wherein the dam structure is disposed on the lower surface of the substrate.

15. The semiconductor device of claim 12, wherein the dam structure includes a dummy grain.

16. The semiconductor device of claim 12, wherein the dam structure includes a thermally conductive material.

17. The semiconductor device of claim 12, wherein the dam structure is exposed from the package.

18. The semiconductor device of claim 12, wherein the dam structure covers an upper surface of the electronic device.

19. The semiconductor element of claim 12, wherein an upper surface of the dam structure is substantially aligned with an upper surface of the package.

20. The semiconductor device of claim 12, further comprising: A wire electrically connects the substrate and the electronic component and passes through the injection groove of the package.

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