Display panel, display device and display panel to be cut

Abstract

A display panel, a display device and a display panel to be cut, the display panel comprising a plurality of pixels (P), a plurality of signal lines (G, D) and a drive circuit, the signal lines (G, D) being electrically connected to the pixels (P), the signal lines (G, D) having first ends (F1) and second ends (F2) in the extension direction thereof, the first ends (F1) of the signal lines (G, D) being electrically connected to the drive circuit, the second ends (F2) being electrically connected to the drive circuit, and the first ends (F2) being electrically connected to the drive circuit. The second end (F2) of the signal line is flush with the outer edge of the display panel.

Description

A display panel, a display device, and a display panel to be cut. Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel, a display device, and a display panel to be cut. Background Technology

[0002] Currently, display panels are manufactured using pre-designed photomasks. Because market requirements for display panel sizes vary, a single photomask can only produce panels of a fixed size. Therefore, when there is a need to change the size of the display panel, a new photomask must be purchased. Since photomasks are expensive, this significantly increases the cost of changing display panel sizes. Furthermore, the long photomask changeover cycle adds to the time cost.

[0003] Summary of the Invention

[0004] This disclosure provides a display panel, a display device, and a display panel to be cut, with the specific solution as follows:

[0005] This disclosure provides a display panel including multiple pixels, multiple signal lines, and a driving circuit. The signal lines are electrically connected to the pixels. Each signal line has a first end and a second end along its extension direction. The first end of the signal line is electrically connected to the driving circuit, and the second end of the signal line is flush with the outer edge of the display panel.

[0006] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the display panel includes a display area and a peripheral area surrounding the display area, the driving circuit is located in the peripheral area, and the peripheral area where the driving circuit is located does not have the pixel; the second end of the signal line is located in the peripheral area, and the peripheral area where the second end of the signal line is located includes the pixel.

[0007] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the outermost pixel among the pixels in the peripheral area where the second end of the signal line is located is a complete pixel or an incomplete pixel.

[0008] In one possible implementation, the display panel provided in the embodiments of this disclosure includes an array substrate and a counter substrate disposed opposite to each other, and the second end of the signal line is flush with the outer edges of the array substrate and the counter substrate.

[0009] The peripheral area is provided with a sealing adhesive that connects the array substrate and the opposing substrate. The outer edge of the sealing adhesive in the peripheral area where the second end of the signal line is located covers at most the outer edges of the array substrate and the opposing substrate.

[0010] In one possible implementation, in the display panel provided in the embodiments of this disclosure, a protective adhesive is provided on the outer edge of the display panel corresponding to the second end of the signal line.

[0011] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the plurality of signal lines include a plurality of data signal lines and a plurality of gate signal lines that are insulated and cross-arranged within the display area. The driving circuit includes a driving chip and a GOA circuit. The driving chip is located in the peripheral area on one side of the first end of the data signal line, and the GOA circuit is located in the peripheral area on one side of the first end of the gate signal line. The GOA circuit includes a plurality of cascaded GOA units.

[0012] The first end of each of the data signal lines is electrically connected to the driver chip, and the first end of each of the gate signal lines is electrically connected to each of the GOA units in a corresponding manner.

[0013] The second end of at least one of the data signal lines and the gate signal lines is flush with the outer edge of the display panel.

[0014] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the second end of the data signal line is flush with the outer edge of the display panel.

[0015] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the second end of the gate signal line is flush with the outer edge of the display panel.

[0016] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the peripheral area where the driver chip is located further includes: a first electrical test pad group located on the side of the driver chip closer to the GOA circuit, and a first silver paste dot located on the side of the first electrical test pad group away from the driver chip.

[0017] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the peripheral area where the driver chip is located further includes: at most a portion of a second electrical test pad group located on the side of the driver chip away from the first electrical test pad group.

[0018] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the display area has a first center line extending along the extension direction of the data signal line, and the driving chip has a second center line extending along the extension direction of the data signal line, the second center line being located between the first center line and the GOA circuit.

[0019] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the peripheral area where the GOA circuit is located further includes a first start signal line and a second start signal line located on the side of the GOA unit away from the display area, and the end of the first start signal line away from the driver chip is floating.

[0020] The output signal terminal of the last row of GOA units closest to the driver chip is connected to the second start signal line. Except for the last row of GOA units, the output signal terminals of the other rows of GOA units are respectively connected to the input signal terminals of the GOA units in the next row connected to them.

[0021] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the peripheral area where the GOA circuit is located further includes a trace group located on the side of the GOA unit away from the display area. Each trace of the trace group extends along the extension direction of the data signal line. The trace group includes a ground trace, a common trace, a GOA signal trace, and a GOA cascade trace arranged sequentially along the extension direction of the gate signal line. The GOA cascade trace is disposed close to the GOA unit.

[0022] The GOA unit includes: a plurality of thin-film transistors, at least one capacitor, and a plurality of connection traces extending along the extension direction of the gate signal line; one end of the connection trace is electrically connected to the corresponding thin-film transistor, and the other end of the connection trace is connected to the corresponding GOA signal trace through a via.

[0023] There is a cut area between adjacent GOA units that extends along the extension direction of the gate signal line and crosses the trace group. The area of ​​the GOA signal trace and the GOA cascade trace corresponding to the cut area is a first area. The connecting trace and the via do not overlap with the first area.

[0024] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the GOA unit includes at least one connection trace disposed close to the first region on both sides along the extension direction of the data signal line, and the connection trace disposed close to the first region is disposed in a conformal manner along the first region.

[0025] The vias connecting the connection traces and the GOA signal traces located near the first region are situated on opposite sides of the first region along the extension direction of the data signal lines.

[0026] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the active layer of the thin-film transistor electrically connected to the connection trace disposed near the first region includes at least two first U-shaped portions arranged along the extension direction of the gate signal line, the at least two first U-shaped portions being closely connected.

[0027] In one possible implementation, in the display panel provided in the embodiments of this disclosure, the active layer of the thin-film transistor electrically connected to the GOA cascade trace and disposed near the first U-shaped portion includes at least three second U-shaped portions arranged along the extension direction of the gate signal line, wherein the height of the second U-shaped portions along the extension direction of the data signal line is less than 3 / 4 of the height of the first U-shaped portion along the extension direction of the data signal line.

[0028] Accordingly, this disclosure also provides a display device, including the display panel provided in the embodiments of this disclosure.

[0029] Accordingly, this disclosure also provides a display panel to be cut, including a display area and a peripheral area surrounding the display area, wherein the peripheral area includes a first peripheral area having a first binding area and a second peripheral area disposed adjacent to the first peripheral area;

[0030] The display panel to be cut also includes:

[0031] Multiple gate signal lines are located in the display area;

[0032] Multiple data signal lines are located in the display area, and the data signal lines and the gate signal lines are insulated from each other and cross each other to define multiple pixels;

[0033] The first GOA circuit is located in the second peripheral area. The first GOA circuit includes a plurality of cascaded first GOA units, and the first GOA units are electrically connected to the gate signal lines one by one.

[0034] The first starting signal line is located in the second peripheral area and on the side of the first GOA unit away from the display area. The input signal terminal of the first GOA unit in the first row is connected to the first starting signal line. Except for the first GOA unit in the first row, the input signal terminals of the first GOA units in the other rows are respectively connected to the output signal terminals of the first GOA units in the row before them.

[0035] The second starting signal line is located in the second peripheral area and on the side of the first GOA unit away from the display area. The output signal terminal of the last row of the first GOA unit is connected to the second starting signal line. Except for the last row of the first GOA unit, the output signal terminals of the first GOA units in each other row are respectively connected to the input signal terminals of the first GOA units in the next row connected to them.

[0036] A first driver chip is located in the first bonding area. The first driver chip includes: a first side that is adjacent to the display area and extends along the extension direction of the first peripheral area, and a second side that is adjacent to the first side and close to the second peripheral area.

[0037] The first electrical test pad group is located in the first bonding area and on one side of the second side of the first driver chip.

[0038] In one possible implementation, the display panel to be cut provided in the embodiments of this disclosure further includes a first silver paste dot located in the first bonding area, and the first electrical test pad group is located between the first silver paste dot and the first driver chip.

[0039] In one possible implementation, in the above-described display panel to be cut provided in the embodiments of this disclosure, the peripheral area further includes a third peripheral area disposed opposite to the second peripheral area, wherein the width of the second peripheral area is greater than the width of the third peripheral area.

[0040] In one possible implementation, in the above-described display panel to be cut provided in the embodiments of this disclosure, the display area has a first center line extending along the extension direction of the data signal line, and the first driver chip has a second center line extending along the extension direction of the data signal line, the second center line being located between the first center line and the first electrical test pad group.

[0041] In one possible implementation, the display panel to be cut provided in the embodiments of this disclosure includes a first cutting line and / or a second cutting line. The first cutting line extends in the same direction as the gate signal line and is located in any area of ​​the display area. The second cutting line extends in the same direction as the data signal line and is located between the first driving chip and the third peripheral area.

[0042] In one possible implementation, in the display panel to be cut provided in the embodiments of this disclosure, the peripheral area further includes a third peripheral area disposed opposite to the second peripheral area, the width of the second peripheral area being the same as the width of the third peripheral area; the first driving chip further includes a third side disposed opposite to the second side;

[0043] The display panel to be cut also includes:

[0044] The second GOA circuit is located in the third peripheral area. The second GOA circuit includes multiple cascaded second GOA units, and each second GOA unit is electrically connected to the gate signal line in a one-to-one correspondence.

[0045] The third starting signal line is located in the third peripheral area and on the side of the second GOA unit away from the display area. The input signal terminal of the second GOA unit in the first row is connected to the third starting signal line. Except for the second GOA unit in the first row, the input signal terminals of the second GOA units in the other rows are respectively connected to the output signal terminals of the second GOA units in the row before them.

[0046] The fourth starting signal line is located in the third peripheral area and on the side of the second GOA unit away from the display area. The output signal terminal of the last row of the second GOA units is connected to the fourth starting signal line. Except for the last row of the second GOA units, the output signal terminals of the other rows of the second GOA units are respectively connected to the input signal terminals of the second GOA units in the next row connected to them.

[0047] The second electrical test pad group is located in the first bonding area and on one side of the third side of the first driver chip;

[0048] The second silver paste dot is located in the first bonding area, and the second electrical test pad group is located between the second silver paste dot and the first driver chip.

[0049] In one possible implementation, in the above-described display panel to be cut provided in the embodiments of this disclosure, the peripheral area further includes a fourth peripheral area disposed opposite to the first peripheral area, the fourth peripheral area includes a second binding area, and the display area has a third center line with the same extension direction as the gate signal line;

[0050] The display panel to be cut also includes:

[0051] The second driver chip is located in the second bonding area, and the second driver chip and the first driver chip are symmetrically arranged about the third center line.

[0052] The third electrical test pad group is located in the second bonding area, and the third electrical test pad group and the first electrical test pad group are symmetrically arranged about the third center line;

[0053] The third silver glue point is located in the second bonding area, and the third silver glue point and the first silver glue point are symmetrically arranged about the third center line.

[0054] The fourth electrical test pad group is located in the second bonding area, and the fourth electrical test pad group and the second electrical test pad group are symmetrically arranged about the third center line;

[0055] The fourth silver adhesive point is located in the second bonding area, and the fourth silver adhesive point and the second silver adhesive point are symmetrically arranged about the third center line.

[0056] In one possible implementation, the display panel to be cut provided in the embodiments of this disclosure includes a first cutting line and / or a second cutting line. The first cutting line extends in the same direction as the gate signal line and is located in any area of ​​the display area. The second cutting line extends in the same direction as the data signal line and is located between the first driving chip and the second peripheral area, or the second cutting line is located between the first driving chip and the third peripheral area.

[0057] In one possible implementation, in the above-described display panel to be cut provided in the embodiments of this disclosure, the display area has a first center line extending along the extension direction of the data signal line, the first center line dividing the display area into a first display area and a second display area, and the first driver chip is located between the first center line and the first electrical test pad group.

[0058] The display panel to be cut also includes a second driving chip corresponding to the second display area, the second driving chip being located between the first center line and the second electrical test pad group.

[0059] In one possible implementation, in the above-described display panel to be cut provided in the embodiments of this disclosure, the first driving chip and the second driving chip are symmetrically arranged about the first center line, the first electrical test pad group and the second electrical test pad group are symmetrically arranged about the first center line, and the first silver paste dots and the second silver paste dots are symmetrically arranged about the first center line.

[0060] In one possible implementation, the display panel to be cut provided in the embodiments of this disclosure includes a first cutting line and / or a second cutting line. The first cutting line extends in the same direction as the gate signal line and is located in any area of ​​the display area. The second cutting line extends in the same direction as the data signal line and is located between the first driver chip and the second driver chip.

[0061] In one possible implementation, in the above-described display panel to be cut provided in the embodiments of this disclosure, the second cutting line coincides with the first center line.

[0062] In one possible implementation, in the above-mentioned display panel to be cut provided in the embodiments of this disclosure, a first sealing adhesive is provided at the first cutting line position, and the first cutting line is located on the side of the first sealing adhesive away from the first peripheral area.

[0063] A second sealing adhesive is provided at the location of the second cutting line, and the second cutting line is located on the side of the second sealing adhesive that is away from the second peripheral area.

[0064] In one possible implementation, in the above-described display panel to be cut provided in the embodiments of this disclosure, the second peripheral area further includes a wiring group located on the side of the first GOA unit away from the display area. Each wiring in the wiring group extends along the extension direction of the data signal line. The wiring group includes a ground wiring, a common wiring, a GOA signal wiring, and a GOA cascade wiring arranged sequentially along the extension direction of the gate signal line. The GOA cascade wiring is disposed close to the first GOA unit.

[0065] The first GOA unit includes: a plurality of thin-film transistors, at least one capacitor, and a plurality of connection traces extending along the extension direction of the gate signal line; one end of the connection trace is electrically connected to the corresponding thin-film transistor, and the other end of the connection trace is connected to the corresponding GOA signal trace through a via.

[0066] There is a cut area between adjacent first GOA units that extends along the extension direction of the gate signal line and crosses the trace group. The area of ​​the GOA signal trace and the GOA cascade trace corresponding to the cut area is the first area. The connecting trace and the via do not overlap with the first area.

[0067] In one possible implementation, in the above-mentioned display panel to be cut provided in the embodiments of this disclosure, the first GOA unit includes at least one connection trace disposed close to the first region on both sides along the extension direction of the data signal line, and the connection trace disposed close to the first region is disposed in accordance with the shape of the first region.

[0068] The vias connecting the connection traces and the GOA signal traces located near the first region are situated on opposite sides of the first region along the extension direction of the data signal lines.

[0069] In one possible implementation, in the above-described display panel to be cut provided in the embodiments of this disclosure, the active layer of the thin-film transistor electrically connected to the connection trace disposed near the first region includes at least two first U-shaped portions arranged along the extension direction of the gate signal line, the at least two first U-shaped portions being closely connected.

[0070] In one possible implementation, in the display panel to be cut provided in the embodiments of this disclosure, the active layer of the thin-film transistor electrically connected to the GOA cascaded trace and disposed near the first U-shaped portion includes at least three second U-shaped portions arranged along the extension direction of the gate signal line, wherein the height of the second U-shaped portions along the extension direction of the data signal line is less than 3 / 4 of the height of the first U-shaped portion along the extension direction of the data signal line.

[0071] In one possible implementation, in the above-described display panel to be cut provided in the embodiments of this disclosure, when the second GOA circuit is included, the second GOA unit of the second GOA circuit and the first GOA unit are symmetrically arranged about the first center line extending along the data signal line extension direction of the display area. Attached Figure Description

[0072] Figure 1 is a top view of a display panel structure provided in the related art;

[0073] Figure 2 is a top view of a display panel to be cut according to an embodiment of this disclosure;

[0074] Figure 3 is a top view of another display panel to be cut according to an embodiment of this disclosure;

[0075] Figure 4 shows the structure of a display panel obtained by cutting the display panel to be cut shown in Figure 2 along the first cutting line and the second cutting line;

[0076] Figure 5 is a top view of another display panel to be cut according to an embodiment of this disclosure;

[0077] Figure 6 shows the structure of a display panel obtained by cutting the display panel to be cut shown in Figure 5 along the first cutting line and the second cutting line;

[0078] Figure 7 is a top view of another display panel to be cut according to an embodiment of this disclosure;

[0079] Figure 8 shows the structure of a display panel obtained by cutting the display panel to be cut shown in Figure 7 along the first cutting line and the second cutting line;

[0080] Figure 9 shows the structure of a display panel obtained by cutting the display panel to be cut shown in Figure 7 along the first cutting line and the second cutting line;

[0081] Figure 10 is a top view of another display panel to be cut according to an embodiment of this disclosure;

[0082] Figure 11 shows the structure of a display panel obtained by cutting the display panel to be cut shown in Figure 10 along the first cutting line and the second cutting line;

[0083] Figure 12 shows the structure of a display panel obtained by cutting the display panel to be cut shown in Figure 10 along the first cutting line and the second cutting line;

[0084] Figure 13 is a top view of another display panel to be cut according to an embodiment of this disclosure;

[0085] Figure 14 shows the structure of a display panel obtained by cutting the display panel to be cut shown in Figure 13 along the first cutting line and the second cutting line;

[0086] Figure 15 shows the structure of a display panel obtained by cutting the display panel to be cut shown in Figure 13 along the first cutting line and the second cutting line;

[0087] Figure 16 shows a simplified structure of the display panel shown in Figure 7;

[0088] Figure 17 is a schematic diagram of the display panel obtained by cutting the display panel to be cut shown in Figure 16 along the first cutting line;

[0089] Figure 18 is a schematic diagram of the specific structure of the four first GOA units and the wiring in the second peripheral area of ​​Figure 16;

[0090] Figure 19 is a schematic diagram of the specific structure of two adjacent first GOA units and their wiring in Figure 18.

[0091] Figure 20 is a partially enlarged schematic diagram of the connection between some GOA signal traces and connecting lines in Figure 19 via vias;

[0092] Figure 21 is a schematic diagram of the cross section along the EE' direction in Figure 20. Detailed Implementation

[0093] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Furthermore, the embodiments and features in the embodiments of this disclosure can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0094] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "comprising" or "including," and similar terms as used in this disclosure, mean that an element or object preceding the term encompasses the elements or objects listed following the term and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "inner," "outer," "upper," and "lower" are used only to indicate relative positional relationships; these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0095] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual scale and are intended only to illustrate the content of this disclosure. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0096] Liquid crystal displays (LCDs) are increasingly widely used due to their advantages such as low power consumption, miniaturization, and thinness, for example, in automotive displays and transparent displays used in shopping mall exhibitions.

[0097] As shown in Figure 1, Figure 1 is the structure of a conventional liquid crystal display screen, including a display area AA and a peripheral area BB surrounding the display area AA. The peripheral area BB can be divided into four border areas: upper, lower, left, and right. The left and right border areas are mainly used to place the gate driving circuit. Each gate driving circuit includes multiple GOA units arranged in cascade. For example, the gate driving circuit of the left border area includes multiple GOA units arranged in cascade (e.g., GOA2, GOA4, GOA6... GOA(n)), and the gate driving circuit of the right border area includes multiple GOA units arranged in cascade (e.g., GOA1, GOA3, GOA5... GOA(n-1)). The display area AA includes multiple crisscrossing gate signal lines G and multiple data signal lines D. The signals on the gate signal lines G are provided by the gate driving circuits of the left and right frame areas. For example, the gate driving circuit of the left frame area is connected to the even-numbered row gate signal lines G, and the gate driving circuit of the right frame area is connected to the odd-numbered row gate signal lines G. The lower frame area includes a fan-out area B1 and a bonding area B2. The bonding area B2 includes an IC and an FPC (not shown). The signals on the data signal lines D are provided by the IC in the bonding area B2. The connection trace between the IC and the data signal lines D of the display area AA is a fan-out line. In addition, the lower frame area also has Ag glue dots 10 and ET units 20, which are essential for the display screen, located on both sides of the IC. The Ag glue dots 10 are mainly used to connect the ground terminal on the FPC and the conductive layer on the color filter substrate to conduct away static electricity. The ET units 20 are mainly used to detect defective displays after the array substrate and color filter substrate are assembled.

[0098] A typical LCD screen is formed by combining an array substrate and a color filter substrate. Each substrate requires a pre-designed mask during manufacturing. However, a single mask can only produce a screen of a fixed size. When there is a need to change the screen size, a new mask must be designed and manufactured. Masks are expensive, significantly increasing the cost of changing screen sizes. Furthermore, the long mask change cycle adds to the time cost.

[0099] To achieve the goal of manufacturing a display screen using only one mask and then producing display screens of different sizes by cutting, this disclosure provides a display panel to be cut, as shown in FIG2. The display panel to be cut includes a display area AA and a peripheral area BB located around the display area AA. The peripheral area BB includes a first peripheral area BB1 having a first binding area BD1 and a second peripheral area BB2 disposed adjacent to the first peripheral area BB1. The width of the second peripheral area BB2 is generally the same as the width of the third peripheral area BB3. The peripheral area BB also includes a third peripheral area BB3 disposed opposite to the second peripheral area BB2 and a fourth peripheral area BB4 disposed opposite to the first peripheral area BB1. The first peripheral area BB1 also includes a fan-out area B1 located between the display area AA and the first binding area BD1.

[0100] Specifically, as shown in Figure 2, the display panel to be cut provided in this embodiment of the present disclosure further includes:

[0101] Multiple gate signal lines G are located in the display area AA;

[0102] Multiple data signal lines D are located in the display area AA. The data signal lines D and the gate signal lines G are insulated and intersected to define multiple pixels P.

[0103] The first GOA circuit 1 is located in the second peripheral area BB2. The first GOA circuit 1 includes multiple cascaded first GOA units (e.g., GOA1, GOA2, GOA3... GOA(n-1), GOA(n)), and the first GOA units are electrically connected to the gate signal lines G one by one.

[0104] The first start signal line (STV1, not shown) is located in the second peripheral area BB2 and on the side of the first GOA unit away from the display area AA. The input signal terminal of the first GOA unit (GOA1) in the first row is connected to the first start signal line. Except for the first GOA unit (GOA1) in the first row, the input signal terminals of the first GOA units in the other rows are respectively connected to the output signal terminals of the first GOA units in the row above them.

[0105] The second start signal line (STV2, not shown) is located in the second peripheral BB2 area and on the side of the first GOA unit away from the display area AA. The output signal terminal of the last row of the first GOA unit (GOA(n)) is connected to the second start signal line. Except for the last row of the first GOA unit (GOA(n)), the output signal terminals of the other rows of the first GOA unit are respectively connected to the input signal terminals of the next row of the first GOA unit connected to them.

[0106] The first driver chip IC1 is located in the first bonding area BD1. The first driver chip IC1 includes: a first side a1 that is adjacent to the display area AA and extends along the extension direction X of the first peripheral area BB1, a second side a2 that is adjacent to the first side a1 and close to the second peripheral area BB2, and a third side a3 that is disposed opposite to the second side a2.

[0107] The first electrical test pad group 2 is located in the first bonding area BD1 and is located on one side of the second side a2 of the first driver chip IC1.

[0108] The display panel to be cut provided in this embodiment of the present disclosure changes the original design of the GOA units, which were alternately arranged on the left and right frame areas on both sides of the display area in the related technology (Figure 1), to be arranged only on one side of the display area. Furthermore, the first electrical test pad group (ET unit) located on both sides of the IC is also designed only on one side of the IC. This allows the display panel to be cut to be manufactured using only one mask, and then different sizes of display panels can be obtained by cutting. For example, the display area can be vertically cut from the right side of the first driver chip, and the upper side of the display area can be horizontally cut to obtain display panels of different sizes. Through the above design, the size of the display panel can be changed simply by cutting without changing the mask. Moreover, the horizontal and vertical dimensions of the display panel can be changed. That is, different sizes of screens can be manufactured using the same mask to meet different customer needs, saving material costs associated with mask changes and reducing the change cycle.

[0109] Specifically, as shown in Figure 2, since the first GOA circuit 1 of this disclosure adopts single-sided driving and supports both forward and reverse scanning modes, as shown in Figure 3, gate signals can be input line by line from top to bottom (arrow K1) and from bottom to top (arrow K2). The start-up of the first GOA unit (GOA1) in the first row is provided by the first start signal line (STV1), and the start-up of the last GOA unit (GOA(n)) is provided by the second start signal line (STV2). Therefore, on the upper side of the display panel to be cut... After the first GOA unit is removed, the remaining lower first GOA unit can still function normally, but it can only use the single-scan GOA mode. This means the second start signal line (STV2) triggers the GOA(n), inputting gate signals line by line from bottom to top. Therefore, horizontal cutting of the display area does not affect the normal operation of the first GOA unit. Furthermore, since the display area is cut vertically from the right side of the first driver chip, ensuring that the first driver chip IC1 is not cut, the data signals of the cut display panel can be normally input to the remaining data signal lines D through the first driver chip IC1. Therefore, when cutting the display panel to be cut according to this disclosure to obtain display panels of different sizes, because the GOA unit connected to the remaining gate signal line G and the first driver chip IC1 connected to the remaining data signal line D still exist, electrical signals can be normally provided to the gate signal line G and the data signal line D. Therefore, the remaining pixels in the display area after cutting can still be displayed normally. Moreover, the timing of the first GOA unit can be changed according to the resolution of the cut display panel.

[0110] In some possible implementations, as shown in FIG2, the display panel to be cut provided in the embodiments of this disclosure further includes a first silver paste point 3 located in the first bonding area BD1, and a first electrical test pad group 2 located between the first silver paste point 3 and the first driver chip IC1. By removing the Ag paste point originally on the right side of IC1 in related technologies and retaining only the Ag paste point on the left side of IC1, it can still operate normally after cutting.

[0111] In some possible implementations, the display panel to be cut provided in the embodiments of this disclosure, as shown in FIG2, includes a first cutting line L1 and / or a second cutting line L2. The first cutting line L1 extends in the same direction as the gate signal line G and is located in any area of ​​the display area AA. The second cutting line L2 extends in the same direction as the data signal line D and is located between the first driver chip IC1 and the third peripheral area BB3. Thus, after the display panel to be cut shown in FIG1 is manufactured, it can be cut along the first cutting line L1 and / or the second cutting line L2 to obtain display panels of different sizes.

[0112] Specifically, as shown in Figure 2, this embodiment takes the example of all first GOA units arranged in the second peripheral area BB2 and all first GOA units in the third peripheral area BB3 being removed. Of course, it is also possible that all first GOA units are arranged in the third peripheral area BB3 and all first GOA units in the second peripheral area BB2 are removed. In this case, the first electrical test pad group 2 and the first silver paste point 3 need to be located on the right side of the first driver chip IC1. In this way, the display area AA can be vertically cut from the left side of the first driver chip IC1 and the upper side of the display area AA can be horizontally cut to obtain display panels of different sizes.

[0113] Specifically, since this embodiment uses a liquid crystal display panel as an example, a liquid crystal layer is disposed between the array substrate and the color filter substrate. In related technologies, a sealing adhesive is disposed around the liquid crystal layer between the array substrate and the color filter substrate corresponding to the peripheral area to seal the liquid crystal layer. In order to ensure that the liquid crystal layer of the cut display panel is still sealed by the sealing adhesive, in the above-mentioned display panel to be cut provided in this embodiment, as shown in FIG2, a first sealing adhesive (not shown) is disposed at the first cutting line L1, and the first cutting line L1 is located on the side of the first sealing adhesive away from the first peripheral area BB1; a second sealing adhesive (not shown) is disposed at the second cutting line L2, and the second cutting line L2 is located on the side of the second sealing adhesive away from the second peripheral area BB2. In this way, the liquid crystal layer of the cut display panel is still sealed around the edge by the sealing adhesive, which does not affect the normal display of the liquid crystal display panel.

[0114] As shown in Figure 4, Figure 4 is a structure of a display panel obtained by cutting the display panel to be cut shown in Figure 2 along the first cutting line L1 and the second cutting line L2. The display panel includes multiple pixels P, multiple signal lines (e.g., including gate signal lines G and data signal lines D) and driving circuits (e.g., including driving chips and GOA circuit 1'). The signal lines (G and D) are electrically connected to the pixels P, and the signal lines (G and D) have a first end F1 and a second end F2 along their extension direction.

[0115] Specifically, as shown in Figure 4, the GOA circuit 1' is the remaining structure after the first GOA circuit 1 shown in Figure 2 is horizontally cut along the upper side of the display area AA, and the driving chip is the first driving chip IC1 in Figure 2.

[0116] Specifically, as shown in Figure 4, the peripheral area where the GOA circuit 1' is located also includes a first start signal line (STV1, not shown) and a second start signal line (STV2, not shown) located on the side of the GOA unit (i.e. the first GOA unit) away from the display area AA. Since the display panel shown in Figure 4 is cut along the first cutting line L1, the end of the first start signal line away from the driver chip (IC1) is cut and is in a floating state.

[0117] The output signal terminal of the last row of GOA units (i.e., GOA(n)) closest to the driver chip (IC1) is connected to the second start signal line. Except for the last row of GOA units (i.e., GOA(n)), the output signal terminals of the remaining rows of GOA units (GOA6 to GOA(n-1)) are respectively connected to the input signal terminals of the GOA units in the row immediately following them. In this way, even if the display panel shown in Figure 4, after being cut, cannot achieve forward scanning (triggered by the first start signal line), it can support reverse scanning (i.e., the second start signal line triggers GOA(n) to work and scans upwards row by row).

[0118] Specifically, as shown in Figure 4, the first end F1 of the signal line (e.g., the gate signal line G) is electrically connected to the driving circuit (GOA circuit 1'), and the first end F1 of the signal line (e.g., the data signal line D) is electrically connected to the driving circuit (the first driving chip IC1).

[0119] Specifically, as shown in Figure 4, the driver chip (IC1) is located in the peripheral area (i.e., the first peripheral area BB1 in Figure 2) on one side of the first end F1 of the data signal line D, and the GOA circuit 1' is located in the peripheral area (i.e., the second peripheral area BB2 in Figure 2) on one side of the first end G of the gate signal line G.

[0120] Specifically, as shown in Figure 4, since the display panel is obtained by cutting the display panel to be cut shown in Figure 2 along the first cutting line L1 and the second cutting line L2, the second end F2 of the signal line (data signal line D) is flush with the outer edge of the display panel, and the second end F2 of the signal line (gate signal line G) is also flush with the outer edge of the display panel.

[0121] Specifically, as shown in Figure 4, the display panel includes an array substrate and a counter substrate arranged opposite to each other. Since the display panel is obtained by cutting the display panel to be cut shown in Figure 2 along the first cutting line L1 and the second cutting line L2, the second end F2 of the signal line (gate signal line G and data signal line D) is flush with the outer edge of the array substrate and the counter substrate.

[0122] Specifically, as shown in Figure 4, the display panel also includes a display area AA (the remaining display area after cutting in Figure 2) and a peripheral area surrounding the display area AA (the remaining peripheral area after cutting in Figure 2). The peripheral area where the driving circuit (the first driving chip IC1 and the GOA circuit 1') is located does not have a pixel P. The second end F2 of the signal line (gate signal line G and data signal line D) is located in the peripheral area. Since the cutting is performed along the upper and right sides of the display area AA, the peripheral area where the second end F2 of the signal line (gate signal line G and data signal line D) is located includes a pixel P.

[0123] Specifically, since the first cutting line L1 and the second cutting line L2 in Figure 2 may fall into the area between adjacent pixels, the outermost pixel in the pixel P included in the peripheral area of ​​the second end F2 of the signal line (gate signal line G and data signal line D) in Figure 4 is a complete pixel. Conversely, since the first cutting line L1 and the second cutting line L2 in Figure 2 may also fall exactly into the pixel area, the outermost pixel in the pixel P included in the peripheral area of ​​the second end F2 of the signal line (gate signal line G and data signal line D) in Figure 4 is an incomplete pixel.

[0124] Specifically, as shown in Figure 4, since the display panel is obtained by cutting the display panel to be cut shown in Figure 2 along the first cutting line L1 and the second cutting line L2, and since the first cutting line L1 and the second cutting line L2 in Figure 2 are provided with sealing glue, the peripheral area of ​​Figure 4 is provided with sealing glue to connect the array substrate and the opposing substrate. Since the sealing glue at the first cutting line L1 and the second cutting line L2 needs to be retained after cutting, the outer edge of the sealing glue in the peripheral area where the second end F2 of the signal line (gate signal line G and data signal line D) is located (i.e. the sealing glue area at the first cutting line L1 and the second cutting line L2 in Figure 2) can at most cover the outer edge of the array substrate and the opposing substrate. That is, the outer edge of the sealing glue in the peripheral area where the second end F2 of the signal line (gate signal line G and data signal line D) is located can be flush with the outer edge of the array substrate and the opposing substrate, or the outer edge of the sealing glue in the peripheral area where the second end F2 of the signal line (gate signal line G and data signal line D) is located is recessed relative to the outer edge of the array substrate and the opposing substrate. This allows you to cut along the outer edge of the sealant or along the inside of the sealant.

[0125] Specifically, as shown in Figure 4, in order to prevent the second end F2 of the cut signal lines (gate signal line G and data signal line D) from being corroded by external moisture, a protective adhesive is provided on the outer edge of the display panel corresponding to the second end F2 of the signal lines (gate signal line G and data signal line D).

[0126] Specifically, as shown in Figure 4, the peripheral area (first peripheral area BB1) where the driver chip (i.e. the first driver chip IC1) is located also includes: a first electrical test pad group 2 located on the side of the driver chip (IC1) close to the GOA circuit 1', and a first silver paste dot 3 located on the side of the first electrical test pad group 2 away from the driver chip (IC1).

[0127] It should be noted that Figure 4 is an example of a display panel obtained by simultaneously cutting the display panel to be cut as shown in Figure 2 along the first cutting line L1 and the second cutting line L2. Of course, it is also possible to cut only along the first cutting line L1 or only along the second cutting line L1. The specific cutting method can be determined according to the size of the display panel.

[0128] As shown in Figure 5, this embodiment provides another structure of a display panel to be cut. The structure of the display panel to be cut shown in Figure 5 is basically the same as that shown in Figure 2. The difference is that the width of the second peripheral area BB2 in Figure 5 is greater than the width of the third peripheral area BB3. This is because although the gate signal is not interrupted by the single-sided GOA arrangement in Figure 2, changing the GOA from a double-sided alternating arrangement to a single-sided arrangement will increase the width requirement of the second peripheral area BB2, and also waste the space of the third peripheral area BB3. Therefore, in this embodiment, the width of the second peripheral area BB2 in Figure 5 is set to be greater than the width of the third peripheral area BB3. That is, the display area AA is no longer centered, but is offset to the right. The traces of the fan-out area B1 can also be designed to be offset to the right. In this way, the space of the second peripheral area BB2 can be fully utilized, and the overall peripheral area width does not need to be increased.

[0129] Specifically, as shown in Figure 5, the display area AA has a first center line M1 extending along the extension direction of the data signal line D, and the first driver chip IC1 has a second center line M2 extending along the extension direction of the data signal line D. The second center line M2 is located between the first center line M1 and the first electrical test pad group 2. This is because when cutting along the second cutting line L2 in Figure 5, the position of IC1 mainly limits the cutting range. Since the cutting cannot damage IC1, IC1 and the fan-out area B1 can be designed as far to the left as possible when space permits, leaving more cutting options for the right side of the display panel to be cut.

[0130] Specifically, as shown in Figure 6, the display area AA has a first center line M1 extending along the extension direction of the data signal line D, and the driver chip (IC1) has a second center line M2 extending along the extension direction of the data signal line D. The second center line M2 is located between the first center line M1 and the GOA circuit 1'.

[0131] As shown in Figure 6, Figure 6 shows a display panel structure obtained by cutting the display panel to be cut shown in Figure 5 along the first cutting line L1 and the second cutting line L2. When the first cutting line L1 and the second cutting line L2 in the display panel to be cut shown in Figure 5 are in the same position as those in the display panel to be cut shown in Figure 2, the main difference between the display panel shown in Figure 6 and the display panel shown in Figure 4 is the different width of the second peripheral area BB2 and the different position of IC1.

[0132] It should be noted that Figure 6 is an example of a display panel obtained by simultaneously cutting the display panel to be cut as shown in Figure 5 along the first cutting line L1 and the second cutting line L2. Of course, it is also possible to cut only along the first cutting line L1 or only along the second cutting line L1. The specific cutting method can be determined according to the size of the display panel.

[0133] As shown in Figure 7, Figure 7 illustrates another structure of a display panel to be cut according to an embodiment of this disclosure. The structure of the display panel to be cut shown in Figure 7 is basically the same as that of the display panel to be cut shown in Figure 2, except that the display panel to be cut shown in Figure 7 further includes:

[0134] The second GOA circuit 4 is located in the third peripheral region BB3. The second GOA circuit 4 includes multiple cascaded second GOA units (e.g., GOA1, GOA2, GOA3... GOA(n-1), GOA(n)). The second GOA units (e.g., GOA1, GOA2, GOA3... GOA(n-1), GOA(n)) are electrically connected to the gate signal line G one-to-one.

[0135] The third start signal line (STV3, not shown) is located in the third peripheral area BB3 and on the side of the second GOA unit away from the display area AA. The input signal terminal of the first row second GOA unit (GOA1) is connected to the third start signal line. Except for the first row second GOA unit (GOA1), the input signal terminals of the other rows of second GOA units are respectively connected to the output signal terminals of the second GOA unit in the row above them.

[0136] The fourth start signal line (STV4, not shown) is located in the third peripheral area BB3 and on the side of the second GOA unit away from the display area AA. The output signal terminal of the last row of second GOA units (GOA(n)) is connected to the fourth start signal line. Except for the last row of second GOA units (GOA(n)), the output signal terminals of the other rows of second GOA units are respectively connected to the input signal terminals of the next row of second GOA units connected to them.

[0137] The second electrical test pad group 5 is located in the first bonding area BD1 and is located on one side of the third side a3 of the first driver chip IC1.

[0138] The second silver paste point 6 is located in the first bonding area BD1, and the second electrical test pad group 5 is located between the second silver paste point 6 and the first driver chip IC1.

[0139] Specifically, the display panel to be cut shown in Figure 7 has the following differences from the display panel to be cut shown in Figure 2: the second cutting line in Figure 7 can be located not only between the first driver chip IC1 and the third peripheral area BB3, but also between the first driver chip IC1 and the second peripheral area BB2.

[0140] Since the design schemes in Figures 2 and 5 require prior knowledge of future change requirements, i.e., whether to cut the left or right side, but this requirement is often difficult to determine, this disclosure proposes a display panel to be cut as shown in Figure 7. The GOA circuit adopts a double-sided counter-current design, i.e., each row of gate signal lines G connects to two GOA units, and the GOA circuit on each side supports forward and reverse scanning. The Ag glue dots and ET units in the first bonding area BD1 still adopt the symmetrical design on the left and right sides as shown in Figure 1. In this way, cutting either the left or right side of the display panel to be cut will not affect the supply of the gate signal, and the display panel can still work normally after cutting. This also provides great freedom for changing the size of the display panel. The top and left sides, or the top and right sides of the display panel to be cut can be cut, that is, the left or right sides and the top part of the display panel to be cut can be arbitrarily cut, and different sizes of display panels can be obtained.

[0141] As shown in Figure 8, Figure 8 is a structure of a display panel obtained by cutting the display panel to be cut shown in Figure 7 along the first cutting line L1 and the second cutting line L2 on the right. When the first cutting line L1 and the second cutting line L2 in the display panel to be cut shown in Figure 7 are in the same position as those in the display panel to be cut shown in Figure 2, the main difference between the display panel shown in Figure 8 and the display panel shown in Figure 4 is that the peripheral area (first peripheral area BB1) where the driver chip (IC1) is located in Figure 8 also includes: at most a portion of the second electrical test pad group 5 located on the side of the driver chip (IC1) away from the first electrical test pad group 2. For example, when the second cut line L2 falls into the second electrical test pad group 5, the peripheral area (first peripheral area BB1) where the driver chip (IC1) is located in FIG8 also includes at most a portion of the second electrical test pad group 5 located on the side of the driver chip (IC1) away from the first electrical test pad group 2; when the second cut line L2 is located between the driver chip (IC1) and the second electrical test pad group 5, the peripheral area (first peripheral area BB1) where the driver chip (IC1) is located in FIG8 does not include the second electrical test pad group 5.

[0142] As shown in Figure 9, Figure 9 is a structure of a display panel obtained by cutting the display panel to be cut shown in Figure 7 along the first cutting line L1 and the second cutting line L2 on the left. When the second cutting line L2 on the left and the second cutting line L2 on the right in Figure 7 are in the same position, the display panel shown in Figure 9 is symmetrical to the display panel shown in Figure 8.

[0143] As shown in Figure 10, Figure 10 illustrates another structure of a display panel to be cut according to an embodiment of this disclosure. The structure of the display panel to be cut shown in Figure 10 is basically the same as that of the display panel to be cut shown in Figure 7. The difference between the two is that the fourth peripheral area BB4 of the display panel to be cut shown in Figure 10 includes a second bonding area BD2, and the display area AA has a third center line M3 that extends in the same direction as the gate signal line G. The display panel to be cut shown in Figure 10 also includes:

[0144] The second driver chip IC2 is located in the second bonding area BD2, and the second driver chip IC2 and the first driver chip IC1 are symmetrically arranged about the third center line M3.

[0145] The third electrical test pad group 2' is located in the second bonding area BD2, and the third electrical test pad group 2' and the first electrical test pad group 2 are symmetrically arranged about the third center line M3;

[0146] The third silver glue point 3' is located in the second bonding area BD2, and the third silver glue point 3' and the first silver glue point 3 are symmetrically arranged about the third center line M3;

[0147] The fourth electrical test pad group 5' is located in the second bonding area BD2, and the fourth electrical test pad group 5' and the second electrical test pad group 5 are symmetrically arranged about the third center line M3;

[0148] The fourth silver glue point 6' is located in the second binding area BD2, and the fourth silver glue point 6' and the second silver glue point 6 are symmetrically arranged about the third center line M3.

[0149] Specifically, in Figures 2, 5, and 7, the upper portion cut off along the first cutting line L1 results in significant waste. As shown in Figure 10, compared to Figure 7, a second bonding area BD2 is added. This second bonding area BD2 is symmetrically designed with the first bonding area BD1, sharing the same constituent units and connections. The second bonding area BD2 also has corresponding Ag glue dots and ET units, and the GOA remains a double-sided offset design. Thus, when the display panel does not require a size change, either the second bonding area BD2 or the first bonding area BD1 can be cut normally. When the display panel needs a size change, the signals of the upper and lower gate signal lines G and data signal lines D are not interrupted along the first cutting line L1, allowing both the upper and lower display panels to function normally. Furthermore, after the display panel shown in Figure 10 is cut into two display panels, the left or right side of each display panel can also be cut along the second cutting line L2. Therefore, using the display panel shown in Figure 10, one display panel can be transformed into two screens of different sizes through cutting, increasing flexibility for display panel size changes without causing resource waste.

[0150] As shown in Figures 11 and 12, Figures 11 and 12 are the structures of the upper and lower display panels obtained by cutting the display panel to be cut shown in Figure 10 along the first cutting line L1 and the second cutting line L2 on the right.

[0151] As shown in Figure 13, which illustrates another structure of a display panel to be cut according to an embodiment of this disclosure, the display area AA of the display panel to be cut has a first center line M1 extending along the extension direction of the data signal line D. The first center line M1 divides the display area AA into a first display area AA1 and a second display area AA2. The structures of the first peripheral area BB1 and the second peripheral area BB2 corresponding to the first display area AA1 are the same as those shown in Figure 2. The display panel to be cut also includes a second driver chip IC2, a second electrical test pad group 5, and a second silver paste point 6, which are disposed corresponding to the second display area AA2. The second driver chip IC2 is located between the first center line M1 and the second electrical test pad group 5. The first driver chip IC1 and the second driver chip IC2 are symmetrically arranged about the first center M1. The first electrical test pad group 2 and the second electrical test pad group 5 are symmetrically arranged about the first center line M1. The first silver paste point 3 and the second silver paste point 6 are symmetrically arranged about the first center line M1. The second cutting line L2 is located between the first driver chip IC1 and the second driver chip IC2.

[0152] The solutions in Figures 2, 5, 7, and 10 are limited by the position of the IC. When making a vertical cut at the second cutting line L2, it cannot be too close to the center of the display panel, otherwise the IC will be damaged, resulting in a poor display. Therefore, as shown in Figure 13, a second driver chip IC2 is added to the first bonding area BD1 of the display panel to be cut. In this way, the data signal line D of the first display area AA1 is connected to the first driver chip IC1, and the data signal line D of the second display area AA2 is connected to the second driver chip IC2, becoming a dual IC drive. The two ICs provide data signals to the first display area AA1 and the second display area AA2 respectively. The two sides of the entire display area AA still have the GOA double-sided offset design. In this way, it is possible to cut arbitrarily between the first driver chip IC1 and the second driver chip IC2, and it can be divided into two display screens, left and right, and the gate signal and data signal can be provided normally. That is, it can still display normally after being divided into two display panels.

[0153] Specifically, as shown in Figure 13, the second cutting line L2 coincides with the first center line M1, thus obtaining two symmetrical display panels after cutting.

[0154] As shown in Figures 14 and 15, Figures 14 and 15 are the structures of the left and right display panels obtained by cutting the display panel to be cut shown in Figure 13 along the first cutting line L1 and the second cutting line L2, respectively.

[0155] It should be noted that Figures 4, 6, 8, 9, 11, 12, 14, and 15 are only schematic representations of several types of display panels obtained after cutting. Of course, they are not limited to these. By moving the positions of the first cutting line L1 and the second cutting line L2, display panels of different sizes can be obtained.

[0156] The aforementioned method of cutting the display panel to be cut along the first cutting line L1 and / or the second cutting line L2 allows for the rapid production of display panels of different sizes, enabling quick sample delivery to customers and timely response, thus saving on sample production costs and time. However, for example, cutting along the first cutting line L1, i.e., a horizontal cut of a fixed-size display panel, can also cause some problems. This is because a horizontal cut severs the entire display panel, including the GOA circuits on both sides and the internal pixel areas. The exposed metal lines after cutting will corrode, and this corrosion will extend along the direction of the metal lines. In particular, the GOA signal traces and GOA cascade traces in the GOA circuit are connected to the entire GOA circuit. Therefore, if one GOA unit fails due to metal line corrosion, the entire GOA circuit will fail.

[0157] To address the issue of metal wire corrosion after transverse cutting, taking the display panel to be cut as shown in Figure 7 as an example, as shown in Figure 16, Figure 16 is a simplified structure of the display panel shown in Figure 7. Figure 17 shows the display panel obtained by cutting the display panel to be cut along the first cutting line L1 shown in Figure 16. As shown in Figure 18, Figure 18 shows the specific structure of the four first GOA units (e.g., GOA2, GOA3, GOA4, and GOA5) and the wiring in the second peripheral area BB2 in Figure 16. As shown in Figure 19, Figure 19 shows the specific structure of two adjacent first GOA units (e.g., GOA2 and GOA3) and the wiring in Figure 18. The peripheral area BB2 also includes a trace group 7 located on the side of the first GOA unit (GOA1, GOA2, GOA3...GOA(n-1), GOA(n)) away from the display area AA. Each trace in the trace group 7 extends along the extension direction Y of the data signal line D. The trace group 7 includes a ground trace 71, a common trace 72, a GOA signal trace 73, and a GOA cascade trace 74 arranged sequentially along the extension direction X of the gate signal line G. The GOA cascade trace 74 is set close to the first GOA unit (e.g., GOA2, GOA3, GOA4, and GOA5). Among them, the GOA signal trace 73 may include a clock signal line (CLK), a low voltage signal line (VGL), a high voltage signal line (VGH), a start signal line (STV1, STV2, etc.), etc. The GOA cascade trace 74 is, for example, connecting the output of the previous row of GOA units and the input of the next row of GOA units.

[0158] The first GOA unit (GOA1, GOA2, GOA3...GOA(n-1), GOA(n)) includes: multiple thin film transistors T, at least one capacitor C, and multiple connection traces 8 extending along the extension direction of the gate signal line G; one end of the connection trace 8 is electrically connected to the corresponding thin film transistor T, and the other end of the connection trace 8 is connected to the corresponding GOA signal trace 73 through a via V.

[0159] Each adjacent first GOA unit (e.g., GOA2 and GOA3) has a cutting region CC that extends along the direction of the gate signal line G and crosses the trace group 7. The area of ​​the GOA signal trace 73 and the GOA cascade trace 74 corresponding to the cutting region CC is the first region 70. The connecting trace 8 and the via V do not overlap with the first region 70. Thus, when the display panel is horizontally cut along the first cutting line L1, for example, when the first cutting line L1 intersects with GOA2, the ground trace 71, the common trace 72, the GOA signal trace 73, and the GOA cascade trace 74, which are at the same horizontal position as GOA2, are all cut off. Since the GOA signal trace 73 and the GOA cascade trace 74 are connected to the entire GOA circuit, once the GOA signal trace 73 and the GOA cascade trace 74 are cut off and exposed for corrosion, the entire GOA circuit will fail. This embodiment of the disclosure sets a cutting region CC between adjacent first GOA units (e.g., GOA2 and GOA3). After cutting along the first cutting line L1, the trace group 7 of the adjacent cutting region CC below the first cutting line L1 is laser-cut. Since the laser cutting only cuts the traces, other insulating layers in the display panel will not be cut. Therefore, vertically cutting the traces can prevent corrosion from entering the GOA area below the cutting region CC along the vertical long traces. Furthermore, the laser cutting of the traces only cuts the vertical traces. Therefore, after all the vertical traces in the trace area are cut, the cutting will not continue to the GOA unit side, thus not affecting the internal traces of the GOA unit. In addition, since the connecting traces 8 and vias V do not overlap with the first region 70, the connecting traces 8 and vias V can be avoided from being affected by the cutting, thus not affecting the operation of the GOA circuit.

[0160] Specifically, as shown in Figures 18 and 19, the first GOA unit (e.g., GOA3) includes at least one connection trace 8 on both sides of the data signal line D extending in the direction of extension, which is close to the adjacent first region 70. The connection trace 8 close to the first region 70 is arranged to follow the shape of the first region 70. In order to avoid the influence of laser cutting on the connection trace 8, all the connection traces 8 connected to the via V are arranged outside the cutting region CC, which can avoid cutting the connection trace 8 close to the first region 70 when the laser cuts the trace group 7 in the cutting region CC.

[0161] Specifically, as shown in Figures 18 and 19, the vias V connecting the connection trace 8 and the GOA signal trace 73, located near the first region 70, are situated on opposite sides of the first region 70 along the extension direction Y of the data signal line D. To avoid the impact of laser cutting on the connection trace 8, the positions of the vias V are redesigned. Taking GOA3 as an example, the vias V connected to the upper connection trace 8 of GOA3 are moved downwards, and the vias V connected to the lower connection trace 8 of GOA3 are moved upwards. This concentrates the vias V in the central region corresponding to the GOA unit, preventing the vias V from burning out when the laser high-temperature cuts the trace group 7 of the cutting area CC, thus avoiding short circuits with surrounding traces and compromising the function of the GOA unit. Furthermore, by concentrating the traces of the original cutting area CC on one side, the cutting time can be effectively reduced. Simultaneously, the vias and connection traces inside the GOA unit are redesigned to avoid short circuits and open circuits in the connection traces caused by cutting.

[0162] As shown in Figures 20 and 21, Figure 20 is a partially enlarged schematic diagram of the connection between part of the GOA signal trace 73 and the connecting line 8 in Figure 19 through via V, and Figure 21 is a cross-sectional schematic diagram along the EE' direction in Figure 20. The display panel generally includes a gate metal layer, a source / drain metal layer and a transparent electrode layer stacked together. The GOA signal trace 73 is generally traced through the gate metal layer, and the connecting line 8 is generally traced through the source / drain metal layer. The GOA signal trace 73 and the connecting line 8 are generally electrically connected to the transparent conductive part 9 located on the transparent electrode layer above through via V. In this way, the electrical signal on the GOA signal trace 73 is transmitted to the thin film transistor T of the GOA unit through the connecting line 8.

[0163] Specifically, as shown in Figures 18 and 19, the active layer Act1 of the thin-film transistor T, which is electrically connected to the connection trace 8 located near the first region 70, includes at least two first U-shaped portions U1 arranged along the extension direction X of the gate signal line G, with the at least two first U-shaped portions U1 closely connected. This allows the thin-film transistor T, which is electrically connected to the connection trace 8 located near the first region 70, to be designed on the right, saving space on the left side and providing more room for deformation of the thin-film transistor T on the left side, so that the connection trace 8 and the via V are located on the upper and lower sides of the first region 70.

[0164] Specifically, as shown in Figures 18 and 19, the active layer Act2 of the thin-film transistor T, which is electrically connected to the GOA cascade trace 74 and located near the first U-shaped portion U1, includes at least three second U-shaped portions U2 arranged along the extension direction X of the gate signal line G. The height of the second U-shaped portions U2 along the extension direction Y of the data signal line D is less than 3 / 4 of the height of the first U-shaped portion U1 along the extension direction Y of the data signal line D. In related technologies, the height of the second U-shaped portion U2 along the data signal line D extension direction Y is generally less than the height of the first U-shaped portion U1 along the data signal line D extension direction Y, but greater than 3 / 4 of the height of the first U-shaped portion U1 along the data signal line D extension direction Y. This disclosure sets the height of the second U-shaped portion U2 along the data signal line D extension direction Y to be shorter, but it is necessary to ensure that the aspect ratio of the thin-film transistor T electrically connected to the GOA cascade trace 74 and located near the first U-shaped portion U1 remains unchanged. That is, the shape of some thin-film transistor T is redesigned. Without changing the electrical parameters, the size of some thin-film transistor T is redesigned so that the connection trace 8 and via V are rearranged internally. This provides more wiring space for the connection trace 8 and via V located near the first region 70, so that the connection trace 8 and via V located near the first region 70 are located on the upper and lower sides of the first region 70.

[0165] Specifically, as shown in Figures 16, 18 and 19, when the second GOA circuit 4 is included, that is, when the GOA of the display panel to be cut adopts a double-sided offset design, the second GOA unit of the second GOA circuit 4 and the first GOA unit are symmetrically arranged about the first center line M1 extending along the data signal line D of the display area AA.

[0166] It should be noted that the GOA unit provided in this disclosure is applicable to various structures in related technologies, and Figures 18 and 19 are only partial structures of one type of circuit.

[0167] Specifically, the structure of GOA circuit 1' in Figures 4, 6, 8, 9, 11, 12, 14 and 15 is the same as the structure shown in Figure 18. That is, the peripheral area where GOA circuit 1' is located also includes a trace group 7 located on the side of the GOA unit away from the display area AA. Each trace of the trace group 7 extends along the extension direction Y of the data signal line D. The trace group 7 includes a ground trace 71, a common trace 72, a GOA signal trace 73 and a GOA cascade trace 74 arranged sequentially along the extension direction of the gate signal line G. The GOA cascade trace 74 is located close to the GOA unit.

[0168] The GOA unit includes: multiple thin-film transistors T, at least one capacitor C, and multiple connection traces 8 extending along the extension direction X of the gate signal line G; one end of the connection trace 8 is electrically connected to the corresponding thin-film transistor T, and the other end of the connection trace 8 is connected to the corresponding GOA signal trace 73 through a via V.

[0169] There is a cutting region CC between adjacent GOA cells that extends along the extension direction X of the gate signal line G and crosses the trace group 7. The area of ​​GOA signal trace 73 and GOA cascade trace 74 corresponding to the cutting region CC is the first region 70. The connecting trace 8 and the via V do not overlap with the first region 70.

[0170] Specifically, as shown in Figures 4, 6, 8, 9, 11, 12, 14, 15, 18 and 19, the GOA unit includes at least one connection trace 8 on both sides of the data signal line D extending in the direction Y, which is close to the first region 70. The connection trace 8 close to the first region 70 is arranged in a conformal manner along the first region 70.

[0171] The via V connecting the connection trace 8 and the GOA signal trace 73, which are located near the first region 70, is located on opposite sides of the first region 70 along the extension direction Y of the data signal line D.

[0172] Specifically, as shown in Figures 4, 6, 8, 9, 11, 12, 14, 15, 18 and 19, the active layer Act1 of the thin-film transistor T, which is electrically connected to the connection trace 8 disposed near the first region 70, includes at least two first U-shaped portions U1 arranged along the extension direction X of the gate signal line G, and the at least two first U-shaped portions U1 are closely connected.

[0173] Specifically, as shown in Figures 4, 6, 8, 9, 11, 12, 14, 15, 18, and 19, the active layer Act2 of the thin-film transistor T, which is electrically connected to the GOA cascade trace 74 and located near the first U-shaped portion U1, includes at least three second U-shaped portions U2 arranged along the extension direction X of the gate signal line G. The height of the second U-shaped portions U2 along the extension direction Y of the data signal line D is less than 3 / 4 of the height of the first U-shaped portion U1 along the extension direction Y of the data signal line D.

[0174] Based on the same inventive concept, this disclosure also provides a display device, including the display panel described above. Since the principle by which this display device solves the problem is similar to that of the display panel described above, the implementation of the display device provided in this disclosure can refer to the implementation of the display panel described above, and repeated details will not be elaborated further.

[0175] In specific implementations, the display device provided in the embodiments of this disclosure can be an organic light-emitting display device or a liquid crystal display device, and there is no limitation herein.

[0176] In specific implementations, the display device provided in the embodiments of this disclosure can be an in-vehicle display screen, etc. Other essential components of this display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting the present invention. This display device includes, but is not limited to: a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply, etc. Furthermore, those skilled in the art will understand that the above structure does not constitute a limitation on the display device provided in the embodiments of this disclosure. In other words, the display device provided in the embodiments of this disclosure may include more or fewer of the above components, or combine certain components, or have different component arrangements.

[0177] This disclosure provides a display panel, display device, and display panel to be cut. By changing the design of the GOA (Getting Object Adapter) units, which were originally arranged alternately on the left and right frame areas on both sides of the display area in related technologies, to be arranged only on one side of the display area, and by designing the first electrical test pad group located on both sides of the IC only on one side of the IC, it is possible to manufacture the display panel to be cut using only one mask, and then obtain display panels of different sizes by cutting. For example, the display area can be vertically cut from the right side of the first driver chip and horizontally cut from the top side of the display area to obtain display panels of different sizes. With the above design, the size of the display panel can be changed only by cutting without changing the mask, and the horizontal and vertical dimensions of the display panel can be changed. That is, different sizes of screens can be made using the same mask to meet different customer needs, which not only saves material costs for mask changes, but also reduces the change cycle.

[0178] Although preferred embodiments have been described in this disclosure, it should be understood that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of the embodiments of this disclosure. Therefore, this disclosure is also intended to include such modifications and variations if they fall within the scope of the claims of this disclosure and their equivalents.

Claims

1. A display panel, wherein, It includes multiple pixels, multiple signal lines, and a driving circuit. The signal lines are electrically connected to the pixels. The signal lines have a first end and a second end along their extension direction. The first end of the signal line is electrically connected to the driving circuit, and the second end of the signal line is flush with the outer edge of the display panel.

2. The display panel as claimed in claim 1, wherein, The display panel includes a display area and a peripheral area surrounding the display area. The driving circuit is located within the peripheral area, and the peripheral area where the driving circuit is located does not have the pixel. The second end of the signal line is located within the peripheral area, and the peripheral area where the second end of the signal line is located includes the pixel.

3. The display panel as described in claim 2, wherein, The outermost pixel in the peripheral area where the second end of the signal line is located is either a complete pixel or an incomplete pixel.

4. The display panel as claimed in claim 3, wherein, It includes an array substrate and a counter substrate arranged opposite each other, and the second end of the signal line is flush with the outer edges of the array substrate and the counter substrate; The peripheral area is provided with a sealing adhesive that connects the array substrate and the opposing substrate. The outer edge of the sealing adhesive in the peripheral area where the second end of the signal line is located covers at most the outer edges of the array substrate and the opposing substrate.

5. The display panel as claimed in claim 4, wherein, The outer edge of the display panel corresponding to the second end of the signal line is provided with protective adhesive.

6. The display panel as described in any one of claims 2-5, wherein, The multiple signal lines include multiple data signal lines and multiple gate signal lines that are insulated and cross each other within the display area. The driving circuit includes a driving chip and a GOA circuit. The driving chip is located in the peripheral area on one side of the first end of the data signal line. The GOA circuit is located in the peripheral area on one side of the first end of the gate signal line. The GOA circuit includes multiple GOA units arranged in cascade. The first end of each of the data signal lines is electrically connected to the driver chip, and the first end of each of the gate signal lines is electrically connected to each of the GOA units in a corresponding manner. The second end of at least one of the data signal lines and the gate signal lines is flush with the outer edge of the display panel.

7. The display panel as claimed in claim 6, wherein, The second end of the data signal line is flush with the outer edge of the display panel.

8. The display panel as claimed in claim 6 or 7, wherein, The second end of the gate signal line is flush with the outer edge of the display panel.

9. The display panel as claimed in claim 8, wherein, The peripheral area where the driver chip is located also includes: a first electrical test pad group located on the side of the driver chip closer to the GOA circuit, and a first silver paste dot located on the side of the first electrical test pad group away from the driver chip.

10. The display panel as claimed in claim 9, wherein, The surrounding area where the driver chip is located also includes: at most a portion of the second electrical test pad group located on the side of the driver chip away from the first electrical test pad group.

11. The display panel as claimed in claim 9, wherein, The display area has a first center line extending along the extension direction of the data signal line, and the driver chip has a second center line extending along the extension direction of the data signal line, the second center line being located between the first center line and the GOA circuit.

12. The display panel according to any one of claims 6-11, wherein, The peripheral area where the GOA circuit is located also includes a first start signal line and a second start signal line located on the side of the GOA unit away from the display area, with the end of the first start signal line away from the driver chip floating. The output signal terminal of the last row of GOA units closest to the driver chip is connected to the second start signal line. Except for the last row of GOA units, the output signal terminals of the other rows of GOA units are respectively connected to the input signal terminals of the GOA units in the next row connected to them.

13. The display panel according to any one of claims 6-12, wherein, The peripheral area where the GOA circuit is located also includes a trace group located on the side of the GOA unit away from the display area. Each trace of the trace group extends along the extension direction of the data signal line. The trace group includes a ground trace, a common trace, a GOA signal trace, and a GOA cascade trace arranged sequentially along the extension direction of the gate signal line. The GOA cascade trace is located close to the GOA unit. The GOA unit includes: a plurality of thin-film transistors, at least one capacitor, and a plurality of connection traces extending along the extension direction of the gate signal line; one end of the connection trace is electrically connected to the corresponding thin-film transistor, and the other end of the connection trace is connected to the corresponding GOA signal trace through a via. There is a cut area between adjacent GOA units that extends along the extension direction of the gate signal line and crosses the trace group. The area of ​​the GOA signal trace and the GOA cascade trace corresponding to the cut area is a first area. The connecting trace and the via do not overlap with the first area.

14. The display panel as claimed in claim 13, wherein, The GOA unit includes at least one connection trace on both sides of the data signal line extension direction, which is close to the first region. The connection trace close to the first region is arranged to follow the shape of the first region. The vias connecting the connection traces and the GOA signal traces located near the first region are situated on opposite sides of the first region along the extension direction of the data signal lines.

15. The display panel as claimed in claim 14, wherein, The active layer of the thin-film transistor electrically connected to the connection trace disposed near the first region includes at least two first U-shaped portions arranged along the extension direction of the gate signal line, the at least two first U-shaped portions being closely connected.

16. The display panel as claimed in claim 15, wherein, The active layer of the thin-film transistor, which is electrically connected to the GOA cascade trace and disposed near the first U-shaped portion, includes at least three second U-shaped portions arranged along the extension direction of the gate signal line, wherein the height of the second U-shaped portions along the extension direction of the data signal line is less than 3 / 4 of the height of the first U-shaped portion along the extension direction of the data signal line.

17. A display device, wherein, Includes the display panel as described in any one of claims 1-16.

18. A display panel to be cut, wherein, It includes a display area and a surrounding area around the display area, the surrounding area including a first surrounding area having a first binding area and a second surrounding area disposed adjacent to the first surrounding area; The display panel to be cut also includes: Multiple gate signal lines are located in the display area; Multiple data signal lines are located in the display area, and the data signal lines and the gate signal lines are isolated. The edges are intersected and defined to limit multiple pixels; The first GOA circuit is located in the second peripheral area. The first GOA circuit includes a plurality of cascaded first GOA units, and the first GOA units are electrically connected to the gate signal lines one by one. The first starting signal line is located in the second peripheral area and on the side of the first GOA unit away from the display area. The input signal terminal of the first GOA unit in the first row is connected to the first starting signal line. Except for the first GOA unit in the first row, the input signal terminals of the first GOA units in the other rows are respectively connected to the output signal terminals of the first GOA units in the row before them. The second starting signal line is located in the second peripheral area and on the side of the first GOA unit away from the display area. The output signal terminal of the last row of the first GOA unit is connected to the second starting signal line. Except for the last row of the first GOA unit, the output signal terminals of the first GOA units in each other row are respectively connected to the input signal terminals of the first GOA units in the next row connected to them. A first driver chip is located in the first bonding area. The first driver chip includes: a first side that is adjacent to the display area and extends along the extension direction of the first peripheral area, and a second side that is adjacent to the first side and close to the second peripheral area. The first electrical test pad group is located in the first bonding area and on one side of the second side of the first driver chip.

19. The display panel to be cut as described in claim 18, wherein, It also includes a first silver paste dot located in the first bonding area, and the first electrical test pad group is located between the first silver paste dot and the first driver chip.

20. The display panel to be cut as described in claim 19, wherein, The surrounding area also includes a third surrounding area disposed opposite to the second surrounding area, wherein the width of the second surrounding area is greater than the width of the third surrounding area.

21. The display panel to be cut as described in claim 20, wherein, The display area has a first center line extending along the extension direction of the data signal line, and the first driver chip has a second center line extending along the extension direction of the data signal line, the second center line being located between the first center line and the first electrical test pad group.

22. The display panel to be cut as described in claim 21, wherein, It includes a first cutting line and / or a second cutting line, wherein the first cutting line extends in the same direction as the gate signal line and is located in any area of ​​the display area; the second cutting line extends in the same direction as the data signal line and is located between the first driver chip and the third peripheral area.

23. The display panel to be cut as described in claim 19, wherein, The peripheral area further includes a third peripheral area disposed opposite to the second peripheral area, the width of the second peripheral area being the same as the width of the third peripheral area; the first driving chip further includes a third side disposed opposite to the second side; The display panel to be cut also includes: The second GOA circuit is located in the third peripheral area. The second GOA circuit includes multiple cascaded second GOA units, and each second GOA unit is electrically connected to the gate signal line in a one-to-one correspondence. The third starting signal line is located in the third peripheral area and on the side of the second GOA unit away from the display area. The input signal terminal of the second GOA unit in the first row is connected to the third starting signal line. Except for the second GOA unit in the first row, the input signal terminals of the second GOA units in the other rows are respectively connected to the output signal terminals of the second GOA units in the row before them. The fourth starting signal line is located in the third peripheral area and on the side of the second GOA unit away from the display area. The output signal terminal of the last row of the second GOA units is connected to the fourth starting signal line. Except for the last row of the second GOA units, the output signal terminals of the other rows of the second GOA units are respectively connected to the input signal terminals of the second GOA units in the next row connected to them. The second electrical test pad group is located in the first bonding area and on one side of the third side of the first driver chip; The second silver paste dot is located in the first bonding area, and the second electrical test pad group is located between the second silver paste dot and the first driver chip.

24. The display panel to be cut as described in claim 23, wherein, The peripheral area also includes a fourth peripheral area disposed opposite to the first peripheral area, the fourth peripheral area including a second binding area, and the display area having a third center line with the same extension direction as the gate signal line; The display panel to be cut also includes: The second driver chip is located in the second bonding area, and the second driver chip and the first driver chip are symmetrically arranged about the third center line. The third electrical test pad group is located in the second bonding area, and the third electrical test pad group and the first electrical test pad group are symmetrically arranged about the third center line; The third silver glue point is located in the second bonding area, and the third silver glue point and the first silver glue point are symmetrically arranged about the third center line. The fourth electrical test pad group is located in the second bonding area, and the fourth electrical test pad group and the second electrical test pad group are symmetrically arranged about the third center line; The fourth silver adhesive point is located in the second bonding area, and the fourth silver adhesive point and the second silver adhesive point are symmetrically arranged about the third center line.

25. The display panel to be cut as described in claim 23 or 24, wherein, It includes a first cutting line and / or a second cutting line, wherein the first cutting line extends in the same direction as the gate signal line and is located in any area of ​​the display area; the second cutting line extends in the same direction as the data signal line and is located between the first driver chip and the second peripheral area, or the second cutting line is located between the first driver chip and the third peripheral area.

26. The display panel to be cut as described in claim 23, wherein, The display area has a first center line extending along the extension direction of the data signal line, the first center line dividing the display area into a first display area and a second display area, and the first driver chip is located between the first center line and the first electrical test pad group. The display panel to be cut also includes a second driving chip corresponding to the second display area, the second driving chip being located between the first center line and the second electrical test pad group.

27. The display panel to be cut as described in claim 26, wherein, The first driver chip and the second driver chip are symmetrically arranged about the first center line, the first electrical test pad group and the second electrical test pad group are symmetrically arranged about the first center line, and the first silver paste point and the second silver paste point are symmetrically arranged about the first center line.

28. The display panel to be cut as described in claim 27, wherein, It includes a first cutting line and / or a second cutting line, wherein the first cutting line extends in the same direction as the gate signal line and is located in any area of ​​the display area; the second cutting line extends in the same direction as the data signal line and is located between the first driver chip and the second driver chip.

29. The display panel to be cut as described in claim 28, wherein, The second cutting line coincides with the first center line.

30. The display panel to be cut as described in any one of claims 22, 25, 28, and 29, wherein, A first sealing adhesive is provided at the first cutting line position, and the first cutting line is located on the side of the first sealing adhesive that is away from the first peripheral area; A second sealing adhesive is provided at the location of the second cutting line, and the second cutting line is located on the side of the second sealing adhesive that is away from the second peripheral area.

31. The display panel to be cut as described in any one of claims 18-30, wherein, The second peripheral area also includes a trace group located on the side of the first GOA unit away from the display area. Each trace of the trace group extends along the extension direction of the data signal line. The trace group includes a ground trace, a common trace, a GOA signal trace, and a GOA cascade trace arranged sequentially along the extension direction of the gate signal line. The GOA cascade trace is located close to the first GOA unit. The first GOA unit includes: a plurality of thin-film transistors, at least one capacitor, and a plurality of connection traces extending along the extension direction of the gate signal line; one end of the connection trace is electrically connected to the corresponding thin-film transistor, and the other end of the connection trace is connected to the corresponding GOA signal trace through a via. There is a cut area between adjacent first GOA units that extends along the extension direction of the gate signal line and crosses the trace group. The area of ​​the GOA signal trace and the GOA cascade trace corresponding to the cut area is the first area. The connecting trace and the via do not overlap with the first area.

32. The display panel to be cut as described in claim 31, wherein, The first GOA unit includes at least one connection trace on both sides of the data signal line extension direction, which is close to the first region. The connection trace close to the first region is arranged to follow the shape of the first region. The vias connecting the connection traces and the GOA signal traces located near the first region are situated on opposite sides of the first region along the extension direction of the data signal lines.

33. The display panel to be cut as described in claim 32, wherein, The active layer of the thin-film transistor electrically connected to the connection trace disposed near the first region includes at least two first U-shaped portions arranged along the extension direction of the gate signal line, the at least two first U-shaped portions being closely connected.

34. The display panel to be cut as described in claim 33, wherein, The active layer of the thin-film transistor, which is electrically connected to the GOA cascade trace and disposed near the first U-shaped portion, includes at least three second U-shaped portions arranged along the extension direction of the gate signal line, wherein the height of the second U-shaped portions along the extension direction of the data signal line is less than 3 / 4 of the height of the first U-shaped portion along the extension direction of the data signal line.

35. The display panel to be cut as described in any one of claims 31-34, wherein, When the second GOA circuit is included, the second GOA unit of the second GOA circuit and the first GOA unit are symmetrically arranged about the first center line extending along the data signal line extension direction of the display area.

Images