Apparatus and method for burst communication within die architecture

Abstract

Methods and apparatus relating to more efficient data transmission within a die architecture. In some examples, a die package includes controller logic electrically coupled to a first communication bus and a second communication bus. The controller logic may receive an initial data transfer request over the first communication bus and determine a final address of the initial data transfer request. In addition, the controller logic component may assert a chip select signal of the second communication bus to initiate the data exchange. Upon asserting the chip select signal, the controller logic may receive an additional data transfer request over the first communication bus and determine an initial address of the additional data transfer request. Based on the determined initial address and final address, the controller logic may initiate an additional data exchange over the second communication bus without de-asserting the chip select signal.

Description

background Technical Field

[0001] This disclosure relates in general to die architecture, and more specifically to communication interfaces within die architecture.

[0002] Related technical descriptions

[0003] In various applications, die architecture relies on communication interfaces and protocols for data exchange. For example, integrated circuits (ICs) can connect to each other using communication interfaces that allow data transfer between ICs using specific protocols. These communication interfaces can include parallel or serial communication interfaces. For instance, the Serial Peripheral Interface (SPI) is a type of serial communication interface widely used in die architecture designs. For example, an SPI-enabled microcontroller can communicate with another IC via an SPI bus using the SPI protocol. Other ICs can be memory devices, sensors, or other processing devices, etc. Opportunities exist to improve communication interfaces, such as by increasing the efficiency and speed of data transfer when using corresponding protocols. Summary of the Invention

[0004] According to one aspect, an apparatus includes a controller logic component configured to receive a first data transmission request via a first communication bus. The controller logic component is also configured to determine a final address based on the first data transmission request. Furthermore, the controller logic component is configured to assert a first chip select signal on a second communication bus in response to the first data transmission request. When asserting the first chip select signal, the controller logic component is configured to: 1) initiate a first data exchange via the second communication bus; 2) receive a second data transmission request via the first communication bus; 3) determine an initial address based on the second data transmission request; 4) determine to continue asserting the first chip select signal based on the initial address and the final address; and 5) initiate a second data exchange via the second communication bus when the first chip select signal is asserted.

[0005] According to another aspect, a method performed by a controller logic component includes receiving a first data transmission request via a first communication bus. The method further includes determining a final address based on the first data transmission request. Additionally, the method includes asserting a first chip select signal on a second communication bus in response to the first data transmission request. When asserting the first chip select signal, the method includes: 1) initiating a first data exchange via the second communication bus; 2) receiving a second data transmission request via the first communication bus; 3) determining an initial address based on the second data transmission request; 4) determining to continue asserting the first chip select signal based on the initial address and the final address; and 5) initiating a second data exchange via the second communication bus when the first chip select signal is asserted.

[0006] According to another aspect, a non-transitory machine-readable storage medium includes instructions that, when executed by at least one processor, cause the at least one processor to perform operations. The operations include receiving a first data transfer request via a first communication bus. The operations also include determining a final address based on the first data transfer request. Furthermore, the operations include asserting a first chip select signal on a second communication bus in response to the first data transfer request. When asserting the first chip select signal, the operations include: 1) initiating a first data exchange via the second communication bus; 2) receiving a second data transfer request via the first communication bus; 3) determining an initial address based on the second data transfer request; 4) determining to continue asserting the first chip select signal based on the initial address and the final address; and 5) initiating a second data exchange via the second communication bus when the first chip select signal is asserted.

[0007] According to another aspect, a die package includes a processor electrically coupled to a controller logic unit via a first communication bus. The controller logic unit is configured to receive a first data transfer request from the processor via the first communication bus. The controller logic unit is also configured to determine a final address based on the first data transfer request. Furthermore, the controller logic unit is configured to assert a first chip select signal on a second communication bus in response to the first data transfer request. When asserting the first chip select signal, the controller logic unit is configured to: 1) initiate a first data exchange via the second communication bus; 2) receive a second data transfer request from the processor via the first communication bus; 3) determine an initial address based on the second data transfer request; 4) determine to continue asserting the first chip select signal based on the initial address and the final address; and 5) initiate a second data exchange via the second communication bus when the first chip select signal is asserted. Attached Figure Description

[0008] Figure 1 It is a block diagram based on some specific implementations of integrated circuits; Figure 2 These are block diagrams illustrating the various parts of an integrated circuit according to some specific implementations; Figure 3 This is a signal sequence diagram of a communication bus; Figure 4A and Figure 4B The diagram illustrates signal sequence diagrams based on some specific implementations; Figure 5 It is a flowchart of an exemplary process for providing burst transmissions via a communication interface, based on some specific implementations; Figure 6 This is a flowchart of another exemplary process for providing burst transmissions via a communication interface, based on some specific implementations; and Figure 7A and Figure 7BExamples of memory configurations for memory devices based on some specific implementations are shown. Detailed Implementation

[0009] While the features, methods, apparatus, and systems described herein may be embodied in various forms, some exemplary and non-limiting embodiments are shown in the accompanying drawings and described below. Some components described in this disclosure are optional, and some specific embodiments may include additional, different, or fewer components compared to those expressly described in this disclosure.

[0010] The implementation described herein relates to a communication interface within a die-based architecture that allows for more efficient data transfer, such as burst data transfer. For example, to perform some Serial Peripheral Interface (SPI) data transfer, the SPI controller receives a first command to read a certain amount of data, for example, from an address of the SPI device (e.g., the starting address of the memory location to be read). In response, the SPI controller asserts a chip select signal to the SPI device, generates a clock signal to the SPI device, and sends a read command to the SPI device, followed by the address, and in some cases, by "dummy" data. The SPI controller can then receive the read data in a subsequent clock cycle and deassert the chip select signal. If burst mode is supported, the SPI controller can assert the chip select signal until the maximum amount of data (e.g., the maximum number of bytes) (e.g., 64 bytes, 256 bytes, etc.) has been read before deasserting the chip select signal.

[0011] If the SPI controller receives a second command to read additional data from the second address, the SPI controller repeats the process described above. For example, the SPI controller re-asserts the chip select signal to the SPI device, generates a clock signal for the SPI device, and sends a second read command to the SPI device, followed by the second address, and in some cases, by additional "dummy" data. The SPI controller can then receive the additional data in a subsequent clock cycle and then deassert the chip select signal. Therefore, for each received read command, the SPI controller follows the process described above.

[0012] For example, Figure 3 An SPI interface 300 is illustrated, which includes a chip select (CS) signal 302, a clock (CLK) signal 304, multiple input / output (I / O) signals 306, and a data strobe (DQS) signal 308. For example, the SPI interface 300 can connect an SPI controller to another SPI device (e.g., an SPI slave device). This example assumes that the CS signal 302 is active low, meaning that the CS signal is asserted when transitioning from a higher voltage (e.g., 3.3 volts) to a lower voltage (e.g., 0 volts).

[0013] As illustrated, after the first assertion 311 of the CS signal 302, the CLK signal 304 begins timing at a frequency (e.g., transitioning from one state to another). Additionally, multiple I / O signals 306 (eight I / O signals in this example) provide the first READ command 320, followed by four address bytes 330 (each address byte 330 timing on alternating rising and falling edges of the CLK signal 304), and twenty fields of dummy data 340. After the dummy data 340, starting from the address location of the SPI device defined by address bytes 330 and ending at the address held for sixty-fourth byte, sixty-four bytes of data 350 are clocked out. After the last data byte 350 is clocked out, the CS signal 302 is deasserted 313.

[0014] To clock another 64 bytes of data (such as 64 bytes of data located in a memory location starting at a memory location after the memory location where the last byte of data was read), a second assertion 317 of the CS signal 302 is required. As illustrated, after the second assertion 317 of the CS signal 302, the CLK signal 304 starts timing, and multiple I / O signals 306 provide a second READ command 360. After the second READ command 360, four address bytes 370 are clocked out, followed by a second set of twenty fields of dummy data 380. After the second set of dummy data 380, starting from the address location of the SPI device defined by the four address bytes 370, a second set of 64 bytes of data 390 is clocked out. After the last data byte 390 is clocked out, the CS signal 302 is deasserted for the second time 319.

[0015] Compared to these data transmission methods, the implementation described herein provides more efficient data transmission, such as more efficient data transmission of the first set of sixty-four bytes of data 350 and the second set of sixty-four bytes of data 390. This implementation eliminates the need, for example, to provide a second READ command 360, a second set of four address bytes 370, and a second set of dummy data 380 to obtain the second set of sixty-four bytes of data 390.

[0016] For example, Figure 1An integrated circuit package 100 is illustrated, comprising a system-on-chip (SoC) 100 electrically connected to a first SPI device 130 and a second SPI device 132. The SoC 100 may include an SPI controller 110 (e.g., an SPI master device) communicatively coupled to one or more processors 106 via a communication bus 161. The communication bus 161 may be, for example, an Advanced High Performance Bus (AHB) or an Advanced Scalable Interface (AXI). Furthermore, each processor in the processors 106 is communicatively coupled to a memory 108 via a communication bus 171. Each processor 106 may be, for example, a graphics processing unit (GPU), a central processing unit (CPU), a microcontroller, or any other suitable processing device. The memory 108 may be, for example, a RAM device (e.g., an SRAM device), a flash memory device, or any other suitable memory device. For example, the processors 106 may be operable to execute instructions stored in the memory 108, or may be able to store and retrieve data.

[0017] Furthermore, each of the first SPI device 130 and the second SPI device (e.g., an SPI slave device) can be any device configured to communicate via an SPI bus, such as a flash memory device, a processing device such as a CPU or GPU, a sensor, or any other suitable device. The SPI controller 110 of the SoC 101 can communicate with each of the first SPI device 130 and the second SPI device 132 via SPI communication buses 121 and 123, respectively. For example, each of the SPI communication buses 121 and 123 may include a corresponding chip select line, as well as clock lines, data strobe lines, and input / output (I / O) lines (e.g., one, two, four, eight, or sixteen I / O lines).

[0018] For example, Figure 2 Examples of SPI communication buses 121 and 123 are illustrated. As illustrated, each of SPI communication buses 121 and 123 shares a clock (CLK) line 204, eight I / O lines 206, and a data strobe (DQS) line 208. Furthermore, each of the CLK line 204, I / O lines 206, and DQS line 208 electrically connects the SPI controller 110 to each of the first SPI device 130 and the second SPI device 132. Additionally, SPI communication bus 121 includes a first chip select (CS) line 202, and SPI communication bus 123 includes a second CS line 212. The first CS line 202 electrically connects the SPI controller 110 to the first SPI device 130, and the second CS line 212 electrically connects the SPI controller 110 to the second SPI device 132. In this example, the SPI controller 110 can be an SPI master device, and each of the first SPI device 130 and the second SPI device 132 can be an SPI slave device.

[0019] SPI controller 110 is configured to provide a clock signal on CLK line 204 and receive an optional data strobe signal (e.g., provided by a slave SPI device such as first SPI device 120) aligned with data on I / O line 206 on DQS line 208. Furthermore, SPI controller 110 is configured to provide a first CS signal on first CS line 202. For example, SPI controller 110 can assert and deassert the first CS signal on first CS line 202 to select and deselect first SPI device 130, respectively. Similarly, SPI controller 110 is configured to provide a second CS signal on second CS line 212. For example, SPI controller 110 can assert and deassert the second CS signal on second CS line 212 to select and deselect second SPI device 132, respectively. Additionally, SPI controller 110 can provide and receive data on I / O line 206, for example, according to the SPI protocol.

[0020] Return to reference Figure 1 The SPI controller 110 includes a control register 111, one or more SPI processors 112, and a timer 113. Each SPI processor 112 can be any suitable processing device, such as a CPU, GPU, or microcontroller. Furthermore, the control register 111 (e.g., an SRAM register, NVRAM register, flash memory register, etc.) includes a burst start address register 111A, a burst end address register 111B, and one or more signal configuration registers 111C. The signal configuration registers 111C define the configuration of the SPI communication buses 121 and 123. The processor 106 can write to the signal configuration registers 111C to configure one or more of the SPI communication buses 121 and 123. For example, the signal configuration registers 111C can define the frequency, phase, and polarity of the clock signals for the SPI communication buses 121 and 123, as well as the baud rate used for data transmission. The signal configuration register 111C can also define the state of the SPI communication buses 121 and 123, and can allow the selection of chip select signals (e.g., chip select signals to either of the SPI communication buses 121 and 123, as well as other configuration settings for the SPI communication buses 121 and 123).

[0021] Furthermore, the burst start address register 111A defines the start address of the requested data exchange (e.g., data exchange received via communication bus 161), and the burst end address register 111B defines the end address of the requested data exchange. Although only one set of control registers 111 is illustrated for simplicity, in some examples, the SPI controller 110 includes a set of control registers 111 for each SPI bus (such as each of the SPI communication buses 121, 123).

[0022] For example, processor 106 can provide signaling representing a data transfer request (such as a data read request) to SPI controller 110 via communication bus 161. A data read request is a request for data to be read from first SPI device 130. The data read request may be based on, for example, an AHB or AXI protocol. The data read request may identify the address of the data to be read (e.g., a relative address mapped to first SPI device 130). SPI processor 112 of SPI controller 110 can determine a start address from the data read request (e.g., the address of the first data byte to be read, for which the data transfer request is received), and can write the start address to burst start address register 111A. Furthermore, SPI processor 112 can determine an end address based on the last address received in the data read request. For example, as described herein, the end address may be the last address received for the data read request.

[0023] In some examples, the SPI processor 112 can determine the end address based on the start address and the number of bytes identified in the data read request. For example, the data read request may identify the number of bytes to be read (or written). The SPI processor 112 can determine the number of bytes to read from the data read request and may add the number of bytes to the start address to determine the end address. In some examples, the SPI processor 112 may divide the number of bytes by a factor (such as four) to determine the number of address locations and may add the number of address locations to the start address to determine the end address. The SPI processor 112 may write the end address to the burst end address register 111B.

[0024] Furthermore, to initiate a data read from the first SPI device 130, the SPI controller 110 can assert the chip select signal on the SPI communication bus 121 and can begin providing a clock signal (e.g., at a configured frequency). The SPI controller 110 can then initiate a data transfer with the first SPI device 130. For example, the SPI controller 110 can provide a READ command via the I / O lines of the SPI communication bus 121, followed by the corresponding SPI start address. The SPI start address can be based on a first address received in the data read request. In some examples, dummy data follows the SPI start address. For example, dummy data can follow the SPI start address to allow the slave device (such as the first SPI device 130 and the second SPI device 132) sufficient time to access the memory and make the data ready to be clocked out. The SPI controller 110 can then receive the requested amount of data from the first SPI device 130 via the I / O lines. For example, as the SPI controller 110 continues to provide the requested amount of data via a clock signal, the first SPI device 130 begins to provide data via I / O lines starting from a memory location mapped to the SPI start address until the data is clocked out, thereby completing the first data transfer of the requested amount of data.

[0025] Once the last data (e.g., the last data byte, the last data word, etc.) is received, the SPI controller 110 stops providing a clock signal, but keeps the chip select signal asserted. In other words, although data transmission is complete, the SPI controller 110 maintains the chip select signal of the first SPI device 130 until it is asserted.

[0026] The SPI controller 110 can then receive additional data transfer requests, such as additional data read requests, from the processor 106 via the communication bus 161. An additional data read request may be a request to read additional data from the first SPI device 130. The additional data read request may identify an additional start address (e.g., the address from which to read or to begin reading), and in some examples, identify the amount of additional data to be read. The SPI processor 112 of the SPI controller 110 can then determine the additional start address based on the additional data read request as described herein. Furthermore, the SPI processor 112 may determine whether the additional start address follows consecutively after the end address stored in the burst end address register 111B. For example, the SPI processor 112 may determine whether the additional start address is greater than the end address stored in the burst end address register 111B by a predetermined amount (e.g., one). The predetermined amount can be any value characterizing a consecutive memory location storing the data requested from the first SPI device 130. For example, the predetermined amount may be one, two, four, eight, or any other suitable value.

[0027] As an example, Figure 7A and Figure 7B Examples of corresponding memory devices with contiguous memory locations in various configurations are shown. Figure 7A A memory device 700 within a first SPI device 130 is illustrated, comprising various memory locations including a first memory location 702, a second memory location 704, a third memory location 706, a fourth memory location 708, and a fifth memory location 710. In this example, the offset between consecutive memory locations is one. For example, the first memory location 702 is located at address 0x0000, and the second memory location 704 is located at address 0x0001. The second memory location 704 follows consecutively from the first memory location 702 (i.e., continuously) (e.g., one, such as 0x0001 - 0x0000 = 1). Similarly, the third memory location 706 follows consecutively from the second memory location 704, and the fourth memory location 708 follows consecutively from the third memory location 706. In this example, as illustrated, the fifth memory location 710 does not follow consecutively from the fourth memory location 708 because an additional memory location lies between the fourth memory location 708 and the fifth memory location 710 (e.g., mapped to an address).

[0028] However, Figure 7B A memory device 750 with consecutive memory locations offset by four is illustrated. For example, memory device 750 includes a first memory location 752, a second memory location 754, a third memory location 756, a fourth memory location 758, and a fifth memory location 760. The first memory location 752 is located at address 0x0000, and the second memory location 754 is located at address 0x0004. The second memory location 754 follows consecutively from the first memory location 752 (i.e., continuously) (e.g., four, such as 0x0004 - 0x0000 = 4). Similarly, the third memory location 756 follows consecutively from the second memory location 754, and the fourth memory location 758 follows consecutively from the third memory location 756. In this example, as illustrated, the fifth memory location 760 does not follow consecutively from the fourth memory location 758 because an additional memory location lies between the fourth memory location 758 and the fifth memory location 760 (e.g., mapped to an address).

[0029] Return to reference Figure 1If the additional start address received in the additional data transfer request is equal to the sum of a predetermined amount and the end address stored in the burst end address register 111B, then the SPI controller 110 may begin a second data transfer of the requested additional data amount. In this case, the SPI controller 110 begins to provide a clock signal and begins to receive additional data from the first SPI device 130 via the I / O lines of the SPI communication bus 121. Receiving additional data from the first SPI device 130 does not require the SPI controller to provide an additional READ command or an additional start address. The SPI controller 110 may also write the additional start address to the burst start address register 111A and further determine the additional end address as described herein, and write the additional end address to the burst end address register 111B.

[0030] However, if the additional start address does not continuously follow the end address stored in the burst end address register 111B (e.g., the additional start address is not equal to the sum of a predetermined amount and the end address stored in the burst end address register 111B), the SPI controller 110 can deassert the chip select signal to the first SPI device 130. The SPI controller 110 can then reassert the chip select signal (e.g., after a predetermined minimum time amount) to perform another complete SPI data transfer. For example, the SPI controller 110 can begin by providing a clock signal and can provide an additional READ command via the I / O lines of the SPI communication bus 121, followed by the requested additional start address. In some examples, dummy data follows the additional start address. The SPI controller 110 can then receive the amount of data requested for the additional data from the first SPI device 130 via the I / O lines. For example, while the SPI controller 110 continues to provide a clock signal, the first SPI device 130 begins by providing additional data via the I / O lines starting from the memory location mapped to the additional start address until the amount of additional data is clocked out. Once the last data (e.g., the last data byte, the last data word, etc.) is received, the SPI controller 110 stops providing a clock signal to complete the second data transfer. If it is determined that the address of the third data transfer is discontinuous, or if no request for the third data transfer is received within a predetermined amount of time, the SPI controller 10 can de-assert the chip select signal, as described herein.

[0031] The above process can then be repeated for additional data transfer requests (such as additional data read requests) received from processor 106. Although the above process has been described for reading data from an SPI device (such as the first SPI device 130), it can also be applied to other types of data transfers, such as data write requests. For example, instead of reading data from the first SPI device 130 via I / O lines, SPI controller 110 may write data to the first SPI device 130 according to the SPI protocol.

[0032] In some examples, the SPI controller 110 may de-assert the chip select signal if a predetermined amount of time has elapsed since the start of the initial data transfer. For example, in response to receiving an initial data transfer request (e.g., a read request) for the first SPI device 130, the SPI processor 112 may configure (e.g., write) a timer 113 with a value characterizing a predetermined amount of time (such as 10 microseconds). In some examples, the predetermined amount of time corresponds to the number of clock cycles of the internal bus of the SoC 101. In some cases, this value is based on the rate at which the consumer may request the next consecutive address and the power cost of the slave device due to keeping its chip request asserted. The SPI processor 112 may then start the timer 113. The timer 113 may expire at the end of the predetermined amount of time, thereby generating a timer signal (e.g., a timer interrupt) within the SPI controller 110. The SPI controller 110 may process the initial data transfer request as described herein. After completing the initial data transfer request and while maintaining the chip select signal to the first SPI device 130, if timer 113 expires (or has expired), the SPI controller 110 is configured to de-assert the chip select signal to the first SPI device 130. In some examples, in response to timer 113 expiring, the SPI controller 110 resets the burst start address register 111A and / or burst end address register 111B by writing data (e.g., all ones or all zeros) to each register. In some examples, and in response to timer 113 expiring, the SPI controller 110 resets the designated "valid bits" of the burst start address register 111A and / or burst end address register 111B. If the SPI controller 110 subsequently receives another data transfer request (e.g., a read or write data transfer request) from the processor 106, the SPI controller 110 initiates a full SPI transfer for the requested data. In other words, the SPI controller 110 initiates a chip select signal to the requested device (such as the first SPI device 130 or the second SPI device 132), providing a command (such as a READ or WRITE command) via I / O lines, followed by a start address, and in some examples, dummy data. Then, as described herein, the data transfer to the processor 106 is completed, and as described herein, the assertion to the device's chip select signal is maintained. The SPI processor 112 may reset timer 113 upon receiving each data transfer request from the processor 106.

[0033] Figure 4AAn example of communication signal 400 is illustrated, which may be provided in at least some examples of a communication bus 161 connecting the SPI controller 110 to the processor 106. In this example, communication bus 161 is an Advanced High-Performance Bus (AHB). As illustrated, communication signal 400 may include HTRANS signal 402, HADDR signal 404, HREADY signal 406, and HRDATA signal 408. As known for the AHB protocol, HTRANS signal 402 indicates the transfer type, HREADY signal 406 indicates the initiation of data transfer, HADDR signal 404 defines the system address, and HRDATA signal 408 defines the data being transferred (e.g., for reading and writing). Communication bus 161 may include additional or alternative AHB signals.

[0034] Figure 4B An example of a communication signal 450 is illustrated, which may be provided in at least some examples of SPI communication buses 121, 123 that connect the SPI controller 110 to each of the first SPI device 130 and the second SPI device 132, respectively. As illustrated, the communication signal 450 includes a chip select (CS) signal 452 (e.g., which may be provided on corresponding CS lines 202, 212) and a clock (CLK) signal 454 (e.g., which may be provided on CLK line 204). The communication signal 450 also includes an I / O signal 456 (e.g., which may be provided on I / O line 206) and a data strobe (DQS) signal 458 (e.g., which may be provided on DQS line 208).

[0035] When the SPI controller 110 receives a data transmission request on the communication bus 161, it initiates data transmission on one of the SPI communication buses 121 and 123 based on the HADDR signal 404. For example, a first SPI device 130 connected to the SPI communication bus 121 can be mapped to a first SPI address, and a first SPI device 130 connected to the SPI communication bus 123 can be mapped to a second SPI address. When a data transmission request is received from the processor 106 on the communication bus 161, the SPI controller 110 can determine the requested address based on the HADDR signal 404, and can determine whether the requested address is mapped to the first SPI address or the second SPI address. Based on which of the first and second SPI addresses the requested address is mapped to, the SPI controller 110 initiates an SPI data transaction on the corresponding SPI communication bus 121 or 123.

[0036] For example, and refer to Figure 4AThe first non-sequential (NS) value 403 of the HTRANS signal 402 indicates the initiation of a first read request, and the second NS value 405 of the HTRANS signal 402 indicates the initiation of a second read request. The first falling edge 420 of the HREADY signal 406 may follow the first NS value 403, and the second falling edge 422 of the HREADY signal 406 may follow the second NS value 405, each falling edge indicating a delay in data transmission across the HRDATA signal 408. When the SPI controller 110 detects the first falling edge 420 of the HREADY signal 406, the SPI controller 110 initiates a first SPI read request on the corresponding SPI communication buses 121, 123 based on the first start address 430 provided on the HADDR signal 404 (e.g., address zero in this example). For example, as... Figure 4B As illustrated, to initiate a first SPI read request, the SPI controller 110 asserts the CS signal 452, as indicated by the falling edge 460 of the CS signal 452, and provides a clock signal 454 (e.g., at a configured frequency). Furthermore, the SPI controller 110 provides a READ command 462 on the I / O signal 456, followed by a start address 464 (e.g., mapped to a first start address 430), and in this example, dummy data 466. After the dummy data 466, the SPI controller 110 receives a first data burst 468, which in this example corresponds to sixty-four bytes of data. The first data burst 468 is pulsed with the DQS signal 458 provided by the SPI controller 110. Figure 4A As illustrated, when the HREADY signal 406 is set high 421 (e.g., rising edge 421 of the HREADY signal 406), the SPI controller 110 begins to provide sixty-four bytes of data to the processor 106 as a first data transfer 417 via the HRDATA signal 408.

[0037] Furthermore, and as described herein, the SPI controller 110 may store the first start address 430 in the burst start address register 111A. The SPI controller 110 may also determine the first end address of the first data burst 468 and may store the first end address in the burst end address register 111B. In this example, the first end address is 63.

[0038] After the first data burst 468 is timed by the SPI controller 110, the SPI controller 110 maintains the CS signal 452 asserted, and in some examples, stops providing the clock signal 454 (e.g., the clock signal for transitions between states), such as Figure 4B As illustrated. Return to reference. Figure 4AAt a certain point after the timing in the first data burst 468, the SPI controller 110 detects the second falling edge 422 of the HREADY signal 406, indicating that data is ready for a second read request from the processor 106. Based on the detection of the second falling edge 422 of the HREADY signal 406, the SPI controller 110 initiates a second SPI read request on the corresponding SPI communication buses 121 and 123.

[0039] For example, the SPI controller 110 may determine a second start address 432 for the second read request based on the HADDR signal 404 corresponding to the falling edge 422 of the HREADY signal 406. In this example, the second start address 432 is sixty-four. Furthermore, the SPI controller 110 may determine whether the second start address 432 consecutively follows a first end address stored in the burst end address register 111B. In this example, the second start address 432 sixty-four consecutively follows the first end address sixty-three. Although in this example the consecutive address is offset by one, in other examples the consecutive address may be offset by another value, such as two, four, or eight, as described herein.

[0040] Based on the determination that the second start address 432 sixty-four continuously follows the first end address sixty-three, the SPI controller 110 begins timing the additional data via I / O signal 456. For example, as Figure 4B As illustrated, the SPI controller 110 begins by providing a clock signal 454 and a DQS signal 458 to time the second data burst 470. In this example, the second data burst 470 comprises sixty-four bytes of data. Figure 4A As illustrated, when the HREADY signal 406 is set high 423 (e.g., rising edge 423 of the HREADY signal 406), the SPI controller 110 provides sixty-four bytes of data to the processor 106 as a second data transmission 419 via the HRDATA signal 408.

[0041] Figure 5 This is a flowchart of an exemplary process 500 for providing burst transmissions via a communication interface, according to some exemplary embodiments. For example, one or more die packages (such as integrated circuit package 100) may perform one or more operations of the exemplary process 500.

[0042] refer to Figure 5At block 502, a first data transfer request is received from the device via the communication bus. For example, SPI controller 110 may receive the first data transfer request from processor 106 via communication bus 161. At block 504, chip selection of the SPI bus is asserted based on the first data transfer request. As an example, as described herein, SPI controller 110 may assert the chip select signal of SPI communication bus 121 based on the data transfer request received from processor 106.

[0043] Furthermore, at block 506, a first data exchange is initiated via the SPI bus. For example, the first data transfer request could be a read request. The SPI controller 110 can provide a READ command 462, followed by multiple address bytes 464 mapped to the address specified by the first data transfer request, and dummy data 466 for multiple fields on I / O lines 206 of the SPI communication bus 121. After the dummy data 466, a first data burst 468 is clocked out and received via I / O lines 206.

[0044] Proceed to block 508 to determine the final address of the first data transfer request. For example, the SPI controller 110 may determine the final address of the first data transfer request based on the final address indicated in the HADDR signal 404 of the communication bus 161. In some examples, as described herein, the SPI controller 110 may store the final address in the burst end address register 111B.

[0045] Additionally, at block 510, a second data transfer request is received from the device via the communication bus. For example, the SPI controller 110 may receive an additional data transfer request from the processor 106. Furthermore, at block 512, the initial address of the second data transfer request is determined. As an example, the SPI controller 110 may determine the initial address of the second data transfer based on a first address indicated in the HADDR signal 404 of the communication bus 161 for the second data transfer request. In some examples, the SPI controller writes the initial address to the burst start address register 111A.

[0046] At block 514, the final address of the first data transfer request is compared with the initial address of the second data transfer request. For example, as described herein, the SPI controller 110 may compare the final address of the first data transfer request with the initial address of the second data transfer request to determine that the initial address follows the final address consecutively.

[0047] Furthermore, at block 516, based on the comparison performed at block 514 and while continuing to assert the chip select signal, a second data exchange is initiated via the SPI bus. For example, as described herein, the second data transfer request could be another read request, and the SPI controller 110 could receive data from the first SPI device 130 via the SPI communication bus 121. For example, the SPI controller 110 could clock the second data burst 470 via I / O line 206 of the SPI communication bus 121.

[0048] Figure 6 This is a flowchart of an exemplary process 600 for providing burst transmissions via a communication interface, according to some exemplary embodiments. For example, one or more die packages (such as integrated circuit package 100) may perform one or more operations of the exemplary process 500.

[0049] refer to Figure 6 At block 602, a first read command is received from the first device. The first read command is a request to read a first number of bytes from the second device, starting at a first address. For example, the first device could be processor 106, and the second device could be a first SPI device 130. At block 604, a chip select signal is asserted to the second device. Furthermore, a first number of bytes are read from the second device, starting at the first address and ending at a second address. For example, the second address could be the address of the last data byte to be read.

[0050] For example, the SPI controller 110 may provide a READ command 462, followed by multiple address bytes 464 mapped to the address specified by the first data transfer request, and dummy data 466 for multiple fields on the I / O line 206 of the SPI communication bus 121. After the dummy data 466, a first data burst 468 is clocked out and received via the I / O line 206.

[0051] Furthermore, at block 606, a first number of bytes is sent to the first device. For example, the SPI controller 110 may send the first number of bytes received from the first SPI device 130 to the processor 106 via a communication bus 161, which may be an AHB or AXI bus as described herein. At block 608, a second read command is received from the first device. The second read command is a request to read a second number of bytes from the second device, starting at a third address.

[0052] At block 610, it is determined whether the third address follows the second address consecutively. For example, as described herein, the SPI controller 110 may determine whether the third address is equal to the second address plus a predetermined amount (e.g., one, two, four, eight, etc.), where the predetermined amount defines the difference between consecutive addresses. If it is determined at block 612 that the third address follows the second address consecutively, the method proceeds to block 614. Furthermore, at block 614, the chip select signal is asserted, and a second number of bytes are read from the second device. For example, the SPI controller 110 may clock the second data burst via I / O line 206 of the SPI communication bus 121. From block 614, the method proceeds to block 620, where the second number of bytes is sent to the first device.

[0053] However, if it is determined at box 612 that the third address does not follow the second address consecutively, the method proceeds to box 616, where the chip select signal to the second device is deasserted. From box 616, the method proceeds to box 618, where the chip select signal is reasserted, and further, a second number of bytes are read from the second device. From box 618, the method proceeds to box 620, where the second number of bytes are sent to the first device.

[0054] Specific implementation examples are further described in the following numbered clauses: 1. An apparatus, the apparatus comprising: First communication bus; Second communication bus; and A controller logic unit, electrically coupled to the first communication bus and the second communication bus, is configured to: Receive a first data transmission request through the first communication bus; The final address is determined based on the first data transmission request; In response to the first data transmission request, assert the chip select signal of the second communication bus; and When asserting the chip selection signal: The first data exchange is initiated through the second communication bus; Receive the second data transmission request through the first communication bus; The initial address is determined based on the second data transmission request; Based on the initial address and the final address, determine whether to continue asserting the chip selection signal; and When the chip select signal is asserted, a second data exchange is initiated through the second communication bus.

[0055] 2. The device according to Clause 1, wherein the controller logic component is configured to: Compare the initial address with the final address; Based on the comparison, the initial address is determined to continuously follow the final address; and Based on the determination that the initial address continuously follows the final address, it is determined to continue asserting the chip selection signal.

[0056] 3. The device according to Clause 2, wherein the controller logic component is configured to determine that the initial address is greater than the final address by a predetermined value.

[0057] 4. The device according to Clause 3, wherein the predetermined value is one.

[0058] 5. The device according to any one of clauses 1 to 4, the device including a register, wherein the controller logic component is configured to: Store the final address in the register; and When asserting the chip select signal, the final address is read from the register.

[0059] 6. The device according to any one of clauses 1 to 5, the device comprising a timer, wherein the controller logic component is configured to: Write the value representing the time interval into the timer; The timer is started upon receiving the first data transmission request; and The timer is reset based on the receipt of the second data transmission.

[0060] 7. The device according to Clause 6, wherein the controller logic component is configured to: Detecting the expiration of the timer; and The chip select signal is de-asserted in response to the detection that the timer has expired.

[0061] 8. The device according to any one of clauses 1 to 7, wherein the first data exchange via the second communication bus includes commands, addresses and a first dataset, and the second data exchange via the second communication bus includes a second dataset.

[0062] 9. The device according to any one of clauses 1 to 8, wherein the second communication bus is a serial peripheral interface bus.

[0063] 10. The device according to any one of clauses 1 to 9, wherein the first communication bus is an advanced high-performance bus.

[0064] 11. A method performed by a processor, the method comprising: Receive the first data transmission request through the first communication bus; The final address is determined based on the first data transmission request; In response to the first data transmission request, assert the chip selection signal of the second communication bus; When asserting the chip selection signal: The first data exchange is initiated through the second communication bus; Receive the second data transmission request through the first communication bus; The initial address is determined based on the second data transmission request; The chip selection signal is further asserted based on the initial address and the final address; and When the chip select signal is asserted, a second data exchange is initiated through the second communication bus.

[0065] 12. The method according to Clause 11, further comprising: Compare the initial address with the final address; Based on the comparison, the initial address is determined to continuously follow the final address; and The chip selection signal is further asserted based on the determination that the initial address continuously follows the final address.

[0066] 13. The method according to Clause 12, the method further comprising determining that the initial address is greater than the final address by a predetermined value.

[0067] 14. The method according to any one of clauses 11 to 13, wherein the predetermined value is one.

[0068] 15. The method according to any one of clauses 11 to 14, the method further comprising: Store the final address in a register; and When asserting the chip select signal, the final address is read from the register.

[0069] 16. The method according to any one of clauses 11 to 15, wherein the method further comprises: Write the value representing the time interval into the timer; The timer is started upon receiving the first data transmission request; and The timer is reset based on the receipt of the second data transmission.

[0070] 17. The method according to Clause 16, further comprising: Detecting the expiration of the timer; and The chip select signal is de-asserted in response to the detection that the timer has expired.

[0071] 18. The method according to any one of clauses 11 to 17, wherein the first data exchange via the second communication bus includes commands, addresses, and a first dataset, and the second data exchange via the second communication bus includes a second dataset.

[0072] 19. The method according to any one of Clauses 11 to 18, wherein the second communication bus is a serial peripheral interface bus.

[0073] 20. The method according to any one of clauses 11 to 19, wherein the first communication bus is an advanced high-performance bus.

[0074] 21. A non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium comprising instructions that, when executed by at least one processor, cause the at least one processor to: Receive the first data transmission request through the first communication bus; The final address is determined based on the first data transmission request; In response to the first data transmission request, assert the chip select signal of the second communication bus; and When asserting the chip selection signal: The first data exchange is initiated through the second communication bus; Receive the second data transmission request through the first communication bus; The initial address is determined based on the second data transmission request; Based on the initial address and the final address, determine whether to continue asserting the chip selection signal; and When the chip select signal is asserted, a second data exchange is initiated through the second communication bus.

[0075] 22. The non-transitory machine-readable storage medium according to Clause 21, wherein the instructions, when executed by the at least one processor, cause the at least one processor to: Compare the initial address with the final address; Based on the comparison, the initial address is determined to continuously follow the final address; and The chip selection signal is further asserted based on the determination that the initial address continuously follows the final address.

[0076] 23. The non-transitory machine-readable storage medium according to Clause 22, wherein the instructions, when executed by the at least one processor, cause the at least one processor to determine that the initial address is greater than the final address by a predetermined value.

[0077] 24. The non-transitory machine-readable storage medium according to any one of clauses 21 to 23, wherein the predetermined value is one.

[0078] 25. A non-transitory machine-readable storage medium according to any one of clauses 21 to 24, wherein the instructions, when executed by the at least one processor, cause the at least one processor to: Store the final address in a register; and When asserting the chip select signal, the final address is read from the register.

[0079] 26. A non-transitory machine-readable storage medium according to any one of clauses 21 to 25, wherein the instructions, when executed by the at least one processor, cause the at least one processor to: Write the value representing the time interval into the timer; The timer is started upon receiving the first data transmission request; and The timer is reset based on the receipt of the second data transmission.

[0080] 27. The non-transitory machine-readable storage medium according to Clause 26, wherein the instructions, when executed by the at least one processor, cause the at least one processor to: Detecting the expiration of the timer; and The chip select signal is de-asserted in response to the detection that the timer has expired.

[0081] 28. The non-transitory machine-readable storage medium according to any one of clauses 21 to 27, wherein the first data exchange via the second communication bus includes commands, addresses, and a first dataset, and the second data exchange via the second communication bus includes a second dataset.

[0082] 29. The non-transitory machine-readable storage medium according to any one of Clauses 21 to 28, wherein the second communication bus is a serial peripheral interface bus.

[0083] 30. The non-transitory machine-readable storage medium according to any one of clauses 21 to 29, wherein the first communication bus is an advanced high-performance bus.

[0084] 31. A die package, the die package comprising: processor; and A controller logic unit, electrically coupled to the processor via a first communication bus, is configured to: Receive a first data transmission request from the processor via the first communication bus; The final address is determined based on the first data transmission request; In response to the first data transmission request, assert the chip select signal of the second communication bus; and When asserting the chip selection signal: The first data exchange is initiated through the second communication bus; Receive a second data transmission request from the processor via the first communication bus; The initial address is determined based on the second data transmission request; Based on the initial address and the final address, determine whether to continue asserting the chip selection signal; and When the chip select signal is asserted, a second data exchange is initiated through the second communication bus.

[0085] 32. The die package according to Clause 31, wherein the controller logic unit is configured to: Compare the initial address with the final address; Based on the comparison, the initial address is determined to continuously follow the final address; and Based on the determination that the initial address continuously follows the final address, it is determined to continue asserting the chip selection signal.

[0086] 33. The die package as described in Clause 32, wherein the controller logic component is configured to determine that the initial address is greater than the final address by a predetermined value.

[0087] 34. The die package as described in Clause 33, wherein the predetermined value is one.

[0088] 35. A die package according to any one of clauses 31 to 34, the die package including a register, wherein the controller logic unit is configured to: Store the final address in the register; and When asserting the chip select signal, the final address is read from the register.

[0089] 36. A die package according to any one of clauses 31 to 35, the die package including a timer, wherein the controller logic unit is configured to: Write the value representing the time interval into the timer; The timer is started upon receiving the first data transmission request; and The timer is reset based on the receipt of the second data transmission.

[0090] 37. The die package as described in Clause 36, wherein the controller logic unit is configured to: Detecting the expiration of the timer; and The chip select signal is de-asserted in response to the detection that the timer has expired.

[0091] 38. The die package according to any one of clauses 31 to 37, wherein the first data exchange via the second communication bus includes commands, addresses and a first dataset, and the second data exchange via the second communication bus includes a second dataset.

[0092] 39. The die package according to any one of clauses 31 to 38, wherein the second communication bus is a serial peripheral interface bus.

[0093] 40. A die package according to any one of clauses 31 to 39, wherein the first communication bus is an advanced high-performance bus.

[0094] Although the method described above refers to the illustrated flowchart, many other ways of performing the actions associated with the method can be used. For example, the order of some operations can be changed, and some implementations can omit one or more of the described operations and / or include additional operations.

[0095] Furthermore, the methods and systems described herein can be embodied, at least in part, in the form of computer-implemented processes and apparatus for performing those processes. The disclosed methods can also be embodied, at least in part, in the form of a tangible, non-transitory machine-readable storage medium encoded with computer program code, which, when executed, causes a machine to manufacture at least one integrated circuit performing one or more of the operations described herein. For example, the methods can be embodied in hardware, executable instructions (e.g., software) executed by a processor, or a combination of both. The medium may include, for example, RAM, ROM, CD-ROM, DVD-ROM, BD-ROM, hard disk drive, flash memory, or any other non-transitory machine-readable storage medium. When the computer program code is loaded into and executed by a computer, the computer becomes an apparatus for causing a machine to manufacture an integrated circuit. The methods can also be embodied, at least in part, in the form of a computer, with the computer program code loaded into or executed in the computer, making the computer a dedicated computer for causing a machine to manufacture an integrated circuit. For example, when implemented on a general-purpose processor, computer program code segments configure the processor to create specific logic circuits. The methods can also alternatively be embodied, at least in part, in an application-specific integrated circuit (ASIC) or any other integrated circuit for performing the methods.

[0096] Furthermore, terms such as “circuit” and “logic component” may individually or in combination include analog circuits, digital circuits, hardwired circuits, programmable circuits, processing circuits, hardware logic circuits, state machine circuits, and any other suitable type of physical hardware component. Additionally, the embodiments described herein can be employed in a wide variety of devices, such as networking devices, telecommunications devices, smartphones, gaming devices, enterprise devices, storage devices (e.g., cloud storage devices), automotive systems (e.g., collision avoidance systems, object detection systems, navigation systems, etc.), and computing devices (e.g., cloud computing devices), as well as other types of devices.

[0097] The subject matter has been described with reference to exemplary embodiments. Because these are merely examples, the claimed invention is not limited to these embodiments. Changes and modifications may be made without departing from the spirit of the claimed subject matter. The claims are intended to cover such changes and modifications.

Claims

1. An apparatus, the apparatus comprising: First communication bus; Second communication bus; and A controller logic unit, electrically coupled to the first communication bus and the second communication bus, is configured to: Receive a first data transmission request through the first communication bus; The final address is determined based on the first data transmission request; In response to the first data transmission request, assert the chip select signal of the second communication bus; as well as When asserting the chip selection signal: The first data exchange is initiated through the second communication bus; Receive the second data transmission request through the first communication bus; The initial address is determined based on the second data transmission request; The chip selection signal is determined to continue asserting based on the initial address and the final address; as well as When the chip select signal is asserted, a second data exchange is initiated through the second communication bus.

2. The device according to claim 1, wherein the controller logic component is configured to: Compare the initial address with the final address; Based on the comparison, the initial address is determined to continuously follow the final address; and Based on the determination that the initial address continuously follows the final address, it is determined to continue asserting the chip selection signal.

3. The device of claim 2, wherein the controller logic component is configured to determine that the initial address is greater than the final address by a predetermined value.

4. The device according to claim 3, wherein the predetermined value is one.

5. The device of claim 1, wherein the device includes a register, and wherein the controller logic component is configured to: Store the final address in the register; and When asserting the chip select signal, the final address is read from the register.

6. The device of claim 1, wherein the device includes a timer, and wherein the controller logic component is configured to: Write the value representing the time interval into the timer; The timer is started upon receiving the first data transmission request; and The timer is reset based on the receipt of the second data transmission.

7. The device of claim 6, wherein the controller logic component is configured to: Detecting the expiration of the timer; and The chip select signal is de-asserted in response to the detection that the timer has expired.

8. The device of claim 1, wherein the first data exchange via the second communication bus includes commands, addresses, and a first dataset, and the second data exchange via the second communication bus includes a second dataset.

9. The device according to claim 1, wherein the second communication bus is a serial peripheral device interface bus.

10. The device of claim 1, wherein the first communication bus is an advanced high-performance bus.

11. A method performed by a processor, the method comprising: Receive the first data transmission request through the first communication bus; The final address is determined based on the first data transmission request; In response to the first data transmission request, assert the chip selection signal of the second communication bus; When asserting the chip selection signal: The first data exchange is initiated through the second communication bus; Receive the second data transmission request through the first communication bus; The initial address is determined based on the second data transmission request; The chip selection signal is determined to continue asserting based on the initial address and the final address; as well as When the chip select signal is asserted, a second data exchange is initiated through the second communication bus.

12. The method according to claim 11, further comprising: Compare the initial address with the final address; Based on the comparison, the initial address is determined to continuously follow the final address; as well as The chip selection signal is further asserted based on the determination that the initial address continuously follows the final address.

13. The method of claim 12, further comprising determining that the initial address is greater than the final address by a predetermined value.

14. The method according to claim 11, further comprising: Store the final address in a register; as well as When asserting the chip select signal, the final address is read from the register.

15. The method according to claim 11, further comprising: Write the value representing the time interval into the timer; The timer is started upon receiving the first data transmission request; as well as The timer is reset based on the receipt of the second data transmission.

16. The method according to claim 15, further comprising: The timer expires; as well as The chip select signal is de-asserted in response to the detection that the timer has expired.

17. The method of claim 11, wherein the first data exchange via the second communication bus includes commands, addresses, and a first dataset, and the second data exchange via the second communication bus includes a second dataset.

18. The method of claim 11, wherein the second communication bus is a serial peripheral device interface bus.

19. A non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium comprising instructions that, when executed by at least one processor, cause the at least one processor to: Receive the first data transmission request through the first communication bus; The final address is determined based on the first data transmission request; In response to the first data transmission request, assert the chip selection signal of the second communication bus; as well as When asserting the chip selection signal: The first data exchange is initiated through the second communication bus; Receive the second data transmission request through the first communication bus; The initial address is determined based on the second data transmission request; The chip selection signal is determined to continue asserting based on the initial address and the final address; as well as When the chip select signal is asserted, a second data exchange is initiated through the second communication bus.

20. A die package, the die package comprising: processor; and A controller logic unit, electrically coupled to the processor via a first communication bus, is configured to: Receive a first data transmission request from the processor via the first communication bus; The final address is determined based on the first data transmission request; In response to the first data transmission request, assert the chip selection signal of the second communication bus; as well as When asserting the chip selection signal: The first data exchange is initiated through the second communication bus; Receive a second data transmission request from the processor via the first communication bus; The initial address is determined based on the second data transmission request; The chip selection signal is determined to continue asserting based on the initial address and the final address; as well as When the chip select signal is asserted, a second data exchange is initiated through the second communication bus.

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