Multi-bit high density read only memory using multiple reference biases

Abstract

Methods and systems related to computer memory are disclosed herein. A multi-bit read-only memory (ROM) includes a plurality of voltage generators for generating a plurality of voltages and a transistor having a first node and a second node. The transistor may be a field effect transistor (FET), and the first node may be a gate node and the second node may be a source node or a drain node. The ROM includes a connection from the first node to a first supply voltage node that is biased by one of the plurality of voltages. The ROM includes a connection from the second node to a second supply voltage node that is biased by one of the plurality of voltages. A value of a multi-bit ROM cell in the multi-bit ROM is stored as a resulting conductivity state of the transistor.

Description

Cross Reference to Related Applications

[0001] This application claims priority to U.S. Patent Application No. 18 / 776,254, filed July 18, 2024, and U.S. Provisional Patent Application No. 63 / 527,825, filed July 20, 2023, which claims the benefit of U.S. Provisional Patent Application No. 63 / 540,362, filed September 25, 2023, which are all hereby incorporated by reference in their entirety for all purposes. BACKGROUND

[0002] The development of read-only memory (ROM) has been an important aspect of the development of computing systems. The origins of ROM date back to the early days of electronic computers in the mid-20th century. Initially, ROM was implemented using physical methods such as diode matrices or jumpers to encode fixed instructions and data directly into the hardware of these early machines. As computing technology advanced, ROM took various forms, including mask ROM, where the data saved by the ROM was formed by a pattern etched onto an integrated circuit using a mask during the manufacture of the integrated circuit. In these systems, the mask used to etch the pattern could be changed to create different memory states for different versions of hardware.

[0003] ROMs that can be modified after formation are commonly referred to as programmable ROMs (PROMs). The first PROMs were invented in the mid-1950s, with U.S. Patent No. 3,028,659 to Wen Tsing Chow serving as an early example. This patent preceded the widespread adoption of field-effect transistors (FETs). As such, the data in early PROMs was stored using other devices such as diodes. Each PROM diode was a cell of memory that could be programmed to a zero value by breaking the diode with a high current, or left alone to represent a one value. In this example, the diode can be referred to as a storage element, as the state of the diode determined the value stored by the associated memory cell.

[0004] Later PROMs utilized FETs as the storage elements of the memory. Figure 1 A standard FET ROM cell is illustrated, where the source or drain node of the FET is connected to a supply voltage or reference voltage. When a control signal is sent to the word line, the cell is read by monitoring the current on the bit line. Mask ROMs and PROMs have a high density relative to other types of memory, such as erasable programmable ROMs (EPROMs) or random access memory (RAMs), as few additional elements are needed beyond the individual storage elements. SUMMARY

[0005] The disclosure herein relates to methods and systems of computer memory. More specifically, the disclosure herein relates to methods and systems of ROM. The ROM can be a multi-bit ROM that stores more than one bit of information per memory cell.

[0006] The value of a multi-bit ROM cell can be stored as a connectivity state of a circuit element, such as a transistor. The connectivity state can be set by connecting the circuit element to different nodes. In particular embodiments, the connectivity state of the element will define a conductive state of the circuit element, such that the value of the multi-bit ROM cell can be stored as a conductive state of a circuit element, such as a transistor. The conductive state of the circuit element can be set by applying different biases, such as bias voltages or bias currents, to the circuit element. The multi-bit ROM cell can be a multi-bit cell in that each circuit element is capable of being connected to different nodes. For example, one of a plurality of nodes can be connected to the circuit element at a given time, where each of the plurality of nodes places the circuit element in a different connectivity state. As another example, one of a plurality of biases can be connected to the circuit element at a given time, where each of the plurality of voltages places the circuit element in a different conductive state. The plurality of biases can be generated by a plurality of bias generators, such as a plurality of voltage generators or voltage regulators.

[0007] In particular embodiments, the circuit element can include a plurality of terminals that can affect the conductive state of the circuit element. For example, the circuit element can include at least two terminals and different biases can be independently programmably connected to the at least two terminals. The circuit element can be configured such that different combinations of potential biases each set the circuit element to a unique conductive state. In these embodiments, the number of conductive states can be significantly increased, and in the alternative or in combination, the information density of the memory cell can be increased without increasing the number of bias generators.

[0008] In particular embodiments of the invention disclosed herein, a read circuit for a multi-bit ROM can provide a sensed current or voltage signal to a neural network. The neural network can be integrated with the multi-bit ROM and can be trained on the multi-bit ROM. As such, the neural network can be trained to filter noise from the multi-bit ROM and determine the true value intended to be stored in the multi-bit ROM. In embodiments where the value is stored as a conductive state of a circuit element with a node connected to the circuit element being a reference voltage or reference current, such an approach can be beneficial because there can be fewer independent sources of noise than the number of memory cells in the memory, such that the neural network can remain significantly small while still learning to filter all noise of the system. Furthermore, because the multi-bit values of the memory are stored and read as analog signals that are approximately equal to the reference voltage or reference current, noise on the signal will not be amplified by the barrier between adjacent digital values, and the neural network will be better able to learn and filter noise on these analog signals.

[0009] In particular embodiments of the invention disclosed herein, instead of similar circuit elements that would otherwise store a single bit of information in a traditional ROM cell, a single circuit element can store multiple bits by using multiple biases. A ROM array according to these embodiments can exhibit a much higher information density compared to a traditional ROM array. For example, using embodiments disclosed herein, it is estimated that an integrated ROM storage of hundreds of billions of bits can be placed in close proximity to the computing elements of an integrated circuit. This can be made more beneficial because the circuit elements used for the ROM cells can be the same high-speed logic transistors used for the computing elements of the integrated circuit. This means that the circuit elements used for the ROM cells can be multi-bit, but do not necessarily need to be placed in a separate part of the chip, such as a dedicated well or power island. This degree of integration and information density can be particularly beneficial in applications such as machine intelligence inference applications, where a large number of parameters representing a trained machine intelligence network must be stored in ROM in order to perform the complex calculations necessary to generate these inferences.

[0010] In particular embodiments of the invention, a method is provided. The method includes providing a plurality of voltage regulators for generating a plurality of voltages for a multi-bit read-only memory; and connecting a first node of a transistor to a first supply voltage node, where the first supply voltage node is biased by one of the plurality of voltages, where the transistor is in a multi-bit read-only memory cell of the multi-bit read-only memory, and whereby a value of the multi-bit read-only memory cell is stored as a connectivity state of the transistor.

[0011] In particular embodiments of the invention, a multi-bit read-only memory is provided. The multi-bit read-only memory includes a plurality of voltage generators for generating a plurality of voltages; a transistor having a first node and a second node; and a connection from the first node to a first supply voltage node. The first supply voltage node is biased by one of the plurality of voltages. A value of a multi-bit read-only memory cell in the multi-bit read-only memory is stored as a connectivity state of the transistor.

[0012] In particular embodiments of the invention, a method is provided. The method includes providing a plurality of voltage regulators for generating a plurality of voltages for a multi-bit read-only memory; and connecting a first node of a transistor to a first supply voltage node. The first supply voltage node is biased by one of the plurality of voltages. The transistor is in a multi-bit read-only memory cell of the multi-bit read-only memory. The method also includes connecting a second node of the transistor to a second supply voltage node. The second supply voltage node is biased by one of the plurality of voltages. Using the above steps, a value of the multi-bit read-only memory cell is stored as a conductivity state of the transistor.

[0013] In a particular embodiment of the invention, a multi-bit read-only memory is provided. The multi-bit read-only memory includes a plurality of voltage generators for generating a plurality of voltages, a transistor having a first node and a second node, and a connection from the first node to a first supply voltage node. The first supply voltage node is biased by one of the plurality of voltages. The memory also includes a connection from the second node to a second supply voltage node. The second supply voltage node is biased by one of the plurality of voltages. A value of a multi-bit read-only memory cell in the multi-bit read-only memory is stored as a conductive state of the transistor. BRIEF DESCRIPTION OF DRAWINGS

[0014] The accompanying drawings illustrate various embodiments of the systems, methods, and various other aspects of the present disclosure. As will be readily appreciated, the boundaries of the components shown in the figures are intended to represent one example of a boundary. It will be readily appreciated that one component can be designed as multiple components or that multiple components can be designed as one component. In some embodiments, an element shown as an internal component of one component can be implemented as an external component of another component, and vice versa. Further, the elements can not be drawn to scale. The non-limiting and non-exhaustive description refers to the following drawings, which are meant to be exemplary and explanatory, and in which:

[0015] Figure 1 A read-only memory (ROM) cell is illustrated in accordance with the related art.

[0016] Figure 2 A programmed multi-bit ROM cell is illustrated in accordance with a particular embodiment of the invention disclosed herein, storing a value in the form of a connectivity state or a conductive state of a transistor.

[0017] Figure 3 A programmed multi-bit ROM cell is illustrated in accordance with a particular embodiment of the invention disclosed herein, storing a value in the form of a conductive state of a transistor.

[0018] Figure 4 A set of voltage regulators for generating a set of voltages is illustrated in accordance with a particular embodiment of the invention disclosed herein.

[0019] Figure 5 Operation of a read circuit for a programmed multi-bit ROM cell of Figure 2 above is illustrated in accordance with a particular embodiment of the invention disclosed herein.

[0020] Figure 6 Operation of a read circuit for a programmed multi-bit ROM cell of Figure 3 above is illustrated in accordance with a particular embodiment of the invention disclosed herein.

[0021] Figure 7 FIG. illustrates a read circuit with a set of voltage regulators and a set of comparators, in accordance with certain embodiments of the application disclosed herein.

[0022] Figure 8 FIG. illustrates a read circuit with a voltage controlled oscillator (VCO), in accordance with certain embodiments of the application disclosed herein.

[0023] Figure 9 FIG. illustrates a read circuit for a ROM memory array augmented with a neural network decoder, in accordance with certain embodiments of the application disclosed herein.

[0024] Figure 10 FIG. illustrates an example of a method for storing a multi-bit ROM cell, in accordance with certain embodiments of the application disclosed herein.

[0025] Figure 11 FIG. illustrates an example of a method for reading a multi-bit ROM cell, in accordance with certain embodiments of the application disclosed herein. DETAILED DESCRIPTION

[0026] Reference will now be made in detail to various aspects and variations of the systems and methods described herein. While several illustrative variations of the systems and methods are described herein, other variations of the systems and methods can include aspects of the systems and methods described herein combined in any suitable manner with all or some of the aspects described.

[0027] Different methods and systems relating to computer memory are disclosed in detail herein. The methods and systems disclosed in this section are non-limiting embodiments of the application, provided for explanatory purposes only, and are not to be used to limit the full scope of the application. It is to be understood that the disclosed embodiments can overlap each other, or can not overlap each other. Thus, part or particular embodiments of one embodiment can or can not fall within the scope of another embodiment or particular embodiments thereof, and vice versa. Different embodiments from different aspects can be combined or practiced separately. Many different combinations and sub-combinations of the representative embodiments disclosed within the broad scope of the application will be apparent to those skilled in the art, though not expressly disclosed or described. Such should not be excluded.

[0028] In certain embodiments of the invention, the value of a multi-bit ROM cell is stored as a state of a circuit element. In certain embodiments of the invention, the value of a multi-bit ROM cell is stored as a state of a circuit element. The circuit element can exhibit various states of connectivity or conductivity, each of which is associated with a value. Thus, the circuit element can serve as a storage medium for a multi-bit ROM cell. The various states of the circuit element can be set by applying different biases to the circuit element or by adjusting the physical properties of the transistor, e.g., by modifying the diffusion layer of the transistor. The application of different biases or adjustment of the physical properties of the transistor can be done when building the circuit using different masks or can be done after the circuit has been built using programmable media such as fuses. Thus, the circuit element can serve as a programmable storage medium for a multi-bit ROM cell, where programming the multi-bit ROM cell includes supplying these different biases to the circuit element.

[0029] A circuit element whose state is associated with a value stored in a multi-bit ROM memory can be referred to as a storage element. The storage element can be an active or passive device. The storage element can be a diode; a field effect transistor, such as a metal insulator field effect transistor, junction field effect transistor, bipolar junction transistor; and other circuit elements. A storage element in the form of a transistor can be referred to as a storage transistor.

[0030] The state of the storage element can be set by applying different biases to one or more terminals of the storage element. The state of the storage element can be set by manufacturing the device using different dopant concentrations or dimensions when manufacturing the device. In this disclosure, examples of applying different supply voltages to the circuit element are used in most examples. However, programming by applying a supply voltage rather than a supply current is not a limitation on all embodiments disclosed herein, as storage elements that receive a supply current to place them in a particular state can be used in certain embodiments of the invention disclosed herein. Thus, as used herein, the term "receive a bias" refers to receiving a voltage or current used to bias the device. The bias can be applied to the circuit element in a controllable manner to alter the state of the circuit element and thereby change the value stored by the circuit element. Controllable setting of the state of the circuit element can be done using configurable mask layers of the memory to program the device when manufacturing the device, or using anti-fuse elements, fuse elements, or other techniques to program the memory after it has been manufactured in ROM or PROM applications.

[0031] Circuit elements can include various terminals. These terminals can be terminals that receive programmable bias and set the state of the circuit element when biased by a particular voltage or current. These terminals can be referred to as programming terminals. These terminals can alternatively or in combination be terminals by which the state of the circuit element is defined (e.g., the state can refer to the impedance between two terminals). Such terminals can be referred to as state terminals. The two types of terminals can overlap or be separate. As an example of overlapping sets of terminals, a circuit element can be a transistor in which the conductivity between the source and drain of the transistor defines the conductive state of the transistor (i.e., the source and drain are state terminals), and the terminals that are biased by programmable bias can be an overlapping set of terminals that includes the drain of the transistor and the gate of the transistor (i.e., the drain and gate are programming terminals). As an example of non-overlapping sets of terminals, a circuit element can be a transistor in which the conductivity between the source and drain of the transistor defines the conductive state of the transistor, and the terminals that are biased by programmable bias can be the gate and body of the transistor. In this example, the drain and source will still be biased in order to read the conductive state of the transistor, but they will not be biased by programmable bias as the gate and body are in this example.

[0032] Storage elements can have a variety of different states, based on a number of different fabrication processes used to fabricate the devices themselves, rather than just the bias applied to the devices. These different fabrication processes can result in different threshold voltages of storage transistors or different sizes of storage capacitors or resistors. Different threshold voltages of storage transistors can be set according to the time at which a diffusion step is performed to alter the conductive state of the channel of the transistor. Different threshold voltages can be associated with different values of the conductive state stored as the storage element. In particular embodiments of the invention, different storage transistors with different thresholds in a single memory array can occupy the same space in the memory array so that the memory array remains uniform, and can only differ with respect to the chemical composition of the channel of the storage transistor.

[0033] The number of configurable biases applied to a circuit element can vary, and the number of potential programmable values of a programmable bias can vary. Likewise, the number of different fabrication processes of a device can vary. The number of configurable biases, the number of potential programmable values thereof, and the number of different fabrication processes will set the number of bits that any multi-bit memory cell including the circuit element can store. These numbers cannot be arbitrarily high and will depend on the characteristics of the storage element and the sensitivity of the read circuitry used for the memory. The number of biases applied to a circuit element will depend on the number of terminals of the circuit element. The number of potential programmable values of a programmable bias and the different effects of different fabrication processes can also be set based on the number of distinguishable conductive states that a device can be placed in. A memory cell can include a single transistor designed to receive a programmable bias on the gate of the device, where the combination of biases can place the device in 4 different conductive states, in which case the memory cell will be able to store 2 bits of information. Alternatively, a memory cell can include a single transistor designed to receive two different programmable biases on the gate and drain of the device. In these embodiments, the device can store log2(N 2 ) bits of information, where N is the number of biases that can be individually applied to the two terminals. Alternatively, the same memory cell can be fabricated using one of 4 different fabrication processes (e.g., four fabrication processes each with a threshold voltage that differs by 100 millivolts). In these embodiments, the device can store 4 log2(N 2 ) bits of information. As seen, the number of potential states increases rapidly with the number of fabrication processes, the number of biases, and the number of terminals that can receive these biases in a programmable manner.

[0034] In particular embodiments where a device has more than one terminal that defines a conductive state of the device, different terminals can be configured to receive the same set of biases or different sets of biases. Whether these sets overlap and whether certain combinations of these sets place the device in a unique conductive state will depend on the characteristics of the device. The approach of having multiple sets of biases that can be applied to multiple terminals on a device overlap or be the same can bring benefits because it can minimize the number of bias circuits needed to generate the bias signals.

[0035] The supply voltages or supply currents applied to set the conductive state of the storage elements can be generated in various ways. For example, a set of supply voltages can be generated from a single supply voltage using a set of voltage regulators such as low-dropout voltage regulators. The supply voltages can be generated by other digital, analog, or hybrid voltage regulators such as linear voltage regulators and switching voltage regulators. The supply voltages can also be provided by a resistive divider between a supply voltage and a reference voltage with different tap points for voltages proportional to the supply voltage. The tap points can be buffered to provide the set of supply voltages. As another example, a set of bias currents can be generated from a single bias current using programmable current mirrors that include an array of FETs typically biased by a set of cascaded connected transistors that supply the single bias current.

[0036] In certain embodiments of the invention, the read circuit can be biased using the same circuitry as the memory cells. For example, when the memory cells are in a given conductive state, the reference voltage applied to the comparator can be the same as the reference voltage applied to the memory cells. These approaches can exhibit certain benefits because variations in the biasing circuitry used to place the storage elements in a given conductive state can be offset when the same biasing circuitry is used to measure the conductive states. For example, if the reference voltage of the storage elements is lower than its designed voltage, the corresponding read circuit can lower the threshold voltage of the comparator accordingly so that the same original expected value associated with the conductive state is read by the read circuit despite variations in the conductive state.

[0037] In certain embodiments of the invention, the ROM can be a low power device. The ROM can be designed so that it only consumes a significant amount of power when it is read, and further so that it only consumes a significant amount of power when it is read and has been programmed to a particular state. For example, the programming node of the storage elements can be selected so that it can be biased without any current flowing through the circuit elements. As a result, the circuit elements can store their values and be ready for reading without consuming any power. In certain embodiments of the invention, the biasing signals can be generated using low power circuitry. In certain embodiments of the invention, a set of bias voltages can be generated by a set of low-dropout voltage regulators.

[0038] Using the methods disclosed herein, ROMs with high levels of integration and high levels of information density can be provided. In particular embodiments, the storage elements and read circuitry for the ROM can include the same transistors used for high-speed logic of the computational elements, the ROM will act as memory for these computational elements. In particular embodiments, the ROMs disclosed herein can be integrated with a processor having at least one processing core including a computational unit. The computational unit can be an arithmetic logic unit, a floating point unit, a specialized matrix multiplication unit, or other custom logic or computational unit. The computational unit can comprise logic transistors connected to form logic gates. The logic transistors can be FET transistors designed for fast and efficient processing. The logic transistors can be finFETs, gate-all-around transistors, nanowire transistors, quantum tunneling FETs, carbon nanotube transistors, graphene and other two-dimensional material transistors, electron spin transistors, or other transistor technologies. The processor can use a set of logic transistors for computation, where the logic transistors are any of the transistor types mentioned above. The storage elements disclosed herein can be the logic transistors disclosed herein. In particular embodiments, the combined system including the computational unit and the ROM can be a specialized system for high-performance computation for applications such as machine learning or machine intelligence applications, cryptography, or other complex computations. In these embodiments, the ROM can provide terabytes of storage space to store content such as weights for a neural network that the specialized system is implementing. For example, the specialized system can be a neural network accelerator that generates inferences based on stored weights representing a neural network. In some machine intelligence applications, training is extremely expensive such that once a neural network is trained, the weights are deployed and stable for a long time. Thus, the weights of a neural network can be programmed into the ROM of a device that is specifically set to generate inferences of that neural network in response to inputs. In particular embodiments, the underlying device can be a generalized inference generation accelerator that can then be configured to accelerate inference generation of a particular neural network by storing the neural network in the ROM of a particular version of the device. For example, weights for a first neural network can be stored in a set of high-level masks to implement the weights in a mask ROM, and weights for a second neural network can be stored in a second set of high-level masks to implement these different weights in the mask ROM, while the underlying device below these high-level masks is still the same accelerator. The resulting two different versions of the device will be optimized to generate inferences of the two different neural networks, while the core underlying computational engines of the device remain the same.

[0039] Figure 1A FET ROM cell 100 is illustrated, where a node 101 (source or drain node) of the FET ROM cell 100 is connected to a supply voltage 102 (VDD) or a reference voltage 105. The FET ROM cell 100 is read by monitoring the current on the bit line 103 when a control signal is sent to the word line 104.

[0040] Figure 2 A method 200 and circuit 201 for storing a multi-bit value as a connectivity state or a conductive state in a transistor 202 is illustrated. In particular embodiments, the transistor 202 can be a different circuit element that can store a multi-bit value as a connectivity state or a conductive state described herein, can be a FET, or can be a type of transistor other than a FET. The transistor 202 can be a read transistor that allows a read circuit to read the connectivity state of the memory cell, or a combined read and storage transistor that has a programmed conductive state to allow a read circuit to read the conductive state of the memory cell. The circuit 201 includes a bit line 203, a word line 204, and voltage regulators 205. The method includes providing a plurality of voltage regulators 205 for generating a plurality of voltages for a multi-bit ROM at 210. The voltage regulators 205 can be Figure 4 The digital low-dropout regulator shown in DD_IN generates N+1 supply voltages. The N supply voltages can be routed to the terminals of a storage element (e.g., transistor 202) in a multi-bit ROM. The voltages can be selected such that they span from above the threshold voltage of the transistor to Figure 4 the supply voltage V DD_IN The spacing between the supply voltages can be linear. The spacing between the supply voltages can also be adjusted by a neural network designed to minimize noise when reading voltages from a ROM array of which the illustrated ROM cell (e.g., circuit 201) is a part. In other words, the neural network described with reference to Figure 9 may be able to adjust the supply voltages to minimize a loss function used to train the neural network. As illustrated, the same labels V DD_0 to V DD_N are used to label the set of voltage regulators 205 (e.g., nodes) in Figure 2 and the set of voltage regulators 405 (e.g., nodes) in Figure 4 .

[0041] The method 200 for storing a multi-bit value as a conductive state in a transistor 202 can continue at 211 with the step of writing to a ROM memory cell by fabricating the transistor 202 according to a particular process flow (e.g., a process flow that generates a device with a particular threshold voltage from among a set of threshold voltages) and biasing the drain of the transistor 202 with a reference voltage (e.g., from a plurality of voltage regulators 205). The selection of the process flow and the reference voltage will determine the conductive state of the transistor 202 and the associated value stored by the ROM. Writing to the ROM memory cell can include selecting a voltage from a plurality of bias voltages to connect to the drain of the transistor 202.

[0042] The method 200 for storing a multi-bit value as a connectivity state in a circuit element, where the circuit element is a transistor 202, can continue from 210 (providing a plurality of reference voltages) with the step 212 of writing to a ROM memory cell by biasing the drain of the transistor 202 with a reference voltage (e.g., from a plurality of voltage regulators 205). Writing to the ROM memory cell can include selecting a voltage from a plurality of bias voltages to connect to the drain of the transistor 202.

[0043] The method for storing a multi-bit value as a connectivity state in a circuit element can continue with the step 214 of connecting a first node of the transistor 202 to a first supply voltage node. The first supply voltage node can be biased by one of a plurality of voltages (e.g., from a plurality of voltage regulators 205). The first node of the transistor 202 can be the drain of the transistor 202 and the first supply voltage node can be the node biased by V DD_1 in the figure. The connection can be a programmed connection that connects the drain of the transistor 202 to the node biased by V DD_1 The foregoing steps (e.g., 214) of programmatically connecting a terminal of the transistor to a voltage result in the value of the multi-bit ROM cell being stored as a connectivity state of the transistor 202.

[0044] The method 200 for storing a multi-bit value as a conductive state in a circuit element, such as a transistor 202, can continue at 213 (e.g., from 211) with the step of connecting a first node of the transistor 202 to a first supply voltage node. The first supply voltage node can be biased by one of a plurality of voltages (e.g., from a plurality of voltage regulators 205). The first node can be the drain of the transistor 202 and the first supply voltage node can be the node biased by V DD_1 in the figure. The connection can be a programmed connection that connects the drain of the transistor 202 to the node biased by V DD_1N other nodes than the biased node are not illustrated in the figure. The aforementioned step (e.g., 213) of programmatically connecting a terminal of the transistor 202 to a voltage and the transistor 202 having a certain threshold voltage determined by a selected processing flow results in the value of the multi-bit ROM cell being stored as a conductive state of the transistor 202 (the transistor 202 being in a multi-bit ROM cell of a multi-bit ROM array).

[0045] The circuit 201 can be part of a ROM cell. A read operation (on the transistor 202) can involve applying a high voltage to the control node of the transistor. The high voltage can be referred to as a read voltage. The control node can be the gate of the transistor. The gate can be coupled to a word line 204 of the memory and the word line 204 can be connected to the gates of transistors in many other memory cells. Individual memory cells in a ROM array can be read by addressing a particular cell by applying signals to a word line (e.g., the word line 204) and a bit line (e.g., the bit line 203) in combination. An address can be applied to a decoder, which generates the appropriate bit line and word line signals to read the state of a given storage element. For example, the connectivity state of the transistor 202 can be read by measuring the voltage on the bit line 203.

[0046] In certain embodiments of the invention disclosed herein, instead of similar circuit elements that would otherwise store a single bit of information in a conventional ROM cell, a single circuit element such as the transistor 202 can store multiple bits by using multiple biases. A ROM array according to these embodiments can exhibit a much higher information density compared to conventional ROM arrays. The integrated ROM storage can be provided on an integrated circuit next to the computational elements of the integrated circuit.

[0047] Figure 3 A method 300 and a circuit 301 for storing a multi-bit value as a conductive state in a circuit element such as a transistor 306 are illustrated. The circuit 301 can include a bit line 303, a word line 304, a transistor 302, a transistor 306, a voltage regulator 305, and a voltage regulator 307. The transistor 302 can be a read transistor and the transistor 306 can be a storage transistor. The transistor 302, the transistor 306, or both can be FETs. The method 300 includes providing a plurality of voltage regulators 305 and 307 for generating a plurality of voltages for a multi-bit ROM at 310. The voltage regulators 305 and 307 can be Figure 4 The digital low-dropout regulator shown in FIG. 1 DD_IN N+1 supply voltages are generated. These N supply voltages can be routed to terminals of storage elements (e.g., the transistor 306) in a multi-bit ROM. The voltages can be selected such that they span from above the threshold voltage of the transistor 306 to Figure 4 the supply voltage V DD_INThe spacing between the supply voltages can be linear, or it can be chosen to have uniform linear spacing between the potential conductive states of the transistor 306. The spacing between the supply voltages can also be adjusted by a neural network designed to minimize noise when reading voltages from a ROM array of which the illustrated ROM cell (e.g., circuit 301) is a part. In other words, referring to Figure 9 The described neural network can be able to adjust these supply voltages to minimize a loss function used to train the neural network. As illustrated in Figure 3 The same labels V DD_0 to V DD_N are used to label the two sets of voltage regulators 305 and 307 (e.g., nodes). In particular embodiments, the voltage regulator 305 and the voltage regulator 307 can be the same voltage regulator. In particular embodiments, the voltage regulator 305 and the voltage regulator 307 can be different voltage regulators. As such, in particular embodiments, all voltages can be adjusted independently to improve the performance of the memory.

[0048] The method 300 for storing a multi-bit value as a conductive state in a transistor 306 (or another circuit element) can continue at 311 with the step of writing to the ROM memory cell by biasing the transistor 306 with a reference voltage. Writing to the ROM memory cell can include selecting a voltage from a plurality of bias voltages (e.g., associated with voltage regulator 305) to connect to the drain of the transistor 306, and selecting a voltage from a plurality of bias voltages (e.g., associated with voltage regulator 307) to connect to the gate of the transistor 306. The reference voltages available for selection for the two terminals (e.g., via voltage regulators 305 and 307) can be the same reference voltages or different sets. The combination of voltages available for selection for the two terminals of the transistor 306 can equal the total number of voltages available for each terminal multiplied together. However, in particular implementations, not all combinations can be distinguishable. For example, if V DD_0 (e.g., corresponding to voltage regulator 307) is below the threshold voltage of the transistor 306, then the value of V DD_0 will result in different voltage values at the drain of the transistor 306 (e.g., corresponding to voltage regulator 305) that are indistinguishable because the transistor 306 is off and has a fixed conductive state regardless of the current at the drain.

[0049] The method 300 for storing a multi-bit value as a conductive state in a circuit element such as transistor 306 can continue at 312 with the step of connecting a first node (e.g., drain) of the transistor 306 to a first supply voltage node (e.g., of voltage regulator 305). The first supply voltage node can be one of a plurality of voltages corresponding to voltage regulator 305, such as VDD_1 Biasing (as shown in the figure). The connection can be a programmed connection that connects the drain of the transistor 306 to V DD_1 a node other than the N-1 other nodes illustrated in the figure.

[0050] The method 300 for storing a multi-bit value as a conductive state in a circuit element can continue at 313 with the step of connecting the second node (e.g., gate) of the transistor 306 to a second supply voltage node (e.g., of the voltage regulator 307). The second supply voltage node can be one of a plurality of voltages, such as V DD_0 Biasing (as shown in the figure). The connection can be a programmed connection that connects the gate of the transistor 306 to V DD_0 a node other than the N-1 other nodes illustrated in the figure. Although in the illustrated case, the second node can be biased by the same set of voltages as the first node, in particular embodiments, the second node can be biased by a different set of voltages, which can overlap or be mutually exclusive with the set of voltages used to bias the first node. For example, in particular embodiments, V DD_0 of the voltage regulator 305 and V DD_0 of the voltage regulator 307 can refer to different voltages. In particular embodiments, V DD_0 of the voltage regulator 305 and V DD_0 of the voltage regulator 307 can refer to the same voltage.

[0051] The foregoing steps (e.g., 312 and 313) of programmatically connecting two terminals (e.g., drain and gate) of the transistor 306 to different voltages (e.g., V DD_1 and V DD_0 ) result in the value of the multi-bit ROM cell being stored as a conductive state of the transistor 306.

[0052] The terminals of the transistor 306 (or other storage device) can be connected to different biases in various ways. For example, the transistor 306 can be constructed to have branch nodes from its terminals connected to different bias nodes. These branches can have fuse or anti-fuse elements that allow the device to be connected to a single bias node via one of the branch nodes by breaking all but one of a set of fuses or by blowing a single anti-fuse from a set of anti-fuses. The branches can also have gaps that can be filled by a jump added when the device is programmed. This jump can be a mask ROM jump and include two vias and metal that can be supplied at a higher level across the gap. The branches can also have gaps that can be selectively filled by altering the mask used for the wiring layer on which the branch appears. As another example, the device can be constructed using a compiler that is programmed to generate an optimal wiring pattern for a set of ROM cells to be interconnected with a set of bias voltages. The connection step can include connecting one of a set of wires extending from a first node to a first supply voltage node and connecting one of a set of wires extending from a second node to a second supply voltage node.

[0053] The circuit 301 can be part of a ROM cell. A read operation (to read the value stored by the transistor 306) can involve applying a high voltage to the word line 304 and measuring the resulting current on the bit line 303. Individual memory cells in a ROM array can be read by addressing a particular cell by applying signals to the word line (e.g., the word line 304) and the bit line (e.g., the bit line 303) in combination. An address can be applied to a decoder that generates the appropriate bit line and word line signals to read the state of a given storage element. In this way, the conductive state of the storage transistor (e.g., the transistor 306) can be read by measuring the current on the bit line. The source or drain of the storage transistor that is coupled to the read transistor can be biased to a low voltage during a read operation that has just enough margin for the input of a comparator. The transistor 302 can be referred to as a read transistor because it controls the read operation of the ROM cell.

[0054] In certain embodiments of the invention disclosed herein, instead of similar circuit elements that would otherwise store a single bit of information in a conventional ROM cell, a single circuit element such as the transistor 306 can store multiple bits by using multiple biases. A ROM array according to these embodiments can exhibit a much higher information density compared to a conventional ROM array. The integrated ROM storage can be provided in close proximity to the computational elements of the integrated circuit on the integrated circuit.

[0055] Figure 4 An example of a circuit 401 that is part of a multi-bit ROM is illustrated, with multiple voltage generators (to generate multiple voltages) and multiple voltage regulators 405. The circuit 401 can include a supply voltage V DD_INand voltages V DD_0 to V DD_N Each voltage is coupled with a voltage regulator 405. Voltage regulators 405 can each comprise a digital low-dropout (LDO) regulator. Circuit 401 can be combined with, incorporated by, or overlap features of circuit 201 and / or circuit 301. For example, voltage regulators 405 can correspond to voltage regulator 205, voltage regulator 305, and voltage regulator 307. A multi-bit ROM can include one or more circuits 401, one or more circuits 201, one or more circuits 301, or a combination thereof.

[0056] A multi-bit ROM including circuit 401 can also include a transistor having a first node and a second node, such as transistor 202 or transistor 306, and Figure 2 and Figure 3 other features of . One or more sets of voltage regulators 405 can be coupled (or not coupled) with transistors in a variety of ways. Voltage regulators 405 can be coupled (programmatically connected) with nodes or terminals of transistors during fabrication, packaging, deployment, or post-fabrication processing. Voltage regulators 405 can be coupled or not coupled with nodes or terminals of transistors via a combination of wires, fuses, antifuses, mask layers, jumpers, tap points, and the like. A variety of processes can be used to form connections between terminals of storage elements and desired voltage sources, or to break connections between terminals of storage elements and undesired voltage sources. Accordingly, biasing can be used to set conductive states of storage elements as desired.

[0057] A first node can be a drain of a transistor or a source of a transistor, and a second node can be a gate of a transistor. A multi-bit ROM can include a connection from the first node to a first supply voltage and a connection from the second node to a word line, as shown in Figure 2 . A multi-bit ROM can also include a connection from the first node to a first supply voltage node and a connection from the second node to a second supply voltage node, as shown in Figure 3 . A first supply voltage node can correspond to a different voltage or the same voltage as a second supply voltage node. As illustrated by the dotted lines in Figure 2 and Figure 3 , one or more nodes of a transistor can each be programmatically connected to a bias node among N+1 bias nodes. Values of a multi-bit ROM cell in a multi-bit ROM can be stored as connectivity states of a transistor or as conductive states of a transistor. Writing to a ROM memory can involve determining addresses of ROM cells, and assigning values to the ROM cells by connecting terminals of storage transistors to bias voltages (e.g., corresponding to voltage regulators 405) associated with the values.

[0058] In particular embodiments of the application, each terminal of a storage element (e.g., a transistor) can be associated with a set of wires that enable it to be connected to a different bias voltage associated with voltage regulator 405. A multi-bit ROM cell can also include a set of wires extending from a first node or terminal of the storage element. Each wire in the set of wires extending from the first node can be uniquely associated with one of a plurality of voltages that can be used to bias the first node. A connection from the first node to a first supply voltage node includes a wire in the set of wires extending from the first node and a programmed connection to the first supply voltage node. A multi-bit ROM cell can also include a set of wires extending from a second node or terminal of the storage device. Each wire in the set of wires extending from the second node can be uniquely associated with one of a plurality of voltages. A connection from the second node to a second supply voltage node includes a wire in the set of wires extending from the second node and a programmed connection to the second supply voltage node.

[0059] In particular embodiments of the application, each terminal of a storage element can have a wire extending from the node, where the wire includes a set of tap points. The set of tap points in the wire can each be uniquely configured to connect to one of a plurality of voltages that can be applied to the terminal of the storage element. The connections between the tap points and the node that is biased by the voltage selected from among the plurality of voltages applied to the terminal of the storage element can be programmed using anti-fuses or fuse elements, one or more custom mask layers, jumpers, or any circuit element that can be used to programmatically connect two nodes of a circuit during manufacturing, packaging, or deployment.

[0060] Programmed connections of storage elements to first and second supply voltages (e.g., voltage regulator 405) can be made by wires formed by one or more masks that are unique to the programmed state of the multi-bit ROM. The programmed connections can be made during the wiring layer of the integrated circuit in which the multi-bit ROM is located. The mask can define a pattern that connects one of the set of wires for each terminal to an associated supply voltage. The pattern is unique to the programmed state of the multi-bit ROM cell because the pattern defines connections to the terminals that in turn define the conductive state of the ROM cell. The pattern can be formed by one or more masks. If the pattern can be used to form on a single wiring layer level, where different masks are unique in which nodes they connect and which nodes they do not connect, a single mask can be used to form the pattern. If the pattern involves vias and other metal layers, multiple masks can be used.

[0061] The programmable connections to write to the ROM cells according to the present disclosure can be made at different times. For example, the connections can be made during the manufacture of an integrated circuit on which the ROM cells are to be integrated during back-end-of-line processing. As another example, the connections can be made using fuses or anti-fuses, such as after the chip has been manufactured but before deployment (e.g., before or during packaging of the integrated circuit). As another example, the connections can be made electronically during packaging or after the chip has been packaged, by applying electrical signals to change the state of conductive elements in the integrated circuit and to form or break connections between terminals of storage elements and biases used to set the conductive state of the storage elements.

[0062] In certain embodiments of the invention disclosed herein, instead of a similar circuit element that would otherwise store a single bit of information in a conventional ROM cell, a single circuit element can store multiple bits by using multiple biases. A ROM array according to these embodiments can exhibit a much higher information density compared to a conventional ROM array. The integrated ROM storage can be provided on the integrated circuit next to the computational elements of the integrated circuit.

[0063] Figure 5 A circuit 501 is illustrated that can include features of the circuit 201 (in Figure 2 the circuit 201) and adds circuitry representing additional features of a bit line and a particular read circuit in the form of multiple comparators (e.g., comparator 503 and comparator 504) coupled to the bit line. The circuit 501 includes a transistor 502 (represented in the figure by a variable resistor), a comparator 503, a comparator 504, a read reference voltage 505, a read reference voltage 506, a bit line capacitance 507, and a supply voltage 508. The transistor 502 can be a FET or can be a different storage element, with the transistor being merely an example. Different read circuits disclosed herein can be used instead of this read circuit, and multiple comparator read circuits are used merely as an example. Although two comparators (503 and 504) are shown, any number of comparators can be part of the circuit 501. The read reference voltage 505 can be associated with the comparator 503 and the read reference voltage 506 can be associated with the comparator 504.

[0064] A read circuit is coupled to the source of transistor 502, which stores the state of the memory cell. The read circuit can include a bit line shared by numerous other storage elements (e.g., transistors) that are not connected to the same word line as transistor 502. Bit line capacitance 507 is represented by a capacitor. The bit line can have a fixed capacitance. Transistor 502 is shown in circuit 501 as a resistor representing the "on" resistance of transistor 502. Supply voltage 508 is connected to the drain node of transistor 502 and is shown in circuit 501 as a variable power supply. However, when the connectivity state of the cell has been set to store the value of the memory cell, the value of supply voltage 508 will be fixed. During a read operation, the voltage applied by the read voltage (through transistor 502) will charge the bit line. The comparator (comparator 503 or comparator 504) with the highest read reference voltage (read reference voltage 505 or read reference voltage 506, respectively) will indicate the connectivity state of the memory cell, which flips its output during a read operation. Thus, a read operation involves reading which comparator output toggles and the reference voltage input to that comparator as the read value. As will be described below, the comparators can be biased with the same voltages generated by the reference generator circuits that generate the bias voltages used to set the connectivity state of the memory cell transistors. Thus, any changes in the reference voltages that set the state of the transistors will be offset by a corresponding change in the comparator levels. Figure 4

[0065] In certain embodiments of the invention disclosed herein, instead of similar circuit elements that would otherwise store a single bit of information in a conventional ROM cell, a single circuit element, such as transistor 502, can store multiple bits by using multiple biases. A ROM array according to these embodiments can exhibit a much higher information density compared to a conventional ROM array. The integrated ROM storage can be provided on the integrated circuit next to the computational elements of the integrated circuit.

[0066] Figure 6 Circuit 601 is illustrated, which can include features of circuit 301 (in Figure 3 Circuit 601 can also incorporate aspects of circuit 201, circuit 401, and circuit 501. Circuit 601 includes transistor 602, comparator 603, read reference voltage 605, capacitor 607, and supply voltage 608. Transistor 602 can be a storage transistor and can be similar to transistor 306. A read circuit is coupled to transistor 602, which stores the state of the memory cell. The read circuit can include a read transistor (e.g., similar to transistor 302) connected between the node of transistor 602 and capacitor 607. The read transistor is not shown in circuit 601. Figure 6 ​independently represent, this is because it is assumed that it is substantially negligible due to being biased by a high relative voltage. However, in a particular implementation, the resistance of the read transistor (switch) can be estimated or measured during calibration and calibrated to not affect the measurement of the conductive state of transistor 602 during a read operation. In a particular embodiment, the read transistor can be sized such that it will not have a significant resistance compared to transistor 602 (e.g., a storage transistor), such as by having a larger channel width and a smaller channel length than transistor 602.

[0067] As Figure 6 As illustrated in the circuit 601, the first node of transistor 602 is a source or drain node and it is connected to a supply voltage 608. The second node of transistor 602 is a gate node and it is connected to another supply voltage (not shown). The read circuit can include a second transistor (not shown) connected to the third node of transistor 602, which is a source or drain node of transistor 602. Transistor 602 is shown in circuit 601 as a resistor with a programmable resistance value. The supply voltage 608 connected to the drain node of transistor 602 is shown in circuit 601 as a variable power source. This voltage will affect the current through the read circuit and thus in a particular embodiment, the logic of circuit 601 tracks the applied voltage (e.g., supply voltage 608) when sensing the conductive state of a ROM cell and can also adjust the measurement threshold voltage of the read circuit described below accordingly.

[0068] The read circuit disclosed herein can be configured to connect to different bit lines in the memory at different times, as controlled by the read address of the memory cell being read. The read circuit for a ROM cell according to certain embodiments disclosed herein can also include a capacitor 607. The capacitor 607 can be used for read operations and is referred to as a read capacitor. The read circuit can be shared by multiple ROM cells such that multiple cells share the same capacitor (e.g., capacitor 607). The capacitor 607 can be a discrete element of the read circuit in the form of a plate capacitor integrated with the memory array. Alternatively, the capacitor 607 can include or comprise the parasitic capacitance of the bit line. Alternatively, the capacitor 607 can include the parasitic capacitance of any circuitry attached to the bit line, such as the comparator 603. The capacitor 607, transistor 602, and read transistor can be coupled such that the current flowing through the transistor 602 and read transistor charges the capacitor 607. By measuring the time taken to charge the capacitor 607, an estimate of the resistance of the transistor 602 can be obtained. The size of the capacitor 607, transistor 602, and bias voltage can be selected to ensure sufficient dynamic range for detecting the conductive state of the storage element (e.g., transistor 602). For a comparable ROM circuit, the expected charging time for the least conductive conductive state should occur within a reasonable read time. Reading a multi-bit ROM cell can involve applying a read signal to the gate of the read transistor mentioned above, charging the capacitor 607 using the current flowing through the transistor 602 and read transistor, and sensing the charging time of the capacitor 607 as it is charged by the current.

[0069] The read circuit for a ROM cell according to certain embodiments disclosed herein can also include a sensing circuit. The sensing circuit can be configured to sense the charging time of the capacitor 607 as it is charged by the current. Sensing the charging time of the capacitor 607 can involve supplying a measurement reference voltage to a comparator (e.g., comparator 603). The measurement reference voltage can be generated using the same circuitry used to generate the bias voltage for the transistor 602. In these approaches, the measurement reference voltage can automatically adjust with changes in the conductive state of the transistor 602 imparted by the bias voltage. The measurement reference voltage can change from one read operation to another based on the value of the bias voltage applied to the drain of the transistor 602. For example, the measurement reference voltage can be set to half of the drain bias voltage. Using this approach and the fact that the capacitor 607 can charge according to an RC time constant curve, the read time to detect a given conductive state will not be affected by changes in the drain bias voltage.

[0070] The sense circuit can include a comparator 603 coupled to the read reference voltage 605 and a capacitor 607 (e.g., a read capacitor). The comparator 603 can have a negative input coupled to the read reference voltage 605 and a positive input coupled to the capacitor 607 (as shown in the figure). Alternatively, the comparator 603 can have a positive input coupled to the read reference voltage 605 and a negative input coupled to the capacitor 607. The output of the comparator 603 can be connected to a counter circuit. The counter circuit can be coupled to the output of the comparator 603 as well as to a ring oscillator. A read operation can then involve sensing the charging time of the capacitor 607 by supplying the measurement reference voltage to the comparator 603, running the ring oscillator, counting the oscillations of the ring oscillator using the counter circuit while current is being supplied to the capacitor 607; and stopping the counter based on the output from the comparator 603. Since the output of the comparator 603 indicates that the capacitor 607 has charged to the measurement reference voltage, the counter circuit will be forced to stop counting based on the comparator output.

[0071] The sense circuit can alternatively include a ring oscillator powered by the voltage of the bit line. A counter circuit can then be operated to count the number of oscillations in the ring oscillator to determine how fast the ring oscillator starts oscillating when the capacitor 607 is given a fixed amount of time to charge and read. A read operation can then involve supplying the bit line voltage as power to the ring oscillator and counting the number of oscillations in the ring oscillator using the counter circuit for a fixed read period. In this fixed read period, a high conductive state will result in a high count, while a low conductive state will result in a low count.

[0072] In certain embodiments of the invention disclosed herein, instead of a similar circuit element that would otherwise store a single bit of information in a conventional ROM cell, a single circuit element such as the transistor 602 can store multiple bits by using multiple biases. A ROM array according to these embodiments can exhibit a much higher information density compared to a conventional ROM array. The integrated ROM storage can be disposed in close proximity to the computing elements of the integrated circuit on the integrated circuit.

[0073] Figure 7 A read circuit 700 with a set of voltage regulators 705 and a set of comparators 703 is illustrated according to certain embodiments of the invention disclosed herein. The voltage regulators 705 can be the same type of regulator as the voltage regulator 405 from Figure 4 . The read circuit 700 also includes a bit line 702, a reference voltage level 707 (e.g., a comparison voltage level), and a V DD_IN .

[0074] The voltage regulators 705 will be labeled as V REFA reference voltage level 707 is provided to comparator 703. As shown, comparator 703 corresponds one-to-one with voltage regulator 705, meaning that in a given read circuit, one voltage regulator is paired with one comparator. In a particular embodiment, voltage regulator 705 may be paired with different comparators 703 in different read circuits of a given multi-bit memory system. The reference voltage level 707 may be approximately equal to the reference voltage provided to the memory cell minus half the step size between adjacent voltages in a set of reference voltages for the memory cell. In other words, each reference voltage level 707 in a set of reference voltage levels 707 may be approximately in the middle of each reference voltage (for the memory cell) in that set of reference voltage levels. The step size between reference voltage levels 707 or between reference voltages may be uniform or non-uniform. In a particular embodiment, the set of voltage regulators providing voltage to the memory cell may overlap with the set of voltage regulators 705 providing voltage to comparator 703. In a particular embodiment, the set of voltage regulators 705 that provides voltage to comparator 703 and the set of regulators that provide voltage to memory cells can be designed such that the common-mode offset in the voltage regulators applies equally to both sets of regulators. For example, the regulators can operate at the same supply voltage and can typically share certain components, such as current source transistors, current mirrors, and bias circuitry.

[0075] As illustrated, bit line 702 is connected to the input terminals of a set of comparators 703, and another input of each of the comparators 703 is connected to a bias voltage (e.g., a reference voltage level 707). When the read circuit 700 reads the data according to... Figure 2 When used together with the memory cells, bit line 702 (corresponding to bit line 203) can operate according to the charge-sharing principle, such that it reaches the voltage applied to the storage element (e.g., transistor 202) in the memory array after a fixed read cycle. The fixed read cycle can be set based on the expected charge-sharing cycle under worst-case conditions, which can be set by the lowest bias that can be applied to the memory element (e.g., reference voltage level 707). The highest comparator 703, which jumps during the read cycle, can be used to determine the value stored in the memory cell (e.g., at transistor 202).

[0076] When the reading circuit 700 is based on Figure 3When used with a memory cell of the type shown in FIG. 2, bit line 702 (corresponding to bit line 303) can be charged according to a charge characteristic set by the conductance of the storage element (e.g., transistor 306) during a fixed read period. The fixed read period can be set based on a desired dynamic range of potential values stored in the memory cell. The highest comparator 703 to toggle during the read period can still be used to determine the value stored in the memory cell (e.g., at transistor 306). Alternatively, the speed at which a particular comparator (of the set of comparators 703) toggles during the read period can be used to determine the value stored in the memory cell. A counter circuit designed to turn off and stop counting when a comparator toggles can be used to measure the speed.

[0077] In certain embodiments of the application disclosed herein, instead of a similar circuit element that would otherwise store a single bit of information in a conventional ROM cell, a single circuit element can store multiple bits by using multiple biases. A ROM array according to these embodiments can exhibit a much higher information density compared to a conventional ROM array. The integrated ROM storage can be placed in close proximity to the computational elements of the integrated circuit on the integrated circuit.

[0078] Figure 8 A read circuit 800 with a voltage controlled oscillator (VCO) 801 is illustrated according to certain embodiments of the application disclosed herein. As illustrated, bit line 803 is connected to an input terminal of VCO 801. When read circuit 800 is used with a memory cell of the type shown in FIG. 2, bit line 803 (corresponding to bit line 203) can operate according to the principle of charge sharing, such that it reaches the voltage applied to the storage element (e.g., transistor, such as transistor 202) in the memory array after a fixed read period. The fixed read period can be set based on an expected period of charge sharing in the worst case scenario, which can be set by the lowest bias that can be applied to the memory element. The frequency output on the output of VCO 801 at the end of the fixed read period can be used to determine the value stored in the memory cell. The frequency can be determined by measuring the distance between pulses at the end of the read period. Figure 2 When read circuit 800 is used with a memory cell of the type shown in FIG. 2, bit line 803 (corresponding to bit line 203) can operate according to the principle of charge sharing, such that it reaches the voltage applied to the storage element (e.g., transistor, such as transistor 202) in the memory array after a fixed read period. The fixed read period can be set based on an expected period of charge sharing in the worst case scenario, which can be set by the lowest bias that can be applied to the memory element. The frequency output on the output of VCO 801 at the end of the fixed read period can be used to determine the value stored in the memory cell. The frequency can be determined by measuring the distance between pulses at the end of the read period.

[0079] Figure 3 ​When used with memory cells, bit line 803 (corresponding to bit line 303) can be charged according to a charging characteristic set by the conductance of a storage element (e.g., a transistor, such as transistor 306) during a fixed read period. The fixed read period can be set based on a desired dynamic range of potential values stored in the memory cells. The number of pulses generated by VCO 801 during the fixed period, determined by counter circuit 804, which can be designed to turn off at the end of the fixed period, can be used to determine the value stored in the memory cell. Alternatively, the speed at which a particular comparator toggles during the read period can be used to determine the value stored in the memory cell. Counter circuit 804, which can be designed to turn off and stop counting when the comparator toggles, can be used to measure this speed.

[0080] In certain embodiments of the invention disclosed herein, instead of similar circuit elements that would otherwise store a single bit of information in a conventional ROM cell, a single circuit element can store multiple bits by using multiple biases. A ROM array according to these embodiments can exhibit a much higher information density compared to a conventional ROM array. The integrated ROM storage can be placed in close proximity to the computing elements of the integrated circuit on the integrated circuit.

[0081] Figure 9 A read circuit 900 for a ROM memory array 903 augmented with a neural network decoder according to certain embodiments of the invention disclosed herein is illustrated. In certain embodiments, a decoder neural network has been trained on the ROM memory array 903 to filter out noise from the ROM memory array 903. The ROM memory array 903 (e.g., a ROM cell array) can be according to the examples described above. As can be seen in the figure, a decoder neural network (e.g., a denoising neural network 905) can modify a noisy output 904 (e.g., noisy output values) to a denoised output 906. The illustrated method also shows how a neural network can be trained. For example, an automatic test environment (ATE) test program 901 can supply golden values (e.g., benchmark true golden values) as test inputs 902 to be stored by the ROM memory array 903, and then compare the read values (e.g., denoised output 906) corresponding to these stored golden values with the golden values 909 via a comparator 907. The difference between the two can be used in a loss function for training the neural network to denoise the noisy output 904 via a training output generator and loss calculator 910. The test inputs 902 can be readings generated by a tester for training. The ATE test program 901 can generate the test inputs 902 for the ROM memory array 903 and can generate the golden values 909 in order to train the neural network.

[0082] The neural network can learn the error sources of the ROM memory array 903, which allows for increasing the density of the ROM cells by storing multiple bits per cell without worrying about the effect of noise on these cells. Noise sources can be attributed to varying routing distances, storage transistor idiosyncrasies, differences in conductivity of the configurable connections (e.g., fuses) between the storage transistors and the bias sources, read circuit variations, and other factors. Notably, the methods such as Figure 2 The methods of the methods in such as

[0083] The illustrated methods can be well suited for ROM arrays that store values using analog conductive states, such as the conductive states mentioned herein (e.g., a bias voltage connected to the source of a single transistor cell or a source-to-drain conductance of an FET with given gate and drain bias voltages). The encoder neural network and the decoder neural network can be implemented in hardware and integrated with the ROM array (e.g., the ROM memory array 903). In particular embodiments, any ROM data used for the decoder neural network and optionally the encoder neural network can be implemented using standard single-valued ROM to avoid the effect of noise on the circuits designed to filter out noise on a multi-bit ROM array. The combined system can include a multiplexer 911 to feed in test inputs 902 (training inputs) from the ATE test program 901 (training data input generator) for the training phase of the neural network.

[0084] As shown, the system can also include a training output generator and loss calculator 910 that is aware of the test input 902 (e.g., golden values 909) provided by the ATE test program 901 (e.g., training data input generator). The figure also shows how the loss 908 can be fed back to the decoder neural network (e.g., denoising neural network 905) during training. Gradients from the training output generator and loss calculator 910 can also be fed back to the decoder neural network (e.g., denoising neural network 905) during training. Once trained, the weights of the decoder neural network can be set for permanent use using ROM or any form of non-volatile memory. Alternatively, the decoder neural network can be retrained periodically in phases between operational use of the ROM memory array 903. A multiplexer 911 can switch input from the ATE test program 901 to a normal input path 912. For example, once the system is trained or between training phases, the multiplexer 911 can switch to the normal input path 912. The normal input path 912 can input data used during normal operation of the ROM memory array 903 (e.g., not during training of the neural network).

[0085] In these embodiments, integration of the ROM memory array 903 with processing circuitry can be facilitated because the noise cancellation effect of the neural network will make the bit lines, word lines, and power supply lines of the ROM memory array 903 more uniform than in standard ROM circuits and multi-bit memory circuits, which will make the layout of the ROM memory array 903 more conformable to the desired layout of the processing circuitry.

[0086] In certain embodiments of the invention disclosed herein, instead of a similar circuit element that would otherwise store a single bit of information in a traditional ROM cell, a single circuit element can store multiple bits by using multiple biases. A ROM array according to these embodiments (e.g., ROM memory array 903) can exhibit a much higher information density compared to traditional ROM arrays. The integrated ROM storage can be disposed in close proximity to the computing elements of the integrated circuit on the integrated circuit.

[0087] Figure 10 An example of a method 1000 for storing a multi-bit ROM cell according to certain embodiments of the invention disclosed herein is illustrated. The values of the multi-bit ROM can be stored in the form of connectivity states or conductive states of transistors. Portions of the method 1000 can be omitted, duplicated, or reconfigured.

[0088] At 1001, a plurality of voltage regulators can be provided. The plurality of voltage regulators can generate a plurality of voltages for the multi-bit ROM.

[0089] In a particular embodiment, at 1002, a transistor of a multi-bit ROM can be fabricated to have a first threshold voltage. A second transistor of the multi-bit ROM can be fabricated to have a second threshold voltage. The second transistor can be part of a different multi-bit ROM cell than the transistor. The second threshold voltage can be different than the first threshold voltage. A value of the multi-bit ROM can be stored as a conductivity state of the transistor.

[0090] At 1003, a first node of the transistor can be connected with a first supply voltage node. The first supply voltage node can be biased by one of a plurality of voltages (e.g., generated at 1001). The transistor can be in a multi-bit ROM cell of a multi-bit ROM. A value of the multi-bit ROM can be stored as a connectivity state or a conductivity state of the transistor. The first node of the transistor and the first supply voltage can be connected by connecting one of a set of conductive lines extending from the first node to the first supply voltage node. The first node and the first supply voltage can be connected during a wiring layer of an integrated circuit in which the multi-bit ROM is located (e.g., some or all steps associated with the connection). Connecting the first node with the first supply voltage (e.g., the process of connecting) can use one or more masks that are unique to a programmed state of the multi-bit ROM.

[0091] In a particular embodiment, at 1004, a second node of the transistor can be connected with a second supply voltage node. The second supply voltage node can be biased by one of a plurality of voltages (e.g., the voltages provided at 1001). A value of the multi-bit ROM cell can be stored as a connectivity state or a conductivity state of the transistor. The second supply voltage node can be biased by a different voltage than the voltage that biases the first supply voltage node. The second supply voltage node can be biased by the same voltage that biases the first supply voltage node. A value of the multi-bit ROM cell can be stored as a conductivity state of the transistor. The second node of the transistor and the second supply voltage can be connected by connecting one of a set of conductive lines extending from the second node to the second supply voltage node. The second node and the second supply voltage can be connected during a wiring layer of an integrated circuit in which the multi-bit ROM is located (e.g., some or all steps associated with the connection). Connecting the second node with the second supply voltage (e.g., the process of connecting) can use one or more masks that are unique to a programmed state of the multi-bit ROM.

[0092] In particular embodiments of the invention disclosed herein, instead of similar circuit elements that would otherwise store a single bit of information in a traditional ROM cell, a single circuit element can store multiple bits (e.g., as a connectivity state) by using multiple biases. A ROM array according to these embodiments can exhibit a much higher information density than a traditional ROM array. The integrated ROM storage can be provided in close proximity to computing elements of an integrated circuit on the integrated circuit.

[0093] Figure 11 An example of a method 1100 for reading a multi-bit ROM cell is illustrated in accordance with certain embodiments of the application disclosed herein. The value of a multi-bit ROM can be stored in the form of a connectivity state or a conductive state of a transistor. Portions of the method 1100 can be omitted, duplicated, or reconfigured.

[0094] At 1101, a value of a multi-bit ROM can be written in accordance with the method 1000. Figure 10 At 1102, a first transistor can be connected to a second transistor. The first transistor can be a storage transistor. The second transistor can be a read transistor. The first transistor can be connected to a third node of the transistor and a capacitor. The second transistor can be connected to a control node of the transistor. The capacitor can be a read capacitor. The capacitor can be shared by at least one other multi-bit memory cell in the multi-bit ROM. The capacitor can be a parasitic capacitor of a bit line.

[0095] At 1105, a read voltage can be supplied to a control node (e.g., gate) of the transistor. The read voltage can be a read signal. In embodiments where the multi-bit ROM cell has only one transistor, the read signal can be applied to the gate of the first transistor, or in embodiments where the multi-bit ROM cell has two transistors, the read signal can be applied to the gate of the second transistor. The read signal can be a read voltage and the gate of the second transistor can be a control node of the second transistor. The second transistor can be connected to a third node of the transistor and a capacitor. The transistor can be a storage transistor. The second transistor can be a read transistor. In certain embodiments, the read transistor and the storage transistor can be the same transistor. The capacitor can be a read capacitor. The capacitor (e.g., read capacitor) can be shared by at least one other multi-bit memory cell in the multi-bit ROM. The capacitor can be a parasitic capacitor of a bit line.

[0096] At 1106, the capacitor can be charged. The capacitor can be charged using a current flowing through the transistor and the second transistor. The capacitor can be connected to the second transistor.

[0097] At 1107, a charging time of the capacitor can be sensed. The charging time can be related to a duration of time that the capacitor is charged by the current. To sense the charging time of the capacitor, at 1108, a measurement reference voltage can be supplied to a comparator. The comparator can be connected to the capacitor. To sense the charging time of the capacitor, at 1109, a ring oscillator can be run. To sense the charging time of the capacitor, at 1110, a number of oscillations of the ring oscillator can be counted. The number of oscillations can be counted while the current is supplied to the capacitor. To sense the charging time of the capacitor, at 1111, a counter circuit can be stopped. The counter circuit can be stopped based on an output from the comparator. There are multiple ways in which a value stored in a multi-bit ROM cell can be read.

[0098] In a particular embodiment, from the step of supplying a read voltage to a control node of a transistor (e.g., 1105), at 1115, a bit line voltage on a bit line can be sensed. A read circuit can be used to sense the bit line voltage. The read voltage (e.g., from 1105) can be supplied to the control node while the bit line voltage is sensed. The bit line can be connected to a second node of the transistor. The read circuit can include a set of comparators. Each comparator in the set of comparators can have an input that is biased in a one-to-one correspondence by a voltage regulator from a plurality of voltage regulators. The read circuit can include a voltage controlled oscillator (VCO). The bit line can be coupled to an input of the VCO.

[0099] In a particular embodiment, at 1116, a number of pulses generated by the VCO can be counted. A counter circuit can be used to count the number of pulses in a fixed read period.

[0100] Regardless of whether a counter counts a number of oscillations of a ring circuit (e.g., at 1110), a counter counts a number of pulses generated by a VCO in a fixed read period (e.g., at 1116), or information about a stored value of a transistor is gathered via some other means, a neural network can be used to denoise an output. In a particular embodiment, at 1120, a bit line voltage can be supplied to the neural network. The neural network can be trained on a multi-bit ROM.

[0101] In a particular embodiment, at 1121, a value of the multi-bit ROM can be determined. For example, the value of the multi-bit ROM can be determined using the neural network and the bit line voltage.

[0102] In particular embodiments of the invention disclosed herein, instead of a similar circuit element that would otherwise store a single bit of information in a conventional ROM cell, by using multiple biases, a single circuit element can store multiple bits (e.g., as a state of conductivity). A ROM array according to these embodiments can exhibit a much higher information density compared to a conventional ROM array. The integrated ROM storage can be disposed in close proximity to computing elements of an integrated circuit on the integrated circuit.

[0103] While the present specification has been described in detail with respect to specific embodiments thereof, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, can readily conceive of alterations, variations and equivalents thereof. Any of the method steps discussed above can be performed by a processor operating with a computer-readable non-transitory medium storing instructions for those method steps. The computer-readable medium can be a memory within a personal user device or a network-accessible memory. While examples in the present disclosure are generally with respect to ROM, the same methods can be used for programmable memory. For example, connections between nodes of transistors and reference voltages can be configured in a programmable manner, rather than formed during manufacture of the memory, such as based on fuses, phase-change materials, or transistors with floating gates that can be programmed by tunneling electrons to the gates. These and other modifications and variations of the present application can be practiced by those skilled in the art, without departing from the scope of the application, which is more particularly set forth in the appended claims.

Claims

1. A method (1000) comprising: Provides (1001) multiple voltage regulators (205; 305; 307; 705) for generating multiple voltages for a multi-bit read-only memory; and A first node of transistors (202; 302; 306; 502; 602) is connected (1003) to a first supply voltage node, wherein the first supply voltage node is biased by one of the plurality of voltages, wherein transistors (202; 302; 306; 502; 602) are in a multi-bit read-only memory cell of the multi-bit read-only memory, and thereby the value of the multi-bit read-only memory cell is stored as the connection state of transistors (202; 302; 306; 502; 602).

2. The method (1000) according to claim 1, further comprising: The transistors (202; 302; 306; 502; 602) are manufactured (1002) to have a first threshold voltage, wherein the second transistors (202; 302; 306; 502; 602) in the multi-bit read-only memory have different second threshold voltages, and thereby the value of the multi-bit read-only memory cell is stored as the conductivity state of the transistors (202; 302; 306; 502; 602).

3. The method (1000) according to claim 1, further comprising: The second node of the transistor (202; 302; 306; 502; 602) is connected (1004) to a second supply voltage node, wherein the second supply voltage node is biased by one of the plurality of voltages; The value of the multi-bit read-only memory cell is stored as the conductivity state of the transistor (202; 302; 306; 502; 602).

4. The method (1000) according to claim 1, further comprising: The read voltage supply (1105) is supplied to the control node of the transistors (202; 302; 306; 502; 602); and Using the read circuit (700; 800) and when the read voltage is supplied (1105) to the control node, the voltage of bit line (103; 203; 303) on bit line (103; 203; 303) is sensed (1115), wherein the bit line (103; 203; 303) is connected to a second node of the transistor (202; 302; 306; 502; 602).

5. The method (1000) according to claim 4, further comprising: The voltage of the bit lines (103; 203; 303) sensed by the read circuitry (700; 800) is supplied (1120) to the neural network, wherein the neural network has been trained on the multi-bit read-only memory; and The value of the multi-bit read-only memory (1121) is determined using the neural network and the bit line (103; 203; 303) voltages.

6. The method (1000) according to claim 4, wherein: The readout circuit (700; 800) includes a set of comparators (703), and each of the comparators (503; 504; 603) has an input biased in a one-to-one correspondence with one of the plurality of voltage regulators (205; 305; 307; 705).

7. The method (1000) according to claim 4, wherein: The readout circuit (700; 800) includes a voltage-controlled oscillator (801), and the bit lines (103; 203; 303) are coupled to the input of the voltage-controlled oscillator (801).

8. The method (1000) according to claim 7, further comprising: The counter circuit (804) counts the number of pulses generated by the voltage-controlled oscillator (801) in a fixed read cycle (1116).

9. A multi-bit read-only memory, comprising: Multiple voltage generators (205; 305; 307; 401; 405; 705) for generating multiple voltages; Transistors (202; 302; 306; 502; 602) having a first node and a second node; and The connection from the first node to the first supply voltage node, wherein the first supply voltage node is biased by one of the plurality of voltages, wherein the values ​​of the multi-bit read-only memory cells in the multi-bit read-only memory are stored as the connection states of the transistors (202; 302; 306; 502; 602).

10. The multi-bit read-only memory according to claim 9, further comprising: The control node of the transistors (202; 302; 306; 502; 602); Bit lines (103; 203; 303) are connected to the second node of the transistors (202; 302; 306; 502; 602); and A readout circuit (700; 800) is used to sense the voltage on the bit line (103; 203; 303) when a voltage supply (1105) is provided to the control node of the transistor (202; 302; 306; 502; 602).

11. The multi-bit read-only memory according to claim 10, further comprising: A neural network, trained on the multi-bit read-only memory and configured to supply (1120) the bit line voltage sensed by the read circuitry (700; 800) to determine (1121) the value of the multi-bit read-only memory.

12. The multi-bit read-only memory according to claim 10, wherein: The readout circuit (700; 800) includes a set of comparators (703), and each of the comparators (503; 504; 603) has an input biased in a one-to-one correspondence with one of the plurality of voltage generators (205; 305; 307; 401; 405; 705).

13. The multi-bit read-only memory according to claim 10, wherein: The readout circuit (700; 800) includes a voltage-controlled oscillator (801), and the bit lines (103; 203; 303) are coupled to the input of the voltage-controlled oscillator (801).

14. The multi-bit read-only memory according to claim 13, further comprising: A counter circuit (804) is configured to count the number of pulses generated by the voltage-controlled oscillator (801) in a fixed read cycle.

15. A method (1000) comprising: Provides (1001) multiple voltage regulators (205; 305; 307; 705) for generating multiple voltages for a multi-bit read-only memory; A first node of transistors (202; 302; 306; 502; 602) is connected (1003) to a first supply voltage node, wherein the first supply voltage node is biased by one of the plurality of voltages, and wherein the transistors (202; 302; 306; 502; 602) are in a multi-bit read-only memory cell of the multi-bit read-only memory; and The second node of the transistor (202; 302; 306; 502; 602) is connected (1004) to a second supply voltage node, wherein the second supply voltage node is biased by one of the plurality of voltages; The values ​​of the multi-bit read-only memory cells are stored as the conductivity states of the transistors (202; 302; 306; 502; 602).

16. The method (1000) according to claim 15, wherein, These connection steps include: Connect one of the set of wires extending from the first node to the first supply voltage node; as well as Connect one of the sets of wires extending from the second node to the second supply voltage node.

17. The method (1000) according to claim 15, wherein: These connection steps are performed during the fabrication of the wiring layer of the integrated circuit in which the multi-bit read-only memory resides; and These connection steps use one or more masks that are uniquely programmed for the multi-bit read-only memory.

18. The method (1000) of claim 15, further comprising reading the multi-bit read-only memory unit by means of: A read signal is applied to the gate of a second transistor (202; 302; 306; 502; 602), wherein the second transistor (202; 302; 306; 502; 602) is connected to: (i) a third node of the transistor (202; 302; 306; 502; 602); and (ii) a capacitor (607); The capacitor (607) is charged (1106) using the current flowing through the transistors (202; 302; 306; 502; 602) and the second transistor (202; 302; 306; 502; 602); and The charging time of the capacitor (607) is sensed (1107) when the capacitor (607) is charged by the current.

19. The method (1000) according to claim 18, wherein: The transistors (202; 302; 306; 502; 602) are storage transistors (202; 302; 306; 502; 602); The second transistor (202; 302; 306; 502; 602) is a read transistor (202; 302; 306; 502; 602); The capacitor (607) is a read capacitor (607); and The read capacitor (607) is shared by at least one other multi-bit memory cell in the multi-bit read-only memory.

20. The method (1000) according to claim 18, wherein: The transistors (202; 302; 306; 502; 602) are storage transistors (202; 302; 306; 502; 602); The second transistor (202; 302; 306; 502; 602) is a read transistor (202; 302; 306; 502; 602); and The capacitor (607) is a parasitic capacitor (607) of the bit line (103; 203; 303).

21. The method (1000) according to claim 18, wherein, The charging time of sensing the capacitor (607) includes: A measurement reference voltage (505; 605) is supplied (1108) to a comparator (503; 504; 603), wherein the comparator (503; 504; 603) is connected to the capacitor (607); Run (1109) ring oscillator; When the current is supplied to the capacitor (607), a counter circuit (804) is used to count (1110) the number of oscillations of the ring oscillator; as well as The counter circuit (804) is stopped (1111) based on the output from the comparator (503; 504; 603).

22. A multi-bit read-only memory, comprising: Multiple voltage generators (205; 305; 307; 401; 405; 705) for generating multiple voltages; Transistors (202; 302; 306; 502; 602) have a first node and a second node; The connection from the first node to the first supply voltage node, wherein the first supply voltage node is biased by one of the plurality of voltages; and The connection from the second node to the second supply voltage node, wherein the second supply voltage node is biased by one of the plurality of voltages; in, The values ​​of the multi-bit read-only memory cells in the multi-bit read-only memory are stored as the conductivity states of the transistors (202; 302; 306; 502; 602).

23. The multi-bit read-only memory according to claim 22, further comprising: A plurality of transistors (202; 302; 306; 502; 602), wherein the transistors (202; 302; 306; 502; 602) are among the plurality of transistors (202; 302; 306; 502; 602); and Multiple connections from multiple first nodes of the plurality of transistors (202; 302; 306; 502; 602) to multiple supply voltage nodes, wherein the plurality of supply voltage nodes are biased by the plurality of voltages.

24. The multi-bit read-only memory according to claim 22, wherein: The first node is one of the drain of the transistor (202; 302; 306; 502; 602) and the source of the transistor (202; 302; 306; 502; 602); and The second node is the gate of the transistor (202; 302; 306; 502; 602).

25. The multi-bit read-only memory according to claim 22, further comprising: A set of wires extending from the first node, wherein each wire in the set of wires extending from the first node is uniquely associated with one of the plurality of voltages, and wherein the connection from the first node to the first supply voltage node includes a wire in the set of wires extending from the first node and a programmed connection to the first supply voltage node; and A set of wires extending from the second node, wherein each wire in the set of wires extending from the second node is uniquely associated with one of the plurality of voltages, and wherein the connection from the second node to the second supply voltage node includes wires in the set of wires extending from the second node and a programmed connection to the second supply voltage node.

26. The multi-bit read-only memory according to claim 22, wherein, Both the connection to the second supply voltage node and the connection to the first supply voltage node are wires formed by one or more masks whose programmed state is unique for the multi-bit read-only memory cell.

27. The multi-bit read-only memory according to claim 22, further comprising: A conductor extending from the first node, wherein the conductor extending from the first node includes a set of taps, and wherein each of the taps in the set of taps in the conductor extending from the first node is uniquely configured to be connected to one of the plurality of voltages; and A conductor extending from the second node, wherein the conductor extending from the second node includes a set of taps, and wherein each of the taps in the set of taps in the conductor extending from the second node is uniquely configured to be connected to one of the plurality of voltages.

28. The multi-bit read-only memory according to claim 22, further comprising: A second transistor (202; 302; 306; 502; 602), wherein the second transistor (202; 302; 306; 502; 602) is connected to a third node of the transistor (202; 302; 306; 502; 602); A capacitor (607), wherein the capacitor (607), the transistor (202; 302; 306; 502; 602), and the second transistor (202; 302; 306; 502; 602) are coupled such that the current flowing through the transistor (202; 302; 306; 502; 602) and the second transistor (202; 302; 306; 502; 602) charges the capacitor (607); and A sensing circuit configured to sense the charging time of the capacitor (607) as it is charged by the current.

29. The multi-bit read-only memory according to claim 28, wherein: The transistors (202; 302; 306; 502; 602) are storage transistors (202; 302; 306; 502; 602); The second transistor (202; 302; 306; 502; 602) is a read transistor (202; 302; 306; 502; 602); The capacitor (607) is a read capacitor (607); and The read capacitor (607) is shared by at least one other multi-bit memory cell in the multi-bit read-only memory.

30. The multi-bit read-only memory according to claim 28, wherein, The sensing circuit includes: Comparators (503; 504; 603) coupled to a reference voltage (505; 605) and the capacitor (607); Ring oscillator; as well as A counter circuit (804) coupled to the output of the comparator (503; 504; 603) and the ring oscillator.

31. The multi-bit read-only memory according to claim 28, wherein: The transistors (202; 302; 306; 502; 602) are storage transistors (202; 302; 306; 502; 602); The second transistor (202; 302; 306; 502; 602) is a read transistor (202; 302; 306; 502; 602); and The capacitor (607) is a parasitic capacitor (607) of the bit lines (103; 203; 303).

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