Microbump based 3D system with interlayer interposer and wafer reconfiguration

Abstract

A system-in-package structure and a manufacturing method using wafer reconstruction are described. In an embodiment, a 3D system includes an intermediate layer interpolator, a first package stage below the intermediate layer interpolator, and a second package stage above the intermediate layer interpolator. The first stage die and the second stage die may be bonded to the interlayer interpolator using hyperfine micro-bumps. The die within the first package stage and / or the second package stage may optionally be connected with one or more optical interconnect paths.

Description

Related applications

[0001] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 586,971, filed September 29, 2023, and U.S. Patent Application No. 18 / 656,367, filed May 6, 2024, each of which is incorporated herein by reference. background Technical Field

[0002] The embodiments described herein relate to semiconductor packaging. More specifically, the embodiments relate to three-dimensional (3D) systems and manufacturing methods. Background Technology

[0003] Current market demands for portable and mobile electronic devices, such as mobile phones, personal digital assistants (PDAs), digital cameras, portable players, gaming devices, and other mobile devices, require the integration of more performance and features into increasingly smaller spaces. As a result, various multi-die packaging solutions, such as system-in-package (SiP) and package-out-of-package (PoP), have become more prevalent to meet the needs of devices with higher die / component densities.

[0004] There are many different possibilities for arranging multiple dies in a SiP (System-in-a-Package). For example, vertical integration of dies in a SiP structure has evolved into 2.5D and 3D solutions. In a 2.5D solution, multiple dies can be flip-chip bonded to an interposer, which may include through-holes and fan-out wiring. Various 3D solutions exist. In one specific implementation, multiple dies can be stacked on top of each other on a SiP substrate and connected together using external lead bonding or solder bumps. In other conventional 3D solutions, via connections or hybrid bonding are utilized using wafer-on-wafer (WoW) or chip-on-wafer (CoW) technologies. In a WoW solution, the top and bottom device area dimensions are precisely matched, and each layer is confined to a technology node. In such a CoW solution, multiple top wafers (chips) can be integrated onto the same bottom wafer with a defined area and technology node. Summary of the Invention

[0005] A three-dimensional (3D) system and manufacturing method are described. In one embodiment, a 3D system includes an intermediate layer interposer; a first packaging stage below the intermediate layer interposer, the first packaging stage including a first-stage die bonded to the intermediate layer interposer using ultrafine microbumps (µbumps); and a second packaging stage above the intermediate layer interposer, the second packaging stage including a second-stage die bonded to the intermediate layer interposer using ultrafine µbumps. Attached Figure Description

[0006] Figure 1 The schematic cross-sectional side view of a multi-chip module (MCM) according to an embodiment is illustrated. The multi-chip module (MCM) includes a 3D system having an intermediate layer interpolator mounted on a module substrate.

[0007] Figure 2 This is a schematic cross-sectional side view illustration of an MCM including a monolithic die mounted on a module substrate.

[0008] Figure 3 This is an example of a schematic cross-sectional side view of an MCM including 3D stacked dies mounted on a module substrate.

[0009] Figures 4 to 5 This is a schematic cross-sectional side view illustration of a 3D system with an intermediate layer interpolator according to the implementation plan.

[0010] Figure 6 This is an example of a schematic cross-sectional side view of the second encapsulation level formed on the partially formed intermediate layer intercalator according to the implementation scheme.

[0011] Figure 7 This is a schematic cross-sectional side view illustration of a 3D system with an intermediate layer interpolator and a main layer removed, according to the implementation scheme.

[0012] Figures 8 to 9 This is a schematic cross-sectional side view illustration of a 3D system with an intermediate layer interpolator and a non-encapsulated first packaging level, according to the implementation scheme.

[0013] Figure 10 It is a schematic top-down layout view of a 3D system with a die-to-die route through the first-stage die, according to the implementation plan.

[0014] Figure 11 This is an example of a schematic cross-sectional side view of a 3D system with a heat-sealed cover according to the implementation plan.

[0015] Figure 12 This is an example of a schematic cross-sectional side view of a 3D system having a heat cap located on a second-stage die, according to the implementation scheme.

[0016] Figure 13 This is an example of a schematic cross-sectional side view of a 3D system with a thermally enhanced intermediate layer intercalator according to the implementation scheme.

[0017] Figure 14 This is a schematic cross-sectional side view illustration of a 3D system with a reconfigurable intermediate layer interpolator including integrated components, according to the implementation scheme.

[0018] Figure 15A This is a schematic flowchart illustrating the repair option processing flow according to the implementation plan.

[0019] Figure 15B This is a schematic cross-sectional side view illustration of a monolithic die assembly with pre-formed die-to-die routing according to the implementation scheme.

[0020] Figures 16 to 17 This is a schematic cross-sectional side view illustration of a scribing die assembly with pre-formed and scribing die-to-die routes mounted on an intercalator in the intermediate layer, according to the implementation scheme.

[0021] Figures 18 to 23 This is a schematic cross-sectional side view illustration of a semiconductor package structure with optical interconnects according to an embodiment.

[0022] Figure 24 This is an example of a schematic cross-sectional side view of a second-stage die including multiple converters and optical vias according to the implementation scheme.

[0023] Figures 25A to 25B This is a schematic cross-sectional side view illustrating the sequence of deep trench capacitor libraries used for testing and connecting intermediate layer interpolators according to the implementation scheme.

[0024] Figure 26 This is an example of a schematic cross-sectional side view of an intercalator with an intermediate layer of a metal-insulator-metal capacitor according to the implementation scheme.

[0025] Figure 27A This is a schematic top view illustrating the via connection of the capacitor to the intercalator in the intermediate layer according to the implementation scheme.

[0026] Figure 27B This is a schematic top view illustrating the connection of the landing pads to the capacitor bank according to the implementation plan. Detailed Implementation

[0027] The implementation describes a three-dimensional (3D) system and a multi-chip module (MCM) and its fabrication method, wherein a 3D system is formed using wafer reconstruction with intermediate layer interpolators, which provides sufficient connectivity between the die and the module substrate, scaling of the 3D system's performance (e.g., process node optimization), and power distribution. Specifically, the intermediate layer interpolators according to the implementation can facilitate wafer reconstruction sequences that utilize ultra-fine microbumps (µbumps) to achieve die connectivity. Compared to hybrid bonding, ultra-fine µbumps can achieve greater manufacturing tolerances and lower costs, while still providing high pin density and low latency, although they may have slightly coarser spacing. Ultra-fine µbumps can further allow the integration of more third-party chips, such as dynamic read-only memory (DRAM) or other memories, caches, power, computing, amplifiers, optics, compound semiconductor devices, other types of novel material devices (such as graphene, carbon nanotubes (CNTs), metamaterials, etc.), subsystems (such as artificial intelligence (AI), machine learning (ML), etc.), and different types of packages (e.g., sub-modules). Intermediate layer interpolators can also provide additional routing area, allowing for die partitioning and process node optimization, as well as flexibility in power delivery and integration of passive devices into 3D systems. In implementations, the 3D system is a three-dimensional integrated circuit (3DIC), a system-in-package (SiP), or another system. Due to integration with ultra-fine µ-bumps, intermediate layer interpolators according to implementations can be formed from a variety of materials, offering greater surface mount planarity tolerances compared to hybrid bonding, thus extending the range of material choices beyond silicon. In this way, material selection (although including silicon) can be extended to other materials that can provide additional properties suitable for a particular 3D system (or package), including cost, thermal conductivity, manufacturability, the ability to integrate heterogeneous components, etc.

[0028] Various embodiments are described with reference to the accompanying drawings. However, certain embodiments may be practiced without one or more of these specific details or in combination with other known methods and constructions. In the following description, numerous specific details, such as particular configurations, dimensions, and processes, are set forth to provide a thorough understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques are not described in detail to avoid unnecessarily obscuring the embodiments. The phrase "an embodiment" as used throughout the specification means that a particular feature, structure, construction, or characteristic described in connection with an embodiment is included in at least one embodiment. Therefore, the repeated use of the phrase "in an embodiment" throughout the specification does not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, construction, or characteristic may be combined in any suitable manner in one or more embodiments.

[0029] The 3D system according to the implementation plan may additionally include an electromagnetic field communication structure for wireless communication.

[0030] As used herein, the terms “below,” “above,” “to,” “between,” and “on” can refer to the relative positioning of a layer with respect to other layers. A layer being “below,” “above,” or “on” another layer, or bonded “to” another layer or “in contact” with another layer, can mean directly contacting other layers or may have one or more interlayers. A layer being “between” multiple layers can mean directly contacting those multiple layers or may have one or more interlayers.

[0031] See now Figure 1 A cross-sectional side view of a multi-chip module (MCM) 100 according to an embodiment is provided, the MCM including a 3D system 110 having an intermediate layer interposer 112 mounted on a circuit board 102. In the embodiment, the 3D system 110 includes the intermediate layer interposer 112, a first package level 120 below the intermediate layer interposer 112, and a second package level 140 above the intermediate layer interposer 112. The first package level 120 may include one or more dies bonded to the interposer 112 using ultrafine µbumps, and the second package level 140 may include at least one logic die bonded to the intermediate layer interposer 112 using ultrafine µbumps. For example, the ultrafine µbump pitch may be scaled to less than 15 µm, less than 10 µm, or even less than 6 µm or lower. The ultrafine µbumps may be solder-based, copper-copper polymer-based, etc. The vertical interconnects according to the embodiment can be implemented using vias (TVs) 132 that extend through the die (e.g., silicon via, silicon-germanium via, etc.), through the encapsulation layer 130 material (e.g., oxide via or die via), and through the intermediate layer inserter 112. The vias can be formed in various ways and at various different process stages.

[0032] Various dies / components may be included in the first package level 120. For example, the die may be a medium-power die 124 (or a low-power die), such as a system-on-a-chip (SOC), logic components, memory, power management integrated circuit (PMIC), etc. Additional dies / components include, but are not limited to, a low-speed input / output (LSIO) die 126, a cache die 128 (or memory buffer), and silicon interconnects 122. For example, silicon interconnects 122 may be chiplets including lateral routing for die-to-die connections. In some embodiments, logic or passive devices are not included in silicon interconnects 122, and the silicon interconnects are primarily used for fine die-to-die wiring. In other embodiments, capacitors or logic components may be included within silicon interconnects 122 in conjunction with fine die-to-die wiring (or optical paths). In the illustrated embodiments, the dies included in the second package level 140 may include a high-speed input / output (HSIO) die 146 and one or more high-power dies 142, 144, such as graphics processing units (GPUs), central processing units (CPUs), artificial intelligence (AI) machine learning logic components, radio frequency (RF) baseband processors, radio frequency (RF) antennas, signal processors, power management integrated circuits (PMICs), logic components, memory, photonics, biochips, silicon interconnects, and any combination thereof. It should be understood that the specific enumeration and illustration of dies / components in the first and second package levels are exemplary, and the embodiments are not limited to these specific examples. According to the embodiments, various dies may include components of different parts, may be heterogeneous, and may be layered. For example, a die may include a separately formed optical converter layer, or multiple attached components. Although silicon interconnect 122 is described as a chiplet, any die in the package can be a chiplet. Furthermore, any die / chiplet in the first or second package level may be an active component, a passive component, or a combination thereof.

[0033] The dimensions of the ultra-fine µ-bumps 152, according to the implementation scheme, can be adjusted based on routing requirements, warpage requirements, and the die or package being assembled. For example, a thicker die may have the tightest spacing of the ultra-fine µ-bumps 152, while 3D stacked dies (or packages) may have a looser spacing (e.g., to accommodate more warpage, thermal expansion mismatch, etc.). The ultra-fine µ-bumps 152 may be arranged with different corresponding spacings in multiple regions under a single die, or with a uniform spacing across the entire die. In the implementation scheme, the dies of the first packaging stage 120 and the second packaging stage 140 do not have the same ultra-fine µ-bump 152 spacing. The dies in the first packaging stage 120 may have a slightly looser ultra-fine µ-bump 152 spacing to accommodate manufacturing requirements, processes (warpage, planarity of this manufacturing stage), cost targets, etc.

[0034] As shown, the 3D system 110 (e.g., a package) can be mounted onto the circuit board 102 of the multi-chip module 100. Additional components such as one or more voltage regulators 104, a high-efficiency inductor voltage regulator 103, passive devices, and other subsystems can be mounted onto the circuit board 102. The voltage regulator 104 can be connected to the 3D system 110 via one or more power rails 106 within the circuit board 102 to provide high and low power. The medium-power die 124 may include, for example, control circuitry comprising various switches to close or open high and low voltage paths from the voltage regulator 104. The high-efficiency inductor voltage regulator 103 may additionally be connected to the power rails, for example, to provide droop assistance when the die is operating in a mode with large current-changing transients.

[0035] The intermediate layer interpolator 112 according to the implementation scheme can be passive and may include an array of passive devices, such as capacitors connected to high-voltage and low-voltage channels, to control the voltage output to the circuit load of various components including high-power dies 142, 144 or other dies. In this way, most of the die power management can be integrated into the 3D system 110 and directly below the high-power dies 142, 144.

[0036] In one aspect, conventional 3D wafer reconstruction techniques have been observed to have limitations on die stacking, where bonded dies cannot be bridged across different die boundaries, such as overlap of bonded dies with two or more die boundaries. These can cause topographic differences, leading to voids, nonbonding, or other problems. The intermediate layer interposer 112 according to an embodiment facilitates such die bridging, featuring high pin (contact pad) density and low latency. Therefore, the intermediate layer interposer 112 and / or silicon interconnect 122 can bridge across high-power dies 142, 144. The intermediate layer interposer 112 according to an embodiment may provide only the bonding interface and electrical interconnects, or may include passive devices such as trench capacitors or metal-insulator-metal (MIM) capacitors, magnetic components (inductors, coupling inductors, etc.), or even active devices. In some embodiments, the intermediate layer interposer 112 substantially spans the surface area of ​​one or both of the first package level 120 and the second package level 140. In some embodiments, the intermediate layer interposer 112 spans a subset of the surface area of ​​the first package level 120 and / or a subset of the surface area of ​​the second package level 140. In some embodiments, at least one lateral dimension of the intermediate layer interposer 112 extends beyond the corresponding lateral dimension of the first package level 120 and / or the second package level 140.

[0037] On the other hand, the implementation scheme facilitates die segmentation, enabling optimization of process nodes for different intellectual property (IP) blocks. To illustrate this effect, in Figure 2The diagram illustrates a cross-sectional side view of an MCM including a monolithic die 150 mounted on a circuit board 102. As illustrated in the exemplary illustration, various IP blocks (corresponding in this example to high power 151, HSIO 157, cache 155, medium power 156, and LSIO 158) are formed in a monolithic die with the same process node (e.g., transistor size). In this way, the selected process node may be ideal for some IP blocks, but not all. Furthermore, a larger die may be associated with a larger number of potential process failures, resulting in higher costs associated with die rejection.

[0038] On another front, the implementation scheme facilitates other key functions, including but not limited to power distribution on the circuit board of the 3D system. See also... Figure 2 This illustrates that such a monolithic die configuration also requires additional circuit board 102 area for passive devices 108 and 109. This may also require additional board routing and power rails 106. While the necessary circuit board 102 area can be reduced to some extent by positioning the passive device 109 below the monolithic die 150, this also has the effect of reducing the area used to deliver power to the monolithic die 150 and increasing the wiring requirements of the monolithic die. It should be understood that although in Figure 2 The passive device 109 is shown mounted on the underside of the monolithic die 150, but this is... Figure 1 A 3D system 110 is also possible.

[0039] See now Figure 3 A schematic cross-sectional side view of an MCM including 3D stacked dies 160 and 170 mounted on a circuit board 102 is shown. The 3D stacked dies can have similar IP blocks (in this example, corresponding to medium power 162, LSIO 164, cache 166, high power 172, high power 174, and HSIO 176, respectively). As shown, 3D die stacking can reduce the overall board area, although power delivery to the 3D die stack can be over-pre-ordered, where the number / area of ​​power rails affects voltage drop (IR), electromigration (EM), and AC impedance. Furthermore, similar to... Figure 1 The single-chip die 150, Figure 2 3D die stacking does not facilitate process node optimization for all IP blocks.

[0040] See you again now. Figure 1The 3D system 110 and intermediate layer interpolator 112 according to the embodiment can be adapted to many attributes, including process node optimization, area reduction, power distribution, and low-inductance interconnects. Essentially, the intermediate layer interpolator 112 can provide a primary bonding surface with controlled roughness, grain, and tolerances, allowing for ultra-fine µ-bumping at pitches less than 15 µm. The intermediate layer interpolator may optionally have additional integrated functionality. In an exemplary embodiment, voltage regulation can be largely integrated within the 3DIC, specifically when capacitors are integrated into the intermediate layer interpolator 112. Furthermore, the wafer size used to form components in different package levels can be arbitrary and does not impose limitations on the stacked 3D system. Dies / components can be of different technologies (IP blocks) and formed with different process nodes (e.g., transistor sizes, etc.). For example, vias through the bottom die / component can be additionally provided to provide a power source or support decoupling capacitors.

[0041] The intermediate layer interposer 112 according to the embodiment may have several metal routing layers (e.g., 3 to 5 metal layers), or may have fewer metal routing layers (e.g., 1 to 2 metal layers) to land various vias and ultra-fine µ-bumps. The ultra-fine µ-bumps according to the embodiment may span different dies / components and have different spacing within larger dies / components. Additionally, the ultra-fine µ-bump spacing on the top / bottom sides of the intermediate layer interposer may not be uniform to accommodate poor spacing or provide fan-out options. The intermediate layer interposer 112 may still include die-to-die routing, or may be offloaded to dies / chiplets in the same or different package levels. Such dies / chiplets may be integrated into either or both package levels and are selected to suit functionality and performance. Similarly, the intermediate layer interpolator 112 may include active devices (e.g., logic components, etc.) and passive components such as waveguides (e.g., integrated passive devices such as capacitors, resistors, inductors, etc.) that may also be coupled to various converters such as photoelectric converters or electro-optic converters.

[0042] The interlayer insert 112 according to the embodiment may additionally include a material with high thermal conductivity for thermal assistance of a high-performance die. For example, a composite material or silicon carbide (SiC) may have a good coefficient of thermal expansion (CTE) matching that of silicon, and the thermal conductivity of the composite material or silicon carbide (SiC) is higher than that of silicon. When formed from a suitable material such as glass or a polymer or composite material (e.g., with silicon filler) to tune characteristics, the interlayer insert 112 may additionally allow for lower parasitic vias.

[0043] Figure 4 This is an example of a schematic cross-sectional side view of a 3D system 110 with an intermediate layer interpolator 112 according to an embodiment. Specifically, Figure 4 Provided such as Figure 1 Additional details of the illustrated 3D system 110, such as the 3D system shown. As illustrated, the 3D system 110 may include an intermediate layer interposer 112, a first package level 120 below the intermediate layer interposer, and a second package level 140 above the intermediate layer interposer. The first package level 120 may include one or more first-level dies 212 (e.g., any of silicon interconnects 122, medium-power dies 124 (such as SOCs, logic devices, memory), LSIO dies 126, cache dies 12, or combinations thereof) that are bonded to the intermediate layer interposer 112 using a plurality of ultra-fine µbumps 152. Thus, the first-level dies 212 may be side-on bonded to the intermediate layer interposer 112 (e.g., landing pads utilizing a back-of-process (BEOL) stacking structure of the component). Alternatively, any of the first-stage dies may be back-side-up bonded to the intermediate layer interposer 112 (e.g., having a back-side oxide bonding layer on the back side of the silicon body layer 147 of the component, or having an adhesive layer). The various first-stage dies 212 in the first package stage may have the same or different thicknesses. For example, a thinner first-stage die 212 may not have vias for vertical interconnects.

[0044] The second package level 140 may similarly include one or more second-level dies 222 (e.g., high-power die 142 (e.g., logic die such as a GPU or CPU), high-power (performance) die 144 (logic die such as a GPU or CPU), HSIO die 146, memory die stack 153), which utilizes a plurality of ultrafine µbumps 152 to bond to the intermediate layer interpolator 112. Each first-level die 212 and second-level die 222 may include a BEOL stack structure. Each BEOL stack structure may include one or more dielectric layers, metal wiring layers (such as copper), and landing pads for receiving ultrafine µbumps 152. It should be understood that the first-level die 212 and second-level die 222 are not limited to these specific examples. BEOL stack structures of various dies may be formed over a silicon host layer 147, which may contain a plurality of devices 149 formed in a particular process node. For example, device 149 may include transistors for active devices and memory devices such as SRAM / DRAM / MRAM (or other technologies) for cache dies. Device 149 may also be formed within a silicon interconnect die and include both passive devices (including trench capacitors) and active devices.

[0045] According to the implementation scheme, the various components in the first and second package levels can be monolithic or stacked dies. For example, memory or other types of components can have stacked dies.

[0046] The metal wiring layers of the silicon interconnect can form die-to-die wiring 192 for interconnection between multiple dies. A complete die-to-die routing path may extend through a portion of the intermediate layer interposer via an assembly of vias 118 (and wiring layers within the top-side routing layer 115 and / or the back-side routing layer 105) and connect to the die-to-die wiring 192. For example, suitable damascene processing can be used to fabricate wiring within a BEOL stack structure. One or more of the first-stage dies 212 in the first package stage 120 may include vias 190 extending at least from the back side into their BEOL stack structure. For example, vias 190 can be used for power delivery, for example, to stacked dies.

[0047] The intermediate layer interposer 112 according to the embodiment may include a body layer 111 (such as silicon, glass, or a dielectric material with high thermal conductivity), a top-side routing layer 115, and an optional back-side routing layer 105, including one or more dielectric layers 116 and metal wiring layers 114, as well as landing pads. Although not illustrated in detail, various metal wiring layers 114 can be formed using conventional damascene or thin-film deposition techniques, and the various levels of the metal wiring layers can be connected to vias extending through one or more dielectric layers 116 (interlayer dielectrics) between the metal wiring layers. Alternatively, the metal routing layers may be absent, having only vias extending through one or more dielectric layers 116, and optional landing pads for receiving ultra-fine µ bumps.

[0048] It should be understood that while an embodiment has been described with respect to the silicon body layer 111, the body layer may be formed of other non-silicon materials, including glass, silicon carbide, and other compound semiconductors. A reconfigurable interpolator, including an embedded device, is also described. Additionally, the intermediate layer interpolator 112 may be active or passive. A plurality of vias 118 (e.g., silicon vias, glass vias, dielectric vias, die vias, etc.) may extend through the body layer 111 and optionally into either the top-side routing layer 115 and / or the back-side routing layer 105. The intermediate layer interpolator 112 may further include a plurality of devices 113, including passive devices such as MIM capacitors (planar or 3D) or trench capacitors, magnetic elements (inductors, coupling inductors, etc.), or even active devices such as transistors. In an embodiment, the intermediate layer interpolator includes an array of trench capacitors.

[0049] Dies / components within the second packaging level 140 may be embedded / encapsulated within an encapsulation layer 148, such as inorganic encapsulation / filling layer materials (e.g., dielectric / oxide or silicon) or organic molding compound layer materials (e.g., molding compound materials). Silicon encapsulation layer materials or gap-filling materials may be used where no vertical interconnects pass through. Metals may also be used to facilitate heat transfer. Similarly, components within the first packaging level 120 may be embedded / encapsulated within an encapsulation layer 130, such as inorganic encapsulation layer materials (e.g., oxides, oxynitrides, silicon) or organic molding compound layer materials. A plurality of vias 132 (e.g., dielectric vias) may extend completely through the thickness of the encapsulation layer 130 and laterally adjacent to components to provide electrical connections within intercalators 112 in the intermediate layer, such as vias 118 (through-silicon vias, glass vias, etc.). A back-side redistribution layer (RDL) 125 may optionally be formed beneath the encapsulation layer 130. The backside RDL 125 may include contact pads formed on vias 132 and 190. The backside RDL 125 may include one or more dielectric layers 195 and a metal routing layer 196, as well as landing pads for receiving solder bumps 101. The metal routing layer 196 may be formed using thin-film technology or alternatively using a damascene process.

[0050] See now Figure 5 Examples similar to Figure 4The 3D system 110 has several variations. First, either a first-level die or a second-level die, specifically a second-level die 222, may include multiple die stacks, such as active dies 222A, 222B, and 22C. The stacked dies 222A, 222B, and 222C may be ultra-fine µ-bumped, hybrid-bonded, and may employ different technologies. A second variation is a memory die stack 153, which illustrates a second-level die formed by die stacking rather than a monolithic die. The dies in the memory die stack may be ultra-fine µ-bumped, hybrid-bonded, or wire-bonded, and may be encapsulated within a molding compound as part of a sub-package. For example, the memory die stack 153 may be high-bandwidth memory (HBM) or dynamic random-access memory (DRAM). While a memory die stack 153 is illustrated, it should be understood that this is exemplary and components having stacked dies are not limited to memory. Additionally, a first-stage die 212 (e.g., a silicon interconnect) with die-to-die wiring 192 is shown. The silicon interconnect can be a chiplet and can be purely passive or active, and may additionally include passive components such as capacitors, inductors, etc. Furthermore, the silicon interconnect can be a monolithic die or a stacked die (stacked chiplet) structure. The intermediate layer interpolator 112 according to the embodiment can facilitate the stacking of complementary metal-oxide-semiconductor (CMOS) or memory dies and individual CMOS dies (e.g., high-performance and thermally confined dies) in the second package stage 140. Furthermore, integrating active devices in the intermediate layer interpolator 112 can be used to actively reduce the footprint of the 3D system 110 (i.e., the package).

[0051] See now Figure 6A schematic cross-sectional side view is provided illustrating a second package level 140 formed on a partially formed intermediate layer interposer according to an embodiment. It should be understood that, at this point, the manufacturing sequence may be at the wafer or panel level before being diced into multiple 3D IC systems. Depending on the material, various substrate sizes and shapes can be used, not limited to the wafer or panel level. As shown, the partially formed intermediate layer interposer may include a body layer 111, such as a host silicon substrate, glass, polymer, or a material having a higher thermal conductivity than silicon, such as silicon carbide. Optionally, a plurality of devices 113 and a top-side routing layer 115 may be formed. A plurality of vias 118 may be formed before, during, or after the formation of the top-side routing layer 115, and therefore may extend into or not extend into the top-side routing layer 115. As shown, the plurality of vias 118 do not need to extend completely through the body layer 111, which may be, for example, a silicon wafer that is later thinned. The vias 118 may be nanovias, microvias, etc. It should be understood that during this manufacturing stage, the components are at the wafer level or panel level before the individual packages or 3D system 110 are cut. For example, the host layer 111 can be a wafer (e.g., a semiconductor wafer, glass, or other material), and a panel such as a glass panel, or other materials such as polymers, composites, ceramics, etc. Various substrate sizes and shapes can be used, and are not limited to the wafer level or panel level.

[0052] The second packaging level 140 can be formed above the top-side routing layer 115 by flip-chip mounting the second-stage die 222 using ultra-fine µ-bumps 152, optionally applying an underfill material 154 below the second-stage die 222 and around the ultra-fine µ-bumps 152, followed by encapsulation using an encapsulation layer 148. At this point, the structure can be flipped, and the body layer 111 can be thinned using suitable techniques (such as polishing and / or laser lift-off) to expose the vias 118. (Refer to previous section) Figures 4 to 5 The back-side routing layer 105 can then be optionally formed, followed by mounting the first-stage die 212, such as via flip-chip mounting utilizing ultra-fine µ-bumps 152. This can then optionally be encapsulated with an encapsulation layer 130, and vias 132 can be formed, which may be, for example, copper pillars formed before the encapsulation layer, or die vias formed after the encapsulation layer 130. The back-side RDL 125 can then optionally be formed, followed by optionally placing solder bumps 101 and dicing into multiple 3D systems (e.g., packages, which may include system-in-package and package-out-of-package stack-up structures).

[0053] Figure 7 This is a schematic cross-sectional side view illustrating a 3D system with an intermediate layer interpolator 112 and a main layer removed, according to the implementation scheme. (See above regarding...) Figure 6 As described, when the main body layer 111 is thinned, in Figure 7In the illustrated implementation, the body layer 111 can be completely removed. Optionally, a back routing layer 105 can then be formed, followed by the formation of the first package level 120. The back routing layer 105 is not required, and the front routing layer 115 may comprise a single metal wiring layer with one or more dielectric layers, multiple metal wiring layers and dielectric layers, or simply vias extending through one or more dielectric layers and optional landing pads. In such implementations, vias 118 can be avoided, reducing cost and potential barriers to via density. In this way, the vertical connections via the intermediate layer interposer 112 can be the via / via patterning common in CMOS BEOL fabrication and / or thin-film RDL technology.

[0054] See now Figures 8 to 9 A schematic cross-sectional side view of a 3D system having an intermediate layer interpolator and a non-encapsulated first packaging level, according to an embodiment, is provided. Figures 8 to 9 They are basically similar, one difference being Figure 9 The intermediate layer interpolator includes active or passive devices 113, while Figure 8 Intermediate layer interpolators are primarily used for routing purposes, although they may include thermal and mechanical functionality. Figures 8 to 9 The 3D system can be manufactured similarly to the previous implementation, except that after mounting the first-stage die 212, instead of encapsulation, a high solder bump 101 or a pillar with solder tips is positioned laterally adjacent to the first-stage die 212. This configuration reduces manufacturing costs and processing time. Additionally, the first-stage die 212 may optionally not include vias. This increases wiring constraints but further reduces costs. Furthermore, one of a plurality of first-stage dies 212 (e.g., chiplets, silicon interconnects, stacks) can support through-silicon vias (TSVs) and under-bump metal (UBM) landing pads, as well as solder bumps 101A (flip chips or ball grid arrays). The height of the flip chip or ball grid array solder bump can be smaller than the regular solder bump 101 to accommodate the height of the first-stage die 212. The silicon interconnect can be a chiplet and can be purely passive or active, and may additionally include passive components such as capacitors, inductors, etc. In addition, silicon interconnects can be monolithic dies or stacked dies (stacked chiplets) structures.

[0055] Intermediate layer interposers, according to the implementation scheme, can provide mechanical, thermal, and routing integrity to 3D systems. In some implementations, integrating more metal wiring layers within the intermediate layer interposer can support mechanical integrity, wiring fan-out, and complex wiring requirements. In some cases, the intermediate layer interposer can provide die-to-die wiring connections. Dies within the 3D system can also provide die-to-die connections, which can reduce the requirements for the number of metal layers in the intermediate layer interposer, as well as wiring width / spacing and even dielectric material requirements.

[0056] Figure 10 This is a schematic top-down layout view of a 3D system with a die-to-die route through the first-stage die 212, according to an embodiment. As shown, the first-stage die 212 (such as silicon interconnects) can facilitate lateral interconnects between input / output regions 221 of the second-stage die 222, which can be located along the die edge 223 and further inward, such as within the die core (logic) region. Each interconnect can be a chiplet and can be purely passive or active, and can additionally include passive components such as capacitors, inductors, etc. Furthermore, the silicon interconnects can be monolithic or stacked die (stacked chiplets) structures.

[0057] The intermediate layer interposer 112 according to the embodiment may still include die-to-die routing, where there are potential limitations on the density of vias 118 in the intermediate layer interposer 112. When using dies from another die level to provide the lateral portion of the die-to-die connection, the density of vias 118 may be increased and / or the number of metal wiring layers in the intermediate layer interposer 112 may be reduced. For example, for a 12µm × 12µm ultra-fine µ-bump pitch, the via density percentage may range from 1% to 5% of the area of ​​the intermediate layer interposer 112, where the via diameter is between 1µm and 3µm, and the intermediate layer interposer thickness is between 10µm and 30µm. For a 6µm × 6µm ultra-fine µ-bump pitch, the via density percentage may range from 1% to 8% of the area of ​​the intermediate layer interposer 112, where the via diameter is between 0.5µm and 2µm, and the intermediate layer interposer thickness is between 5µm and 20µm.

[0058] The 3D system according to the implementation plan can be further designed to manage heat dissipation from the die, specifically a high-performance die within the second packaging level.

[0059] Figure 11This is a schematic top view of a 3D system with a heat spreader according to an embodiment. As shown, the heat spreader 180 can be attached to a second packaging level 140, and specifically to one or more of the second-level dies 222, to dissipate / absorb heat generated by the die. The heat spreader 180 can be, for example, a carrier substrate, or another layer with the same dimensions as the diced 3D system. The heat spreader 180 can be formed of various thermally conductive materials, including metals, aluminum nitride, silicon, etc. In an embodiment, the heat spreader is formed of a silicon substrate having sufficient thermal conductivity to draw heat away from the die and a coefficient of thermal expansion (CTE) compatible with the chip material. The heat spreader can be bonded to an underlying structure using a bonding layer, which can be a thin oxide, metal, solder, etc. In an embodiment, the heat spreader is bonded to the underlying structure using oxide-oxide bonding of the bonding layer. In another embodiment, the thermal cap is bonded to the underlying structure using metallic bonding, such as transient liquid phase (TLP) bonding (where one or more intermetallic compounds are formed through the mutual diffusion of the bonding layers) . The thermal cap 180 can be cut along with the 3D system as part of a remodeling fabrication sequence (e.g., when also used as a carrier substrate during the remodeling sequence), or even applied later as a separate component.

[0060] The heat-cap 180 can also be bonded to specific dies, such as... Figure 12 The second-stage die 222 shown can generate a significant amount of heat, such as a high-performance die. In this way, thermal benefits can be achieved at a reduced manufacturing / material cost. Thermal assistance can also be integrated into the intermediate layer interposer 112. Figure 13 This is a schematic top view of a 3D system with a thermally enhanced intermediate layer interpolator according to an embodiment. For example, the body layer 111 of the intermediate layer interpolator 112 may be formed of a material having a higher thermal conductivity than silicon. For example, silicon carbide, composite materials, or other materials may be used as the body layer 111 and processed similarly to those previously described. Silicon carbide may additionally provide sufficient thermal expansion matching with silicon while also providing thermal diffusion for the 3D system.

[0061] The material selection for the intercalator in the intermediate layer, and specifically for the body layer 111, can be based on considerations other than thermal. For example, the glass body layer 111 can be used to provide a lower parasitic via 118. Low CTE (e.g., below 4) polymers can also be used, and composite materials (e.g., including silica) can be used to tune mechanical, thermal, and electrical properties.

[0062] Integrating the intermediate layer interpolator 112 into a 3D system for reconstructing manufacturing sequences and slicing can also be compatible with monolithic die assembly repair. Figure 15A This is a schematic flowchart illustrating the repair option processing flow according to the implementation plan. Figure 15BThis is a schematic cross-sectional side view illustration of a monolithic die assembly with pre-formed die-to-die routing according to the implementation scheme. See also Figures 15A to 15B A die assembly of two or more dies may be bonded together with a die-to-die route 145 formed in a BEOL stack structure 143, which is formed above a host layer 147 (such as a silicon substrate). The die-to-die route 145 may be formed in a metal wiring layer 107 of the BEOL stack structure 143 and may optionally extend through or over a metal sealing structure 141 (e.g., a sealing ring) surrounding die regions 103A, 103B of adjacent die assemblies. As shown, each die may include a device for communicating across the die-to-die route 145, such as a transceiver 187 and a receiver 188.

[0063] Figure 14 This is a schematic cross-sectional side view illustrating a 3D system with a reconfigurable intermediate layer interpolator 112 according to an embodiment, the reconfigured intermediate layer interpolator including discrete integrated components 119 embedded in a gap-filling material. For example, integrated components 119 may be integrated passive devices, optical components / structures, etc. In such embodiments, the body layer 111 may be a gap-filling material, such as a molding compound (organic), oxide, oxynitride, silicon, or other inorganic material. Such organization balances the functionality and cost of system components. As shown, the top-side routing layer 115 and the back-side routing layer 105 are optional. Through-holes 118 (e.g., through-silicon vias, through-glass vias, dielectric vias, molded vias, etc.) may additionally extend through the body layer / gap-filling material to support circuitry. As previously described, the top-side routing layer 115 and the back-side routing layer 105 are optional and allow direct electrical connections from various package levels to the integrated components 119.

[0064] See Figure 15A The die assembly can be tested across the wafer before slicing to ensure functionality is within design limits. In the event of a defective die, adjacent dies in the die assembly can be scribed along the slicing line between dies. This can also proceed through pre-existing die-to-die routing, which is now exposed along the die edges. In such a repair sequence, depending on the implementation, the diced, operable dies can then be integrated with the intermediate layer interpolator 112.

[0065] Figures 16 to 17 This is a schematic cross-sectional side view illustration of a scribing die assembly with pre-formed and scribing die-to-die routes mounted on an intermediate layer inserter, according to an embodiment. Figure 16In the illustrated embodiment, the die, or the illustrated second-stage die 222, can be flip-chip mounted onto the bonding pads of the intermediate layer interposer 112 using multiple ultra-fine µ-bumps 152. The second-stage die 222 can then optionally be die-to-die wiring connected to the metal wiring layer 114 of the intermediate layer interposer 112. Figure 22 In the illustrated embodiment, the second-stage die 222 may be connected to a die-to-die wiring 192 within the first-stage die 212 (such as a silicon interconnect / chiplet), which is bonded to the bottom side of the intermediate layer interposer 112 and connected to the second-stage die via one or more metal wiring layers 114. The silicon interconnect may be a chiplet and may be purely passive or active, and may additionally include passive components such as capacitors, inductors, etc. Furthermore, the silicon interconnect may be a monolithic die or a stacked die (stacked chiplet) structure. It should be understood that... Figures 16 to 17 The illustrated embodiments are compatible with the previously illustrated and described embodiments, and certain structural features are not shown in order to more clearly illustrate the die-to-die connection.

[0066] Various 3D systems and assembly techniques have been described to date, among which ultrafine µ-bumping technology can be used to achieve fine bump pitch across multiple package levels. These 3D systems and assembly techniques are also compatible with electromagnetic field communication structures such as capacitive, magnetic, or photonic coupling for communication across dielectric layers or even thin metal layers. Photonic coupling can include, for example, photonic waveguides or photonic leads, as well as electro-optic (EO) converters and optoelectronic (OE) converters. Such electromagnetic field communication structures can also be integrated with ultrafine µ-bumping. EO converters can include conversion electronics and any suitable optical transmitter, such as lasers, light-emitting diodes or other light sources, modulators, etc. OE converters can include optical receivers, such as photodetectors (avalanche photodiodes, pin photodiodes, etc.) and conversion electronics. One or more optical repeater structures can be additionally included in the optical path to receive, amplify, and then retransmit optical signals. One example is an optical amplifier (e.g., a semiconductor optical amplifier). Other repeaters can be electro-optical and can be integrated into active silicon connected to optical paths with various features, such as logic components, flip-flops, caches, memory compressors and decompressors, controllers, local processing elements, etc. OE / EO converters may also include optical multiplexers and demultiplexers.

[0067] The die described herein may further comprise components of different parts, may be heterogeneous, and may be arranged in layers. For example, the die may include a separately formed optical converter layer, or multiple attachment components.

[0068] The optical path generated by the waveguide or photonic wire bonding can be rigid or flexible. In an exemplary embodiment, the waveguide is formed of a suitable material (such as an oxide or nitride) that is easy to integrate into semiconductor device fabrication and packaging. For example, the waveguide may be integrated into the top-side routing layer 115 and / or the back-side routing layer 105 of the intermediate layer interpolator 112. Optical vias, grating couplers, mirrors, prisms, or additional waveguide or photonic wire bonding elements can be used to further negotiate vertical photonic communication (such as across ultrafine µ-bumped surfaces).

[0069] See now Figures 18 to 23 A schematic cross-sectional side view of an exemplary 3D system within an optical interconnect according to an embodiment is provided. The 3D system structure may correspond to the 3D system structure previously described herein, and therefore, the illustrative details focus on the optical interconnect structure rather than the common shared features previously described herein.

[0070] Figure 18 The specific implementation scheme illustrated may be similar to, for example, regarding... Figures 4 to 5 The embodiments illustrated and described include a first package level 120 having one or more first-level dies 212 (e.g., any of silicon interconnect 122, medium-power die 124, LSIO die 126, cache die 128, or combinations thereof) and a second package level 140 having one or more second-level dies 222 (e.g., any of high-power die 142, high-power die 144, HSIO die 146, memory die stack 153). It should be understood that the first-level dies 212 and the second-level dies 222 are not limited to these specific examples. To avoid obscuring the subject of optical paths, the illustrated details focus on the optical interconnect structures rather than the common shared features that may be included as previously described herein.

[0071] In the illustrated specific embodiment, the optical path is entirely contained within the intermediate layer interposer 112 and connects multiple second-stage dies 222. Similarly, the optical path may connect multiple first-stage dies 212. In an exemplary embodiment, the various second-stage dies 222 may include transceivers (Tx) 224 and receivers (Rx) 225, which may be electrically connected to the landing pads 186 of the second-stage dies 222. Similar to the previously described process flow, one or more second-stage dies 222 may be encapsulated in an encapsulation layer 148, wherein the landing pads 186 are aligned with the landing pads 117 of the intermediate layer interposer 112. The first-stage dies 212 may also be ultra-fine µ-bumped to the back-side routing layer 105 and / or the vias 118 of the intermediate layer interposer 112. In the illustrated implementation, Tx 224 / Rx 225 and Rx 225 / Tx 224 are in electrical communication with the optical transducers (and more specifically, electro-optical (EO) transducers 203 and optoelectronic (OE) transducers 204) in the intermediate layer interpolator 112. One or more optical interconnects 206 (e.g., waveguides, photonic leads) within the top-side routing layer 115 can then be connected to adjacent optical transducers to provide an optical path. Such optical paths can provide short or long-distance communication and are not limited to die-edge connections, but can provide core-to-core connections between dies or between opposite edges. Various configurations are possible. In some implementations, one or more repeaters 209 may be included along the optical path and connected to the optical interconnects 206 to receive, amplify, and then retransmit optical signals. In an exemplary configuration, Tx 224 may be electrically connected to EO converter 203, which converts an electrical signal into an optical signal. This optical signal is then passed across optical interconnect 206 (e.g., waveguide, photonic lead) to OE converter 204, which transmits the optical signal to an electrical signal, which is then electrically connected to Rx 225 in a separate second-stage die 222. A complementary system is also in place for reverse communication between the second-stage dies 222.

[0072] It should be understood that although die-to-die connections are illustrated and described as connecting multiple second-stage dies 222 via intermediate layer interpolators 112, die-to-die connections can exist between multiple first-stage dies 212. Furthermore, although waveguides are used to describe the optical communication path as optical interconnects 206, this can be replaced by another suitable optical interconnect (such as photonic leads wire-bonded to corresponding EO and OE converters).

[0073] Figure 18The diagram also illustrates optical paths that can enter from the interlayer interposer 112 and the 3D system. As shown, the interlayer interposer may include exposed optical interconnects 206 along the edges of the interlayer interposer to receive light from outside the 3D system or transmit light outward from the 3D system. While this is shown with respect to the lateral side edges, it could also be the top or bottom. For example, light can be transmitted from outside the 3D system and received by optical interconnects 206 (e.g., waveguides, photonic leads) connected to OE converter 204. OE converter 204 may optionally be connected to a receiver 225 in any die mounted into the interlayer interposer 112, or connected to a receiver within the interlayer interposer. Complementary structures for transceiver 224, OE converter 203, and optical interconnects 206 are also shown for transmitting light outward from the interlayer interposer 112 and the 3D system. The arrangement of the transceiver / receiver and converter can be between any combination of dies and / or interlayer interposers.

[0074] See now Figure 19 It provides similar Figure 18 A schematic cross-sectional side view illustrating the 3D system structure of optical interconnects. Figure 18 same, Figure 19 Similar to Figure 5 The structure is described below. To avoid obscuring the main subject of the optical path, the illustrative details focus on the optical interconnect structure rather than the common shared features that may be included as previously described herein. In a particular embodiment, the EO converter 203 and OE converter 204 may be positioned together with the second-stage die 222, while the optical interconnect 206 (waveguide or photonic lead) is located in the intermediate layer interposer 112. Furthermore, an optical via 211 may optionally extend through any or all layers between the converter and the optical interconnect 206 to facilitate the optical path. For example, the optical via may be filled with a transparent material of a specific refractive index.

[0075] As shown in the figures, according to the various embodiments described herein, a die may include multiple three-dimensional (3D) stacked dies (e.g., 222A, 222B, 222C, etc.). Although three dies are illustrated, it should be understood that this is exemplary and embodiments may include two or more stacked dies. According to embodiments, optical vias 211 may extend through one or more dies in the die, which may also be electrically connected to TSVs, contact pads, etc. In the illustrated embodiments, optical paths (e.g., through one or more optical vias 211) may advance through one or more stacked dies in the stacked die set. Each die (or chiplet) may resemble a die as defined herein, and the 3D stack may be fused, TCB, hybrid bonded, or bonded with ultra-fine µbumps. In this way, optical paths (and optical interconnects) may extend to any die within the 3D stack. It should be understood that the illustrated examples of multiple stacked dies are exemplary, and embodiments do not require multiple stacked dies within a die set.

[0076] Optical paths can connect all the dies (222A, 222B, 222C) or some arrangements thereof (e.g., 222A and 222C or 222C as shown in the figure). Furthermore, depending on the EO / OE, waveguide, and wavelength, the optical paths can be shared or separate. See brief description. Figure 24 A schematic cross-sectional side view of a second-stage die 222, comprising multiple EO converters 203, OE converters 204, and optical vias 211, is provided according to an embodiment. In this manner, each die may include a corresponding transceiver and / or receiver, as well as a converter. The illustrated optical vias 211 may be single or multiple, as shown. Optical vias 211 may be bidirectional (for optical transmission and reception) or unidirectional. Arrays of optical vias 211 may be included to support communication with different wavelengths and / or to different dies. For example, optical vias 211 may connect dies 222B and 222C, and connect one or more dies to an intermediate layer interposer 112 or to one or more first-stage dies.

[0077] One or more mirrors 208, diffraction grating couplers, prisms, etc., can also facilitate the connection of the vertical optical path to the optical interconnect 206. In this way, the optical path can travel from the EO converter 203 through an optional optical via 211 (or other intermediate dielectric / insulating layer), through the optical interconnect 206 (waveguide or photonic lead), return through the optional optical via (or other intermediate dielectric / insulating layer), and reach the OE converter 204 located in a separate die. See also Figure 20One or more optical vias 211 may also extend at least partially through the intermediate layer interposer 112 to connect to one or more first-stage dies 212. For example, the optical via 211 may extend through any of the body layer 111, the top-side routing layer 115, and the back-side routing layer 105. In the illustrated embodiment, an optical path may connect the second-stage die 222 to the first-stage die 212.

[0078] See now Figures 21 to 22 It provides similar Figures 18 to 19 A schematic cross-sectional side view illustrating a 3D system of optical interconnects is shown, where the EO and OE converters are positioned differently. Figures 18 to 19 same, Figures 21 to 22 Similar to Figures 4 to 5 The structure. To avoid obscuring the subject of the optical path, the illustrative details focus on the optical interconnect structure rather than the common shared features that may be included as previously described herein. In such embodiments, the optical path can be much shorter, thereby effectively bridging the package level and the intermediate layer interposer 112 (e.g., Figure 21 (as shown) or between dies in different package levels (such as Figure 22 The vertical distance (as shown). The optical path can also extend through one or more dies 222A, 222B, 222C, etc., as previously mentioned. Figure 19 and Figure 24 As described. In Figure 22 In the illustrated embodiment, the optical path can advance through an optical via 211 that extends fully through the intermediate intercalator 112.

[0079] See now Figure 23 It provides similar Figure 18 A schematic cross-sectional side view illustrating the 3D system structure of the optical interconnects is shown, wherein different connections exist between the die and the intermediate layer interposer. Figure 18 same, Figure 23 Similar to Figures 4 to 5 The structure is described below. To avoid obscuring the subject of the optical path, the illustrative details focus on the optical interconnect structure rather than the common shared features that may be included as previously described herein. In such embodiments, various electromagnetic field communication structures with capacitive coupling, magnetic coupling, and optical coupling can be used to achieve short-range communication paths (e.g., less than 100µm (magnetic, and less than 1µm capacitive coupling)). For example, electromagnetic field communication structure 214 may include coils or capacitors to facilitate coupling and may be vertically aligned. Electromagnetic field communication structure 214 can wirelessly communicate between the second-stage die 222 and the intermediate layer interposer 112. Electromagnetic field communication structure 214 within the intermediate layer interposer 112 can be further connected to the EO converter 203 and the OE converter 204, wherein the optical interconnect 206 connects the converters.

[0080] It should be understood that, although Figures 18 to 23 The implementation scheme is illustrated as a standalone 3D system architecture, but various optical interconnects can be combined. Furthermore, Figures 18 to 23 The optical interconnects can also be combined with the metal wiring paths described herein. Furthermore, dies within various package levels can include multiple 3D stacked dies.

[0081] The intermediate layer interposer 112 according to the embodiments may include electrical routing and passive and / or active devices. In some embodiments, the intermediate layer interposer 112 may include a library of passive devices such as trench capacitors or MIM capacitors. However, connecting all capacitors and capacitor libraries may not be suitable for all applications or in the case of defective devices. According to the embodiments, the intermediate layer interposer may include customized routing and connectivity to the device.

[0082] In the following description, various intermediate layer interpolators 112 can be used for repair options. Specifically, the following description and examples can be used for decoupling capacitor repair. This concept can also be used to repair various routing paths, memory blocks, circuit blocks, etc.

[0083] Figures 25A to 25B This is a schematic cross-sectional side view illustrating a sequence of deep trench capacitor banks used for testing and connecting intermediate layer interpolators according to an implementation scheme. Figure 25A As shown, the top-side routing layer 115 (or the back-side routing layer 105) is partially fabricated to include device 113 (deep trench capacitor) as well as dielectric layer 116 and metal wiring layer 114. At this stage, the device can be tested in-line. A good device 113 can be electrically connected to via 199, and via 199 may optionally not be formed as a connection defect device 113X (including passive devices such as MIM capacitors (planar or 3D) or trench capacitors, magnetic components, or even active devices such as transistors), such as... Figure 25B As shown. Therefore, the intermediate layer interposer may include a dielectric layer 116 within the top routing layer 115 (or the back routing layer 105), wherein the via 199 is connected only to some devices in device 113. Thus, defective device 113X may remain floating or electrically isolated.

[0084] exist Figure 26 A similar embodiment is shown, in which device 113 is a MIM capacitor, including a lower terminal 242 (plate), an upper terminal 244 (plate), and a high-dielectric-constant dielectric material 246 therebetween. The lower terminal 242 and upper terminal 244 may be formed by a metal wiring layer 114. The dielectric material 246 may have a higher dielectric constant than the dielectric layer 116 forming the top-side routing layer 115 (or the back-side routing layer 105).

[0085] See still Figure 26 The via 199 is optionally connected to one of the terminals of the defective device 113X. This can also be... Figure 25B This is the case with trench capacitors. For example, this could be a low-power (Vss) connection. However, a high-power (Vdd) connection might not be made through via 199 to the defective device 113X.

[0086] Programmable writing can be used to connect appropriate vias 199 or provide open-circuit wiring. Although Figures 25A to 25B and Figure 26 Shown on a device scale, but programmable writes can be used to connect or alternatively mask the entire device library. Figure 27A This is a schematic top view illustrating the via 199 connection to device 113 within the intermediate layer interposer according to an embodiment. As shown, individual devices 113 can be arranged as groups of libraries 240. In the case of identifying a defective device 113X, the entire masking library 240X can be specified. For example, in the case of measuring a single defective device 113X, the via 199 connection can be skipped for the entire associated masking library 240X. Alternatively, the measurement may be less precise, and testing may be performed at the library level, and thus a defective library can be measured, indicating one or more defective devices 113X within the masking library 240X. In an embodiment, the intermediate layer interposer 112 may include a plurality of libraries 240, including one or more masking libraries 240X, which comprise arrays of capacitors that are not electrically connected or are not fully connected, such as those with only Vss via 199 connections.

[0087] Figure 27B This is a schematic top view illustrating the landing pad connection to the capacitor library according to the implementation scheme. Therefore, Figure 27B An intermediate layer interpolator 112 is illustrated further along the manufacturing sequence. As shown, landing pads 117 can still be formed for each library 240 and mask library 240X. This can facilitate further metal-to-metal bonding. For example, the two illustrated connection pads 117 can be used for low-power (Vss) and high-power (Vdd) connections. The mask library may include one or more dummy landing pads 117D that are not connected to capacitors. For example, dummy landing pads can be used for both Vss and Vdd connections, or only for Vdd connections in an exemplary embodiment. The implementation is not limited to two landing pads 117, and this is merely exemplary. According to an embodiment, the dummy landing pads 117D of the mask library 240X may cover the array of capacitors that are not electrically connected or not fully connected to the corresponding landing pads 117 of the mask library.

[0088] When utilizing the various aspects of the embodiments, it will become apparent to those skilled in the art that combinations or variations of the above embodiments are possible for forming a 3D system with intermediate layer interpolators. Although the embodiments have been described in language specific to structural features and / or methodological behavior, it should be understood that the appended claims are not necessarily limited to the specific features or behaviors described. Rather, the specific features and behaviors disclosed should be understood as embodiments of the claims for illustrative purposes.

Claims

1. A three-dimensional (3D) system, said three-dimensional (3D) system comprising: Intermediate layer interpolator; A first packaging stage below the intermediate layer interposer, the first packaging stage including a first first-stage die bonded to the intermediate layer interposer using a first plurality of ultra-fine microbumps (µbumps); A second packaging stage above the intermediate layer interposer, the second packaging stage including a first second stage die bonded to the intermediate layer interposer using a second plurality of ultra-fine microµ bumps.

2. The 3D system according to claim 1, wherein the second plurality of ultrafine µbumps have a spacing of less than 15 µm.

3. The 3D system according to claim 2, wherein the second plurality of ultrafine µbumps have a spacing of less than 10 µm.

4. The 3D system of claim 2, further comprising a series of through-holes extending at least partially through the intermediate layer intercalator.

5. The 3D system of claim 2, wherein the interpolator comprises a main body layer and a top-side routing layer, and the first and second stage dies are bonded to the top-side routing layer.

6. The 3D system of claim 5, wherein the interpolator includes a back-side routing layer, and the first stage die is bonded to the back-side routing layer.

7. The 3D system of claim 6, wherein the intermediate layer interpolator comprises a capacitor array, a magnet element array, or both.

8. The 3D system of claim 6, wherein the intermediate layer interpolator comprises an active device.

9. The 3D system of claim 5, wherein the host layer is formed of a material characterized by a higher thermal conductivity than silicon.

10. The 3D system of claim 5, wherein the main body layer is glass.

11. The 3D system of claim 10, wherein the first stage die is a passive component.

12. The 3D system of claim 10, wherein the first and second stage dies are passive components.

13. The 3D system of claim 2, further comprising a second second-stage die bonded to the intermediate layer intercalator using a third plurality of ultra-fine microµ bumps.

14. The 3D system of claim 13, wherein the first first-stage die includes a portion of the die-to-die routing path between the first second-stage die and the second second-stage die.

15. The 3D system of claim 13, wherein the intermediate layer interpolator includes a die-to-die routing path between the first second-stage die and the second second-stage die.

16. The 3D system of claim 15, wherein the die-to-die routing path includes an optical path.

17. The 3D system according to claim 16, wherein: The intermediate layer interpolator includes an electro-optic (EO) converter electrically connected to the first and second stage dies and an opto-optic (OE) converter electrically connected to the second and second stage dies. and The EO converter is connected to a first electromagnetic field communication structure, and the first and second stage dies include a second electromagnetic field communication structure.

18. The 3D system of claim 17, wherein the first electromagnetic field communication structure and the second electromagnetic field communication structure are vertically aligned, and the first electromagnetic field communication structure and the second electromagnetic field communication structure are coils or capacitors.

19. The 3D system of claim 13, wherein the first and second stage dies comprise die-to-die routing paths of slices terminating along the die edge of the first and second stage dies.

20. The 3D system of claim 13, wherein the second stage die comprises a plurality of stacked dies.

21. The 3D system of claim 2, further comprising a second first-stage die bonded to the intermediate layer interpolator using a third plurality of ultra-fine microµ bumps, wherein the first second-stage die includes a portion of a die-to-die routing path between the first first-stage die and the second first-stage die.

22. The 3D system of claim 2, further comprising a thermal cap attached to the second packaging level.

23. The 3D system according to claim 2: The first-stage die or the intermediate layer interposer includes an optoelectronic (OE) converter, and the second-stage die includes an electro-optical (EO) converter; and The 3D system also includes an optical via, which optically connects the EO converter to the OE converter.

24. The 3D system according to claim 23, wherein: The first stage die includes the OE converter; and The optical via extends vertically through the intermediate interposer between the first-stage die and the second-stage die.

25. The 3D system of claim 23, wherein the second-stage die comprises a plurality of stacked dies, and the optical via extends through one or more of the plurality of stacked dies.

26. The 3D system of claim 25, wherein the intermediate layer interpolator includes the OE converter.

27. The 3D system of claim 2, wherein the intermediate layer interpolator comprises an electro-optical (EO) converter electrically connected to the first second-stage die, an optoelectronic (OE) converter electrically connected to the second second-stage die, and an optical interconnect connecting the EO converter and the OE converter.

28. The 3D system of claim 27, wherein the optical interconnect comprises a waveguide or a photonic lead.

29. The 3D system according to claim 2, wherein: The first and second stage dies include an electro-optical (EO) converter, and the second and second stage dies include an optoelectronic (OE) converter; and The intermediate layer interpolator includes optical interconnects that are optically connected to the EO converter and the OE converter.

30. The 3D system of claim 2, wherein the second plurality of ultrafine micro-µ bumps are characterized by a finer spacing than the first plurality of ultrafine micro-µ bumps.

31. The 3D system of claim 2, wherein the intermediate layer interpolator comprises one or more integrated components embedded within a gap-filling material.

32. The 3D system of claim 2, wherein the intermediate layer interpolator comprises a plurality of device libraries, wherein the plurality of device libraries includes a masking library having dummy landing pads not connected to devices in the masking library.

33. The 3D system of claim 2, wherein the intermediate layer interpolator includes exposed optical interconnects along the edge of the intermediate layer interpolator to receive light from outside the 3D system or to transmit light outward from the 3D system.

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