Nanosheet size design for power delivery

Abstract

Various structures that implement nanosheet transistors are disclosed. Various structures include nanosheet transistors having different widths inside the transistor device. Varying the width of the nanosheet transistor within the transistor device allows the input stage and the output stage of the transistor device to be differently designed, which can improve the power utilization and performance of the transistor device. In some cases, the input stage has a width of the nanosheet fins of the nanosheet transistor that is less than that of the nanosheet transistor in the output stage. The variation in the width of the nanosheet transistor may also be accomplished within the input stage or the output stage by the merging of the nanosheet fins.

Description

TECHNICAL FIELD

[0001] Embodiments described herein relate to transistor structures for semiconductor devices. More specifically, embodiments described herein relate to structures for nanosheet transistors in integrated circuit devices. BACKGROUND

[0002] Nanosheet (e.g., all-around gate) transistors are increasingly being used in integrated circuits. Nanosheet transistors can have more efficient turn-on / turn-off transistor characteristics than planar FETs or FinFETs due to the enhanced gate control of the channel provided by the geometry of the nanosheet transistor design. Higher efficiency in turning on or off transistors can reduce leakage and improve power utilization (e.g., voltage reduction) for integrated circuits that utilize nanosheet transistors. Nanosheet transistors can have more complex designs than planar FETs or FinFETs. As integrated circuit designs evolve, more approaches for utilizing more complex nanosheet transistor designs can be envisioned. BRIEF DESCRIPTION OF DRAWINGS

[0003] The features and advantages of the methods and apparatuses of the embodiments described in this disclosure will be more fully understood with reference to the following detailed description, when taken in conjunction with the accompanying drawings, in which: Figure 1 A perspective representation of a nanosheet transistor is depicted in accordance with some embodiments.

[0004] Figure 2 An end view representation of a channel region is depicted in accordance with some embodiments.

[0005] Figure 3 A top plan view representation of a standard cell layout with nanosheet transistors is depicted in accordance with some embodiments.

[0006] Figure 4 A top plan view representation of a layout of a transistor device with nanosheet transistors is depicted in accordance with some embodiments.

[0007] Figure 5 A top plan view representation of a layout of a transistor device with nanosheet transistors is depicted in accordance with some embodiments, the nanosheet transistors having merged nanosheet fins in an output stage.

[0008] Figure 6 A top plan view representation of a layout of a transistor device with nanosheet transistors is depicted in accordance with some embodiments, the nanosheet transistors having merged nanosheet fins in both an input stage and an output stage.

[0009] Figure 7This is a block diagram of one implementation of the example system.

[0010] While the embodiments disclosed herein are susceptible to various modifications and alternatives, specific embodiments of the invention are illustrated by way of example in the accompanying drawings and described in detail herein. However, it should be understood that the drawings and their detailed description are not intended to limit the scope of the claims to the specific forms disclosed. Rather, this application is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure of this application as defined by the appended claims. Detailed Implementation

[0011] As used herein, the term "standard cell" refers to a set of transistor structures, passive structures, and interconnect structures formed on a substrate to provide logic or memory functions for a variety of specific implementation standards. For example, a single standard cell may be one cell from a library of cells from which various suitable cells can be selected to implement a particular cell design. As another example, a standard cell may be a cell design that is created (e.g., designed) and then implemented multiple times to produce an integrated circuit device via, for example, a synthesis or automated process. Integrated circuit cells may also include custom circuit design cells designed separately for a specific implementation. Implementations of the circuit design cells described herein can be implemented in various specific implementations of logic integrated circuits or memory integrated circuits.

[0012] Figure 1 A perspective representation of a nanosheet transistor according to some embodiments is depicted. In the illustrated embodiments, a nanosheet transistor 100 is formed on a substrate 150. In some embodiments, the transistor 100 includes a gate 110 and a channel region 120. The gate 110 may be a polysilicon gate or a metal gate. The channel region 120 includes nanosheet fins 130 and a substrate channel 140. The nanosheet fins 130 are fins made of silicon, another semiconductor, or a combination of semiconductors, which pass through the structure (e.g., material) of the gate 110. In various embodiments, the nanosheet fins 130 are thin rectangular sheets of semiconductor material aligned parallel to the substrate 150 (e.g., the horizontal plane of the nanosheet fins 130 is parallel to the horizontal plane of the substrate 150). The transistor 100 typically includes a plurality of nanosheet fins 130 passing through the gate 110. For example, as Figure 1 As shown, transistor 100 includes three nanosheet fins 130 extending through gate 110.

[0013] In various embodiments, a substrate channel 140 is formed in a substrate 150 beneath the nanosheet fin 130. The substrate channel 140 can be formed by forming shallow trench isolation (STI) 145 on both sides of the substrate channel in the substrate 150. Thus, the substrate channel 140 is the portion of the substrate 150 between the STIs 145. In some embodiments, the substrate channel 140 is aligned with the nanosheet fin 130 and has similar horizontal dimensions (e.g., length or width) to the nanosheet fin. In some embodiments, the substrate channel 140 is made of the same semiconductor material as the nanosheet fin 130. For example, both the nanosheet fin 130 and the substrate channel 140 can be made of silicon.

[0014] Figure 2 An end view representation of a channel region 120 according to some embodiments is depicted. In the illustrated embodiment, the channel region 120 includes a nanosheet fin 130 inside a gate 110 above a substrate channel 140. In some embodiments, the gate 110 substantially surrounds (e.g., “fully surrounds”) the nanosheet fin 130. It should be noted that at least some kind of gate dielectric material (not shown) may be present between the nanosheet fin 130 and the gate 110. Surrounding the nanosheet fin 130 with the gate 110 provides better control over gate operation and reduces current leakage from the gate, resulting in more efficient characteristics for turning the gate on and off.

[0015] Figure 3 A top plan view representation of a standard cell layout with nanosheet transistors according to some embodiments is depicted. In the illustrated embodiments, the standard cell 300 includes active gate structures 310A to 310C and dummy (e.g., passive) gate structures 320A to 320B. In various embodiments, the active gate structures 310A to 310C and the dummy gate structures 320A to 320B are formed of the same material and are structurally similar. In such embodiments, the gate structure can be determined as "active" or "dummy" based on whether the gate is connected in the layout and design of the cell 300.

[0016] In some implementations, dummy gate structures 320A to 320B are implemented to define (e.g., isolate) structures in a cell or cell layout from other structures. For example, as Figure 3 As shown, the dummy gate structure 320A is placed at the left edge of cell 300 in the gate pitch direction 302 (e.g., the horizontal direction of the cell), and the dummy gate structure 320B is placed at the right edge of cell 300. Therefore, the dummy gate structures 320A to 320B isolate the active gate structures 310A to 310C from the cells or other structures located on the left and right sides of cell 300 in the gate pitch direction 302.

[0017] In various embodiments, the active gate structures 310A to 310C and the dummy gate structures 320A to 320B are fingers or lines of gate material extending (e.g., extending) across cell 300 in the cell height direction 304 (e.g., the vertical direction of the cell). Examples of gate materials include, but are not limited to, polysilicon or metal. In some embodiments, the gate material of the gate structures 310A to 310C may extend beyond the boundary of cell 300. For example, the gate structures 310A to 310C may include gate material extending in adjacent cells above or below cell 300 in the cell height direction 304.

[0018] In various embodiments, unit 300 includes channel regions 330A to 330B. In some embodiments, channel regions 330A to 330B include nanosheet fins 340A to 340B. Nanosheet fins 340A to 340B may include multiple stacked nanosheet fins, such as... Figure 1 and Figure 2 The nanosheet fin 130 is shown. Therefore, in Figure 3 In the top plan view, only the top nanosheet fins are shown as nanosheet fins 340A and nanosheet 340B. In various embodiments, such as Figure 3 As shown, nanosheet fins 340A to 340B extend across the width of cell 300 in the gate spacing direction 302. For example, nanosheet fins 340A to 340B extend between dummy gate structure 320A and dummy gate structure 320B.

[0019] In some embodiments, an active gate 350 (dashed box) is formed at the region where the nanosheet fins 340A to 340B (oriented in the gate pitch direction 302) intersect with the active gate structures 310A to 310C (oriented in the cell height direction 304). For example, in Figure 3 In the illustrated embodiment, active gates 350A to 350C are formed at the regions where nanosheet fins 340A intersect with active gate structures 310A to 310C, and active gates 350D to 350F are formed at the regions where nanosheet fins 340B intersect with active gate structures 310A to 310C. Therefore, cell 300 includes six active gates (gates 350A to 350F) within the boundaries of a standard cell. The active gates 350A to 350F may have... Figure 1 and Figure 2 The gate 110 shown has a similar structure.

[0020] In the current specific implementation of the standard unit (such as unit 300), the nanosheet fins 340A to 340B have the same horizontal width (e.g., a fixed width determined by the design and dimensions of the unit). For example, the width 342A of nanosheet fin 340A is approximately the same as the width 342B of nanosheet fin 340B. Note that widths 342A and 342B are... Figure 3 The example is shown vertically, but it is the horizontal width of the nanosheet fins (e.g., Figure 1 and Figure 2 (The horizontal width of the nanosheet fin 130 shown). In various embodiments, the transistor device based on cell 300 may have an input stage and an output stage. For example, as Figure 3 As shown, unit 300 may include an input stage 360 ​​and an output stage 370 (dashed box).

[0021] In cell 300, since the nanosheet fins 340A to 340B have the same width and the gates 350A to 350F all have substantially the same operating properties (e.g., drive current capacity, capacitance, and power), the different operating properties desired for the input stage 360 ​​and the output stage 370 can be achieved by selecting the number of gates used in the input and output stages. For example, in the illustrated embodiment of cell 300, the input stage 360 ​​includes two active gates (active gate 350A and active gate 350D), while the output stage 370 includes four active gates (active gate 350B, active gate 350C, active gate 350E, and active gate 350F). The output stage 370 has more active gates to achieve a larger drive output, while the input stage 360 ​​has fewer active gates to have lower capacitance in the input. Because the nanosheet fins 340 in cell 300 have substantially the same width, there may be limited flexibility in designing the input and output stages of the transistor device used for cell 300. For example, changes to the design of these stages can often only be achieved by varying the number of active gates in each stage.

[0022] This disclosure recognizes that by providing variations in the width of nanosheet fins on the transistors within a transistor device, additional design flexibility can be achieved, providing greater flexibility in the design of both the input and output stages of the transistor device. This greater flexibility improves power efficiency and performance compared to transistor devices with nanosheet transistors having the same width between each transistor. For example, the flexibility in the input / output stage design allows the transistor device to have greater current drive capability from the output stage to other devices, while having lower capacitance in the input stage (as viewed from other devices).

[0023] Some embodiments disclosed herein have four wide elements: 1) a plurality of gate structures oriented along a first direction; 2) a plurality of elongated channel regions oriented along a second direction, wherein the elongated channel regions include two or more stacked nanosheet fins; 3) an input stage including an elongated channel region having nanosheet fins having a first width along the first direction; and 4) an output stage including an elongated channel region having nanosheet fins having a second width along the first direction, the second width being greater than the first width. In some embodiments, the elongated channel region extends through the gate structure, wherein an active gate is located at the intersection of the nanosheet fin and the gate structure. In some embodiments, the input stage and the output stage are located in separate cells separated in the cell height direction, wherein the gate structure extends across both stages.

[0024] Various examples of embodiments having these wide elements are now described in this disclosure. It should be noted that the illustrated embodiments of this disclosure depict design templates for cells having various nanosheet transistors that can be implemented in the input and output stages of transistor devices. These design templates provide basic building blocks that can be used to construct many different types of devices based on the interconnection schemes of the transistors in the design templates. For example, simple devices (such as inverters, NAND devices, multiplexers (MUX)) and more complex devices (e.g., complex FETs) can be constructed based on the basic building blocks of this disclosure.

[0025] Figure 4 A top plan view depicting the layout of a transistor device with nanosheet transistors according to some embodiments is shown. In the illustrated embodiments, transistor device 400 is a device having a cell width as a standard cell width in the gate pitch direction 402 and a cell height reaching twice the standard cell height in the cell height direction 404 (e.g., 2 × standard cell heights 406A to 406B). In some embodiments, the standard cell height is the cell height accommodating two rows of channel regions and nanosheet transistor fins (e.g., two channel regions 430 having nanosheet fins 440).

[0026] In some embodiments, device 400 includes active gate structures 410A to 410B and dummy (e.g., passive) gate structures 420A to 420B. The dummy gate structures 420A to 420B define the edges of device 400 in the gate pitch direction 402 and isolate device 400 from other devices in the gate pitch direction, wherein dummy gate structure 420A defines the left edge and dummy gate structure 420B defines the right edge. In various embodiments, the active gate structures 410A to 410B and the dummy gate structures 420A to 420B are fingers or lines of gate material extending (e.g., extending) across device 400 in the cell height direction 404 (e.g., the vertical direction of the illustrated device). The gate material may be, for example, polysilicon or metal. In some embodiments, the gate material of gate structures 410A to 410B or dummy gate structures 420A to 420B may extend beyond the boundaries of device 400.

[0027] In some embodiments, device 400 is divided into an input stage 460 (as defined by standard cell height 406A) in the top portion of the device and an output stage 470 (as defined by standard cell height 406B) in the bottom portion of the device. This can be achieved... Figure 4 Various wirings in the layer above the structure shown define the connection between input stage 460 and output stage 470.

[0028] In some embodiments, input stage 460 includes channel regions 430A to 430B, while output stage 470 includes channel regions 430C to 430D. In various embodiments, channel regions 430A to 430B include nanosheet fins 440A to 440B, and channel regions 430C to 430D include nanosheet fins 440C to 440D. Each of the nanosheet fins 440A to 440D may include stacked nanosheet fins, such as... Figure 1 and Figure 2 The nanosheet fin 130 is shown. Nanosheet fins 440A to 440D extend across the width of device 400 in the gate spacing direction 402. For example, nanosheet fins 440A to 440D may extend between dummy gate structure 420A and dummy gate structure 420B.

[0029] In various embodiments, input stage 460 includes active gates 450A to 450D. Active gates 450A to 450D (dashed box) may be formed at the regions where nanosheet fins 440A to 440B (oriented in the gate pitch direction 402) intersect with active gate structures 410A to 410B (oriented in the cell height direction 404). For example, active gates 450A to 450B are formed at the regions where nanosheet fins 440A intersect with active gate structures 410A to 410B, while active gates 450C to 450D are formed at the regions where nanosheet fins 440B intersect with active gate structures 410A to 410B.

[0030] In various embodiments, output stage 470 includes active gates 450E to 450H. Active gates 450E to 450H (dashed boxes) may be formed at the regions where nanosheet fins 440C to 440D (oriented in the gate spacing direction 402) intersect with active gate structures 410A to 410B (oriented in the cell height direction 404). For example, active gates 450E to 450F are formed at the regions where nanosheet fins 440C intersect with active gate structures 410A to 410B, while active gates 450G to 450H are formed at the regions where nanosheet fins 440D intersect with active gate structures 410A to 410B. Therefore, both input stage 460 and output stage 470 may include the same number of active gates (e.g., four active gates each in device 400).

[0031] exist Figure 4In the illustrated embodiment, nanosheet fins 440A to 440B in input stage 460 have a width 442A, while nanosheet fins 440C to 440D in output stage 470 have a width 442B. In some embodiments, width 442A differs from width 442B. For example, width 442A may be smaller than width 442B, and nanosheet fins 440A to 440B are heterogeneous relative to nanosheet fins 440C to 440D. Variations in the width of nanosheet fins 440 between input stage 460 and output stage 470 can be achieved to provide varying properties in the active gate 450 associated with the nanosheet fins. For example, in device 400, input stage 460 includes active gates 450A to 450D with nanosheet fins 440A to 440B, which have a smaller width (width 442A) compared to active gates 450E to 450H with nanosheet fins 440C to 440D in output stage 470. The smaller width of the nanosheet fins in input stage 460 reduces the capacitance that other devices around device 400 may experience. Additionally, the larger width of the nanosheet fins implemented in output stage 470 increases the drive current capacity of device 400, allowing for as much drive output as possible to other devices outside device 400. Reducing the capacitance of device 400 from the perspective of other devices while providing as much drive output as possible improves the performance and power utilization of device 400 (and other devices associated with device 400).

[0032] An example of a transistor device that can benefit from reduced capacitance in the input stage and increased drive output to other devices is a clock implemented in a flip-flop circuit. Setting a clock with reduced capacitance in the input stage reduces the impact of its capacitance on other devices connected to the clock, while providing a high signal output from the clock that is easily received by other devices. Such clock devices can also be implemented in a smaller area within a flip-flop circuit, thus reducing the area loss of the clock in the flip-flop circuit.

[0033] Additional embodiments of the device are conceivable, in which the width of the device is increased to place the input and output stages side-by-side (e.g., side-by-side in the gate pitch direction) within the device. Placing the input and output stages side-by-side in the gate pitch direction allows for further variations in the design of the channel region and the gate formed by the channel region. For example, the width of the channel region may vary between the gates in the input or output stages, or a wider channel region may be formed by merging the channel regions. Various example embodiments are now described, and it should be understood that the elements in each example are applicable to other embodiments, including the contemplations explicitly depicted herein.

[0034] Figure 5A top plan view depicting the layout of a transistor device according to some embodiments is provided, the transistor device having nanosheet transistors having merged nanosheet fins in the output stage. In the illustrated embodiment, transistor device 500 has a larger than [missing information - likely a specific feature] in the gate pitch direction 502. Figure 3 and Figure 4 The device 500 has a wider cell width than the standard cell width in the cell height direction 504. This cell height is twice the standard cell height (e.g., 2 × standard cell heights 506A to 506B), and is similar in height to... Figure 4 The device shown is 400.

[0035] In some embodiments, device 500 includes active gate structures 510A to 510C and dummy (e.g., passive) gate structures 520A to 520C. In various embodiments, the active gate structures 510A to 510C and the dummy gate structures 520A to 520C are fingers or lines of gate material extending (e.g., extending) across device 500 in the cell height direction 504 (e.g., the vertical direction of the illustrated device). The gate material may be, for example, polysilicon or metal. In some embodiments, the gate material of the gate structures 510A to 510C or the dummy gate structures 520A to 520C may extend beyond the boundary of device 500.

[0036] In various embodiments, dummy gate structures 520A to 520B define the edges of device 500 in the gate pitch direction 502 and isolate device 500 from other devices in the gate pitch direction, wherein dummy gate structure 520A defines the left edge and dummy gate structure 520B defines the right edge. In some embodiments, dummy gate structure 520C divides device 500 into an input stage 560 and an output stage 570. For example, device 500 is divided by dummy gate structure 520C into an input stage 560 in the left portion of the device (in the gate pitch direction 502) and an output stage 570 in the right portion of the device. Figure 5 Various wirings in the layer above the structure shown define the connection between input stage 560 and output stage 570.

[0037] In some embodiments, input stage 560 includes channel regions 530A to 530D, while output stage 570 includes channel regions 530E to 530G. Channel regions 530A to 530G may include corresponding nanosheet fins 540A to 540G. Each of the nanosheet fins 540A to 540G may include stacked nanosheet fins, such as… Figure 1 and Figure 2The nanosheet fin 130 is shown. In various embodiments, nanosheet fins 540A to 540D extend across the width of input stage 560 in the gate pitch direction 502. For example, nanosheet fins 540A to 540D may extend between dummy gate structures 520A and dummy gate structures 520C. Nanosheet fins 540E to 540G extend across the width of output stage 570 between dummy gate structures 520C and dummy gate structures 520B in the gate pitch direction 502.

[0038] In various embodiments, input stage 560 includes active gates 550A to 550H. Active gates 550A to 550D (dashed box) may be formed at the region where nanosheet fins 540A to 540B (oriented in the gate pitch direction 502) intersect with active gate structures 510A to 510B (oriented in the cell height direction 504). Additionally, active gates 550E to 550H (dashed box) may be formed at the region where nanosheet fins 540C to 540D (oriented in the gate pitch direction 502) intersect with active gate structures 510A to 510B (oriented in the cell height direction 504). For example, active gates 550A to 550B are formed in the region where nanosheet fin 540A intersects with active gate structures 510A to 510B, active gates 550C to 550D are formed in the region where nanosheet fin 540B intersects with active gate structures 510A to 510B, active gates 550E to 550F are formed in the region where nanosheet fin 540C intersects with active gate structures 510A to 510B, and active gates 550G to 550H are formed in the region where nanosheet fin 540D intersects with active gate structures 510A to 510B.

[0039] exist Figure 5 In the illustrated embodiment, nanosheet fins 540A to 540B in the input stage 560 have a width of 542A, and nanosheet fins 540C to 540D in the input stage have a width of 542B. In some embodiments, the width 542A is different from the width 542B. For example, the width 542A may be smaller than the width 542B, and the nanosheet fins 540A to 540B are heterogeneous relative to the nanosheet fins 540C to 540D. The variation in the width of the nanosheet fins 540 in the input stage 560 allows for connectivity to gates of different sizes within the input stage. Therefore, the input stage 560 increases the design flexibility of the device 500 by providing gate properties and corresponding gate connectivity that can be implemented in a wide variety of transistor devices.

[0040] In some embodiments, the output stage 570 includes active gates 550I to 550K formed between dummy gate structures 520C and dummy gate structures 520B, in regions where nanosheet fins 540E to 540G (oriented in the gate pitch direction 502) intersect with active gate structure 510C (oriented in the cell height direction 504). For example, an active gate 550I (dashed box) is formed in the region where nanosheet fin 540E intersects with active gate structure 510C, an active gate 550J (dashed box) is formed in the region where nanosheet fin 540F intersects with active gate structure 510C, and an active gate 550K (dashed box) is formed in the region where nanosheet fin 540G intersects with active gate structure 510C.

[0041] In various implementations, the output stage 570 is based on a layout comprising four nanosheets of similar size (e.g., similar width), wherein two nanosheets are merged to form a single nanosheet. For example, in Figure 5 In the illustrated embodiment, nanosheet fins 540E (in channel region 530E) and 540G (in channel region 530G) are individual nanosheet fins, wherein nanosheet fin 540F (in channel region 530F) is formed by merging two individual nanosheet fins. The merging of the nanosheet fins to form nanosheet fin 540F can be achieved by designing the formation of the two individual nanosheet fins to be substantially adjacent or have some overlap in the layout.

[0042] Therefore, in Figure 5 In the illustrated embodiments, both nanosheet fins 540E and 540G have a width 542C, while nanosheet fin 540F has a width 542D, which is approximately twice the width 542C. Therefore, nanosheet fin 540F in output stage 570 is larger than nanosheet fins 540E or 540G, and active gate 550J (corresponding to nanosheet fin 540F) has a higher drive current capacity than active gate 550I (corresponding to nanosheet fin 540E) or active gate 550K (corresponding to nanosheet fin 540G). In some embodiments, width 542D is approximately twice the width 542C, and therefore the drive current capacity of active gate 550J is approximately twice the drive current capacity of active gate 550I or active gate 550K. Although Figure 5 The nanosheet fins 540E and 540G shown have the same width, but some embodiments in which the nanosheet fins 540E and 540G have different widths are conceivable.

[0043] With the variation in the width (and drive current capacity) of the active gates 550I to 550K in the output stage 570, the design flexibility of device 500 is increased because different outputs can be achieved based on providing different connections with the active gates. For example, in one envisioned implementation, active gate 550J (which has the largest drive current capacity) can be connected to another device that requires a higher drive output from device 500, while active gates 550I and 550K can be connected to other devices that have lower requirements for drive output from device 500.

[0044] Device 500 also has the following features: Figure 4 The device 400 shown provides design benefits for the input stage 560 and output stage 570. For example, the smaller nanosheet fins in the input stage 560 can be used to reduce the capacitance that other devices around the device 500 may experience, while the larger nanosheet fins in the output stage 570 can be used to increase the drive current capacity of the device 500 and provide as much drive output as possible to other devices outside the device 500.

[0045] Figure 6 A top plan view depicting the layout of a transistor device according to some embodiments is provided. This transistor device has nanosheet transistors with integrated nanosheet fins in both the input and output stages. In the illustrated embodiment, the transistor device 600 is substantially the same as [previous embodiment], except for a change in the input stage. Figure 5 The device 500 shown is similar. For example, except that the channel region (and nanosheet fins) in the vertical center portion of the input stage are merged, Figure 6 The input level 560' shown is basically the same as Figure 5 The input level shown is similar to 560.

[0046] In various embodiments, the input stage 560' includes a merged channel region 630BC having merged nanosheet fins 640BC. The channel region 630BC may be formed, for example, by moving at or near the boundary between standard cell heights 506A and 506B. Figure 5 The individual channel regions 530B and 530C shown are adjacent to each other (or have some overlap) to merge the individual channel regions and form a single channel region 630BC. The nanosheet fin 640BC is correspondingly formed by merging the channel regions as a combination between the individual nanosheet fins 530B and 530C.

[0047] With the combined channel region 630BC and combined nanosheet fins 640BC formed in the input stage 560', the active gate 650CE (dashed box) and active gate 650DF (dashed box) can be formed in conjunction with... Figure 5The active gates 550C to 550F shown are associated with the combined active gates. For example, an active gate 650CE may be formed at the region where the combined nanosheet fin 640BC (oriented in the gate pitch direction 502) intersects with the active gate structure 510A (oriented in the cell height direction 504), and a combined active gate 650DF (dashed box) may be formed at the region where the combined nanosheet fin 640BC intersects with the active gate structure 510B (oriented in the cell height direction 504).

[0048] In the illustrated embodiment, the merged nanosheet fin 640BC has a width of 642AB. Width 642AB can be, for example, widths 542A and 542B (in...). Figure 5 and Figure 6 The width of the combined nanosheet fin 640BC is shown in both examples. Therefore, the formation of the merged nanosheet fin 640BC produces a third dimension design of the nanosheet fin width in the input stage (input stage 560'). For example, width 642AB is a third available width added in addition to the first available width (width 542A) and the second available width (width 542B), which are widths of different sizes as described above.

[0049] The varying widths of the nanosheet fins in input stage 560' provide active gates with different capabilities within the input stage. Additionally, the merging of the channel region and nanosheet fins reduces the total number of active gates in input stage 560' while maintaining the total area of ​​active gates in the input stage (e.g., current drive capability). Figure 6 The input stage 560' shown has six active gates, while Figure 5 The input stage 560 shown has eight active gates, but the total active gate area (and therefore current drive capability) is approximately the same. Additional variations in the width of the nanosheet fins in the input stage 560' provide additional flexibility in the design of the device 600 by offering three options for gate properties and corresponding gate connectivity that can be implemented in various types of transistor devices.

[0050] Example computer system Next, turn to Figure 7This diagram illustrates a block diagram of one embodiment of system 700, which may incorporate and / or otherwise utilize the methods and mechanisms described herein. In the illustrated embodiment, system 700 includes at least one instance of a system-on-a-chip (SoC) 706, which may include various types of processing units (such as a central processing unit (CPU), graphics processing unit (GPU), or others), communication architectures, and interfaces to memory and input / output devices. In some embodiments, one or more processors in SoC 706 include multiple execution lanes and instruction dispatch queues. In various embodiments, SoC 706 is coupled to external memory 702, peripheral devices 704, and power supply 708.

[0051] A power supply 708 is also provided, which supplies power voltage to the SoC 706 and one or more power voltages to the memory 702 and / or peripheral devices 704. In various embodiments, the power supply 708 represents a battery (e.g., a rechargeable battery in a smartphone, laptop, tablet, or other device). In some embodiments, more than one instance of the SoC 706 is included (and more than one external memory 702 is also included).

[0052] Memory 702 is any type of memory, such as Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Dual Data Rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, and / or low-power versions of SDRAM, such as LPDDR2), RAMBUS DRAM (RDRAM), Static RAM (SRAM), etc. One or more memory devices are coupled onto a circuit board to form a memory module, such as a Single In-line Memory Module (SIMM), a Dual In-line Memory Module (DIMM), etc. Alternatively, the devices may be mounted with a SoC or integrated circuit in a chip stack configuration, package stack configuration, or multi-chip module configuration.

[0053] Depending on the type of system 700, peripheral device 704 includes any desired circuitry. For example, in one embodiment, peripheral device 704 includes devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular phones, GPS, etc. In some embodiments, peripheral device 704 also includes additional storage devices, including RAM storage devices, solid-state storage devices, or disk storage devices. Peripheral device 704 includes user interface devices (such as displays, including touch displays or multi-touch displays), keyboards or other input devices, microphones, speakers, etc.

[0054] As illustrated, system 700 is shown to have applications in a wide range of fields. For example, system 700 can be used as part of a chip, circuit, component, etc., in a desktop computer 710, laptop computer 720, tablet computer 730, cellular or mobile phone 740, or television 750 (or a set-top box coupled to a television). Smartwatches and health monitoring devices 760 are also illustrated. In some embodiments, a smartwatch may include various general computing-related functions. For example, a smartwatch may provide access to email, mobile phone services, user calendars, etc. In various embodiments, a health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functionality. For example, a health monitoring device may monitor a user's vital signs, track the user's proximity to other users for epidemiological social distancing purposes, contact tracing, provide communication to emergency services in the event of a health crisis, etc. In various embodiments, the aforementioned smartwatch may or may not include some or any health monitoring-related functions. Other wearable devices are also envisioned, such as devices worn around the neck, implantable devices, glasses designed to provide augmented and / or virtual reality experiences, etc.

[0055] System 700 can be further used as part of cloud-based service 770. For example, the previously mentioned devices and / or other devices can access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, system 700 can be used in one or more devices in home 780, in addition to those previously mentioned devices. For example, home appliances can monitor and detect noteworthy situations. For example, various devices in the home (e.g., refrigerators, cooling systems, etc.) can monitor the status of the devices and should provide an alert to the homeowner (or, for example, a repair service) upon detecting a specific event. Alternatively, a thermostat can monitor the temperature in the home and can automatically adjust the heating / cooling system based on the homeowner's history of responses to various situations. Figure 7 The document also exemplifies the application of system 700 to various modes of transportation 790. For example, system 700 can be used as a control and / or entertainment system for airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, and (for rental or private use) motorcycles. In various cases, system 700 can be used to provide automated guidance (e.g., autonomous vehicles) and general system control. Many other implementations are possible and contemplated. It should be noted that... Figure 7 The devices and applications illustrated are merely illustrative and not intended to be limiting. Other devices are possible and envisioned.

[0056] This disclosure includes references to “implementation” or groups of “implementation” (e.g., “some implementations” or “various implementations”). An implementation is a different specific implementation or instance of the disclosed concepts. References to “implementation,” “an implementation,” “a particular implementation,” etc., do not necessarily refer to the same implementation. A large number of possible implementations are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the substance or scope of this disclosure.

[0057] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all specific implementations of all these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular embodiment achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an embodiment falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure, in conjunction with one embodiment of the disclosed embodiments, which negates or diminishes one or more of the disclosed advantages. Furthermore, suboptimal design execution of a particular embodiment (e.g., the implementing technique or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technique, the realization of advantages may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors outside this disclosure, it is hereby expressed that any potential advantages described herein should not be construed as a limitation of the claims that must be satisfied in order to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the types of improvements available to the designer who benefits from this disclosure. Describing such advantages permanently (e.g., stating that a particular advantage "may occur") is not intended to convey a question about whether such advantages can actually be realized, but rather to recognize that the realization of such advantages often depends on the technological reality of additional factors.

[0058] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The disclosed embodiments are intended to be illustrative and not restrictive, without any statement to the contrary in this disclosure. Therefore, this application is intended to allow for claims covering the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art to the advantage of this disclosure.

[0059] For example, the features in the present application can be combined in any suitable manner. Therefore, during the filing of the present application (or an application claiming priority therefrom), new claims can be made for any such combination of features. Specifically, referring to the appended claims, the features of the dependent claims can, where appropriate, be combined with the features of other dependent claims, including claims that depend on other independent claims. Similarly, where appropriate, the features from the corresponding independent claims can be combined.

[0060] Thus, although the appended dependent claims can be drafted such that each dependent claim depends on a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated, and these combinations can be claimed in the present application or another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0061] Where appropriate, it is also contemplated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims in another format or statutory type (e.g., method).

[0062] Since the present disclosure is a legal document, various terms and phrases are subject to administrative and judicial interpretation. Notice is hereby given that the following paragraphs, as well as the definitions provided throughout the present disclosure, will be used to determine how claims drafted based on the present disclosure are to be interpreted.

[0063] Unless the context clearly dictates otherwise, a reference to an item in the singular form (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, without accompanying context, a reference to an "item" in a claim does not exclude additional instances of that item. "Multiple" items means a collection of two or more items in the set of items.

[0064] The word "can" is used herein in an allowable sense (i.e., having the potential to be able to), rather than in a mandatory sense (i.e., must).

[0065] The terms "comprising" and "including" and their forms are open-ended and mean "including but not limited to."

[0066] When the term “or” is used in this disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense unless the context otherwise provides. Thus, the expression “x or y” is equivalent to “x or y, or both”, and therefore covers 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as “either x or y, but not both” make it clear that “or” is used in an exclusive sense.

[0067] The expressions “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” are intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “...at least one of w, x, y, and z” therefore refers to at least one element in the set [w, x, y, z], thus covering all possible combinations of that list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0068] In this disclosure, various “labels” may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0069] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors might influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors along with other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0070] The phrases “responding to” and “responding” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, whether these factors are used in conjunction with or independently of the specified factor. That is, the effect may respond solely to these factors, or it may respond to the specified factor as well as other unspecified factors. Consider the phrase “responding to B and executing A.” This phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. This phrase does not exclude that the execution of A may also respond to certain other factors, such as C. This phrase also does not exclude that the execution of A may be jointly executed in response to B and C. This phrase is also intended to cover implementation schemes where A is executed solely in response to B. As used herein, the phrase “responding” is synonymous with the phrase “at least partially responding to.” Similarly, the phrase “responding to” is synonymous with the phrase “at least partially responding to.”

[0071] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or protected by the claims as being “configured” to perform one or more tasks or operations. This expression—[entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a tangible thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be considered “configured” to perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as being “configured” to perform a task refers to tangible things such as devices, circuits, systems with processor units, and memory storing program instructions that can be executed to perform the task. This phrase is not used herein to refer to intangible things.

[0072] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured" to perform those tasks / operations, even if not specifically stated.

[0073] The term "configured as" is not intended to mean "able to be configured as." For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA can be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform a specific function.

[0074] For the purposes of this U.S. patent application, the statement in the claims that the structure is “configured” to perform one or more tasks is expressly intended for the claim element. NotReferencing 35 USC § 112(f). If an applicant wishes to invoke part 112(f) during the filing of a U.S. patent application based on this disclosure, it will use the structure “component for [performing function]” to describe the elements of the claims.

[0075] Different “circuits” may be described in this disclosure. These circuits, or “circuits,” constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom-designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, depending on the circumstances. Certain types of circuits may be commonly referred to as “cells” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such cells also refer to circuits.

[0076] Therefore, the circuits / units / components and other elements illustrated in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoding unit” can be described as having the function of executing “the opcode of a processing instruction and routing that instruction to one or more of a plurality of functional units,” meaning that the decoding unit is “configured” to perform that function. To those skilled in the art of computers, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0077] In various implementations, as discussed in the preceding paragraphs, the arrangement of circuits, cells, and other elements defined by the functions or operations they are configured to perform, their relationship to each other, and the manner in which such circuits / cells / components interact form a microarchitecture definition of hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations are derived, all of which fall within the broader structure described by the microarchitecture definition. That is, those skilled in the art, with the microarchitecture definition provided according to this disclosure, can implement this structure without excessive experimentation and using the application of a person of ordinary skill in the art, by encoding the description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a way that can be revealed as functional. However, for those skilled in the art, the HDL description is a way of translating the structure of a circuit, cell, or component into the details of the next level of implementation. Such HDL descriptions can take the following forms: behavioral code (which is typically non-synthesizable), Register Transfer Language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). HDL descriptions can be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry. The integrated circuit can include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a Field Programmable Gate Array (FPGA) and implemented within the FPGA. This decoupling between the design of a set of circuits and their subsequent low-level implementations often results in a situation where the circuit or logic designer never specifies a particular set of structures for the low-level implementation that goes beyond a description of what the circuit is configured to do, because that process is performed at different stages of the circuit implementation process.

[0078] The fact that a circuit can be implemented to the same specifications using many different low-level combinations of circuit elements results in a large number of equivalent circuit structures. As noted, these low-level circuit implementations can vary depending on the manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of different design tools or methods to produce these different implementations can be arbitrary.

[0079] Furthermore, for a given implementation, a single concrete implementation of the circuit's specific functional specifications typically involves a large number of devices (e.g., millions of transistors). Therefore, the shearing volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single implementation, let alone a large number of equivalent possible implementations. To this end, this disclosure describes the structure of a circuit using functional abbreviations commonly used in industry.

Claims

1. An integrated circuit device, the integrated circuit device comprising: Substrate; A plurality of gate structures, the plurality of gate structures being oriented above the substrate along a first direction in the horizontal dimension; Multiple elongated channel regions, the multiple elongated channel regions being oriented along a second direction in the horizontal dimension, the second direction being perpendicular to the first direction, wherein the elongated channel regions pass through at least one gate structure in the gate structure, and wherein the elongated channel regions include two or more nanosheet fins stacked in the vertical dimension above the substrate. An input stage, the input stage including at least one elongated channel region in the elongated channel region, wherein the nanosheet fins in the at least one elongated channel region of the input stage have a first width along the first direction in the horizontal dimension; as well as An output stage, the output stage including at least one other elongated channel region among the elongated channel regions, wherein the nanosheet fins in the at least one other elongated channel region of the output stage have a second width along the first direction in the horizontal dimension, the second width being greater than the first width.

2. The device of claim 1, wherein the nanosheet fins are aligned parallel to the substrate in the vertical dimension.

3. The device according to claim 1, wherein an active gate is formed at the intersection of at least one elongated channel region in the elongated channel region and at least one gate structure in the gate structure.

4. The device of claim 1, wherein the elongated channel region extends between a first dummy gate structure on a first side of the device in the horizontal dimension and a second dummy gate structure on a second side of the device in the horizontal dimension.

5. The device of claim 1, wherein the nanosheet fins are substantially surrounded by a portion of the at least one gate structure, wherein the nanosheet fins pass through the at least one gate structure at the portion thereof.

6. The device of claim 1, wherein the input stage includes at least two elongated channel regions, and the nanosheet fins in the at least two elongated channel regions of the input stage have the first width.

7. The device of claim 6, wherein the input stage further comprises at least two additional elongated channel regions in the elongated channel region, the nanosheet fins in the at least two additional elongated channel regions of the input stage having a third width along the first direction in the horizontal dimension, the third width being greater than the first width.

8. The device of claim 1, wherein the output stage includes at least two elongated channel regions in the elongated channel regions, and the nanosheet fins in the at least two elongated channel regions of the output stage have the second width.

9. The device of claim 1, wherein the output stage includes at least two elongated channel regions, and the nanosheet fins in the at least two elongated channel regions of the output stage are combined.

10. The device of claim 1, wherein the device comprises one or more integrated circuit cells, and wherein the first direction in the horizontal dimension is the cell height direction, and the second direction in the horizontal dimension is the gate pitch direction.

11. The device of claim 10, wherein at least one gate structure of the gate structure extends across both the input stage and the output stage in the cell height direction.

12. The device of claim 10, wherein the output stage is separated from the input stage in the gate pitch direction by at least one dummy gate structure oriented in the cell height direction.

13. An integrated circuit device, the integrated circuit device comprising: A plurality of gate structures oriented above a substrate along a first direction in a horizontal dimension, wherein the plurality of gate structures include: A first dummy gate structure is positioned on a first side of the device along a second direction in the horizontal dimension, the second direction being perpendicular to the first direction; A second dummy gate structure, wherein the second dummy gate structure is positioned on a second side of the device along the second direction; and At least one active gate structure, wherein the at least one active gate structure is positioned between the first dummy gate structure and the second dummy gate structure; Multiple elongated channel regions, the multiple elongated channel regions being oriented along the second direction and extending between the first dummy gate structure and the second dummy gate structure, wherein the elongated channel regions pass through the at least one active gate structure, and wherein the elongated channel regions include two or more nanosheet fins stacked in the vertical dimension above the substrate. An input stage, the input stage including at least one elongated channel region among the elongated channel regions, wherein the nanosheet fins in the at least one elongated channel region of the input stage have a first width along the first direction in the horizontal dimension; and An output stage, the output stage including at least one other elongated channel region among the elongated channel regions, wherein the nanosheet fins in the at least one other elongated channel region of the output stage have a second width along the first direction in the horizontal dimension, the second width being greater than the first width.

14. The device of claim 13, wherein the output stage is separated from the input stage along the first direction.

15. The device of claim 13, wherein the gate structure extends across both the input stage and the output stage.

16. The device of claim 13, wherein the input stage includes at least two elongated channel regions of the elongated channel regions, the nanosheet fins of the at least two elongated channel regions of the input stage having the first width, and wherein the output stage includes at least two elongated channel regions of the elongated channel regions, the nanosheet fins of the at least two elongated channel regions of the output stage having the second width.

17. An integrated circuit device, the integrated circuit device comprising: A plurality of gate structures oriented above a substrate along a first direction in a horizontal dimension, wherein the plurality of gate structures include: A first dummy gate structure is positioned on a first side of the device along a second direction in the horizontal dimension, the second direction being perpendicular to the first direction; The second dummy gate structure is positioned on the second side of the device along the second direction; Two or more active gate structures, said two or more active gate structures being positioned between the first dummy gate and the second dummy gate; and A third dummy gate structure is positioned between at least two active gate structures in the active gate structure; Input stage, the input stage includes: A plurality of first elongated channel regions, the plurality of first elongated channel regions being oriented along a second direction and extending between a first dummy gate structure and a third dummy gate structure, wherein the first elongated channel region passes through at least one of the active gate structures, wherein the first elongated channel region includes two or more first nanosheet fins stacked in a vertical dimension above the substrate, and the first nanosheet fins in at least one of the first elongated channel regions of the input stage having a first width along the first direction in the horizontal dimension; and Output stage, the output stage including: A plurality of second elongated channel regions, the plurality of second elongated channel regions being oriented along the second direction and extending between the third dummy gate structure and the second dummy gate structure, wherein the second elongated channel regions pass through at least one other active gate structure in the active gate structure, wherein the second elongated channel region includes two or more second nanosheet fins stacked above the substrate in the vertical dimension, and at least one of the second elongated channel regions of the input stage has a second width along the first direction in the horizontal dimension, the second width being greater than the first width.

18. The device of claim 17, wherein the output stage is separated from the input stage by the third dummy gate structure.

19. The device of claim 17, wherein the second nanosheet fins in at least two of the second elongated channel regions are merged.

20. The device of claim 17, wherein the input stage further comprises at least one first nanosheet fin, the at least one first nanosheet fin being located in at least one other first elongated channel region of the first elongated channel region of the input stage and having the second width.

Images