Chip testing equipment, chip sorting equipment and chip testing system

Abstract

The invention provides chip testing equipment, chip sorting equipment and a chip testing system. The chip testing system comprises the chip testing equipment, the chip sorting equipment, a plurality of first sensors and a processor. The chip testing device is provided with a first butt joint face, the chip sorting device is provided with a second butt joint face, and the first butt joint face is used for being in butt joint with the second butt joint face of the chip sorting device. The first sensors are used for sensing distance information of the first butt joint face and the second butt joint face at different positions. The processor is electrically connected with the first sensors and used for determining the inclination angle between the first butt joint face and the second butt joint face according to the distance information sensed by the first sensors. According to the invention, by arranging the plurality of first sensors and the processor, the distance information and the inclination angle between the butt joint surfaces can be accurately obtained, and the butt joint state can be judged through the distance information and the inclination angle, so that the abnormal butt joint state can be found in time, the chip test efficiency and yield are improved, and the test cost is reduced.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a chip testing device, a chip sorting device, and a chip testing system. Background Technology

[0002] During chip manufacturing, various performance tests are required. Chip testing equipment and chip sorting (handler) equipment are crucial components of chip testing. During chip testing, the chip testing equipment needs to interface with the chip sorting equipment so that the chip sorting equipment can provide chips for testing to the chip testing equipment.

[0003] However, during and after the docking process between the chip testing equipment and the chip sorting equipment, the docking surfaces are often obscured by other components, preventing operators from directly observing the docking status and hindering timely detection of docking anomalies. During chip testing, the docking status is only indirectly assessed based on the test results. A certain number of consecutive failures at the same location trigger an error, prompting the operator to conduct an inspection. Consequently, by the time the operator detects an anomaly, a large number of chips have already entered the equipment for retesting, significantly reducing testing efficiency and yield, and increasing testing costs. Summary of the Invention

[0004] This application provides a chip testing device, a chip sorting device, and a chip testing system to improve the efficiency and yield of chip testing and reduce testing costs.

[0005] In a first aspect, embodiments of this application provide a chip testing device, which can be used to test chips. The chip testing device may include: a first device body, a plurality of first sensors, and a processor. The first device body has a first mating surface for mating with a second mating surface of a chip sorting device. Each first sensor is disposed at a different position on the first mating surface, and each first sensor is used to sense distance information between the first mating surface and the second mating surface at different positions. The processor is electrically connected to each first sensor and is used to determine the tilt angle between the first mating surface and the second mating surface based on the distance information sensed by each first sensor.

[0006] In related technologies, the docking status of the mating surfaces is indirectly fed back based on the chip's test results. This method fails to detect docking anomalies in a timely manner, leading to a significant decrease in chip testing efficiency and yield, and an increase in testing costs. The chip testing equipment provided in this application, by setting up multiple first sensors and a processor, can accurately obtain the distance information and tilt angle between the first and second mating surfaces. Therefore, the docking status can be determined using the distance information and tilt angle, enabling timely detection of docking anomalies, improving chip testing efficiency and yield, and reducing testing costs. In practical applications, the docking status between the chip testing equipment and the chip sorting equipment can be determined through data processing based on the distance information and tilt angle between the first and second mating surfaces. Alternatively, the distance information and tilt angle can be provided to the operator, who can then judge the docking status based on experience.

[0007] Furthermore, in related technologies, during the docking and debugging process of chip testing equipment and chip sorting equipment, operators need to manually measure the parallelism of the docking surfaces. This requires a high level of experience and skill from the operator, and the accuracy is low, which is detrimental to equipment maintenance. The chip testing equipment provided in this application embodiment, by setting up multiple first sensors and a processor, can accurately obtain the distance information and tilt angle between the first docking surface and the second docking surface, eliminating the need for manual measurement by the operator, greatly improving the accuracy of the measurement, and facilitating equipment maintenance.

[0008] In one possible implementation, the chip testing equipment may further include: a docking pressure-bearing component disposed on the side of the first equipment body, with the surface of the docking pressure-bearing component facing away from the first equipment body serving as a first docking surface. Each first sensor may be disposed at a different position on the docking pressure-bearing component facing away from the first equipment body. The chip sorting equipment may include: a second equipment body, with a groove on its side. The groove has space for accommodating the docking pressure-bearing component, which can be used to accommodate a portion of the docking pressure-bearing component when the chip testing equipment and the chip sorting equipment are docked. The bottom surface of the groove serves as the second docking surface. After the chip testing equipment and the chip sorting equipment are docked, part or all of the docking pressure-bearing component is embedded in the groove of the second equipment body. Both the first and second docking surfaces are located at the bottom of the groove, preventing the operator from visually observing the docking status from the outside of the equipment. In the chip testing equipment provided in this application embodiment, by setting multiple first sensors and a processor, the distance information and tilt angle between the first and second docking surfaces can be accurately obtained, allowing for real-time monitoring of the docking status between the chip testing equipment and the chip sorting equipment.

[0009] In this embodiment, the surface of the mating pressure-bearing component facing away from the main body of the first device includes a test area and a peripheral area, with each first sensor disposed in the peripheral area. The first sensors in the peripheral area can be evenly distributed; alternatively, they can be non-uniformly distributed. The chip testing equipment can test the chip in the test area. In specific configurations, the test area and peripheral area of ​​the mating pressure-bearing component can be reasonably set according to testing requirements. For example, the peripheral area can surround the test area. In this embodiment, by placing each first sensor in the peripheral area, the process of the first sensor sensing distance information will not interfere with the chip testing process.

[0010] In one possible implementation, the chip testing equipment may further include an information display screen, which may be located on the side of the first device body excluding the first mating surface. The information display screen is electrically connected to the processor and can be used to display distance information and tilt angle. This allows for visualization of the distance information and tilt angle between the chip testing equipment and the chip sorting equipment, facilitating timely observation of the equipment's mating status by the operator. In specific configurations, the information display screen can be electrically connected to the processor via a serial port or other means, or it can be electrically connected to the processor via wireless transmission. In one possible implementation, the processor can be integrated into the processing chip of the information display screen, thereby improving the integration level of the chip testing equipment. Alternatively, the processor can be integrated into the processing chip of the first device body; the specific implementation of the processor is not limited here. Of course, in some cases, the information display screen can also be electrically connected to each of the first sensors, and each of the first sensors can directly send distance information to the information display screen, or each of the first sensors can send distance information to the information display screen through the processor.

[0011] During the docking process between the chip testing equipment and the chip sorting equipment, the information display screen can show the distance and tilt angle between the first and second docking surfaces in real time. This allows the operator to judge the docking progress of the chip testing equipment and the chip sorting equipment based on the distance information and tilt angle displayed on the information display screen. Furthermore, if a docking abnormality occurs between the chip testing equipment and the chip sorting equipment, the operator can promptly detect the abnormality and take appropriate action accordingly.

[0012] In one possible implementation, the processor can also be used to determine attitude adjustment information based on the distance and tilt angle between the first and second mating surfaces during the docking process between the chip testing equipment and the chip sorting equipment. The information display screen can also be used to display this attitude adjustment information. This allows the operator to directly obtain the attitude adjustment information by viewing the content displayed on the information display screen and perform corresponding adjustments accordingly, improving the efficiency and accuracy of the docking process.

[0013] To monitor the docking status of the chip testing equipment and the chip sorting equipment in real time, the processor can also compare the distance between the first docking surface and the second docking surface with a preset distance threshold after docking is completed. In specific implementations, the distance information sensed by a single first sensor can be compared with this distance threshold, or the average distance information sensed by at least two first sensors can be compared with the distance threshold. And / or, the tilt angle can be compared with a preset angle threshold to determine whether the docking status of the chip testing equipment and the chip sorting equipment is normal. For ease of visual management, the processor can also send a first alert to an information display screen when the docking status is abnormal, and the information display screen can display information based on the first alert.

[0014] In one possible implementation, the chip testing equipment may further include a second sensor located on the side of the mating pressure-bearing component facing the main body of the first device. The second sensor can be used to sense the deformation information of the mating pressure-bearing component. Exemplarily, the second sensor may include components capable of sensing deformation, such as strain gauges or displacement sensors. The processor can also be used to determine whether the stress state of the mating pressure-bearing component is normal based on the deformation information. Specifically, the processor can compare the deformation amount sensed by the second sensor with a deformation threshold; if the deformation amount is greater than the deformation threshold, it can determine that the stress state of the mating pressure-bearing component is abnormal. In specific implementations, the deformation threshold can be reasonably set according to the pressure-bearing capacity of the mating pressure-bearing component; exemplarily, the deformation threshold can be 0.5 mm. In some cases, the second sensor may also include a pressure sensor, which can sense the pressure borne by the mating pressure-bearing component, and the deformation information can be indirectly calculated from the pressure value sensed by the pressure sensor.

[0015] During chip testing, to improve testing efficiency, chip sorting equipment simultaneously supplies multiple chips to chip testing equipment, applying significant pressure. This pressure acts on the mating pressure-bearing component. Excessive pressure from the chip sorting equipment can compromise the long-term reliability of the mating pressure-bearing component. Any malfunction in this component can damage the testing tools within the chip testing equipment, resulting in substantial losses. In this embodiment, a second sensor is installed on the side of the mating pressure-bearing component facing the main body of the first device. Specifically, the second sensor can be positioned at a location corresponding to the testing area of ​​the mating pressure-bearing component. By comparing the deformation sensed by the second sensor with a deformation threshold, the stress state of the mating pressure-bearing component can be monitored in real time, preventing abnormal deformation or damage caused by excessive pressure.

[0016] Furthermore, the processor can also be used to send a pause operation command to the chip sorting equipment when the stress state is abnormal. Upon receiving the pause operation command, the chip sorting equipment suspends the supply of chips to the chip testing equipment. This allows for timely control of the chip sorting equipment to stop applying pressure to the mating pressure-bearing components, preventing reliability issues. In practical implementation, a motor for driving chip movement can be installed in the chip sorting equipment; upon receiving the pause operation command, the chip sorting equipment can control the motor to stop running.

[0017] In one possible implementation, the processor is also used to send a second alert to the information display screen when the stress state of the docking pressure-bearing component is abnormal, so as to remind the operator to promptly detect the abnormal stress state of the docking pressure-bearing component and take appropriate action.

[0018] Secondly, this application also provides a chip sorting device. The chip sorting device provided in this application can be used to interface with chip testing equipment, provide chips to the chip testing equipment, and sort the chips that have completed testing.

[0019] The chip sorting device provided in this application embodiment may include: a second device body, each first sensor, and a processor. The second device body has a second mating surface for mating with a first mating surface of a chip testing device. Each first sensor is disposed at a different position on the second mating surface, and the multiple first sensors are used to sense distance information between the first mating surface and the second mating surface at different positions. The processor is electrically connected to the multiple first sensors and is used to determine the tilt angle between the first mating surface and the second mating surface based on the distance information sensed by the multiple first sensors.

[0020] The chip sorting equipment provided in this application embodiment, by setting multiple first sensors and a processor, can accurately obtain the distance information and tilt angle between the first mating surface and the second mating surface. Therefore, the mating status can be determined based on the distance information and tilt angle, enabling timely detection of mating status anomalies, improving chip testing efficiency and yield, and reducing testing costs. Furthermore, it eliminates the need for manual measurement by the operator, greatly improving measurement accuracy and facilitating equipment maintenance.

[0021] In some embodiments of this application, the side of the second device body has a groove, which provides space for accommodating a docking pressure-bearing component. This groove can be used to accommodate a portion of the docking pressure-bearing component when the chip testing equipment and the chip sorting equipment dock. Each first sensor can be disposed at a different position on the bottom surface of the groove. Specifically, to avoid interference between the first sensor's distance sensing process and the chip testing process, each first sensor can be disposed at a position corresponding to the peripheral area of ​​the docking pressure-bearing component. The first sensors on the bottom surface of the groove can be uniformly distributed; alternatively, they can be non-uniformly distributed.

[0022] In one possible implementation, the chip sorting device may further include an information display screen, which may be disposed on the side of the second device body excluding the second mating surface. The information display screen is electrically connected to the processor and can be used to display the distance information sensed by each of the first sensors 13 and the tilt angle determined by the processor. This allows for visualization of the distance information and tilt angle between the chip testing device and the chip sorting device, facilitating timely observation of the device's mating status by the operator. In specific configurations, the information display screen can be electrically connected to the processor via a serial port or other means, or it can be electrically connected to the processor via wireless transmission. In one possible implementation, the processor can be integrated into the processing chip of the information display screen, thereby improving the integration of the chip sorting device. Alternatively, the processor can be integrated into the processing chip within the second device body; the specific implementation of the processor is not limited here. Of course, in some cases, the information display screen can also be electrically connected to each of the first sensors, and each first sensor can directly send distance information to the information display screen, or each first sensor can send distance information to the information display screen via the processor.

[0023] In one possible implementation, the processor can also be used to determine attitude adjustment information based on the distance and tilt angle between the first and second mating surfaces during the docking process between the chip testing equipment and the chip sorting equipment. The information display screen can also be used to display this attitude adjustment information. This allows the operator to directly obtain the attitude adjustment information by viewing the content displayed on the information display screen and perform corresponding adjustments accordingly, improving the efficiency and accuracy of the docking process.

[0024] In one possible implementation, to monitor the docking status of the chip testing equipment and the chip sorting equipment in real time, the processor can also compare the distance between the first docking surface and the second docking surface with a preset distance threshold after the docking is completed. Specifically, the distance information sensed by a single first sensor can be compared with the distance threshold, or the average distance information sensed by at least two first sensors can be compared with the distance threshold. And / or, the tilt angle can be compared with a preset angle threshold to determine whether the docking status of the chip testing equipment and the chip sorting equipment is normal. To facilitate visual management, the processor can also send a first alert to an information display screen when the docking status is abnormal, and the information display screen can display information based on the first alert.

[0025] In the second aspect, when each first sensor and information display screen are set in the chip sorting device, the functions and specific implementation methods of each first sensor, information display screen and processor can be implemented with reference to the description in the first aspect above, and the repeated parts will not be repeated.

[0026] Thirdly, embodiments of this application also provide a chip testing system. The chip testing system provided in this application embodiment may include: any of the chip testing devices described in the first aspect above and a chip sorting device; or, the chip testing system provided in this application embodiment may include: a chip testing device and any of the chip sorting devices described in the second aspect above. The chip testing device has a first mating surface, and the chip sorting device has a second mating surface. The first mating surface of the chip testing device is used to mate with the second mating surface of the chip sorting device. The chip testing device is used to test chips. The chip sorting device, after mating with the chip testing device, provides chips to the chip testing device and sorts the tested chips.

[0027] The chip testing equipment in the first aspect mentioned above is equipped with multiple first sensors and processors, or the chip sorting equipment in the second aspect mentioned above is equipped with multiple first sensors and processors. Through each first sensor and processor, the distance information and tilt angle between the first mating surface and the second mating surface can be accurately obtained. Therefore, the mating status can be determined based on the distance information and tilt angle, thereby enabling timely detection of mating status anomalies, improving chip testing efficiency and yield, and reducing testing costs. Attached Figure Description

[0028] Figure 1 This is a three-dimensional structural diagram of the chip testing system provided in the embodiments of this application;

[0029] Figure 2 for Figure 1A schematic diagram of the cross-section at the dashed line AA';

[0030] Figure 3 This is a schematic diagram illustrating the docking process between the chip testing equipment and the chip sorting equipment in an embodiment of this application;

[0031] Figure 4 This is a three-dimensional structural diagram of the chip testing equipment provided in the embodiments of this application;

[0032] Figure 5 This is a schematic diagram of the planar structure of the chip testing equipment in the embodiments of this application;

[0033] Figure 6 This is a schematic diagram showing the chip testing equipment and chip sorting equipment after docking in an embodiment of this application;

[0034] Figure 7 A schematic diagram illustrating a connection error between chip testing equipment and chip sorting equipment.

[0035] Figure 8 This is a side view of the chip testing equipment in an embodiment of this application;

[0036] Figure 9 This is a schematic diagram of the chip sorting device in the embodiments of this application.

[0037] Figure label:

[0038] 11-Chip testing equipment; 111-First equipment body; 112-Dating pressure-bearing component; 12-Chip sorting equipment; 121-Second equipment body; 13-First sensor; 14-Information display screen; 15-Second sensor; S1-First mating surface; S2-Second mating surface; C1-Test area; C2-Surrounding area; U-Groove. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0040] It should be noted that the accompanying drawings in this application are for illustrative purposes only and do not represent actual scale. The same reference numerals in the accompanying drawings denote the same or similar structures, and therefore, repeated descriptions of them will be omitted.

[0041] The terms describing position and direction used in this application, such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," are merely illustrative examples based on the orientation or positional relationships shown in the accompanying drawings. They are intended solely for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Changes may be made as needed, and all such changes are included within the scope of protection of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0042] To address the problems of low efficiency, low yield, and high cost in chip testing caused by the inability to directly observe the docking status between chip testing equipment and chip sorting equipment, leading to the inability to promptly detect docking anomalies, this application provides a chip testing device, a chip sorting device, and a chip testing system. The chip testing system in this application can be used to test various types of chips, such as memory chips, data processing chips, sensor chips, communication chips, analog chips, and digital chips.

[0043] Figure 1 This is a three-dimensional structural diagram of the chip testing system provided in the embodiments of this application. Figure 2 for Figure 1 A schematic diagram of the cross-section at the dashed line AA', combined with... Figure 1 and Figure 2 The chip testing system provided in this application embodiment may include a chip testing device 11 and a chip sorting device 12. The chip testing device 11 is used to test chips, performing electrical performance tests and functional verifications. Depending on different testing requirements, the chip testing device 11 can perform various tests on the chips, such as voltage, current, power, frequency, and timing. The chip sorting device 12, after docking with the chip testing device 11, provides chips to the chip testing device 11 and sorts the tested chips. For example, the chip sorting device 12 can use image recognition and processing to select unqualified chips, or it can classify the chips according to certain standards. The chip testing device 11 has a first docking surface S1, and the chip sorting device 12 has a second docking surface S2. The first docking surface S1 of the chip testing device 11 is used to dock with the second docking surface S2 of the chip sorting device 12. Figure 1 It is evident that when the chip testing equipment 11 and the chip sorting equipment 12 are in a docking state, their docking surfaces are blocked by other components, and the docking state cannot be directly observed from the outside of the equipment. Figure 1The example shown is that chip testing equipment 11 and chip sorting equipment 12 are in a docking state. It is easy to understand that during the docking process of chip testing equipment 11 and chip sorting equipment 12, the docking state cannot be directly observed from the outside of the equipment.

[0044] The chip testing equipment provided in this application embodiment may include: a plurality of first sensors 13 and a processor (not shown in the figure). In this application embodiment, the chip testing equipment including a plurality of first sensors 13 means that the number of first sensors 13 is at least two. Each first sensor 13 is used to sense distance information between the first mating surface S1 and the second mating surface S2 at different positions. The processor is electrically connected to each first sensor 13 and is used to determine the tilt angle between the first mating surface S1 and the second mating surface S2 based on the distance information sensed by each first sensor 13.

[0045] In related technologies, the docking status of the mating surfaces is indirectly fed back based on the chip test results. This method cannot detect docking anomalies in a timely manner, resulting in a significant decrease in chip testing efficiency and yield, and an increase in testing costs. The chip testing system provided in this application embodiment, by setting up multiple first sensors 13 and a processor, can accurately obtain the distance information and tilt angle between the first mating surface S1 and the second mating surface S2. Therefore, the docking status can be determined based on the distance information and tilt angle, thereby enabling timely detection of docking anomalies, improving chip testing efficiency and yield, and reducing testing costs. In practical applications, the docking status between the chip testing equipment 11 and the chip sorting equipment 12 can be determined through data processing based on the distance information and tilt angle between the first mating surface S1 and the second mating surface S2. Alternatively, the distance information and tilt angle between the first mating surface S1 and the second mating surface S2 can be provided to the operator, who can then judge the docking status between the chip testing equipment 11 and the chip sorting equipment 12 based on experience.

[0046] Furthermore, in related technologies, during the docking and debugging process of the chip testing equipment 11 and the chip sorting equipment 12, the operator needs to manually measure the parallelism of the docking surfaces. This requires a high level of experience and skill from the operator, and the accuracy is low, which is detrimental to equipment maintenance. The chip testing system provided in this application embodiment, by setting up multiple first sensors 13 and a processor, can accurately obtain the distance information and tilt angle between the first docking surface S1 and the second docking surface S2, eliminating the need for manual measurement by the operator, greatly improving the accuracy of the measurement, and facilitating equipment maintenance.

[0047] Figure 3 This is a schematic diagram illustrating the docking process between the chip testing equipment and the chip sorting equipment in an embodiment of this application. Figure 3As shown in the embodiments of this application, the chip testing device 11 may include: a first device body 111 and a docking pressure-bearing component 112. The docking pressure-bearing component 112 is disposed on the side of the first device body 111, and the surface of the docking pressure-bearing component 112 facing away from the first device body 111 is the first docking surface S1. The chip sorting device 12 may include: a second device body 121. The side of the second device body 121 has a groove U. The groove U has space for accommodating the docking pressure-bearing component 112, which can be used to accommodate a part of the docking pressure-bearing component 112 when the chip testing device 11 docks with the chip sorting device 12. The bottom surface of the groove U is the second docking surface S2.

[0048] Reference Figure 3 During the docking process between the chip testing device 11 and the chip sorting device 12, the chip testing device 11 can be controlled to move towards the chip sorting device 12 in the direction indicated by arrow Q in the diagram, gradually reducing the distance between them. Alternatively, during the docking process, the chip sorting device 12 can also be controlled to move towards the chip testing device 11, or they can move towards each other together; this is not limited to any particular method. When the distance between the chip testing device 11 and the chip sorting device 12 is reduced to a level that meets the testing requirements, the docking is complete, and the chip is sorted. Figure 2 The structure shown. (As illustrated) Figure 2 As shown, after the chip testing equipment 11 and the chip sorting equipment 12 are docked, part or all of the docking pressure-bearing component 112 is embedded in the groove U of the second equipment body 121. The first docking surface S1 and the second docking surface S2 are both located at the bottom of the groove U, making it impossible for the operator to observe the docking status from the outside of the equipment. In the chip testing system provided in this application embodiment, by setting multiple first sensors 13 and a processor, the distance information and tilt angle between the first docking surface S1 and the second docking surface S2 can be accurately obtained, and the docking status between the chip testing equipment 11 and the chip sorting equipment 12 can be monitored in real time.

[0049] Figure 4 This is a three-dimensional structural diagram of the chip testing equipment provided in the embodiments of this application, such as... Figure 4 As shown, in some embodiments of this application, each first sensor 13 can be disposed in the chip testing equipment 11. Specifically, each first sensor 13 can be disposed at different positions on the side of the mating pressure bearing component 112 away from the first equipment body 111. In embodiments of this application, one or more mating pressure bearing components 112 can be disposed on the side of the first equipment body 111 according to the chip testing requirements, for example... Figure 4The example shown is that two docking pressure-bearing components 112 are set on the side of the main body 111 of the first equipment.

[0050] Figure 5 This is a schematic diagram of the planar structure of the chip testing equipment in an embodiment of this application, as shown below. Figure 5 As shown, the surface of the mating pressure-bearing component 112 facing away from the first device body 111 includes a test area C1 and a peripheral area C2. Each first sensor 13 can be respectively disposed in the peripheral area C2. The chip testing device 11 can test the chip in the test area C1. In specific settings, the test area C1 and the peripheral area C2 of the mating pressure-bearing component 112 can be reasonably set according to the testing requirements. For example, the peripheral area C2 can surround the test area C1. In this embodiment, by disposing each first sensor 13 in the peripheral area C2, the process of the first sensor 13 sensing distance information will not affect the chip testing process.

[0051] In specific configurations, the first sensors 13 in the surrounding area C2 can be evenly distributed; alternatively, the first sensors 13 in the surrounding area C2 can be non-uniformly distributed. In specific configurations, the number and position of the first sensors 13 can be reasonably set according to the specific structure of the docking pressure-bearing component 112 and the measurement requirements. For example... Figure 5 In the example of a chip testing device 11 with two mating pressure-bearing components 112, four first sensors 13 can be set in the peripheral area C2 of each mating pressure-bearing component 112. For example, taking a rectangular outline of the peripheral area C2, one first sensor 13 can be set at each apex of the peripheral area C2, or four first sensors 13 can be set at two opposite sides of the peripheral area C2. In specific implementations, the number and position of the first sensors 13 can be reasonably set according to the shape of the peripheral area C2; further examples are not provided here.

[0052] In one possible implementation, such as Figure 4As shown, the chip testing system may further include an information display screen 14, which may be disposed on the side of the first device body 111 excluding the first mating surface S1. The information display screen 14 is electrically connected to the processor and can be used to display the distance information sensed by each of the first sensors 13 and the tilt angle determined by the processor. Thus, the distance information and tilt angle between the chip testing device 11 and the chip sorting device can be visualized, facilitating the operator to observe the docking status of the devices in a timely manner. In specific configurations, the information display screen 14 may be electrically connected to the processor via a serial port or other means, or it may be electrically connected to the processor via wireless transmission. In one possible implementation, the processor may be integrated into the processing chip of the information display screen 14, thereby improving the integration of the chip testing device 11. Alternatively, the processor may be integrated into the processing chip in the first device body 111 or the second device body 121; the specific implementation of the processor is not limited here. Of course, in some cases, the information display screen 14 can also be electrically connected to each of the first sensors 13. Each of the first sensors 13 can directly send distance information to the information display screen 14, or each of the first sensors 13 can send distance information to the information display screen 14 through a processor.

[0053] Combination Figure 3 and Figure 4 During the docking process between the chip testing equipment 11 and the chip sorting equipment 12, the information display screen 14 can display the distance and tilt angle between the first docking surface S1 and the second docking surface S2 in real time. This allows for the quantification of the docking progress, enabling the operator to judge the docking progress of the chip testing equipment 11 and the chip sorting equipment 12 based on the distance information and tilt angle displayed on the information display screen 14. Furthermore, if a docking abnormality occurs between the chip testing equipment 11 and the chip sorting equipment 12, the operator can promptly detect the abnormality and take appropriate action accordingly.

[0054] In one possible implementation, the processor can also be used to determine attitude adjustment information based on the distance and tilt angle between the first docking surface S1 and the second docking surface S2 during the docking process between the chip testing equipment 11 and the chip sorting equipment 12. The information display screen 14 can also be used to display the attitude adjustment information. Thus, the operator can directly obtain the attitude adjustment information by viewing the content displayed on the information display screen 14 and perform corresponding adjustments based on this information, shortening the docking time and achieving higher precision and faster attitude adjustment. Furthermore, it avoids the impact of manual adjustment on the operator and measuring tools, thereby improving the efficiency and accuracy of the docking process.

[0055] Figure 6This is a schematic diagram showing the chip testing equipment and chip sorting equipment after docking in an embodiment of this application. Figure 6 As shown, after the chip testing equipment 11 and the chip sorting equipment 12 are docked, the distance d between the first docking surface S1 and the second docking surface S2 and the tilt angle θ must meet the set requirements to satisfy the chip testing needs. During the chip testing process, the relative positions of the chip testing equipment 11 and the chip sorting equipment 12 may change. In order to monitor the docking status of the two in real time, the processor can also compare the distance d between the first docking surface S1 and the second docking surface S2 with a preset distance threshold after the chip testing equipment 11 and the chip sorting equipment 12 are docked. In specific implementation, the distance information sensed by a certain first sensor 13 can be compared with the distance threshold, or the average value of the distance information sensed by at least two first sensors 13 can be compared with the distance threshold. And / or, the tilt angle θ can be compared with a preset angle threshold to determine whether the docking status of the chip testing equipment 11 and the chip sorting equipment 12 is normal.

[0056] Figure 7 This is a schematic diagram illustrating a connection error between the chip testing equipment and the chip sorting equipment. Figure 7 As shown, if the distance d between the first mating surface S1 and the second mating surface S2 is too large, or if the tilt angle θ between the first mating surface S1 and the second mating surface S2 is too large, the mating state between the chip testing device 11 and the chip sorting device 12 will be abnormal. Therefore, if at least one of the distance d between the first mating surface S1 and the second mating surface S2 and the tilt angle θ exceeds a threshold, the mating state can be determined to be abnormal. Specifically, the processor is specifically used to: determine that the mating state between the chip testing device 11 and the chip sorting device 12 is normal when the distance between the first mating surface S1 and the second mating surface S2 is less than or equal to the distance threshold and the tilt angle θ is less than or equal to the angle threshold; determine that the mating state between the chip testing device 11 and the chip sorting device 12 is abnormal when the distance between the first mating surface S1 and the second mating surface S2 is greater than the distance threshold; and / or when the tilt angle θ is greater than the angle threshold.

[0057] For example, the aforementioned distance threshold can be 0.05mm. When the distance sensed by the first sensor 13 is greater than 0.05mm, the distance between the first mating surface S1 and the second mating surface S2 is too far, making effective mating impossible, and the mating state of the chip testing device 11 and the chip sorting device 12 is abnormal. The aforementioned angle threshold can be 0.1 degrees. When the tilt angle is greater than 0.1 degrees, the angle between the first mating surface S1 and the second mating surface S2 is too large, making effective mating impossible, and the mating state of the chip testing device 11 and the chip sorting device 12 is abnormal.

[0058] To facilitate visual management, the processor can also send a first alert to the information display screen 14 when the docking status is abnormal. The information display screen 14 can then display the alert based on this first alert. For example, the information display screen 14 can display messages such as "Abnormal docking status," "Dock surface distance too large," or "Tilting angle too large" as the first alert. Alternatively, if the information display screen 14 has a speaker, it can emit a warning sound as the first alert. Or, the information display screen 14 can change its screen color as the first alert; for example, the screen color can be green when docking is normal, and red when docking is abnormal. Of course, the first alert can have many other implementations, as long as they serve the purpose of alerting; these will not be listed here.

[0059] Figure 8 This is a side view of the chip testing equipment in an embodiment of this application, such as... Figure 8 As shown, in one possible implementation, the chip testing device 11 may further include a second sensor 15 located on the side of the docking pressure-bearing component 112 facing the first device body 111. The second sensor 15 can be used to sense the deformation information of the docking pressure-bearing component 112. For example, the second sensor 15 may include components capable of sensing deformation, such as strain gauges or displacement sensors. The processor can also be used to determine whether the stress state of the docking pressure-bearing component 112 is normal based on the deformation information. Specifically, the processor can compare the deformation sensed by the second sensor 15 with a deformation threshold. If the deformation exceeds the deformation threshold, it is determined that the stress state of the docking pressure-bearing component 112 is abnormal. In specific implementations, the deformation threshold can be reasonably set according to the pressure bearing capacity of the docking pressure-bearing component 112. For example, the deformation threshold can be 0.5 mm. In some cases, the second sensor 15 may also include a pressure sensor, which can sense the pressure borne by the docking pressure-bearing component 112. The deformation information can be indirectly calculated from the pressure value sensed by the pressure sensor.

[0060] During the operation of the chip testing system, in order to improve testing efficiency, the chip sorting device simultaneously provides multiple chips to the chip testing device 11. The chip sorting device applies significant pressure to the chip testing device 11 (as shown by arrow F in the figure), which acts on the mating pressure-bearing component 112. When the pressure applied by the chip sorting device is too high, the mating pressure-bearing component 112 cannot guarantee long-term reliability. Once the mating pressure-bearing component 112 malfunctions, it will damage the testing tools in the chip testing device 11, causing significant losses. In this embodiment, a second sensor 15 is provided on the side of the mating pressure-bearing component 112 facing the first device body 111. Specifically, the second sensor 15 can be positioned at a location corresponding to the testing area of ​​the mating pressure-bearing component 112. By comparing the deformation sensed by the second sensor 15 with a deformation threshold, the stress state of the mating pressure-bearing component 112 can be monitored in real time, preventing abnormal deformation or damage to the mating pressure-bearing component 112 due to excessive pressure.

[0061] Furthermore, the processor can also be used to send a pause operation command to the chip sorting device when the stress state is abnormal. Upon receiving the pause operation command, the chip sorting device suspends the supply of chips to the chip testing device. This allows for timely control of the chip sorting device to stop applying pressure to the docking pressure-bearing component 112, preventing reliability issues with the docking pressure-bearing component 112. In a specific implementation, a motor for driving chip movement can be installed in the chip sorting device; when a pause operation command is received, the chip sorting device can control the motor to stop running.

[0062] In one possible implementation, the processor is further configured to send a second alert message to the information display screen 14 when the stress state of the docking pressure-bearing component 112 is abnormal, so as to remind the operator to promptly detect the abnormal stress state of the docking pressure-bearing component 112 and take appropriate action. For example, the information display screen 14 may display content such as "abnormal stress state" or "excessive deformation" as the second alert message; or, if the information display screen 14 has a speaker, it may emit a warning sound as the second alert message. Of course, the second alert message can also have many other implementations, as long as they serve the alerting purpose; these will not be listed here.

[0063] Figure 9 This is a schematic diagram of the chip sorting device in an embodiment of this application, as shown below. Figure 9As shown, in some other embodiments of this application, each first sensor 13 can be disposed in the chip sorting device 12, and each first sensor 13 can be disposed at different positions on the second mating surface S2. Specifically, each first sensor 13 can be disposed at different positions on the bottom surface of the groove U. In specific settings, to avoid the process of the first sensor 13 sensing distance information from interfering with the chip testing process, each first sensor 13 can be disposed at a position corresponding to the peripheral area of ​​the mating pressure-bearing component. The first sensors 13 on the bottom surface of the groove U can be uniformly distributed; or, the first sensors 13 on the bottom surface of the groove U can be non-uniformly distributed.

[0064] In one possible implementation, the chip testing system may further include an information display screen 14, which may be disposed on the side of the second device body 121 excluding the second mating surface S2. The information display screen 14 is electrically connected to the processor and can be used to display the distance information sensed by each of the first sensors 13 and the tilt angle determined by the processor. This allows for visualization of the distance information and tilt angle between the chip testing device and the chip sorting device 12, facilitating timely observation of the device's mating status by the operator. Specifically, the information display screen 14 may be electrically connected to the processor via a serial port or other means, or it may be electrically connected to the processor via wireless transmission. In one possible implementation, the processor may be integrated into the processing chip of the information display screen 14, thereby improving the integration of the chip sorting device 12. Alternatively, the processor may be integrated into the processing chip within the first or second device body 121; the specific implementation of the processor is not limited here. Of course, in some cases, the information display screen 14 can also be electrically connected to each of the first sensors 13. Each of the first sensors 13 can directly send distance information to the information display screen 14, or each of the first sensors 13 can send distance information to the information display screen 14 through a processor.

[0065] In one possible implementation, the processor can also be used to determine attitude adjustment information based on the distance and tilt angle between the first docking surface and the second docking surface S2 during the docking process between the chip testing equipment and the chip sorting equipment 12. The information display screen 14 can also be used to display the attitude adjustment information. Thus, the operator can directly obtain the attitude adjustment information by viewing the content displayed on the information display screen 14 and perform corresponding adjustments based on this information, improving the efficiency and accuracy of the docking process.

[0066] In one possible implementation, to monitor the docking status of the chip testing equipment and the chip sorting equipment 12 in real time, the processor can also compare the distance between the first docking surface and the second docking surface S2 with a preset distance threshold after the docking is completed. Specifically, the distance information sensed by a single first sensor 13 can be compared with the distance threshold, or the average distance information sensed by at least two first sensors 13 can be compared with the distance threshold. And / or, the tilt angle can be compared with a preset angle threshold to determine whether the docking status of the chip testing equipment and the chip sorting equipment 12 is normal. To facilitate visual management, the processor can also send a first reminder message to the information display screen 14 when the docking status is abnormal, and the information display screen 14 can display the message accordingly.

[0067] In the embodiments of this application, when each first sensor 13 and information display screen 14 are disposed in the chip sorting device 12, the functions and specific implementation methods of each first sensor 13, information display screen 14 and processor can be implemented with reference to the above description, and repeated parts will not be described again.

[0068] In the above description, each first sensor 13 can be disposed in the chip testing equipment 11, or each first sensor 13 can be disposed in the chip sorting equipment 12. In some cases, some of the first sensors 13 can be disposed in the chip testing equipment 11, and other parts of the first sensors 13 can be disposed in the chip sorting equipment 12. In other cases, the first sensor 13 can include a transmitter and a receiver. The transmitter can be disposed in the chip testing equipment 11, and the receiver can be disposed in the chip sorting equipment 12; or, the transmitter can be disposed in the chip sorting equipment 12, and the receiver can be disposed in the chip testing equipment 11.

[0069] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0070] Obviously, those skilled in the art can make various modifications and variations to the embodiments of this application without departing from the spirit and scope of the embodiments of this application. Therefore, if these modifications and variations to the embodiments of this application fall within the scope of the claims of this application and their equivalents, this application also intends to include these modifications and variations.

Claims

1. A chip testing device, characterized in that, The chip testing equipment is used to test the chip; The chip testing equipment includes: a first equipment body, multiple first sensors, and a processor; The first device body has a first mating surface, which is used to mate with the second mating surface of the chip sorting device; The plurality of first sensors are disposed at different positions on the first docking surface, and the plurality of first sensors are used to sense the distance information between the first docking surface and the second docking surface at different positions; The processor is electrically connected to the plurality of first sensors and is used to determine the tilt angle between the first mating surface and the second mating surface based on the distance information sensed by the plurality of first sensors.

2. The chip testing equipment as described in claim 1, characterized in that, The chip testing equipment also includes: a docking pressure-bearing component; The docking pressure-bearing component is disposed on the side of the first equipment body, and the surface of the docking pressure-bearing component facing away from the first equipment body is the first docking surface; The plurality of first sensors are respectively disposed at different positions on the side of the docking pressure-bearing component away from the main body of the first device.

3. The chip testing equipment as described in claim 2, characterized in that, The surface of the docking pressure-bearing component on the side away from the main body of the first device includes a test area and a surrounding area; The plurality of first sensors are respectively disposed in the surrounding area.

4. The chip testing equipment as described in claim 2, characterized in that, The chip testing equipment also includes a second sensor located on the side of the docking pressure-bearing component facing the main body of the first equipment; The second sensor is used to sense the deformation information of the docking pressure-bearing component; The processor is also used to determine whether the stress state of the docking pressure-bearing component is normal based on the deformation information; when the stress state is abnormal, it sends a pause operation command to the chip sorting device so that the chip sorting device stops providing chips to the chip testing device.

5. The chip testing equipment according to any one of claims 1 to 4, characterized in that, The chip testing equipment also includes: an information display screen; The information display screen is located on the side of the first device body, excluding the first docking surface; The information display screen is electrically connected to the processor and is used to display the distance information and the tilt angle.

6. The chip testing equipment as described in claim 5, characterized in that, The processor is also used to determine attitude adjustment information based on the distance information and the tilt angle during the docking process between the chip testing equipment and the chip sorting equipment. The information display screen is also used to display the posture adjustment information.

7. The chip testing equipment as described in claim 5 or 6, characterized in that, The processor is further configured to, after the chip testing equipment and the chip sorting equipment have docked, compare the distance between the first docking surface and the second docking surface with a preset distance threshold; and / or compare the tilt angle with a preset angle threshold, so as to determine whether the docking status of the chip testing equipment and the chip sorting equipment is normal; When the docking status is abnormal, a first reminder message is sent to the information display screen; The information display screen is used to display information based on the first reminder message.

8. A chip sorting device, characterized in that, The chip sorting device is used to interface with the chip testing device, provide chips to the chip testing device, and sort the chips that have completed testing. The chip sorting device includes: a second device body, multiple first sensors, and a processor; The second device body has a second mating surface, which is used to mate with the first mating surface of the chip testing device; The plurality of first sensors are disposed at different positions on the second docking surface, and the plurality of first sensors are used to sense the distance information between the first docking surface and the second docking surface at different positions; The processor is electrically connected to the plurality of first sensors and is used to determine the tilt angle between the first mating surface and the second mating surface based on the distance information sensed by the plurality of first sensors.

9. The chip sorting device as described in claim 8, characterized in that, The second device body has a groove on its side, the groove having space for accommodating the docking pressure-bearing component of the chip testing device, for accommodating at least a portion of the docking pressure-bearing component when the chip testing device docks with the chip sorting device; The bottom surface of the groove is the second mating surface, and the plurality of first sensors are respectively disposed at different positions on the bottom surface of the groove.

10. The chip sorting device as described in claim 8 or 9, characterized in that, The chip sorting device also includes: an information display screen; The information display screen is located on the side of the second device body, excluding the second docking surface; The information display screen is electrically connected to the processor and is used to display the distance information and tilt angle sensed by the plurality of first sensors.

11. The chip sorting device as described in claim 10, characterized in that, The processor is also used to determine attitude adjustment information based on the distance information and the tilt angle during the docking process between the chip testing equipment and the chip sorting equipment. The information display screen is also used to display the posture adjustment information.

12. The chip sorting device as described in claim 10 or 11, characterized in that, The processor is further configured to, after the chip testing equipment and the chip sorting equipment have docked, compare the distance between the first docking surface and the second docking surface with a preset distance threshold; and / or compare the tilt angle with a preset angle threshold, so as to determine whether the docking status of the chip testing equipment and the chip sorting equipment is normal; When the docking status is abnormal, a first reminder message is sent to the information display screen; The information display screen is used to display information based on the first reminder message.

13. A chip testing system, characterized in that, The chip testing system includes: a chip testing device and a chip sorting device as described in any one of claims 1 to 7; or, the chip testing system includes: a chip testing device and a chip sorting device as described in any one of claims 8 to 12; The chip testing equipment has a first mating surface, and the chip sorting equipment has a second mating surface; the first mating surface of the chip testing equipment is used to mate with the second mating surface of the chip sorting equipment. The chip testing equipment is used to test the chip; The chip sorting device is used to interface with the chip testing device, provide chips to the chip testing device, and sort the chips that have completed testing.

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