Board-to-board type core board interface fault detection and state visualization method

Abstract

The invention relates to a board-to-board type core board interface fault detection and state visualization method, provides machine learning, and belongs to the field of electrical digital data process.The method comprises the steps that an interface fault intelligent detection model of any to-be-detected interface is adopted at an auxiliary function unit on a bottom board; according to the multi-source fault detection basic data of any to-be-detected interface, intelligently detecting a fault type of any to-be-detected interface and a fault type of a core board in a set time segment; and executing visual interface display of each fault type. Aiming at the technical problems that an industrial-grade core board detection mechanism excessively depends on manpower, the state information is invisible, the test efficiency is low and the test deployment cost is high, different interface fault intelligent detection models and different multi-source fault detection basic data are introduced for different interfaces respectively; therefore, one-by-one intelligent detection of fault types of the external interfaces of the core board is completed, and the technical problem is solved.

Description

Technical Field

[0001] The machine learning proposed in this invention relates to the field of electronic digital data processing, and in particular to a method for fault detection and status visualization of board-to-board core board interface. Background Technology

[0002] With the introduction of AI technology, traditional manual fault detection methods are gradually being replaced by intelligent and automated fault detection systems, significantly improving detection efficiency and accuracy. The artificial intelligence models used in these intelligent and automated fault detection systems require massive amounts of machine learning to ensure that fault detection results meet expectations. Specifically, for fault detection of various circuit boards, the learning data used in the machine learning process and the basic data used in the actual fault detection are all types of electrical digital data associated with the circuit board. Therefore, intelligent and automated fault detection actually involves the processing of electrical digital data from the circuit board.

[0003] For example, Chinese invention patent publication CN118584309A proposes a rapid intelligent fault diagnosis method, system, and storage medium for circuit boards. It collects image data of the circuit board when it is not in operation and performs grayscale processing to identify pseudo-faulty circuit boards and the circuit board under test. It then collects temperature data (WD), current data (DL), and magnetic field strength data (CC) of the circuit board under test when it is in operation and calculates a judgment value P to identify normal circuit boards, short-circuit faulty circuit boards, and open-circuit faulty circuit boards. This application first performs an appearance inspection of the circuit board, then performs a state inspection during operation. Based on the state during operation, it determines the direction of the problem. Then, based on the type of fault, it analyzes the magnetic field image to determine the specific cause of the problem. This eliminates the need to perform magnetic field image analysis on every circuit board, reducing the computational difficulty of the analysis and improving the efficiency of circuit board fault detection.

[0004] For example, Chinese invention patent publication CN121091032A discloses an intelligent circuit board fault detection system. This invention designs a detection system that meets the functions of circuit fault detection, supporting human-computer interaction display, rapid circuit board fault location, and recording and viewing of detection data. To meet the intelligent requirements, the detection system disclosed in this application has a human-computer interaction module, through which the data processing module can interact with the user. Simultaneously, the detection system disclosed in this application has a data storage module and a wireless communication module, allowing users to view recorded detection information on the interactive interface or other terminals. To address the requirement of rapid circuit board fault location, the detection system disclosed in this application employs a rapid circuit board fault detection strategy with low data computation requirements, making it suitable for rapid circuit board fault location.

[0005] Therefore, it is evident that the intelligent testing solutions for circuit boards involved in the aforementioned existing technologies have limited intelligence levels and cannot address complex and specific circuit boards by designing targeted automated and intelligent fault detection mechanisms. For example, they cannot handle the specific hardware environment formed by industrial-grade core board modules and baseboards connected by board-to-board connectors, nor can they perform automated and intelligent testing and automatic display operations on each interface of the core board module through the baseboard. This results in the lack of a dedicated intelligent fault detection mechanism for board-to-board industrial-grade core board modules in the existing technologies, and fails to solve the technical problems of board-to-board industrial-grade core board module testing mechanisms being overly reliant on manual labor, lacking visible status information, having low testing efficiency, and high testing deployment costs. Summary of the Invention

[0006] To address technical challenges in related fields, this invention provides a board-to-board core board interface fault detection and status visualization method. Facing a specific hardware environment comprised of an industrial-grade core board module and a baseboard connected via a board-to-board connector, while maintaining the manual fault type detection function by connecting test cables and test modules to the baseboard's communication interface unit, an intelligent fault type detection mechanism is introduced. This mechanism enables synchronous intelligent detection of fault types present in any interface to be tested and in the core board within a set time segment, and automatically displays the synchronous intelligent detection results on-site. Crucially, by designing different customized intelligent fault detection models for different interfaces to be tested and introducing different multi-source fault detection base data for different interfaces, the stable and reliable execution of intelligent detection is ensured. This achieves automated and intelligent detection and automatic display of each interface external to the baseboard, giving the core board automated detection and visualization capabilities.

[0007] According to the present invention, a method for fault detection and status visualization of board-to-board core board interface is provided, the method comprising:

[0008] The auxiliary function unit on the base plate receives the current interface to be tested as determined by the user and establishes an intelligent detection model for the interface fault corresponding to the current interface to be tested. The current interface to be tested is any bidirectional communication interface in the communication interface unit on the base plate.

[0009] Access the core board through the auxiliary function unit to obtain various configuration information of the interface under test, communication data of the interface under test in each past time segment before the set time segment, key operating parameters of the core board at the start of the set time segment, and the duration of each time segment, and use them as the basic data for multi-source fault detection of the interface under test.

[0010] At the auxiliary function unit, the interface fault intelligent detection model corresponding to the current interface to be detected is adopted. Based on the multi-source fault detection basic data of the current interface to be detected, the fault type of the current interface to be detected and the fault type of the core board are intelligently detected within a set time segment.

[0011] The display screen is connected to any one-way communication interface in the communication interface unit to perform a visual interface display of various fault types obtained by intelligent detection;

[0012] Among them, the intelligent detection model for interface faults corresponding to the interface to be detected is a deep neural network that has been learned multiple times;

[0013] The core board is a board-to-board core board, and the baseboard is connected to the core board via a board-to-board connector and includes a communication interface unit, an auxiliary function unit, and a power management unit. The communication interface unit includes a bidirectional communication interface and a unidirectional passage interface.

[0014] Compared with the prior art, the present invention has at least the following outstanding substantive features:

[0015] Substantive Feature A: For specific hardware environments consisting of industrial-grade core board modules and baseboards connected by board-to-board connectors, while maintaining the communication interface unit for connecting test cables and test modules to the baseboard to perform manual fault type detection, an intelligent fault type detection mechanism is introduced to perform synchronous intelligent detection of fault types present in any interface to be tested and fault types present in the core board within a set time segment, and to automatically display the synchronous intelligent detection results on-site. This completes the automated and intelligent detection operation and automatic display operation of each interface of the core board through the baseboard, giving the core board automated detection capability and visualization expression capability.

[0016] Substantive Feature B: When performing synchronous intelligent detection of fault types in any interface to be tested and fault types in the core board within a set time segment, different customized intelligent detection models for interface faults are designed for different interfaces to be tested. The intelligent detection model for the current interface to be tested, as determined by the user, is a deep neural network that has undergone multiple learning iterations. Crucially, the number of learning iterations of the deep neural network is positively correlated with the number of pins in the current interface to be tested, and the number of hidden layers in the deep neural network is proportional to the transmission bandwidth of the current interface to be tested. The deep neural network has a single input layer, various hidden layers, and a single output layer connected in sequence. Both the single input layer and the single output layer use the Sigmoid function as the activation function, and each hidden layer uses the ReLU function as the activation function. The different customized intelligent detection models for interface faults designed for different interfaces to be tested ensure the stability and reliability of the intelligent detection results.

[0017] Substantive Feature C: In each learning iteration of the deep neural network, the known fault types of the current interface under test and the fault types of the core board within a certain past time segment are used as the output content of the deep neural network. The configuration information of the current interface under test, the communication data of the current interface under test in each past time segment before the current past time segment, the key operating parameters of the core board at the start time of the current past time segment, and the duration of each time segment are used as the input content of the deep neural network to complete the learning, thereby ensuring the learning effect of each iteration of the deep neural network.

[0018] Substantive Feature D: When performing synchronous intelligent detection of fault types existing in any interface to be tested and fault types existing in the core board within a set time segment, multi-source fault detection basic data of any interface to be tested is introduced, including various configuration information of any interface to be tested, various communication data of any interface to be tested in previous time segments before the set time segment, various key operating parameters of the core board at the start time of the set time segment, and the duration of each time segment. The comprehensive and sufficient selection of the above multi-source fault detection basic data further ensures the stability and reliability of the intelligent detection results.

[0019] Substantive Feature E: Specifically, the configuration information of any interface to be tested includes the interface type encoding value, interface voltage, communication rate, connection medium type encoding value, communication protocol type encoding value, sampling period, and maximum buffer capacity of any interface to be tested. The key operating parameters of the core board at the start of the set time segment include the CPU utilization rate, memory occupancy rate, CPU temperature, ambient temperature, current timestamp, and internal clock accuracy of the core board at the start of the set time segment. The single communication data of any interface to be tested in each time segment is the binary representation of the data stream successfully transmitted by any interface to be tested within the time segment. This provides a customized data structure for the basic data of multi-source fault detection of any interface to be tested. Attached Figure Description

[0020] The embodiments of the present invention will now be described with reference to the accompanying drawings, wherein:

[0021] Figure 1 This is a schematic diagram of the internal structure of the core board used in the board-to-board core board interface fault detection and status visualization method according to the present invention.

[0022] Figure 2 This is a schematic diagram of the internal structure of the base plate used in a board-to-board core board interface fault detection and status visualization method according to the present invention.

[0023] Figure 3 This is a flowchart illustrating the steps of a board-to-board core board interface fault detection and status visualization method according to Embodiment 1 of the present invention.

[0024] Figure 4 The present invention is illustrated in Embodiment 2 of the present invention as a flowchart of a board-to-board core board interface fault detection and status visualization method.

[0025] Figure 5 This is a flowchart illustrating the steps of a board-to-board core board interface fault detection and status visualization method according to Embodiment 3 of the present invention.

[0026] Figure 6 This is a flowchart illustrating the steps of a board-to-board core board interface fault detection and status visualization method according to Embodiment 4 of the present invention.

[0027] Figure 7 This is a flowchart illustrating the steps of a board-to-board core board interface fault detection and status visualization method according to Embodiment 5 of the present invention. Detailed Implementation

[0028] like Figure 1As shown, a schematic diagram of the internal structure of the core board used in the board-to-board core board interface fault detection and status visualization method according to the present invention is presented. Figure 2 The diagram shows the internal structure of the baseboard used in a board-to-board core board interface fault detection and status visualization method according to the present invention.

[0029] exist Figures 1 to 2 In this design, the core board is an industrial-grade core board module, and it is connected to the baseboard via a board-to-board connector, enabling the external placement of all interfaces of the core board at the baseboard location. The machine learning proposed in this invention relates to the field of electronic digital data processing.

[0030] The specific technical process of this invention is as follows:

[0031] Technical Process 1: For the core board, when performing synchronous intelligent detection of the fault types of any interface to be tested within a set time segment and the fault types of the core board, design different customized intelligent detection models for interface faults for different interfaces to be tested.

[0032] Specifically, the user determines the current interface to be tested through operation, and an intelligent interface fault detection model is designed for the current interface to be tested. The customized structural design is mainly reflected in the following aspects:

[0033] First: The intelligent interface fault detection model designed for the current interface to be detected is a deep neural network that has undergone multiple learning iterations;

[0034] Second: The number of times the deep neural network has been trained is positively correlated with the number of pins of the interface to be tested.

[0035] For example, when the number of pins of the interface to be tested is 3, the number of learning times is 600; when the number of pins of the interface to be tested is 5, the number of learning times is 1000; when the number of pins of the interface to be tested is 9, the number of learning times is 1800; when the number of pins of the interface to be tested is 21, the number of learning times is 4200, and so on.

[0036] Third: The number of hidden layers in the deep neural network used is directly proportional to the transmission bandwidth of the interface to be detected;

[0037] Specifically, the larger the transmission bandwidth of the interface to be detected, the more hidden layers are selected;

[0038] Fourth: The deep neural network used has a single input layer, hidden layers and a single output layer connected in sequence, and the single input layer and the single output layer both use the Sigmoid function as the activation function, and the hidden layers use the ReLU function as the activation function;

[0039] Fifth: In each learning process performed on the deep neural network, the known fault types of the current interface to be detected and the fault types of the core board within a certain past time segment are used as the output content of the deep neural network. The configuration information of the current interface to be detected, the communication data of the current interface to be detected in each past time segment before the certain past time segment, the key operating parameters of the core board at the start time of the certain past time segment, and the duration of each time segment are used as the input content of the deep neural network to complete the learning process, thereby ensuring the learning effect of each learning process of the deep neural network.

[0040] In this way, different customized intelligent detection models for interface faults can be designed for different interfaces to be tested, thereby ensuring the stability and reliability of the intelligent detection results.

[0041] Technical Process 2: For the core board, when performing synchronous intelligent detection of the fault types existing in the current interface to be tested and the fault types existing in the core board within a set time segment, multi-source fault detection basic data of the current interface to be tested is introduced.

[0042] Specifically, the basic data for multi-source fault detection of the current interface to be tested includes various configuration information of the current interface to be tested, various communication data of the current interface to be tested in each past time segment before the set time segment, various key operating parameters of the core board at the start of the set time segment, and the duration of each time segment.

[0043] More specifically, the configuration information of the interface under test includes the interface type encoding value, interface voltage, communication rate, connection medium type encoding value, communication protocol type encoding value, sampling period, and maximum buffer capacity. The key operating parameters of the core board at the start of the set time segment include the CPU utilization, memory occupancy, CPU temperature, ambient temperature, current timestamp, and internal clock accuracy of the core board at the start of the set time segment. The single communication data of the interface under test in each time segment is the binary representation of the data stream successfully transmitted by the interface under test within the time segment. This provides a customized data structure for the multi-source fault detection basic data of the interface under test.

[0044] In this way, the stability and reliability of the intelligent detection results are further guaranteed by the comprehensive and sufficient selection of the above-mentioned multi-source fault detection basic data;

[0045] Technical Process 3: For the core board, for the interface to be tested as determined by the user through operation, the interface fault intelligent detection model designed for the interface to be tested in Technical Process 1 is adopted. Based on the multi-source fault detection basic data of the interface to be tested introduced in Technical Process 2, the synchronous intelligent detection of the fault types of the interface to be tested and the fault types of the core board within the set time segment is completed.

[0046] Specifically, since the current interface to be tested can be selected by user operation or by automatic polling, and the time segment can also be set, it can intelligently detect the fault types of each interface to be tested on the core board within any time segment, as well as the fault types existing on the core board, thereby improving the automation and intelligence level of interface fault detection of industrial-grade core board modules.

[0047] Technical Process 4: Connect the display screen to any one-way communication interface in the core board's communication interface unit to execute the visualization interface display of various fault types obtained by intelligent detection in Technical Process 3;

[0048] Specifically, such as Figure 2 As shown, the board-to-board connector for the baseboard to the core board includes a communication interface unit, an auxiliary function unit, and a power management unit. The communication interface unit includes a bidirectional communication interface and a one-way communication interface. There are multiple bidirectional communication interfaces, which are the interface types to be detected. The one-way communication interface is the interface type used to perform display operations.

[0049] More specifically, at the auxiliary function unit on the base plate, the user can select from the following bidirectional communication interfaces: RS232, RS485, CAN, USB HOST, PCIE, TF card, 100Mbps Ethernet, and Gigabit Ethernet, to determine the current interface to be tested. Meanwhile, the unidirectional communication interface is either LVDS or MIPI DSI.

[0050] Technical Process 5: Connect the test cables and test modules to the communication interface unit of the baseboard to perform manual testing of the fault types existing in the current interface under test and the fault types existing in the core board within a set time segment, such as... Figure 2 As shown;

[0051] Specifically, the test cable is located between the communication interface unit of the test module and the baseboard;

[0052] In this way, manual detection of fault types can be completed, thereby achieving mutual verification between manual and automatic fault type detection.

[0053] Therefore, through the coordinated operation of the above-mentioned technical processes, for a specific hardware environment formed by the combination of industrial-grade core board modules and baseboards via board-to-board connectors, while maintaining the communication interface unit of the baseboard for manual fault type detection by connecting test cables and test modules, an intelligent fault type detection mechanism is introduced to complete the synchronous intelligent detection of fault types existing in any interface to be tested and the fault types existing in the core board within a set time segment, and to automatically display the synchronous intelligent detection results on site. This completes the automated and intelligent detection operation and automatic display operation of each interface of the core board through the baseboard, enabling the core board to have automated detection capabilities and visualization expression capabilities.

[0054] The key points of this invention are: the compatibility and mutual verification of manual and automatic fault detection under specific hardware environments; the directional design of intelligent fault detection models for different interfaces with different customized structures; the targeted introduction of different multi-source fault detection basic data for different interfaces; and the synchronous intelligent detection and real-time on-site display of fault types existing in the current interface under test and fault types existing in the core board.

[0055] The following will describe in detail, by way of an embodiment, a method for fault detection and status visualization of board-to-board core board interface according to the present invention.

[0056] Example 1

[0057] Figure 3 This is a flowchart illustrating the steps of a board-to-board core board interface fault detection and status visualization method according to Embodiment 1 of the present invention.

[0058] like Figure 3 As shown, the method for fault detection and status visualization of the board-to-board core board interface includes the following specific steps:

[0059] Step S301: Receive the currently detected interface determined by the user at the auxiliary function unit on the base plate, and establish an intelligent detection model for the interface fault corresponding to the currently detected interface. The currently detected interface is any bidirectional communication interface in the communication interface unit on the base plate.

[0060] Specifically, the board-to-board connector for the baseboard to connect to the core board includes a communication interface unit, an auxiliary function unit, and a power management unit. The core board is an industrial-grade core board module. The core board connects to the baseboard to enable the externalization of various interfaces of the core board.

[0061] More specifically, the communication interface unit includes a bidirectional communication interface and a one-way passage interface. There are multiple bidirectional communication interfaces, which are of the interface type to be detected, and the one-way passage interface is of the interface type used to perform display operations.

[0062] Step S302: Access the core board through the auxiliary function unit to obtain the configuration information of the interface under test, the communication data of the interface under test in each past time segment before the set time segment, the key operating parameters of the core board at the start time of the set time segment, and the duration of each time segment, and use them as the basic data for multi-source fault detection of the interface under test.

[0063] Specifically, the number of each previous time segment before the time segment is set is positively correlated with the number of pins of the current interface to be tested;

[0064] For example, the number of pins of the interface to be tested is 3, the number of pins of each previous time segment before the set time segment is 6, the number of pins of the interface to be tested is 5, the number of pins of each previous time segment before the set time segment is 10, the number of pins of the interface to be tested is 9, the number of pins of each previous time segment before the set time segment is 18, the number of pins of the interface to be tested is 21, the number of pins of each previous time segment before the set time segment is 42, and so on;

[0065] For example, the duration of each time segment can be 2 minutes. The number of pins on the interface to be tested is 5, and the number of previous time segments before the current time segment is 10. When the current time segment is from 10:00 AM to 10:02 AM, the previous time segments before the current time segment are 9:58 AM to 10:00 AM, 9:56 AM to 9:58 AM, 9:54 AM to 9:56 AM, 9:52 AM to 9:54 AM, 9:50 AM to 9:52 AM, 9:48 AM to 9:50 AM, 9:46 AM to 9:48 AM, 9:44 AM to 9:46 AM, 9:42 AM to 9:44 AM, and 9:40 AM to 9:42 AM.

[0066] Therefore, in the example above, the starting time of the time segment is set to 10:00 AM.

[0067] Step S303: At the auxiliary function unit, the interface fault intelligent detection model corresponding to the current interface to be detected is adopted. Based on the multi-source fault detection basic data of the current interface to be detected, the fault types of the current interface to be detected and the fault types of the core board are intelligently detected within the set time segment.

[0068] Specifically, different fault types correspond to different fault type code values. At the same time, even if the same time segment is selected, different interfaces to be detected will have different multi-source fault detection base data.

[0069] Step S304: Connect the display screen using any one-way access interface in the communication interface unit to perform a visual interface display of each fault type obtained by intelligent detection;

[0070] For example, the display screen is connected to any one-way access interface in the communication interface unit to perform a visualization interface display of various fault types obtained by intelligent detection, including: the display screen is a liquid crystal display screen, an LCD display array, or an LCD display array;

[0071] Among them, the intelligent detection model for interface faults corresponding to the interface to be detected is a deep neural network that has been learned multiple times;

[0072] Among them, the core board is a board-to-board core board, and the base plate is connected to the board-to-board connector of the core board and includes a communication interface unit, an auxiliary function unit and a power management unit. The communication interface unit includes a bidirectional communication interface and a unidirectional passage interface.

[0073] Specifically, such as Figure 2 As shown, the power management unit is connected to the communication interface unit and the auxiliary function unit respectively, and is used to supply power to the communication interface unit and the auxiliary function unit respectively;

[0074] Among them, the fault types of the interface to be tested include clock loss fault, open circuit fault, short circuit fault, surge fault, abnormal temperature fault, strong magnetic field fault, poor pin contact fault and no fault type. The fault types of the core board include memory leak, overheating and frequency reduction and no fault type.

[0075] The configuration information of the interface under test includes the interface type encoding value, interface voltage, communication rate, connection medium type encoding value, communication protocol type encoding value, sampling period, and maximum buffer capacity of the interface under test. The key operating parameters of the core board at the start of the set time segment include the CPU utilization rate, memory occupancy rate, CPU temperature, ambient temperature, current timestamp, and internal clock accuracy of the core board at the start of the set time segment. The single communication data of the interface under test in each time segment is the binary representation of the data stream successfully transmitted by the interface under test in the time segment.

[0076] For example, the interface type encoding value, interface voltage, communication rate, connection medium type encoding value, communication protocol type encoding value, sampling period, and maximum buffer capacity of the interface to be tested can all be represented by binary values.

[0077] Similarly, the key operating parameters of the core board at the start of the set time segment, including the CPU utilization, memory occupancy, CPU temperature, ambient temperature, current timestamp, and internal clock precision at the start of the set time segment, can also be represented by binary values.

[0078] The communication interface unit includes bidirectional communication interfaces and unidirectional communication interfaces. The communication interface unit includes RS232 interface, RS485 interface, CAN interface, USB HOST interface, PCIE interface, TF card interface, 100M Ethernet interface and Gigabit Ethernet interface, which are all bidirectional communication interfaces, and also includes LVDS interface and MIPI DSI interface, which are all unidirectional communication interfaces.

[0079] The auxiliary function unit includes LED indicator lights, mechanical buttons and programmable logic devices. The programmable logic devices are used to establish an intelligent detection model for the interface fault corresponding to the current interface to be tested.

[0080] For example, users can select one interface from the bidirectional communication interfaces as the current interface to be tested via mechanical buttons, or they can use automatic polling to traverse each bidirectional communication interface of the communication interface unit to perform intelligent fault detection for each interface. The one-way communication interface in the communication interface unit is used to perform on-site display of the fault detection results.

[0081] Among them, the intelligent detection model for interface faults corresponding to the current interface to be detected is a deep neural network that has undergone multiple learning processes, including: the number of times the deep neural network has undergone learning is positively correlated with the number of pins of the current interface to be detected;

[0082] For example, the number of times the deep neural network has been trained is positively correlated with the number of pins of the current interface to be tested, including: when the number of pins of the current interface to be tested is 3, the number of training times is 600; when the number of pins of the current interface to be tested is 5, the number of training times is 1000; when the number of pins of the current interface to be tested is 9, the number of training times is 1800; when the number of pins of the current interface to be tested is 21, the number of training times is 4200, and so on.

[0083] Among them, the intelligent detection model for interface faults corresponding to the current interface to be detected is a deep neural network that has been learned multiple times. It also includes: the deep neural network used has a single input layer, a single output layer and various hidden layers, and the number of hidden layers is proportional to the transmission bandwidth of the current interface to be detected, and each hidden layer uses the ReLU function as the activation function.

[0084] Specifically, the number of hidden layers is proportional to the transmission bandwidth of the current interface to be detected, including: the larger the transmission bandwidth of the current interface to be detected, the more hidden layers are selected;

[0085] In each learning iteration of the deep neural network, the known fault types of the current interface to be detected and the fault types of the core board within a certain past time segment are used as the outputs of the deep neural network. The configuration information of the current interface to be detected, the communication data of the current interface to be detected in each past time segment before the current past time segment, the key operating parameters of the core board at the start time of the current past time segment, and the duration of each time segment are used as the inputs of the deep neural network to complete this learning iteration.

[0086] For example, a numerical simulation mode can be selected to test and simulate each learning process performed on the deep neural network used.

[0087] Example 2

[0088] Figure 4 The present invention is illustrated in Embodiment 2 of the present invention as a flowchart of a board-to-board core board interface fault detection and status visualization method.

[0089] like Figure 4 As shown, with Figure 3 Unlike the embodiments described above, in the board-to-board core board interface fault detection and status visualization method, after connecting the display screen using any one-way communication interface in the communication interface unit to perform the visualization interface display of various fault types obtained by intelligent detection, that is, after step S304, the method further includes:

[0090] Step S305: Connect the test cable and test module to the communication interface unit of the baseboard to perform manual detection of the fault types of the current interface to be tested and the fault types of the core board within the set time segment;

[0091] The process of connecting the test cable and test module to the communication interface unit of the baseboard for manually detecting the fault types of the current interface to be tested and the fault types of the core board within a set time segment includes: the test cable is located between the test module and the communication interface unit of the baseboard;

[0092] Specifically, connecting the test cables and test modules to the communication interface unit of the baseboard to perform manual detection of the fault types existing in the current interface to be tested and the fault types existing in the core board within a set time segment also includes: selecting different types of test cables according to different test modules, connecting the test template to the test cables, and then connecting the test cables to the communication interface unit of the baseboard.

[0093] Example 3

[0094] Figure 5 This is a flowchart illustrating the steps of a board-to-board core board interface fault detection and status visualization method according to Embodiment 3 of the present invention.

[0095] like Figure 5 As shown, with Figure 3 Unlike the embodiments described above, in the board-to-board core board interface fault detection and status visualization method, after connecting the display screen using any one-way communication interface in the communication interface unit to perform the visualization interface display of various fault types obtained by intelligent detection, that is, after step S304, the method further includes:

[0096] Step S306: Delete the interface fault intelligent detection model corresponding to the current interface to be detected in the auxiliary function unit on the base plate to release the physical storage space occupied by the interface fault intelligent detection model corresponding to the current interface to be detected.

[0097] The step of deleting the intelligent detection model of the interface fault corresponding to the current interface to be detected in the auxiliary function unit on the base plate to release the physical storage space occupied by the intelligent detection model of the interface fault corresponding to the current interface to be detected includes: setting a dynamic caching device in the auxiliary function unit on the base plate to cache the intelligent detection model of the interface fault corresponding to the current interface to be detected.

[0098] For example, a dynamic caching device is provided in the auxiliary function unit on the base plate to cache the intelligent detection model of the interface fault corresponding to the current interface to be detected. This includes using different physical storage addresses of the dynamic caching device to store the various model parameters of the intelligent detection model of the interface fault corresponding to the current interface to be detected.

[0099] Example 4

[0100] Figure 6 This is a flowchart illustrating the steps of a board-to-board core board interface fault detection and status visualization method according to Embodiment 4 of the present invention.

[0101] like Figure 6 As shown, with Figure 3Unlike the previous embodiment, in the board-to-board core board interface fault detection and status visualization method, the user-determined current interface to be detected is received at the auxiliary function unit on the baseboard, and an intelligent fault detection model corresponding to the current interface to be detected is established. Before the current interface to be detected is any bidirectional communication interface in the communication interface unit on the baseboard, that is, before step S301, the method further includes:

[0102] Step S307: On the auxiliary function unit on the base plate, determine the current interface to be tested from the RS232 interface, RS485 interface, CAN interface, USB HOST interface, PCIE interface, TF card interface, 100M Ethernet interface and Gigabit Ethernet interface, which are all bidirectional communication interfaces, according to the user's selection operation;

[0103] Specifically, the process of determining the interface to be detected in the auxiliary function unit on the base plate based on the user's selection operation includes: the user completing the selection operation by manipulating the mechanical buttons on the auxiliary function unit.

[0104] For example, the user's selection operation is completed by manipulating the mechanical buttons at the auxiliary function unit, including: there is one or more mechanical buttons at the auxiliary function unit, for example, a mechanical keyboard array.

[0105] Example 5

[0106] Figure 7 This is a flowchart illustrating the steps of a board-to-board core board interface fault detection and status visualization method according to Embodiment 5 of the present invention.

[0107] like Figure 7 As shown, with Figure 3 Unlike the previous embodiment, in the board-to-board core board interface fault detection and status visualization method, the user-determined current interface to be detected is received at the auxiliary function unit on the baseboard, and an intelligent fault detection model corresponding to the current interface to be detected is established. After the current interface to be detected is any bidirectional communication interface in the communication interface unit on the baseboard, that is, after step S301, the method further includes:

[0108] Step S308: Receive the intelligent detection model of the interface fault corresponding to the current interface to be detected, and store the intelligent detection model of the interface fault corresponding to the current interface to be detected into the dynamic cache device set in the auxiliary function unit;

[0109] The process of receiving the intelligent detection model of the interface fault corresponding to the current interface to be detected and storing the intelligent detection model of the interface fault corresponding to the current interface to be detected into the dynamic cache device set in the auxiliary function unit includes: storing the various model parameters of the intelligent detection model of the interface fault corresponding to the current interface to be detected to complete the model storage of the intelligent detection model of the interface fault corresponding to the current interface to be detected.

[0110] For example, the method of receiving the intelligent detection model of the interface fault corresponding to the current interface to be detected and storing the intelligent detection model of the interface fault corresponding to the current interface to be detected in the dynamic cache device set at the auxiliary function unit further includes: the dynamic cache device is an SDRAM chip.

[0111] Next, the various method embodiments of the present invention will be described in detail.

[0112] In a board-to-board core board interface fault detection and status visualization method according to various embodiments of the present invention:

[0113] The core board is a board-to-board industrial-grade core board module. The core board uses Rockchip Electronics' RK3562J processor as the main control processor and integrates EMMC flash memory, DDR memory and PMIC power management chip.

[0114] For example, the core board runs an embedded Linux operating system, which consists of uboot, kernel and root file system, and is persistently stored in the EMMC flash memory chip. After the core board is powered on, the PMIC power management chip provides independent power to the CPU main controller, EMMC flash memory and DDR memory. Then the main controller loads the system firmware from the EMMC flash memory to the DDR memory for startup.

[0115] In the baseboard, the power management unit receives an external input DC power supply of 12V / 1A. The external input DC power supply of 12V / 1A is converted into 5V, 3.3V and 1.8V power supplies by the DC-DC and LDO voltage regulation circuits inside the baseboard. The communication interface unit is an interface resource for the RK3562J processor and is led out through the board-to-board connector.

[0116] In a board-to-board core board interface fault detection and status visualization method according to various embodiments of the present invention:

[0117] At the auxiliary function unit, the interface fault intelligent detection model corresponding to the current interface to be tested is adopted. Based on the multi-source fault detection basic data of the current interface to be tested, the intelligent detection of the fault types of the current interface to be tested and the fault types of the core board within the set time segment includes: inputting the multi-source fault detection basic data of the current interface to be tested into the interface fault intelligent detection model corresponding to the current interface to be tested.

[0118] Among them, the auxiliary function unit adopts the interface fault intelligent detection model corresponding to the interface to be detected. Based on the multi-source fault detection basic data of the interface to be detected, the intelligent detection of the fault types of the interface to be detected and the fault types of the core board within the set time segment also includes: running the interface fault intelligent detection model corresponding to the interface to be detected to obtain the fault types of the interface to be detected and the fault types of the core board within the set time segment output by the interface fault intelligent detection model corresponding to the interface to be detected.

[0119] Among them, the multi-source fault detection basic data of the current interface to be detected is subjected to numerical normalization processing before being input into the interface fault intelligent detection model corresponding to the current interface to be detected. The fault types of the current interface to be detected and the fault types of the core board output by the interface fault intelligent detection model corresponding to the current interface to be detected within the set time segment are both numerical representations after numerical normalization processing.

[0120] For example, before the multi-source fault detection basic data of the current interface to be detected is input into the interface fault intelligent detection model corresponding to the current interface to be detected, it undergoes numerical normalization processing. The fault types of the current interface to be detected and the fault types of the core board output by the interface fault intelligent detection model corresponding to the current interface to be detected within a set time segment are both numerically represented after numerical normalization processing. This includes: before the multi-source fault detection basic data of the current interface to be detected is input into the interface fault intelligent detection model corresponding to the current interface to be detected, it undergoes binary numerical conversion processing. The fault types of the current interface to be detected and the fault types of the core board output by the interface fault intelligent detection model corresponding to the current interface to be detected within a set time segment are both numerically represented after binary numerical conversion processing.

[0121] And in a board-to-board core board interface fault detection and status visualization method according to various method embodiments of the present invention:

[0122] The auxiliary function unit includes LED indicator lights, mechanical buttons, and editable logic devices. The editable logic devices are used to establish an intelligent detection model for the interface fault corresponding to the current interface to be tested. The editable logic devices are FPGA chips, and the FPGA chips are designed and edited using VHDL language.

[0123] The auxiliary function unit on the base plate receives the current interface to be tested as determined by the user and establishes an intelligent detection model for the interface fault corresponding to the current interface to be tested. The current interface to be tested is any bidirectional communication interface in the communication interface unit on the base plate, including: different communication interface units have different interface encoding values.

[0124] For example, different communication interface units may have different interface encoding values, including: the different interface encoding values ​​are different binary values ​​with the same number of bits.

[0125] In addition, the following technical content can be cited to further highlight the essential features of the present invention:

[0126] The positive correlation between the number of times the deep neural network has been trained and the number of pins of the current interface to be tested includes: using a numerical conversion function to represent the numerical conversion relationship between the number of times the deep neural network has been trained and the number of pins of the current interface to be tested;

[0127] In the numerical conversion function, the number of pins of the current interface to be detected is the input value of the numerical conversion function, and the number of times the deep neural network used, which is positively correlated with the number of pins of the current interface to be detected, has been trained is the output value of the numerical conversion function.

[0128] For example, using a numerical transformation function to represent the positive correlation between the number of times the deep neural network has been trained and the number of pins of the current interface to be tested includes: the test and simulation of the data processing process of using a numerical transformation function to represent the positive correlation between the number of times the deep neural network has been trained and the number of pins of the current interface to be tested can be implemented using the MATLAB toolbox;

[0129] The deep neural network used has a single input layer, a single output layer, and various hidden layers. The number of hidden layers is proportional to the transmission bandwidth of the interface to be detected. Each hidden layer uses the ReLU function as its activation function. The hidden layers are located between the single input layer and the single output layer, and both the single input layer and the single output layer use the Sigmoid function as their activation function.

[0130] Although various embodiments of the invention have been shown and described, those skilled in the art will understand that various other modifications can be made and equivalents can be substituted without departing from the true scope of the invention. Furthermore, many modifications can be made to make a particular situation suitable for the teachings of the invention without departing from the concept of the invention described herein. Therefore, the invention is not limited to the specific embodiments disclosed, but rather includes all embodiments falling within the scope of the appended claims.

Claims

1. A method for fault detection and status visualization of board-to-board core board interfaces, characterized in that, The method includes: The auxiliary function unit on the base plate receives the current interface to be tested as determined by the user and establishes an intelligent detection model for the interface fault corresponding to the current interface to be tested. The current interface to be tested is any bidirectional communication interface in the communication interface unit on the base plate. Access the core board through the auxiliary function unit to obtain various configuration information of the interface under test, communication data of the interface under test in each past time segment before the set time segment, key operating parameters of the core board at the start of the set time segment, and the duration of each time segment, and use them as the basic data for multi-source fault detection of the interface under test. At the auxiliary function unit, the interface fault intelligent detection model corresponding to the current interface to be detected is adopted. Based on the multi-source fault detection basic data of the current interface to be detected, the fault type of the current interface to be detected and the fault type of the core board are intelligently detected within a set time segment. The display screen is connected to any one-way communication interface in the communication interface unit to perform a visual interface display of various fault types obtained by intelligent detection; Among them, the intelligent detection model for interface faults corresponding to the interface to be detected is a deep neural network that has been learned multiple times; The core board is a board-to-board core board, and the baseboard is connected to the core board via a board-to-board connector and includes a communication interface unit, an auxiliary function unit, and a power management unit. The communication interface unit includes a bidirectional communication interface and a unidirectional passage interface.

2. The method for fault detection and status visualization of board-to-board core board interface as described in claim 1, characterized in that: The fault types currently present in the interfaces under test include clock loss fault, open circuit fault, short circuit fault, surge fault, abnormal temperature fault, strong magnetic field fault, poor pin contact fault, and no fault type. The fault types present in the core board include memory leak, overheating and frequency reduction, and no fault type. The configuration information of the interface under test includes the interface type encoding value, interface voltage, communication rate, connection medium type encoding value, communication protocol type encoding value, sampling period, and maximum buffer capacity of the interface under test. The key operating parameters of the core board at the start of the set time segment include the CPU utilization rate, memory occupancy rate, CPU temperature, ambient temperature, current timestamp, and internal clock accuracy of the core board at the start of the set time segment. The single communication data of the interface under test in each time segment is the binary representation of the data stream successfully transmitted by the interface under test in the time segment. The communication interface unit includes bidirectional communication interfaces and unidirectional communication interfaces. The communication interface unit includes RS232 interface, RS485 interface, CAN interface, USB HOST interface, PCIE interface, TF card interface, 100M Ethernet interface and Gigabit Ethernet interface, all of which are bidirectional communication interfaces. It also includes LVDS interface and MIPI DSI interface, both of which are unidirectional communication interfaces. The auxiliary function unit includes LED indicators, mechanical buttons, and programmable logic devices. The programmable logic devices are used to establish an intelligent detection model for the interface fault corresponding to the current interface to be tested.

3. The method for fault detection and status visualization of board-to-board core board interface as described in claim 2, characterized in that: The intelligent fault detection model for the interface to be tested is a deep neural network that has undergone multiple learning iterations, including: the number of times the deep neural network has been learned is positively correlated with the number of pins of the interface to be tested. Among them, the intelligent detection model for interface faults corresponding to the current interface to be detected is a deep neural network that has been learned multiple times. It also includes: the deep neural network used has a single input layer, a single output layer and various hidden layers, and the number of hidden layers is proportional to the transmission bandwidth of the current interface to be detected, and each hidden layer uses the ReLU function as the activation function. In each learning iteration of the deep neural network, the known fault types of the current interface under test and the fault types of the core board within a certain past time segment are used as the outputs of the deep neural network. The configuration information of the current interface under test, the communication data of the current interface under test in each past time segment before the current past time segment, the key operating parameters of the core board at the start of the current past time segment, and the duration of each time segment are used as the inputs of the deep neural network to complete the learning process.

4. The method for fault detection and status visualization of board-to-board core board interface as described in claim 3, characterized in that, After connecting the display screen using any one-way communication interface in the communication interface unit to perform a visual interface display of various fault types obtained by intelligent detection, the method further includes: Connect the test cables and test modules to the communication interface unit of the baseboard to perform manual testing of the fault types of the current interface to be tested and the fault types of the core board within a set time segment; The process of connecting the test cable and test module to the communication interface unit of the baseboard for manually detecting the fault types of the current interface to be tested and the fault types of the core board within a set time segment includes: the test cable is located between the test module and the communication interface unit of the baseboard.

5. The method for fault detection and status visualization of board-to-board core board interface as described in claim 3, characterized in that, After connecting the display screen using any one-way communication interface in the communication interface unit to perform a visual interface display of various fault types obtained by intelligent detection, the method further includes: Delete the intelligent detection model of the interface fault corresponding to the current interface to be detected in the auxiliary function unit on the base plate to release the physical storage space occupied by the intelligent detection model of the interface fault corresponding to the current interface to be detected. The step of deleting the intelligent detection model of the interface fault corresponding to the current interface to be tested in the auxiliary function unit on the base plate to release the physical storage space occupied by the intelligent detection model of the interface fault corresponding to the current interface to be tested includes: setting a dynamic caching device in the auxiliary function unit on the base plate to cache the intelligent detection model of the interface fault corresponding to the current interface to be tested.

6. The method for fault detection and status visualization of board-to-board core board interface as described in claim 3, characterized in that, The method further includes receiving the currently detected interface as determined by the user at the auxiliary function unit on the base plate, and establishing an intelligent interface fault detection model corresponding to the currently detected interface. Before the currently detected interface is any bidirectional communication interface in the communication interface unit on the base plate, the method also includes: Based on the user's selection, the auxiliary function unit on the base plate determines the current interface to be tested from among the following bidirectional communication interfaces: RS232, RS485, CAN, USB HOST, PCIE, TF card, 100Mbps Ethernet, and Gigabit Ethernet. Specifically, the process of determining the interface to be detected in the auxiliary function unit on the base plate based on the user's selection operation includes: the user completing the selection operation by manipulating the mechanical buttons on the auxiliary function unit. This process involves selecting the interface from among the following bidirectional communication interfaces: RS232, RS485, CAN, USB HOST, PCIE, TF card, 100Mbps Ethernet, and Gigabit Ethernet.

7. The method for fault detection and status visualization of board-to-board core board interface as described in claim 3, characterized in that, The method further includes receiving the currently detected interface as determined by the user at the auxiliary function unit on the base plate, and establishing an intelligent interface fault detection model corresponding to the currently detected interface. After the currently detected interface is any bidirectional communication interface in the communication interface unit on the base plate, the method also includes: Receive the intelligent detection model of the interface fault corresponding to the current interface to be detected, and store the intelligent detection model of the interface fault corresponding to the current interface to be detected into the dynamic cache device set in the auxiliary function unit; The process of receiving the intelligent detection model of the interface fault corresponding to the current interface to be detected and storing the intelligent detection model of the interface fault corresponding to the current interface to be detected into the dynamic cache device set in the auxiliary function unit includes: storing the various model parameters of the intelligent detection model of the interface fault corresponding to the current interface to be detected to complete the model storage of the intelligent detection model of the interface fault corresponding to the current interface to be detected.

8. A method for fault detection and status visualization of a board-to-board core board interface as described in any one of claims 3-7, characterized in that: The core board is a board-to-board industrial-grade core board module. The core board uses Rockchip Electronics' RK3562J processor as the main control processor and integrates EMMC flash memory, DDR memory and PMIC power management chip. In the baseboard, the power management unit receives an external input DC power supply of 12V / 1A. The external input DC power supply of 12V / 1A is converted into 5V, 3.3V and 1.8V power supplies by the DC-DC and LDO voltage regulation circuits inside the baseboard. The communication interface unit is an interface resource for the RK3562J processor and is led out through the board-to-board connector.

9. A method for fault detection and status visualization of a board-to-board core board interface as described in any one of claims 3-7, characterized in that: At the auxiliary function unit, the interface fault intelligent detection model corresponding to the current interface to be tested is adopted. Based on the multi-source fault detection basic data of the current interface to be tested, the intelligent detection of the fault types of the current interface to be tested and the fault types of the core board within the set time segment includes: inputting the multi-source fault detection basic data of the current interface to be tested into the interface fault intelligent detection model corresponding to the current interface to be tested. Among them, the auxiliary function unit adopts the interface fault intelligent detection model corresponding to the interface to be detected. Based on the multi-source fault detection basic data of the interface to be detected, the intelligent detection of the fault types of the interface to be detected and the fault types of the core board within the set time segment also includes: running the interface fault intelligent detection model corresponding to the interface to be detected to obtain the fault types of the interface to be detected and the fault types of the core board within the set time segment output by the interface fault intelligent detection model corresponding to the interface to be detected. Among them, the multi-source fault detection basic data of the current interface to be detected is subjected to numerical normalization processing before being input into the interface fault intelligent detection model corresponding to the current interface to be detected. The fault types of the current interface to be detected and the fault types of the core board output by the interface fault intelligent detection model corresponding to the current interface to be detected within the set time segment are both numerical representations after numerical normalization processing.

10. A method for fault detection and status visualization of a board-to-board core board interface as described in any one of claims 3-7, characterized in that: The auxiliary function unit includes LED indicator lights, mechanical buttons, and editable logic devices. The editable logic devices are used to establish an intelligent detection model for the interface fault corresponding to the current interface to be tested. The editable logic devices are FPGA chips, and the FPGA chips are designed and edited using VHDL language. The auxiliary function unit on the base plate receives the current interface to be tested as determined by the user and establishes an intelligent detection model for the interface fault corresponding to the current interface to be tested. The current interface to be tested is any bidirectional communication interface in the communication interface unit on the base plate, including different communication interface units with different interface encoding values.

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