Dual-polarization three-dimensional Gray code GPR acquisition system

Abstract

The invention belongs to the technical field of ground penetrating radars, and particularly relates to a dual-polarization three-dimensional Gray code GPR acquisition system, which solves the technical problem that target information contained in echoes is limited when detection is performed in a single polarization mode, and comprises an FPGA (Field Programmable Gate Array) transmitting unit, a dual-polarization antenna array and an FPGA receiving unit, the FPGA transmitting unit comprises a transmitting end FPGA logic controller, a power amplifier, a power divider and a controllable delay circuit; the dual-polarized antenna array comprises at least two transmitting antennas in the orthogonal direction and two receiving antennas, a VV polarization channel and an HH polarization channel are formed, and co-polarized data acquisition is achieved through switching control. The FPGA receiving unit comprises N + 1 paths of front-end signal conditioning circuits, N + 1 paths of high-speed ADC acquisition circuits, a clock synchronization controller, a receiving end FPGA logic controller, a DDR3 data caching unit, a PCIe data uploading unit and an upper computer. According to the acquisition system, detection requirements of different precisions can be met at the same time, the profile data consistency is good, and the imaging and detection effects can be fully ensured.

Description

Technical Field

[0001] This invention relates to the field of ground penetrating radar technology, specifically to a dual-polarization three-dimensional Gray code GPR acquisition system. Background Technology

[0002] Ground-penetrating radar (GPR), a recognized non-destructive testing tool, has been widely used in the field of underground defect detection, especially in infrastructure and structural health monitoring. By using high-frequency electromagnetic waves, GPR can quickly and accurately acquire information about underground targets. The advantages of 3D GPR technology are becoming increasingly apparent: through high-density data acquisition and seamless stitching, it can provide comprehensive imaging of underground structures, avoiding omissions or biases, accurately presenting underground targets, and helping users conduct comprehensive underground defect analysis.

[0003] Currently, most three-dimensional ground-penetrating radar systems for detecting underground defects use a single polarization mode for detection. The echoes contain limited target information, resulting in inaccurate detection and failing to meet detection requirements. Summary of the Invention

[0004] To overcome the technical defect that the target information contained in the echo is limited when using a single polarization mode for detection, resulting in inaccurate detection, this invention provides a dual-polarization three-dimensional Gray code GPR acquisition system.

[0005] This invention provides a dual-polarization three-dimensional Gray code GPR acquisition system, characterized by comprising an FPGA transmitting unit for transmitting Gray complementary code radar signals, a dual-polarization antenna array, and an FPGA receiving unit for acquiring high-speed signals. The FPGA transmitting unit includes a transmitting-end FPGA logic controller, a power amplifier, a power divider, and a controllable delay circuit. The dual-polarization antenna array includes at least two orthogonal transmitting antennas and two receiving antennas, forming VV and HH polarization channels, which are switched by the transmitting-end FPGA logic controller to achieve co-polarization data acquisition. The FPGA receiving unit includes N+1 front-end signal conditioning circuits, N+1 high-speed ADC acquisition circuits, a clock synchronization controller, a receiving-end FPGA logic controller, a DDR3 data buffer unit, a PCIe data upload unit, and a host computer. The transmitting-end FPGA logic controller generates a pair of Gray complementary code sequences, A code and B code, which are transmitted in the order of A code followed by a fixed delay and then B code. The output of the transmitting-end FPGA logic controller is divided into two paths, one of which is connected to the controllable delay circuit to generate a reference Gray complementary code signal. The reference Gray complement code signal is sequentially input to the N+1th front-end signal conditioning circuit and the N+1th high-speed ADC acquisition circuit of the FPGA receiving unit for analog-to-digital conversion. The other output signal of the transmitting FPGA logic controller is amplified and then enters the power divider to generate N Gray complement code signals. The N Gray complement code signals are used to detect the current underground target in the same polarization through the VV polarization channel of the dual-polarized antenna array. After the detection is completed, the receiving antenna array corresponding to the VV polarization channel will transmit the echo signal back to the N front-end signal conditioning circuits and the N high-speed ADC acquisition circuits of the FPGA receiving unit for analog-to-digital conversion. The N+1 high-speed ADC acquisition circuits of the FPGA receiving unit are all connected to the clock synchronization controller. Each high-speed ADC acquisition circuit sends the digital signal after analog-to-digital conversion to the receiving FPGA logic controller according to a predetermined frame structure. The receiving FPGA logic controller parses and manages the received information and stores it in the DDR3 data cache unit. The receiving FPGA logic controller reads the cached data from the DDR3 data cache unit and transmits the data to the host computer through the PCIe data upload unit.

[0006] Preferably, in the Gray complementary code sequence, the fixed delay following the A code is 20~50µs. This avoids the superposition of sidelobe interference between the A code and the B code.

[0007] Preferably, each front-end signal conditioning circuit includes a low-noise amplifier, a variable gain amplifier, a bandpass filter, and a protection limiter connected in sequence.

[0008] Compared with the prior art, the technical solution provided by this invention has the following technical effects: This invention adopts a dual-polarization antenna array design, which can simultaneously meet different accuracy detection requirements for different polarization modes, and the profile data has good consistency, which can fully guarantee the imaging and detection effects; Gray complementary codes have good autocorrelation characteristics and a high peak-to-sidelobe ratio, which can significantly improve the signal-to-noise ratio of the signal, enhance the anti-interference ability and signal accuracy of the detection system in complex environments, and are very suitable for the detection of weakly reflective targets in complex environments. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0010] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of the overall structure of a dual-polarization three-dimensional Gray code GPR acquisition system according to a certain embodiment of the present invention;

[0012] Figure 2 This is a schematic diagram of the structure of the dual-polarized antenna array unit in a certain embodiment of the present invention. Detailed Implementation

[0013] To better understand the above-mentioned objectives, features, and advantages of the present invention, the solutions of the present invention will be further described below. It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other.

[0014] In this description, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances.

[0015] Many specific details are set forth in the following description in order to provide a full understanding of the invention, but the invention may also be practiced in other ways different from those described herein; obviously, the embodiments in the specification are only some embodiments of the invention, and not all embodiments.

[0016] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0017] In one embodiment, such as Figure 1 As shown, a dual-polarization three-dimensional Gray code GPR acquisition system is disclosed. It is characterized by comprising an FPGA transmitting unit for transmitting Gray complementary code radar signals, a dual-polarization antenna array, and an FPGA receiving unit for acquiring high-speed signals. The FPGA transmitting unit includes a transmitting-end FPGA logic controller, a power amplifier, a power divider, and a controllable delay circuit. The dual-polarization antenna array includes at least two orthogonal transmitting antennas and two receiving antennas, forming VV-polarization and HH-polarization channels, which are switched by the transmitting-end FPGA logic controller to achieve same-polarization data acquisition. The FPGA receiving unit includes N+1 front-end signal conditioning circuits, N+1 high-speed ADC acquisition circuits, a clock synchronization controller, a receiving-end FPGA logic controller, a DDR3 data buffer unit, a PCIe data upload unit, and a host computer. The transmitting-end FPGA logic controller generates a pair of Gray complementary code sequences, A code and B code, which are transmitted in the order of A code followed by a fixed delay and then B code. The output of the transmitting-end FPGA logic controller is divided into two paths, one of which is connected to the controllable delay circuit to generate a reference Gray complementary code signal. The reference Gray complement code signal is sequentially input to the N+1th front-end signal conditioning circuit and the N+1th high-speed ADC acquisition circuit of the FPGA receiving unit for analog-to-digital conversion. The other output signal of the transmitting FPGA logic controller is amplified and then enters the power divider to generate N Gray complement code signals. The N Gray complement code signals are used to detect the current underground target in the same polarization through the VV polarization channel of the dual-polarized antenna array. After the detection is completed, the receiving antenna array corresponding to the VV polarization channel will transmit the echo signal back to the N front-end signal conditioning circuits and the N high-speed ADC acquisition circuits of the FPGA receiving unit for analog-to-digital conversion. The N+1 high-speed ADC acquisition circuits of the FPGA receiving unit are all connected to the clock synchronization controller. Each high-speed ADC acquisition circuit sends the digital signal after analog-to-digital conversion to the receiving FPGA logic controller according to a predetermined frame structure. The receiving FPGA logic controller parses and manages the received information and stores it in the DDR3 data cache unit. The receiving FPGA logic controller reads the cached data from the DDR3 data cache unit and transmits the data to the host computer through the PCIe data upload unit.

[0018] A dual-polarized antenna array is used to transmit and receive dual-polarized radar detection signals. The A and B codes generated by the transmitter's FPGA logic controller have variable code lengths and adjustable rates. The transmitter's FPGA logic controller also generates polarization switching control signals to control the polarization mode. For millimeter-level cracks, which can be considered high-impedance dielectric anomalies, backscattering in the HH polarization mode is more sensitive than backscattering in the VV polarization mode. For centimeter-level cracks, they are more sensitive to backscattering in the VV polarization mode. This array achieves polarization switching without physically rotating the antenna, with a switching time of less than 1 second, ensuring the accuracy of VV and HH polarization data during 3D acquisition and improving the comprehensiveness and accuracy of underground defect detection.

[0019] The power amplifier amplifies the signal power, the power divider generates N Gray code complementary signals, and the controllable delay circuit ensures that the reference signal and the received echo signal arrive at the sample-and-hold terminal synchronously. In the N+1 front-end signal conditioning circuits, the first N circuits process the echo signal, and the N+1th circuit processes the reference signal. The N+1 high-speed ADC acquisition circuits perform synchronous high-speed analog-to-digital conversion on the front-end conditioned echo signal and the reference signal, achieving high sampling rate digital acquisition. The clock synchronization controller generates and distributes a system-level high-stability clock signal to ensure precise synchronous triggering of the N+1 high-speed ADC acquisition circuits, guaranteeing sampling timing consistency between different polarization channels and the reference channel. The receiver-side FPGA logic controller coordinates the timing logic, data flow management, and signal processing of the entire GPR acquisition system. The DDR3 data buffer unit matches the rate of the high-speed data stream, buffers bursts, and optimizes system real-time performance. The PCIe data upload unit is used to transmit the dual-polarized GPR data read from the DDR3 cache unit by the receiving FPGA logic controller to the host computer at high speed, enabling reliable uploading and subsequent data processing of the 3D meshed acquisition data. The host computer receives the dual-polarized GPR 3D dataset transmitted by the PCIe data upload unit, performs advanced data processing, and performs imaging visualization. The reference channel of the transmitting FPGA logic controller provides a reference signal that is strictly synchronized with the transmitted Gray complement code and serves as a benchmark for cross-correlation calculations to extract the true propagation delay of the echo signal, thereby stably forming the underground hyperbolic feature.

[0020] Based on the above embodiments, in a preferred embodiment, the fixed delay following the A code in the Gray complement code sequence is 20~50µs. This avoids the superposition of sidelobe interference between the A code and the B code.

[0021] Based on the above embodiments, in a preferred embodiment, each front-end signal conditioning circuit includes a low-noise amplifier, a variable gain amplifier, a bandpass filter, and a protection limiter connected in sequence.

[0022] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the present invention. Although detailed descriptions have been provided with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments, and all should be covered by the protection scope of the claims.

Claims

1. A dual-polarization three-dimensional Gray code GPR acquisition system, characterized in that, It includes an FPGA transmitting unit for transmitting Gray complement code radar signals, a dual-polarized antenna array, and an FPGA receiving unit for acquiring high-speed signals; The FPGA transmitting unit includes a transmitting FPGA logic controller, a power amplifier, a power divider, and a controllable delay circuit; the dual-polarized antenna array includes at least two orthogonal transmitting antennas and two receiving antennas, forming VV polarization and HH polarization channels, which are switched by the transmitting FPGA logic controller to achieve same-polarization data acquisition; the FPGA receiving unit includes N+1 front-end signal conditioning circuits, N+1 high-speed ADC acquisition circuits, a clock synchronization controller, a receiving FPGA logic controller, a DDR3 data buffer unit, a PCIe data upload unit, and a host computer; The transmitting FPGA logic controller generates a pair of Gray complementary code sequences, namely code A and code B. The Gray complementary code sequences are transmitted in the order of code A followed by a fixed delay and then code B. The output of the transmitting FPGA logic controller is divided into two paths. One of the output signals of the transmitting FPGA logic controller is connected to a controllable delay circuit to generate a reference Gray complementary code signal. The reference Gray complementary code signal is sequentially input to the N+1th front-end signal conditioning circuit and the N+1th high-speed ADC acquisition circuit of the FPGA receiving unit for analog-to-digital conversion. Another output signal from the transmitting FPGA logic controller is amplified and then sent to a power divider to generate N Gray complement code signals. These N Gray complement code signals are used to perform co-polarization detection of the current underground target through the VV polarization channel of the dual-polarized antenna array. After detection, the receiving antenna array corresponding to the VV polarization channel transmits the echo signal back to the N front-end signal conditioning circuits and N high-speed ADC acquisition circuits of the FPGA receiving unit for analog-to-digital conversion. The N+1 high-speed ADC acquisition circuits of the FPGA receiving unit are all connected to the clock synchronization controller. Each high-speed ADC acquisition circuit sends the digital signal after analog-to-digital conversion to the receiving FPGA logic controller according to a predetermined frame structure. The receiving FPGA logic controller parses and manages the received information and stores it in the DDR3 data cache unit. The receiving FPGA logic controller reads the cached data from the DDR3 data cache unit and transmits the data to the host computer through the PCIe data upload unit.

2. The dual-polarization three-dimensional Gray code GPR acquisition system according to claim 1, characterized in that, In Gray complementary code sequences, the fixed delay following the A code is 20~50µs.

3. The dual-polarization three-dimensional Gray code GPR acquisition system according to claim 2, characterized in that, Each front-end signal conditioning circuit includes a low-noise amplifier, a variable gain amplifier, a bandpass filter, and a protection limiter connected in sequence.

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