Method and device for improving SLC writing performance of SSD, equipment and medium

Abstract

The invention discloses a method, a device, equipment and a medium for improving SLC writing performance of an SSD (Solid State Disk). The method comprises the following steps: receiving an SLC writing request for a physical page and caching the SLC writing request; judging whether the number of the physical pages corresponding to all the write requests of the current cache reaches a merging threshold value or not; if the merging threshold value is reached, merging a plurality of write requests with a corresponding number into a first merging programming command, and if the merging threshold value is not reached, waiting for receiving a new write request, and judging whether waiting time reaches a time threshold value or not; and if the waiting time reaches the time threshold value and the number of the physical pages does not reach the merging threshold value, generating at least one supplementary write request, merging all cached write requests and the supplementary write requests into a second merging programming command reaching the merging threshold value, and issuing the first or second merging programming command to the NAND flash memory particles. By intelligently combining a plurality of SLC write requests into a one-time multi-page programming operation, the actual write bandwidth is significantly improved.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive technology, and in particular to a method, apparatus, device, and medium for improving the SLC write performance of SSDs. Background Technology

[0002] In existing technologies, to improve the reliability and response speed of data writing, especially to ensure data security in scenarios such as unexpected power outages, SSDs often use SLC mode to store critical data. Currently, common implementations process only one page per write operation, typically containing four sectors, corresponding to approximately 16KB of data. In actual writing, from the host issuing the write request to the application layer returning confirmation of completion, a complete SLC data write takes approximately 250-300 microseconds. However, based on the typical characteristics of NAND flash memory chips, their write latency (the time required for data to travel from the NAND interface to its actual programming into the storage cell) is typically only around 180 microseconds. Because existing solutions generally use a single-page write mechanism, actual write performance is limited, reaching only about 500MB / s.

[0003] Therefore, existing technologies have the problem that write performance fails to fully utilize the theoretical speed of NAND flash memory. Especially in power-down scenarios, the limited data retention speed may affect the integrity and reliability of data preservation. Summary of the Invention

[0004] The problem solved by this invention is to provide a method, apparatus, device, and medium for improving the SLC write performance of SSDs.

[0005] In a first aspect, embodiments of the present invention provide a method for improving the SLC write performance of an SSD, including: Receive SLC write requests for physical pages issued by the business layer and cache the write requests; Determine whether the number of physical pages corresponding to all write requests in the current cache has reached the preset merging threshold; If the merging threshold is reached, the corresponding number of write requests are merged into a first merge programming command, and the first merge programming command is sent to the NAND flash memory chip. The first merge programming command carries flag information indicating that multiple physical pages are programmed at once. If the merging threshold is not reached, wait to receive new write requests and determine whether the waiting time has reached the time threshold. If the number of physical pages corresponding to all current cached write requests has not reached the merging threshold when the waiting time reaches the time threshold, at least one supplementary write request is generated, and all cached write requests are merged with the at least one supplementary write request into a second merge programming command that reaches the merging threshold. The second merge programming command is then sent to the NAND flash memory chip.

[0006] Secondly, embodiments of the present invention provide an apparatus for improving the SLC write performance of an SSD, used to perform the method described in the first aspect, the apparatus comprising: A caching unit is used to receive SLC write requests for physical pages issued by the business layer and cache the write requests; The first judgment unit is used to determine whether the number of physical pages corresponding to all write requests in the current cache has reached the preset merging threshold. The first merging unit is configured to merge multiple write requests of a corresponding number into a first merge programming command if the merging threshold is reached, and issue the first merge programming command to the NAND flash memory chip, wherein the first merge programming command carries flag information indicating that multiple physical pages are programmed at one time. The second judgment unit is used to wait to receive a new write request if the merging threshold is not reached, and to determine whether the waiting time has reached the time threshold. The supplementary and second merging unit is used to generate at least one supplementary write request if the number of physical pages corresponding to all write requests in the current cache has not reached the merging threshold when the waiting time reaches the time threshold, merge all write requests in the cache with the at least one supplementary write request into a second merge programming command that reaches the merging threshold, and issue the second merge programming command to the NAND flash memory chip.

[0007] Thirdly, embodiments of the present invention provide a computer device, the device including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; The processor, when executing a program stored in memory, implements the steps of the method for improving SLC write performance of an SSD disk as described in the first aspect.

[0008] Fourthly, embodiments of the present invention provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method for improving SLC write performance of an SSD disk as described in the first aspect. This invention provides a method, apparatus, device, and medium for improving SLC write performance of an SSD. The method includes: receiving an SLC write request for a physical page issued by a service layer and caching the write request; determining whether the number of physical pages corresponding to all currently cached write requests has reached a preset merging threshold; if the merging threshold has been reached, merging the corresponding number of write requests into a first merge programming command and issuing the first merge programming command to the NAND flash memory chip, wherein the first merge programming command carries flag information indicating that multiple physical pages are programmed at once; if the merging threshold has not been reached, waiting to receive a new write request and determining whether the waiting time has reached a time threshold. If the number of physical pages corresponding to all current cached write requests has not reached the merging threshold when the waiting time reaches the time threshold, at least one supplementary write request is generated. All cached write requests are then merged with the at least one supplementary write request into a second merge programming command that reaches the merging threshold. This second merge programming command is then sent to the NAND flash memory chip. By intelligently merging multiple SLC write requests into a single multi-page programming operation and cleverly handling the tail packet problem, the fixed overhead of a single programming operation is effectively amortized, resulting in a significant improvement in actual write bandwidth. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A flowchart illustrating a method for improving SLC write performance of an SSD disk according to an embodiment of the present invention; Figure 2 A sub-flowchart of the method for improving SLC write performance of SSD disks provided in an embodiment of the present invention; Figure 3 A schematic block diagram of an apparatus for improving SLC write performance of an SSD disk according to an embodiment of the present invention; Figure 4 A schematic block diagram of a computer device provided for an embodiment of the present invention. Detailed Implementation

[0011] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0012] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0013] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0014] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0015] It should also be noted that, unless otherwise explicitly specified and limited, terms such as "installation," "connection," "linking," "fixing," and "setting" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. When an component is referred to as being "on" or "below" another component, the component can be located "directly" or "indirectly" on the other component, or there may be one or more intermediary components. The terms "first," "second," "third," etc., are only for the convenience of describing this technical solution and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," "third," etc., may explicitly or implicitly include one or more of that feature. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0016] Please see Figure 1 This invention provides a method for improving the SLC write performance of an SSD, which can be applied in the controller of a solid-state drive, including steps S1 to S5.

[0017] S1. Receive the SLC write request for the physical page issued by the service layer, and cache the write request.

[0018] In this embodiment, an SLC write request for a physical page issued by the service layer is received and cached. When the SSD controller receives a write request from the service layer via the host interface (such as PCIe / NVMe, SATA), if the request is identified as needing to be executed in SLC (Single Cell) mode, the controller places the write request into a dedicated request cache queue. Here, a physical page is the smallest unit for programming NAND flash memory, typically 16KB in size. An SLC write request specifically refers to a command to write data to flash memory in SLC mode (i.e., each storage cell stores only 1 bit of data). This mode is typically used for caching or storing critical data to achieve faster write speeds and higher reliability.

[0019] S2. Determine whether the number of physical pages corresponding to all write requests in the current cache has reached the preset merging threshold.

[0020] In this embodiment, it is determined whether the number of physical pages corresponding to all write requests currently cached has reached a preset merging threshold. The controller continuously checks and determines the number of physical pages corresponding to the accumulated write requests in the request cache queue. The merging threshold (N) is a preset integer value representing the minimum number of physical pages required to trigger multi-page merging programming, with a preferred value of 2, i.e., two physical pages. The purpose of setting this threshold is to merge multiple independent single-page write operations into a larger programming operation to distribute fixed overhead and improve overall bandwidth. This threshold can be dynamically configured according to the specific hardware characteristics of the solid-state drive (e.g., at least one of the following factors: the physical page size of the solid-state drive, the multi-plane programming capability of the NAND flash memory chips, or the cache register size).

[0021] S3. If the merging threshold is reached, the corresponding number of write requests are merged into a first merge programming command, and the first merge programming command is sent to the NAND flash memory chip. The first merge programming command carries flag information indicating that multiple physical pages are programmed at once.

[0022] In this embodiment, if the merging threshold is reached, multiple write requests of the corresponding number are merged into a first merge programming command, and the first merge programming command is issued to the NAND flash memory chip. The first merge programming command carries flag information indicating that multiple physical pages can be programmed at once. If the number of physical pages to be written in the cache queue reaches or exceeds the merging threshold N (e.g., N=2), a merging operation is performed. The NAND chip can perform a programming operation based on the first merge programming command, programming N (e.g., N=2) page data to a specific physical storage unit.

[0023] Please see Figure 2In one embodiment, merging a corresponding number of write requests into a first merge programming command includes sub-steps S31 to S32.

[0024] S31. Combine the data carried by the multiple write requests into a continuous data block in the cache that corresponds to the number of merging thresholds.

[0025] In this embodiment, the data carried by the multiple write requests are combined in the cache into a continuous data block corresponding to the number of merging thresholds. The controller extracts the user data carried by each of these N write requests from the internal cache and concatenates them sequentially into a continuous data block. The size of this data block is equal to the total capacity of N physical pages (e.g., 32KB when N=2).

[0026] S32. Encapsulate the continuous data block and the programming command containing the flag information into the merged programming command.

[0027] In this embodiment, the consecutive data blocks and the programming command containing the flag information are encapsulated into the merged programming command. The controller generates a programming command for the NAND flash memory chip. In addition to the target flash memory address and the aforementioned consecutive data blocks, this command also contains specific flag information. This flag information is used to notify the NAND flash memory chip that the goal of this programming operation is to program N physical pages consecutively, rather than traditional single-page programming. This allows the NAND chip to optimize its operation sequence internally, for example, by initiating multi-plane parallel programming or more efficient data loading.

[0028] S4. If the merging threshold is not reached, wait to receive a new write request and determine whether the waiting time has reached the time threshold.

[0029] In this embodiment, if the merging threshold is not reached, the system waits to receive new write requests and determines whether the waiting time has reached a time threshold. If the check finds that the number of physical pages in the cache queue is less than the merging threshold N (e.g., only one request), the controller will not immediately issue the request but will enter a waiting state to receive subsequent requests to reach N (e.g., N=2). Simultaneously, the controller starts a timer. This timer is used to set a maximum waiting time threshold to prevent excessive delays caused by a single request not being able to be paired for an extended period, thus affecting the system's tail latency performance.

[0030] S5. If the number of physical pages corresponding to all current cached write requests has not reached the merging threshold when the waiting time reaches the time threshold, then at least one supplementary write request is generated, and all cached write requests are merged with the at least one supplementary write request into a second merge programming command that reaches the merging threshold. The second merge programming command is then sent to the NAND flash memory chip.

[0031] In this embodiment, if the number of physical pages corresponding to all currently cached write requests has not yet reached the merging threshold when the waiting time reaches the time threshold, at least one supplementary write request is generated. All cached write requests and the at least one supplementary write request are merged into a second merge programming command that reaches the merging threshold. This second merge programming command is then sent to the NAND flash memory chip to handle the "tail packet" problem and ensure that all requests are ultimately sent in the optimal (or suboptimal) merging manner. The NAND chip can perform programming operations based on the second merge programming command, programming N (e.g., N=2) page data to a specific physical storage unit. The second merge programming command also carries flag information indicating that multiple physical pages can be programmed at once. The specific process of merging all cached write requests and the at least one supplementary write request into a second merge programming command that reaches the merging threshold can be referred to as the steps of merging multiple corresponding number of write requests into a first merge programming command, i.e., steps S31-S32, and will not be repeated here.

[0032] If the number of physical pages corresponding to all write requests in the current cache reaches the merging threshold when the waiting time reaches the time threshold, then step S3 is executed.

[0033] In one embodiment, generating at least one supplementary write request includes: Construct at least one supplementary write request, wherein the supplementary write request carries invalid data or padding data of a predetermined pattern.

[0034] In this embodiment, at least one supplementary write request is constructed, and the data carried by the supplementary write request is invalid data or padding data of a predetermined pattern. When the timer expires, i.e., the waiting time reaches the time threshold, it indicates that no new valid write request has arrived after a reasonable waiting time. At this time, the controller will actively generate one or more supplementary write requests (also known as dummy requests). The data carried by this supplementary write request is not user data, but invalid data or padding data of a predetermined pattern (e.g., all 0s, all 1s, or a specific pseudo-random sequence). Its function is to "make up the numbers" so that the total number of pages of data to be sent reaches the merging threshold N. The controller merges the cached valid write request (e.g., 1) with the generated supplementary write request (e.g., 1) to form a second merge programming command containing N physical pages of data, and sends it to the NAND flash memory chip.

[0035] See again Figure 1 In one embodiment, after step S5, the method further includes steps S6 to S8.

[0036] S6. Receive the programming result returned by the NAND flash memory chip after executing the merge programming command.

[0037] In this embodiment, the controller receives the programming result returned by the NAND flash memory chip after executing the merge programming command. After completing the programming operation, the NAND flash memory chip returns a status report to the controller, indicating the programming result (success or failure). The controller then performs subsequent processing based on this result.

[0038] S7. If the programming result is successful, return a completion response corresponding to the multiple original write requests to the business layer.

[0039] In this embodiment, if the programming result is successful, a completion response corresponding to the multiple original write requests is returned to the business layer. If the programming is successful, the controller generates and sends an independent completion response corresponding to each of the multiple original write requests based on the identifiers of the merge programming command. This is because the controller needs to "de-merge," that is, generate a completion response for each original user write request covered by this merge command, and report them to the business layer sequentially according to the identifiers of the original requests. Thus, from the perspective of the business layer, all the multiple independent requests it sent have been successfully processed.

[0040] S8. If the programming result is a failure, an exception is reported to the business layer.

[0041] In this embodiment, if the programming result is a failure, an exception is reported to the service layer. If the NAND flash memory returns a programming failure (e.g., a programming voltage verification error), the controller needs to handle the exception. This typically includes: logging an error, attempting to retry the programming, or, if the retry fails, marking a bad block, and ultimately reporting the failure status to the service layer.

[0042] Through the above embodiments, the present invention intelligently merges multiple SLC write requests into a single multi-page programming operation and cleverly handles the tail packet problem, effectively amortizing the fixed overhead of a single programming operation, thereby significantly improving the actual write bandwidth. Taking the merging threshold N=2 as an example, the write bandwidth can be increased from 500M / s to 800M / s, improving SLC write performance. This is especially beneficial in scenarios such as power failure protection where a large amount of data needs to be saved instantly, ensuring data security and integrity.

[0043] This invention also provides an apparatus for improving the SLC write performance of an SSD. This apparatus can be configured in the controller of the solid-state drive (SSD) and is used to execute any embodiment of the aforementioned method for improving SLC write performance of an SSD. Specifically, please refer to... Figure 3 , Figure 3 This is a schematic block diagram of an apparatus for improving SLC write performance of an SSD disk, provided in an embodiment of the present invention.

[0044] like Figure 3As shown, the device 100 for improving SSD SLC write performance includes: The cache unit 110 is used to receive SLC write requests for physical pages issued by the service layer and cache the write requests; The first judgment unit 120 is used to determine whether the number of physical pages corresponding to all write requests in the current cache has reached the preset merging threshold. The first merging unit 130 is configured to merge multiple write requests of a corresponding number into a first merge programming command if the merging threshold is reached, and issue the first merge programming command to the NAND flash memory chip, wherein the first merge programming command carries flag information indicating that multiple physical pages are programmed at one time. The second judgment unit 140 is used to wait to receive a new write request if the merging threshold is not reached, and to determine whether the waiting time has reached the time threshold. The supplementary and second merging unit 150 is used to generate at least one supplementary write request if the number of physical pages corresponding to all write requests in the current cache has not reached the merging threshold when the waiting time reaches the time threshold, merge all write requests in the cache with the at least one supplementary write request into a second merge programming command that reaches the merging threshold, and issue the second merge programming command to the NAND flash memory chip.

[0045] In one embodiment, the first merging unit 130 is further configured to combine the data carried by the plurality of write requests in the cache into a continuous data block corresponding to the number of merging thresholds; and encapsulate the continuous data block and the programming command containing the flag information into the merged programming command.

[0046] In one embodiment, the supplementation and second merging unit 150 is further configured to construct at least one supplementary write request, wherein the data carried by the supplementary write request is invalid data or padding data of a predetermined pattern.

[0047] In one embodiment, the apparatus 100 for improving SSD SLC write performance further includes: The result receiving unit 160 is used to receive the programming result returned by the NAND flash memory chip after executing the merge programming command; The success feedback unit 170 is used to return a completion response corresponding to multiple original write requests to the business layer if the programming result is successful. The failure feedback unit 180 is used to report an exception to the business layer if the programming result is a failure.

[0048] In one embodiment, the success feedback unit 170 is further configured to generate and issue an independent completion response corresponding to each original write request based on the identifiers of the multiple original write requests corresponding to the merge programming command.

[0049] The aforementioned device for improving SLC write performance of SSDs can be implemented as a computer program, which can, for example... Figure 4 It runs on the computer device shown.

[0050] Please see Figure 4 , Figure 4 This is a schematic block diagram of a computer device provided in an embodiment of the present invention.

[0051] The computer device 500 includes a processor 502, a memory, and a network interface 505 connected via a communication bus 501. The memory may include a storage medium 503 and internal memory 504.

[0052] The storage medium 503 may store an operating system 5031 and a computer program 5032. When the computer program 5032 is executed, it may cause the processor 502 to perform a method to improve the SLC write performance of the SSD disk. The storage medium 503 may be a volatile storage medium or a non-volatile storage medium.

[0053] The processor 502 provides computing and control capabilities to support the operation of the entire computer device 500.

[0054] The internal memory 504 provides an environment for the computer program 5032 in the storage medium 503 to run. When the computer program 5032 is executed by the processor 502, the processor 502 can execute a method to improve the SLC write performance of the SSD disk.

[0055] This network interface 505 is used for network communication, such as providing data transmission. Those skilled in the art will understand that... Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present invention and does not constitute a limitation on the computer device 500 to which the present invention is applied. The specific computer device 500 may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0056] The processor 502 is used to run the computer program 5032 stored in the memory to implement the corresponding functions in the above-mentioned method for improving the SLC write performance of SSD disks.

[0057] Those skilled in the art will understand that Figure 4The embodiments of the computer device shown do not constitute a limitation on the specific configuration of the computer device. In other embodiments, the computer device may include more or fewer components than illustrated, or combine certain components, or have different component arrangements. For example, in some embodiments, the computer device may include only memory and a processor. In such embodiments, the structure and function of the memory and processor are different from those shown. Figure 4 The embodiments shown are consistent and will not be described again here.

[0058] It should be understood that, in this embodiment of the invention, the processor 502 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0059] In another embodiment of the invention, a computer-readable storage medium is provided. This computer-readable storage medium may be volatile or non-volatile. The computer-readable storage medium stores a computer program, wherein when executed by a processor, the computer program implements the steps included in the above-described method for improving SLC write performance of an SSD.

[0060] Those skilled in the art will readily understand that, for the sake of convenience and brevity, the specific working processes of the devices, apparatuses, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this invention.

[0061] In the embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Units with the same function may be grouped into one unit. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interfaces, devices, or units, or it may be an electrical, mechanical, or other form of connection.

[0062] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments of the present invention, depending on actual needs.

[0063] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0064] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a computer-readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned computer-readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), magnetic disks, or optical disks.

[0065] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for improving the SLC write performance of an SSD, characterized in that, include: Receive SLC write requests for physical pages issued by the business layer and cache the write requests; Determine whether the number of physical pages corresponding to all write requests in the current cache has reached the preset merging threshold; If the merging threshold is reached, the corresponding number of write requests are merged into a first merge programming command, and the first merge programming command is sent to the NAND flash memory chip. The first merge programming command carries flag information indicating that multiple physical pages are programmed at once. If the merging threshold is not reached, wait to receive new write requests and determine whether the waiting time has reached the time threshold. If the number of physical pages corresponding to all current cached write requests has not reached the merging threshold when the waiting time reaches the time threshold, at least one supplementary write request is generated, and all cached write requests are merged with the at least one supplementary write request into a second merge programming command that reaches the merging threshold. The second merge programming command is then sent to the NAND flash memory chip.

2. The method for improving SLC write performance of an SSD according to claim 1, characterized in that, The merging threshold is two physical pages.

3. The method for improving SLC write performance of an SSD according to claim 1 or 2, characterized in that, The step of merging multiple write requests of a corresponding number into a first merge programming command includes: The data carried by the multiple write requests are combined in the cache into a continuous data block corresponding to the number of merging thresholds; The continuous data blocks and the programming commands containing the flag information are encapsulated into the merged programming command.

4. The method for improving SLC write performance of an SSD according to claim 1, characterized in that, The generation of at least one supplementary write request includes: Construct at least one supplementary write request, wherein the supplementary write request carries invalid data or padding data of a predetermined pattern.

5. The method for improving SLC write performance of an SSD according to claim 1, characterized in that, The method further includes: Receive the programming result returned by the NAND flash memory chip after executing the merge programming command; If the programming result is successful, a completion response corresponding to the multiple original write requests is returned to the business layer; If the programming fails, an exception is reported to the business layer.

6. The method for improving SLC write performance of an SSD according to claim 5, characterized in that, The step of returning a completion response corresponding to multiple original write requests to the business layer includes: Based on the identifiers of the multiple original write requests corresponding to the merge programming command, generate and issue an independent completion response corresponding to each original write request.

7. The method for improving SLC write performance of an SSD according to claim 1, characterized in that, The preset merging threshold is dynamically configured based on at least one of the following factors: the physical page size of the solid-state drive, the multi-plane programming capability of the NAND flash memory chips, or the cache register size.

8. A device for improving the SLC write performance of an SSD, characterized in that, The apparatus for performing the method according to any one of claims 1 to 7, the apparatus comprising: A caching unit is used to receive SLC write requests for physical pages issued by the business layer and cache the write requests; The first judgment unit is used to determine whether the number of physical pages corresponding to all write requests in the current cache has reached the preset merging threshold. The first merging unit is configured to merge multiple write requests of a corresponding number into a first merge programming command if the merging threshold is reached, and issue the first merge programming command to the NAND flash memory chip, wherein the first merge programming command carries flag information indicating that multiple physical pages are programmed at one time. The second judgment unit is used to wait to receive a new write request if the merging threshold is not reached, and to determine whether the waiting time has reached the time threshold. The supplementary and second merging unit is used to generate at least one supplementary write request if the number of physical pages corresponding to all write requests in the current cache has not reached the merging threshold when the waiting time reaches the time threshold, merge all write requests in the cache with the at least one supplementary write request into a second merge programming command that reaches the merging threshold, and issue the second merge programming command to the NAND flash memory chip.

9. A computer device, characterized in that, The device includes a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the steps of the method for improving SLC write performance of an SSD disk as described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method for improving SLC write performance of an SSD disk as described in any one of claims 1-7.

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