Training and reasoning system, training method and reasoning method
By heterogeneously integrating the resistive random access memory (RRAM) computing layer and the dynamic random access memory (DRAM) storage layer, and combining them with a data scheduling module, the requirements for high bandwidth, low power consumption, high capacity, and high precision computing during AI training and inference are addressed, achieving efficient data storage and computation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NACUN TECHNOLOGY (HANGZHOU) CO LTD
- Filing Date
- 2025-12-29
- Publication Date
- 2026-04-14
AI Technical Summary
Existing technologies cannot simultaneously meet the demands of high bandwidth, low power consumption, high capacity, and high precision computing during AI training and inference.
By employing heterogeneous integration of resistive random access memory (RRAM) storage layer and dynamic random access memory (DRAM) storage layer, combined with a data scheduling module, efficient storage and computation of weights can be achieved.
It meets the computing requirements of high bandwidth, low power consumption, high capacity and high precision, supports high-frequency data updates and low-latency data transmission, and improves the efficiency of AI training and inference.
Smart Images
Figure CN121859967A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of artificial intelligence technology, and in particular to a training and inference system, training method and inference method. Background Technology
[0002] In the engineering process of artificial intelligence (AI), AI training and inference constitute the two core processes in the model lifecycle. The core operations of AI training and inference are matrix multiplication and addition, requiring frequent access to massive amounts of parameters and intermediate data, placing stringent demands on the bandwidth, power consumption, capacity, and access latency of the storage system. Related technologies cannot simultaneously meet the requirements of high bandwidth, low power consumption, high capacity, and high-precision computation in AI training and inference. Therefore, how to simultaneously meet the requirements of high bandwidth, low power consumption, high capacity, and high-precision computation has become a pressing technical problem for those skilled in the art. Summary of the Invention
[0003] The purpose of this application is to provide a training and inference system, training method, and inference method that can simultaneously meet the requirements of high bandwidth, low power consumption, high capacity, and high-precision computing.
[0004] To address the aforementioned technical problems, this application provides a training and inference system, comprising:
[0005] The resistive random access memory (RRAM) storage layer, the dynamic random access memory (DRAM) storage layer, and the data scheduling module;
[0006] The resistive random access memory storage layer is used to store the weights after training and to perform multiply-accumulate operations.
[0007] The dynamic random access memory storage layer is used to store intermediate results obtained during training and inference.
[0008] The data scheduling module is used to store the weights to be updated in the dynamic random access memory storage layer during training, store the weights after training stabilization in the resistive random access memory storage layer, and store the intermediate results obtained based on multiply-accumulate operations in the dynamic random access memory storage layer during training and inference.
[0009] In some embodiments, the resistive random access memory (RRAM) computing layer and the dynamic random access memory (DRAM) storage layer are integrated using heterogeneous integration technology; the RRAM computing layer is located on the upper layer, and the DRAM storage layer is located on the lower layer.
[0010] In some embodiments, the data scheduling module is a hardware logic circuit.
[0011] In some embodiments, the dynamic random access memory storage layer includes an intermediate result area and a temporary cache area;
[0012] The intermediate results area is used to store intermediate results obtained during training and inference.
[0013] The temporary buffer is used to store the initial weight values and calibration parameters.
[0014] In some embodiments, the data scheduling module is used to preprocess the initial weight values in the dynamic random access memory storage layer during training to generate a resistive random access memory programming pulse sequence; write the trained and stable weights into the resistive random access memory computing layer; write the weights to be updated into the dynamic random access memory storage layer; write the intermediate results obtained during the forward computation into the dynamic random access memory storage layer; and write the updated and stable weights in the dynamic random access memory storage layer into the resistive random access memory computing layer.
[0015] In some embodiments, the data scheduling module is used to detect the fluctuation range of the updated weights in the dynamic random access memory storage layer, and when the fluctuation range of the weights after a preset number of consecutive updates is less than a preset threshold, the weights are determined to be stable, and the stable weights are calibrated and written into the resistive random access memory storage layer.
[0016] In some embodiments, the data scheduling module is used to read the trained weights and write them into the resistive random access memory (RRAM) storage layer during inference; transmit the inference input data to the dynamic random access memory (DRAM) storage layer; perform format transformation on the inference input data and load it into the RRAM array word line driver circuit; process the target digital signal and store the intermediate results obtained from the processing into the DRAM storage layer; the digital signal is obtained by converting the analog signal obtained by performing multiplication and addition operations on the RRAM storage layer.
[0017] In some embodiments, the resistive random access memory (RRAM) computing layer includes multiple RRAM cross arrays; each RRAM cross array corresponds to a layer or a sub-module of a neural network.
[0018] To address the aforementioned technical problems, this application also provides a training method applied to the training and inference system described above, comprising:
[0019] The weights that are stable after training are written into the resistive random access memory storage layer, and the weights to be updated are written into the dynamic random access memory storage layer.
[0020] The intermediate results obtained during the forward computation are written into the dynamic random access memory storage layer.
[0021] The weight to be updated is updated based on the intermediate results in the dynamic random access memory storage layer;
[0022] Once the updated weights are detected to be stable, the stable weights are written into the resistive random access memory (RRAM) storage layer.
[0023] To address the aforementioned technical problems, this application also provides a reasoning method applied to the training and reasoning system described above, comprising:
[0024] The trained weights are read and written into the resistive random access memory (RRAM) storage layer.
[0025] The inference input data is transmitted to the dynamic random access memory storage layer, and after the inference input data is format-converted, it is loaded into the word line driver circuit of the resistive random access memory array.
[0026] The analog signal output from the multiply-accumulate operation of the resistive random access memory storage layer is converted from analog to digital to obtain a digital signal.
[0027] The digital signal is processed and the intermediate results are stored in the dynamic random access memory storage layer.
[0028] The training and inference system provided in this application includes a dynamic random access memory (DRAM) storage layer and a resistive random access memory (RRAM) computation layer. The high reliability and high rewrite frequency of the DRAM storage layer meet the high-frequency update requirements of intermediate data during AI training. The in-memory computation characteristics and low power consumption of the RRAM computation layer effectively solve the bandwidth and power consumption bottlenecks in the inference process. The complementary functions of the DRAM storage layer and the RRAM computation layer effectively address the performance limitations of a single storage medium. Furthermore, the dynamic data scheduling mechanism reduces the number of data transfers across media, enabling the system to support both high-precision AI training and high-energy-efficiency inference.
[0029] The training and reasoning methods provided in this application have the aforementioned technical effects. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0031] Figure 1 A schematic diagram of a training and inference system provided in an embodiment of this application;
[0032] Figure 2 This is a schematic diagram of an AI training process provided in an embodiment of this application;
[0033] Figure 3 This is a schematic diagram of an AI inference process provided in an embodiment of this application;
[0034] Figure 4 A flowchart illustrating a training method provided in an embodiment of this application;
[0035] Figure 5 This is a flowchart illustrating a reasoning method provided in an embodiment of this application. Detailed Implementation
[0036] The core of this application is to provide a training and inference system, training method, and inference method that can simultaneously meet the requirements of high bandwidth, low power consumption, high capacity, and high-precision computing.
[0037] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0038] Please refer to Figure 1 , Figure 1 This is a schematic diagram of a training and inference system provided in an embodiment of this application, with reference to... Figure 1 As shown, the system includes:
[0039] The resistive random access memory (RRAM) storage layer 10, the dynamic random access memory (DRAM) storage layer 20, and the data scheduling module 30 are included.
[0040] The resistive random access memory storage layer 10 is used to store the weights after training and to perform multiply-accumulate operations.
[0041] The dynamic random access memory storage layer 20 is used to store intermediate results obtained during training and inference.
[0042] The data scheduling module 30 is used to store the weights to be updated in the dynamic random access memory storage layer 20 during training, store the weights after training stabilization in the resistive random access memory storage layer 10, and store the intermediate results obtained based on multiply-accumulate operations in the dynamic random access memory storage layer 20 during training and inference.
[0043] The training and inference system provided in this application includes an RRAM (Resistive Random-Access Memory) in-memory layer, a DRAM (Dynamic Random-Access Memory) storage layer, and a data scheduling module 30.
[0044] The resistive random access memory (RRAM) storage layer 10 is used to store the weights after training stabilization and the fixed weights during inference. Through the multi-level storage characteristic of conductance values, it achieves multi-bit weight storage, thereby improving storage density. Additionally, the RRAM storage layer 10 is used to perform multiply-accumulate operations.
[0045] In some embodiments, the resistive random access memory (RRAM) storage layer 10 includes a plurality of RRAM cross arrays; each RRAM cross array corresponds to a layer or a sub-module of a neural network.
[0046] In this embodiment, the resistive random access memory (RRAM) storage layer 10 consists of multiple independent RRAM cross arrays. Each RRAM array corresponds to a layer or a sub-module of the neural network and is used to store the weights after training and the fixed weights during the inference process.
[0047] The dynamic random access memory storage layer 20 is mainly used to store weights to be updated.
[0048] In some embodiments, the dynamic random access memory storage layer 20 includes an intermediate result area and a temporary cache area;
[0049] The intermediate result area is used to store the intermediate results;
[0050] The temporary buffer is used to store the initial weight values and calibration parameters.
[0051] In this embodiment, the dynamic random access memory (DRAM) storage layer 20 is divided into two functional areas: an intermediate result area and a temporary cache area. The intermediate result area stores intermediate results such as gradient data and activation values that need to be frequently rewritten during AI training. The temporary cache area stores the initial weight values and calibration parameters to be written to the resistive random access memory (DRAM) storage layer 10. This embodiment utilizes the high reliability and high rewrite frequency of the DRAM storage layer 20 to support high-frequency data updates during training.
[0052] In some embodiments, the resistive random access memory (RRAM) storage layer 10 and the dynamic random access memory (DRAM) storage layer 20 are integrated using heterogeneous integration technology; the RRAM storage layer 10 is located on the upper layer, and the DRAM storage layer 20 is located on the lower layer.
[0053] The resistive random access memory (RRAM) computing layer 10 and the dynamic random access memory (DRAM) storage layer 20 are integrated using a heterogeneous integration process. The RRAM computing layer 10 is located on the upper layer, and the DRAM storage layer 20 is located on the lower layer, achieving tight physical coupling. The RRAM computing layer 10 and the DRAM storage layer 20 are interconnected with the data scheduling module 30 via an on-chip high-speed bus.
[0054] The resistive random access memory (RRAM) storage layer 10 and the dynamic random access memory (DRAM) storage layer 20 are heterogeneously integrated, which can reduce transmission latency.
[0055] The data scheduling module 30 adopts a high-speed synchronous interface, supporting low-latency data transmission between the resistive random access memory (RRAM) storage layer 10 and the dynamic random access memory (DRAM) storage layer 20. The interface bandwidth matches the computation bandwidth of the RRAM storage layer 10 and the read / write bandwidth of the DRAM storage layer 20. The data scheduling module 30 integrates a weight calibration module, a data format conversion module, a task identification module, and a priority scheduler. It can convert the digital weight data output from the DRAM storage layer 20 into pulse parameters (voltage amplitude, width, and quantity) required for RRAM programming. Simultaneously, it converts the analog calculation results output from the RRAM storage layer 10 into a digital format compatible with the DRAM storage layer 20 after ADC conversion. The data scheduling module 30 dynamically allocates data storage paths based on the AI task type (training / inference). During training, it prioritizes routing frequently updated intermediate results to the DRAM storage layer 20, and writes them to the RRAM storage layer 10 after the weight iteration stabilizes. During the inference process, the weights are read directly from the resistive random access memory storage layer 10, and intermediate results are stored as needed in the temporary cache area of the dynamic random access memory storage layer 20.
[0056] In some embodiments, the data scheduling module 30 is a hardware logic circuit.
[0057] In this embodiment, the data scheduling strategy is implemented through hardware logic circuits, which can control the response latency to the nanosecond level and avoid software scheduling overhead.
[0058] It is understood that the data scheduling module 30 can also adopt a software-programmable data scheduling scheme, which can dynamically adjust the storage strategy through firmware algorithm, and can adapt to more types of AI models.
[0059] In some embodiments, the data scheduling module 30 is used to preprocess the initial weight values in the dynamic random access memory storage layer 20 during training to generate a resistive random access memory programming pulse sequence; write the trained and stable weights into the resistive random access memory storage layer 10; write the weights to be updated into the dynamic random access memory storage layer 20; write the intermediate results obtained during the forward computation process into the dynamic random access memory storage layer 20; and write the updated and stable weights in the dynamic random access memory storage layer 20 into the resistive random access memory storage layer 10.
[0060] refer to Figure 2 As shown, the AI training process mainly includes initialization, weight pre-calibration, partial weight writing, forward calculation, backpropagation, stable weight transfer, and convergence judgment.
[0061] Initialization includes loading AI model parameters, storing initial weight values in the temporary cache of dynamic random access memory storage layer 20, and configuring the working parameters of each module of the AI model.
[0062] Partial weight writing includes the data scheduling module 30 writing the stabilized weights into the resistive random access memory storage layer 10, and temporarily storing the weights to be updated in the dynamic random access memory storage layer 20.
[0063] The forward computation includes a data scheduling module 30 that sends stable input data to the resistive random access memory (RANM) storage layer 10 and the input data to be updated to the dynamic random access memory (DRAM) storage layer 20, achieving parallel distribution. The weights to be updated in the DRAM storage layer 20 are multiplied and added in the digital domain with the input data to be updated. The RANM storage layer 10 performs in-memory multiplication and addition operations. Both intermediate results (the intermediate result obtained by multiplying and adding the weights to be updated with the input data to be updated in the DRAM storage layer 20 and the intermediate result obtained by performing in-memory multiplication and addition operations in the RANM storage layer 10) are stored in the intermediate result area of the DRAM storage layer 20.
[0064] Backpropagation involves calculating the gradient based on the intermediate results in the dynamic random access memory storage layer 20, updating the weights to be updated in the dynamic random access memory storage layer 20 through the weight calibration module, and completing one iteration.
[0065] The stable weight migration includes the data scheduling module 30 detecting whether the weight is stable, and when the weight is detected to be stable, writing the stable weight into the resistive random access memory storage layer 10.
[0066] In some embodiments, the data scheduling module 30 is used to detect the fluctuation range of the updated weights in the dynamic random access memory storage layer 20, and when the fluctuation range of the weights after a preset number of consecutive updates is less than a preset threshold, the weights are determined to be stable, and the stable weights are calibrated and written into the resistive random access memory storage layer 10.
[0067] The data scheduling module 30 detects the fluctuation range of the updated weights in the dynamic random access memory storage layer 20. If the fluctuation range is less than the preset threshold for a preset number of consecutive times (e.g., 3 times), the weights are determined to be stable. The stabilized weights are then calibrated and written into the resistive random access memory storage layer 10, and the storage resources of the dynamic random access memory storage layer 20 are released.
[0068] Convergence criteria include: if the model accuracy reaches a preset threshold, output the training result; otherwise, return to the previous iteration for repeated computation.
[0069] In some embodiments, the data scheduling module 30 is used to read the trained weights and write them into the resistive random access memory (RRAM) storage layer 10 during inference; transmit the inference input data to the dynamic random access memory (DRAM) storage layer 20; perform format transformation on the inference input data and load it into the DRAM array word line driver circuit; process the target digital signal and store the intermediate results obtained from the processing into the DRAM storage layer 20; the digital signal is obtained by converting the analog signal obtained by performing multiplication and addition operations on the RRAM storage layer 10.
[0070] refer to Figure 3 As shown, the AI inference process mainly includes model loading, input data import, in-store computation, result processing, multi-round computation, and output of inference results.
[0071] Model loading includes the data scheduling module 30 reading the pre-trained weights and writing them into the resistive random access memory storage layer 10 to complete the conductivity value programming.
[0072] The input data import process includes: transferring the inference input data to the temporary buffer of the dynamic random access memory storage layer 20, and loading it into the word line drive circuit of the resistive random access memory array after format conversion.
[0073] The in-memory computing includes a resistive random access memory (RRAM) storage layer 10 that performs multiplication and addition operations, and the analog signals output from the bit lines are converted into digital signals by an ADC.
[0074] The result processing includes post-processing of the digital signal obtained by ADC conversion, such as activation function operation by the data scheduling module 30, and the intermediate results are stored as needed in the dynamic random access memory storage layer 20.
[0075] Multi-round computation includes, if it is a deep network model, using the intermediate results in the dynamic random access memory storage layer 20 as the input of the next layer, repeating the integrated storage and computation operation and result processing.
[0076] The output inference results include reading the final results from the dynamic random access memory storage layer 20 and outputting them after all layers of calculations are completed.
[0077] The above embodiments of this application implement AI training and inference based on the dynamic random access memory storage layer 20 and the resistive random access memory storage layer 10. As a specific implementation method, the dynamic random access memory storage layer 20 can be replaced with an SRAM (Static Random-Access Memory) storage layer. The faster read and write speed of SRAM further reduces data access latency, which is suitable for edge AI inference scenarios with extremely high real-time requirements.
[0078] In summary, the training and inference system provided in this application includes a dynamic random access memory (DRAM) storage layer and a resistive random access memory (RRAM) computation layer. The high reliability and high rewrite frequency of the DRAM storage layer can meet the high-frequency update requirements of intermediate data in AI training. The in-memory computation characteristics and low power consumption of the RRAM computation layer effectively solve the bandwidth and power consumption bottlenecks in the inference process. The complementary functions of the DRAM storage layer and the RRAM computation layer can effectively solve the performance shortcomings of a single storage medium. In addition, the dynamic data scheduling mechanism can reduce the number of data transfers across media, enabling the system to support both high-precision AI training and high-energy-efficiency inference.
[0079] This application also provides a training method applied to the training and inference system described in the above embodiments, referencing... Figure 4 As shown, the training methods also include:
[0080] S101: Write the stable weights after training into the resistive random access memory storage layer, and write the weights to be updated into the dynamic random access memory storage layer.
[0081] S102: Write the intermediate results obtained during the forward computation process into the dynamic random access memory storage layer;
[0082] S103: Update the weight to be updated based on the intermediate results in the dynamic random access memory storage layer;
[0083] S104: When the updated weights are detected to be stable, the stable weights are written into the resistive random access memory storage layer.
[0084] The AI model parameters are loaded, and the initial weight values are stored in the temporary cache area of the dynamic random access memory (DRAM) storage layer. After configuring the working parameters of each module of the AI model, the data scheduling module writes the stabilized weights into the resistive random access memory (RRAM) in-memory processing layer and temporarily stores the weights to be updated in the DRAM storage layer. The data scheduling module sends stable input data to the RRAM in-memory processing layer and input data to be updated to the DRAM storage layer, respectively, to achieve parallel distribution. The weights to be updated in the DRAM storage layer are multiplied and added in the digital domain with the input data to be updated. The RRAM in-memory processing layer performs in-memory multiplication and addition operations. Both intermediate results (the intermediate result obtained by multiplying and adding the weights to be updated in the DRAM storage layer with the input data to be updated in the digital domain and the intermediate result obtained by performing in-memory multiplication and addition operations in the RRAM storage layer) are stored in the intermediate result area of the DRAM storage layer. Based on the gradient calculated using intermediate results stored in the dynamic random access memory (DRAM) layer, the data scheduling module updates the weights to be updated in the DRAM layer, completing one iteration. The data scheduling module checks whether the weights are stable, and when stability is detected, writes the stable weights into the DRAM layer.
[0085] The training methods described above can be used to train image recognition models, speech recognition models, etc. Then, image recognition can be performed using the trained image recognition model, and speech recognition can be performed using the trained speech recognition model.
[0086] This application also provides a reasoning method applied to the training and reasoning system described in the above embodiments, referencing... Figure 5 As shown, the reasoning methods also include:
[0087] S201: Read the trained weights and write them into the resistive random access memory storage layer;
[0088] S202: Transmit the inference input data to the dynamic random access memory storage layer, and load the inference input data into the word line driver circuit of the resistive random access memory array after format conversion.
[0089] S203: Perform analog-to-digital conversion on the analog signal output from the multiply-accumulate operation of the resistive random access memory storage layer to obtain a digital signal;
[0090] S204: Process the digital signal and store the intermediate results obtained from the processing into the dynamic random access memory storage layer.
[0091] The data scheduling module reads the pre-trained weights and writes them into the RRAM (Resistive Random Access Memory) computation layer to complete the conductance programming. After transmitting the inference input data to the temporary buffer of the DRAM, and converting the format before loading it into the RRAM array word line driver circuit, the RRAM computation layer performs multiply-accumulate operations. The analog signal output from the bit line is converted into a digital signal by an ADC. The digital signal obtained from the ADC conversion undergoes post-processing, such as activation function operations, by the data scheduling module. The intermediate results are stored in the DRAM as needed. If the model is a deep network model, the intermediate results in the DRAM are used as the input for the next layer, repeating the in-memory computation and result processing. After all layers of computation are completed, the final result can be read from the DRAM and output.
[0092] The above reasoning method can be used for image recognition reasoning, speech recognition reasoning, etc.
[0093] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses, devices, and computer-readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple; relevant details can be found in the method section.
[0094] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0095] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0096] The training and inference system, training method, and inference method provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.
Claims
1. A training and reasoning system, characterized in that, include: The resistive random access memory (RRAM) storage layer, the dynamic random access memory (DRAM) storage layer, and the data scheduling module; The resistive random access memory storage layer is used to store the weights after training and to perform multiply-accumulate operations. The dynamic random access memory storage layer is used to store intermediate results obtained during training and inference. The data scheduling module is used to store the weights to be updated in the dynamic random access memory storage layer during training, store the weights after training stabilization in the resistive random access memory storage layer, and store the intermediate results obtained based on multiply-accumulate operations in the dynamic random access memory storage layer during training and inference.
2. The training and inference system according to claim 1, characterized in that, The resistive random access memory (RRAM) computing layer and the dynamic random access memory (DRAM) storage layer are integrated through heterogeneous integration technology; the RRAM computing layer is located in the upper layer, and the DRAM storage layer is located in the lower layer.
3. The training and inference system according to claim 1, characterized in that, The data scheduling module is a hardware logic circuit.
4. The training and inference system according to claim 1, characterized in that, The dynamic random access memory storage layer includes an intermediate result area and a temporary cache area; The intermediate results area is used to store intermediate results obtained during training and inference. The temporary buffer is used to store the initial weight values and calibration parameters.
5. The training and inference system according to claim 1, characterized in that, The data scheduling module is used to preprocess the initial weight values in the dynamic random access memory storage layer during training to generate a resistive random access memory programming pulse sequence; write the stable weights after training into the resistive random access memory computing layer; and write the weights to be updated into the dynamic random access memory storage layer. The intermediate results obtained during the forward computation are written into the dynamic random access memory storage layer. The updated and stable weights in the dynamic random access memory storage layer are written into the resistive random access memory storage layer.
6. The training and inference system according to claim 5, characterized in that, The data scheduling module is used to detect the fluctuation range of the updated weights in the dynamic random access memory storage layer. When the fluctuation range of the weights after a preset number of consecutive updates is less than a preset threshold, the weights are determined to be stable, and the stable weights are calibrated and written into the resistive random access memory storage layer.
7. The training and inference system according to claim 1, characterized in that, The data scheduling module is used to read the trained weights during inference and write them into the resistive random access memory (RRAM) storage layer; transmit the inference input data to the dynamic random access memory (DRAM) storage layer, and load the inference input data into the RRAM array word line driver circuit after format conversion; process the target digital signal and store the intermediate results obtained from the processing into the DRAM storage layer; the digital signal is obtained by converting the analog signal obtained by performing multiplication and addition operations on the RRAM storage layer.
8. The training and inference system according to claim 1, characterized in that, The resistive random access memory (RRAM) storage layer includes multiple RRAM cross arrays; each RRAM cross array corresponds to a layer or a sub-module of the neural network.
9. A training method, characterized in that, Applied to the training and inference system as described in claim 1, comprising: The weights that are stable after training are written into the resistive random access memory (RRAM) storage layer, and the weights to be updated are written into the dynamic random access memory (DRAM) storage layer. The intermediate results obtained during the forward computation are written into the dynamic random access memory storage layer. The weight to be updated is updated based on the intermediate results in the dynamic random access memory storage layer; Once the updated weights are detected to be stable, the stable weights are written into the resistive random access memory (RRAM) storage layer.
10. A reasoning method, characterized in that, Applied to the training and inference system as described in claim 1, comprising: Read the trained weights and write them into the resistive random access memory (RRAM) storage layer; The inference input data is transmitted to the dynamic random access memory storage layer, and after the inference input data is format-converted, it is loaded into the word line driver circuit of the resistive random access memory array. The analog signal output from the multiply-accumulate operation of the resistive random access memory storage layer is converted from analog to digital to obtain a digital signal. The digital signal is processed and the intermediate results are stored in the dynamic random access memory storage layer.