Quantum random access memory implementation method and system based on superconducting quantum platform
By replacing SWAP and CSWAP gates with native multi-qubit gates on a superconducting quantum platform, and combining complementary control and two-dimensional layout optimization, the problems of increased circuit depth and decoherent noise accumulation in the prior art are solved, and a high-efficiency and scalable quantum random access memory is realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-17
- Publication Date
- 2026-04-14
- Estimated Expiration
- Not applicable · inactive patent
AI Technical Summary
Existing superconducting quantum random access memory (QRAM) requires multiple two-bit gate decompositions on a superconducting platform to implement SWAP and CSWAP gates, which leads to increased circuit depth and accumulation of decoherent noise, making it difficult to achieve high fidelity and scalability.
A native multi-qubit gate, physically adapted to the superconducting quantum bit platform, is used to directly realize state exchange and controlled state exchange operations between qubits, replacing the traditional SWAP and CSWAP gates. Combined with complementary control and two-dimensional layout optimization, the circuit depth and the number of multi-qubit gates are reduced.
It significantly reduces circuit depth and the number of multi-bit gates, reduces decoherence effects and operational errors, achieves high-fidelity and scalable quantum memories, and improves hardware efficiency and noise immunity.
Smart Images
Figure CN121860085A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of quantum computing and quantum information processing technology, and in particular to a method and system for implementing a quantum random access memory based on a superconducting quantum platform. Background Technology
[0002] Quantum random access memory (QRAM), as a key component for implementing quantum algorithms, enables queries on superposition states of classical data. However, existing QRAM implementations rely on SWAP gates and controlled SWAP (CSWAP) gates, which require multiple two-bit gate decompositions on superconducting platforms. This leads to increased circuit depth and accumulation of decoherent noise, making it difficult to achieve high-fidelity and scalable QRAM.
[0003] Bucket-Brigade quantum random access memory (BB-QRAM) has attracted attention due to its good noise immunity, but its implementation still suffers from insufficient hardware efficiency in existing technologies. Currently, although various physical systems, such as optical and acoustic systems, have been proposed as implementation platforms for BB-QRAM, superconducting quantum circuits are widely considered the most promising physical system for supporting large-scale quantum storage and computation due to their mature manufacturing processes, high scalability, and high parameter controllability.
[0004] However, the intrinsic interactions of existing superconducting qubits cannot be directly used to implement SWAP or CSWAP operations. Therefore, in current technologies, a large number of operations in QRAM must be performed through lengthy gate decomposition. This not only significantly increases circuit depth and the number of gate operations, but also leads to large resource consumption and error accumulation, thus severely limiting the scalability and practical application prospects of QRAM.
[0005] Therefore, there is an urgent need for a new type of native gate set that can combine the physical characteristics of superconducting platforms to directly replace existing SWAP and CSWAP gates, thereby reducing circuit depth and gate count, improving operational fidelity, and significantly improving the hardware efficiency and scalability of QRAM. Summary of the Invention
[0006] The purpose of this invention is to overcome the shortcomings of the existing technology. To achieve the above objective, a method and system for implementing a quantum random access memory based on a superconducting quantum platform is adopted to solve the problems mentioned in the background technology.
[0007] A method for implementing a quantum random access memory based on a superconducting quantum platform includes the following steps: In the routing circuit of the bucket-type quantum random access memory, the state exchange operation between qubits is directly realized using the first native multi-qubit gate, which is physically adapted to the superconducting qubit platform. The controlled state exchange operation is directly implemented using a second native multi-bit gate that is physically adapted to the platform. The combination of the first native multi-bit gate and the second native multi-bit gate is used to replace the SWAP gate and the controlled SWAP gate, which are composed of the decomposition of the basic double-bit gate, in order to reduce the depth of the routing circuit.
[0008] As a further aspect of the present invention: the first native multi-bit gate is an iSCZ gate, which, when combined with a local phase gate, is equivalent to a SWAP gate.
[0009] As a further aspect of the present invention: the second native multi-bit gate is a C-iSCZ gate, which, when combined with a controlled phase gate, is equivalent to a controlled SWAP gate.
[0010] As a further aspect of the present invention: in the routing node, the paired controlled state exchange operation is simplified into two second native multi-bit gate and auxiliary single-bit gate operations by means of the complementary control principle.
[0011] As a further aspect of the present invention, the additional phase gate introduced during the state switching operation is moved to the input and / or output of the routing circuit through a commutation relationship.
[0012] As a further aspect of the present invention: the first native multi-bit gate and / or the second native multi-bit gate are directly implemented through a single microwave pulse or a multi-pulse sequence on a superconducting quantum platform.
[0013] As a further aspect of the present invention: the qubits of the bucket-type quantum random access memory are mapped onto a two-dimensional superconducting quantum bit chip in a binary tree structure.
[0014] As a further aspect of the present invention, the first native multi-bit gate is used to realize long-range state exchange between non-nearest neighbor qubits on the two-dimensional chip.
[0015] As a further aspect of the present invention, it also includes: increasing the total number of multi-bit gates and circuit depth of the quantum random access memory during query operations.
[0016] The second aspect of the technical solution: A system employing a quantum random access memory implementation method based on a superconducting quantum platform as described in any of the above claims, comprising: A superconducting quantum chip, on which multiple qubits are fabricated to form a barrel-type quantum random access memory routing structure; A quantum gate control device is used to drive the superconducting quantum chip to perform gate operations on the qubits; The quantum gate control device is configured to: directly realize state exchange operations between qubits by applying a first native multi-bit gate that is physically compatible with superconducting qubits, and directly realize controlled state exchange operations by applying a second native multi-bit gate, thereby constructing a quantum query path.
[0017] Compared with the prior art, the present invention has the following technical advantages: By adopting the above technical solution, the routing circuit of the bucket-type quantum random access memory (QRAM) abandons the traditional complex decomposition of SWAP gates and controlled SWAP gates, and instead uses native multi-qubit gates that are naturally compatible with the physical characteristics of the superconducting quantum bit platform. This directly realizes the state exchange and controlled state exchange operations between qubits, thereby constructing a hardware-efficient quantum query path. This avoids the redundant circuits and numerous operations caused by traditional gate decomposition, significantly reducing the circuit depth and the number of multi-qubit gates in the entire quantum random access memory. Consequently, it greatly reduces the accumulation of decoherence effects and operational errors, ultimately achieving a key breakthrough in constructing a scalable, high-fidelity quantum memory on a superconducting platform. Attached Figure Description
[0018] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings: Figure 1 This is a schematic diagram illustrating the steps of the memory implementation method according to an embodiment of this application; Figure 2 This is a schematic diagram of the circuit structure of a bucket-queue quantum random access memory (BB-QRAM) with a depth of 3, according to an embodiment of this application. Figure 3 This diagram illustrates the equivalence between the native iSCZ gate and the traditional SWAP gate in the embodiments disclosed in this application. Figure 4 This diagram illustrates the equivalence between the native gate C-iSCZ and the traditional CSWAP gate in the embodiments disclosed in this application. Figure 5 This is a schematic diagram of a single pulse of the iSCZ gate on a superconducting platform according to an embodiment of this application; Figure 6 This is a schematic diagram of the layout of a barrel-type quantum random access memory with a depth of 5 on a two-dimensional superconducting qubit grid, according to an embodiment of this application. Figure 7 This table compares the resource consumption of QRAM routing operations implemented using different gate sets at different layers according to the embodiments disclosed in this application. Detailed Implementation
[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0020] Please refer to Figure 1 In this embodiment of the invention, a method for implementing a quantum random access memory based on a superconducting quantum platform includes the following steps: Step S1: In the routing circuit of the bucket-type quantum random access memory, the state exchange operation between qubits is directly realized using the first native multi-qubit gate, which is physically adapted to the superconducting qubit platform. Step S2: Use a second native multi-bit gate that is physically adapted to the platform to directly implement the controlled state exchange operation; The combination of the first native multi-bit gate and the second native multi-bit gate is used to replace the SWAP gate and the controlled SWAP gate, which are composed of the decomposition of the basic double-bit gate, in order to reduce the depth of the routing circuit.
[0021] like Figure 2 The diagram illustrates the circuit structure of the bucket-queue quantum random access memory (BB-QRAM) according to an embodiment of the present invention at a depth of 3. A hierarchical routing and switching structure is employed, with address and data being transferred layer by layer through internal swap and routing operations at each layer, ensuring that query requests can reach the target storage unit.
[0022] in: The horizontal line represents the quantum bit channel, and the three lines above it are the bus and the address bits a0, a1, a2, respectively. The qubit pairs (l,i)-a and (l,i)-d below represent the address register and data register located at the i-th node of the l-th layer, respectively. The cross symbol (X) indicates a SWAP or controlled SWAP operation; The yellow highlighted parts represent internal swap and routing operations, such as Internal Swap(0), Routing(0,1), Internal Swap(1), etc. The green highlighted section represents the inter-layer routing operation Routing(l, l+1), which is used to select data paths under the control of address bits; Arrow labels such as Routing(1,2) indicate the routing process between different layers.
[0023] This circuit achieves the layer-by-layer transfer of address information in the binary tree structure by sequentially performing internal switching and routing operations at each layer, thereby completing the quantum query for the target memory unit.
[0024] In this embodiment, the first native multi-bit gate is an iSCZ gate, which, when combined with a local phase gate, is equivalent to a SWAP gate.
[0025] In this embodiment, the second native multi-bit gate is a C-iSCZ gate, which, when combined with a controlled phase gate, is equivalent to a controlled SWAP gate.
[0026] like Figure 3 As shown in the figure, this invention illustrates the equivalence between the native iSCZ gate and the traditional SWAP gate. The iSCZ gate can be converted into a SWAP gate through a local phase gate. This avoids multiple CX decompositions, reducing circuit depth and error accumulation.
[0027] like Figure 4 As shown in the figure, the diagram illustrates the equivalence between the native gate C-iSCZ proposed in this invention and the traditional CSWAP gate. By introducing a phase gate, the C-iSCZ gate can efficiently replace the CSWAP gate.
[0028] In this embodiment, in the routing node, the paired controlled state exchange operation is simplified to two second native multi-bit gates and an auxiliary single-bit gate operation through the complementary control principle. Utilizing the complementary control characteristics, the paired CSWAP in the router is simplified to only two C-iSCZ operations and a small number of single-bit gates, thereby reducing the number of multi-bit gates from 6 to 2.
[0029] In this embodiment, the additional phase gate introduced during the state switching operation is moved to the input and / or output of the routing circuit through a commutation relationship.
[0030] In this embodiment, the first native multi-bit gate and / or the second native multi-bit gate are directly implemented through a single microwave pulse or a multi-pulse sequence on a superconducting quantum platform.
[0031] In this embodiment, the qubits of the bucket-type quantum random access memory are mapped onto a two-dimensional superconducting quantum bit chip in a binary tree structure.
[0032] In this embodiment, the first native multi-bit gate is used to realize long-range state exchange between non-nearest neighbor qubits on the two-dimensional chip.
[0033] In this embodiment, it also includes: increasing the total number of multi-bit gates and the circuit depth of the quantum random access memory during query operations.
[0034] like Figure 5 As shown in the figure, this is a single-pulse implementation scheme of the iSCZ gate on a superconducting platform. The horizontal axis represents time (ns), and the vertical axis represents frequency (GHz). The blue curve represents the frequency change of the modulation pulse, the red line represents the reference frequency, and the yellow dashed line represents the operation termination time. The scheme controls the operation time to approximately 52 ns, and the gate fidelity can reach 99.994%.
[0035] like Figure 6 As shown in the diagram, a bucket-type quantum random access memory with a depth of 5 is laid out on a two-dimensional superconducting qubit grid. In this grid, yellow diamonds represent bus bits, blue dots represent root data registers, red plus signs represent address registers, black dots represent data registers, and green arrows represent long-range switching paths. By combining the long-range switching capability of iSCZ gates, the path indicated by the green arrow can achieve efficient routing, further reducing the impact of decoherence.
[0036] In a specific implementation, a set of native quantum gates is defined: A new primordial quantum gate, iSCZ, is defined, with the following matrix form:
[0037]
[0038] in, For phase gates, defined as:
[0039] This gate satisfies the following equivalence relation:
[0040] In other words, the combination of iSCZ and local phase gate is equivalent to the traditional SWAP operation, which can be implemented with a single pulse, a gate time of about 52 ns, and a fidelity of up to 99.994%.
[0041] A new three-bit gate C-iSCZ is defined to replace the traditional CSWAP operation, and its decomposition form is as follows:
[0042] This enables a highly efficient barrel-shaped quantum router.
[0043] In a specific implementation, complementary control optimization is performed as follows: Based on the principle of "complementary control", the paired CSWAP operation in the router is simplified to only two C-iSCZ operations and a small number of single-bit gates, thereby reducing the number of multi-bit gates from 6 in the original scheme to 2, which significantly reduces the circuit complexity.
[0044]
[0045]
[0046] Phase gate virtualization: By virtualizing the phase gates and commutating them, the additional phase gates are moved to the beginning and end of the circuit, reducing the number of phase gate layers from O(n) to O(1), thereby reducing the overall time complexity.
[0047] 2D layout optimization: An improved H-tree structure is adopted in a two-dimensional superconducting qubit network, combined with iSCZ gates to realize long-range quantum state exchange, which further shortens the circuit depth and effectively improves the resistance to decoherence.
[0048] Through the above technical solutions, this invention can efficiently realize barrel-type transfer QRAM on a superconducting platform, avoiding the complex gate decomposition process in traditional solutions, and significantly reducing the circuit depth and the number of multi-bit gates, thereby greatly improving the implementation efficiency and noise immunity of QRAM, and having good scalability and practical value.
[0049] like Figure 7 As shown in the figure, the table compares the resource consumption of QRAM routing operations using different gate sets at different layers. It lists the number of gates and circuit depth of the CSWAP, C-iSCZ and CX decomposition schemes.
[0050] The gate count and circuit depth of traditional CSWAP, C-iSCZ, and CX decomposition schemes were compared at different levels. The results show that the proposed {iSCZ, C-iSCZ, S†} native gate set can reduce the circuit depth by approximately one order of magnitude and the number of multi-bit gates by approximately 8 times while maintaining functional correctness, thus significantly improving the hardware efficiency and scalability of QRAM.
[0051] The second aspect of the technical solution: A system employing a quantum random access memory implementation method based on a superconducting quantum platform as described in any of the above claims, comprising: A superconducting quantum chip, on which multiple qubits are fabricated to form a barrel-type quantum random access memory routing structure; A quantum gate control device is used to drive the superconducting quantum chip to perform gate operations on the qubits; The quantum gate control device is configured to: directly realize state exchange operations between qubits by applying a first native multi-bit gate that is physically compatible with superconducting qubits, and directly realize controlled state exchange operations by applying a second native multi-bit gate, thereby constructing a quantum query path.
[0052] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention. The scope of the invention is defined by the appended claims and their equivalents, all of which should be included within the scope of protection of the invention.
Claims
1. A method for implementing a quantum random access memory based on a superconducting quantum platform, characterized in that, Includes the following steps: In the routing circuit of the bucket-type quantum random access memory, the state exchange operation between qubits is directly realized using the first native multi-qubit gate, which is physically adapted to the superconducting qubit platform. The controlled state exchange operation is directly implemented using a second native multi-bit gate that is physically adapted to the platform. The combination of the first native multi-bit gate and the second native multi-bit gate is used to replace the SWAP gate and the controlled SWAP gate, which are composed of the decomposition of the basic double-bit gate, in order to reduce the depth of the routing circuit.
2. The method for implementing a quantum random access memory based on a superconducting quantum platform according to claim 1, characterized in that, The first native multi-bit gate in the step is an iSCZ gate, which, when combined with a local phase gate, is equivalent to a SWAP gate.
3. The method for implementing a quantum random access memory based on a superconducting quantum platform according to claim 1, characterized in that, The second native multi-bit gate is a C-iSCZ gate, which, when combined with a controlled phase gate, is equivalent to a controlled SWAP gate.
4. The method for implementing a quantum random access memory based on a superconducting quantum platform according to claim 1, characterized in that, In the routing node, the paired controlled state exchange operation is simplified into two second native multi-bit gate and auxiliary single-bit gate operations through the complementary control principle.
5. The method for implementing a quantum random access memory based on a superconducting quantum platform according to claim 1, characterized in that, The additional phase gates introduced during state switching operations are moved to the input and / or output of the routing circuit via commutation relations.
6. The method for implementing a quantum random access memory based on a superconducting quantum platform according to claim 1, characterized in that, The first and / or second native multi-bit gates are directly realized via a single microwave pulse or a multi-pulse sequence on a superconducting quantum platform.
7. The method for implementing a quantum random access memory based on a superconducting quantum platform according to claim 1, characterized in that, The qubits of the bucket-type quantum random access memory are mapped onto a two-dimensional superconducting quantum bit chip in a binary tree structure.
8. The method for implementing a quantum random access memory based on a superconducting quantum platform according to claim 7, characterized in that, The first native multi-bit gate is used to realize long-range state exchange between non-nearest neighbor qubits on the two-dimensional chip.
9. The method for implementing a quantum random access memory based on a superconducting quantum platform according to claim 1, characterized in that, Also includes: This increases the total number of multi-bit gates and the circuit depth of the quantum random access memory during query operations.
10. A system employing the quantum random access memory implementation method based on a superconducting quantum platform as described in any one of claims 1 to 9, characterized in that, include: A superconducting quantum chip, on which multiple qubits are fabricated to form a barrel-type quantum random access memory routing structure; A quantum gate control device is used to drive the superconducting quantum chip to perform gate operations on the qubits; The quantum gate control device is configured to: directly realize state exchange operations between qubits by applying a first native multi-bit gate that is physically compatible with superconducting qubits, and directly realize controlled state exchange operations by applying a second native multi-bit gate, thereby constructing a quantum query path.