Nonvolatile memory device and memory device

Abstract

The invention provides a nonvolatile memory device and a storage device. The memory device includes: a non-volatile memory chip including a first non-volatile memory chip and a second non-volatile memory chip; and a storage controller. The first non-volatile memory chip includes: a first chip enabling interface circuit; and a first chip interface pin connected to the first chip enabling interface circuit. The first non-volatile memory chip performs a first DMA operation. The first chip enable interface circuit internally generates a self-termination signal indicating completion of the first DMA operation and transmits the self-termination signal to the second non-volatile memory chip through the first chip interface pin. The second non-volatile memory chip includes a second chip interface pin and a second chip enable interface circuit connected to the second chip interface pin, is self-enabled based on the self-termination signal, and performs a second DMA operation without a select chip enable command from the memory controller.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2024-0139124, filed on October 14, 2024, with the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This application relates to non-volatile memory devices and storage devices. Background Technology

[0003] Semiconductor memory devices used for storing data can be classified into volatile memory devices and non-volatile memory devices. Volatile memory devices (such as dynamic random access memory (DRAM) devices) are typically configured to store data by charging or discharging capacitors in memory cells and to lose the stored data when power is off.

[0004] Non-volatile memory devices (such as flash memory devices) are widely used to store large amounts of data. Recently, in non-volatile memory devices, data input / output (I / O) speeds have increased to handle large amounts of data, and I / O efficiency has decreased due to direct memory access (DMA) overhead. Summary of the Invention

[0005] Some example implementations may provide storage devices that can self-terminate and / or self-enable without external commands.

[0006] Some example implementations provide non-volatile memory devices that can self-terminate and / or self-enable without external commands.

[0007] According to some example embodiments, a storage device includes: a plurality of non-volatile memory chips, including a first non-volatile memory chip and a second non-volatile memory chip; and a storage controller for controlling the plurality of non-volatile memory chips. The first non-volatile memory chip includes: a first memory cell array; a first chip enable interface circuit; a first chip interface pin connected to the first chip enable interface circuit; and a first control circuit for controlling the operation of the first non-volatile memory chip. The first non-volatile memory chip performs a first direct memory access (DMA) operation to send first read data from the first memory cell array to the storage controller based on a first data output command from the storage controller. The first chip enable interface circuit internally generates a first self-termination signal indicating completion of the first DMA operation based on a first start address associated with the first read data, and provides the first self-termination signal to the second non-volatile memory chip via the first chip interface pin. The second non-volatile memory chip includes: a second chip interface pin for receiving the first self-termination signal, and a second chip enable interface circuit connected to the second chip interface pin. The second non-volatile memory chip self-enabled based on the first self-termination signal from the first non-volatile memory chip.

[0008] According to some example embodiments, a non-volatile memory device includes: a memory cell array including a plurality of memory planes, the plurality of memory planes including a first memory plane and a second memory plane; a plurality of page buffer circuits corresponding to the plurality of memory planes; data input / output (I / O) circuitry connected to the plurality of page buffer circuits via corresponding data lines; a chip enable interface circuitry; chip interface pins connected to the chip enable interface circuitry; and control circuitry for controlling the operation of the non-volatile memory device. Each of the plurality of page buffer circuits is connected to a corresponding one of the plurality of memory planes via a corresponding bit line. Based on a first data output command from a memory controller, the control circuitry performs a first direct memory access (DMA) operation to output first read data from the first memory plane to the memory controller via the data I / O circuitry; based on the first DMA operation being performed, a second data output command is received from the memory controller. The chip enable interface circuitry generates a self-termination signal indicating the completion of the first DMA operation based on a first start address associated with the first read data, and generates a self-enable signal based on the self-termination signal. In response to the second data output command and the self-enable signal, the control circuit performs a second DMA operation to output the second read data from the second memory plane to the memory controller via the data I / O circuit.

[0009] According to some example embodiments, a storage device includes: a plurality of non-volatile memory chips, including a first non-volatile memory chip and a second non-volatile memory chip; and a storage controller for controlling the plurality of non-volatile memory chips. The first non-volatile memory chip includes a first memory cell array, a first chip enable interface circuit, a first chip interface pin connected to the first chip enable interface circuit, and a first control circuit for controlling the operation of the first non-volatile memory chip. The first non-volatile memory chip performs a first direct memory access (DMA) operation to send first read data from the first memory cell array to the storage controller based on a first data output command from the storage controller. The first chip enable interface circuit generates a first self-termination signal indicating the completion of the first DMA operation based on a first start address associated with the first read data, and provides the first self-termination signal to the second non-volatile memory chip through the first chip interface pin. The second non-volatile memory chip includes a second chip interface pin for receiving the first self-termination signal and a second first chip enable interface connected to the second chip interface pin. The second non-volatile memory chip is self-enabled based on a first self-termination signal from the first non-volatile memory chip; and performs a second DMA operation based on a second data output command to send second read data from the second memory cell array to the memory controller. The second non-volatile memory chip receives the second data output command from the memory controller during the first non-volatile memory chip's execution of the first DMA operation.

[0010] Therefore, in the storage device according to the example embodiment, the first non-volatile memory chip can perform a first DMA operation based on a first data output command to output first read data to the storage controller, can internally generate a self-termination signal indicating the completion of the first DMA operation based on an address, and can transmit the self-termination signal to the second non-volatile memory chip. The second non-volatile memory chip can self-enable based on the self-termination signal provided from the first non-volatile memory device, and can perform a second DMA operation (as associated with the second data output command) to output second read data to the storage controller without a select chip enable command from the storage controller. Therefore, the non-volatile memory chip can continuously perform DMA operations without select chip enable commands and select chip terminate commands from the storage controller, and thus I / O overhead can be reduced. Attached Figure Description

[0011] The illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 This is a block diagram illustrating a storage device according to an example embodiment.

[0013] Figure 2 This illustrates an example implementation. Figure 1 A block diagram of an example storage controller in a storage device.

[0014] Figure 3 Showing an example implementation Figure 1 An example of the connection between a storage controller and one of a plurality of non-volatile memory devices in a storage device.

[0015] Figure 4 This illustrates an example implementation. Figure 1 A block diagram of an example of one of a plurality of non-volatile memory devices in a storage device.

[0016] Figure 5 This illustrates an example implementation. Figure 4 A block diagram of an example CEI circuit in a non-volatile memory device.

[0017] Figure 6 This illustrates an example implementation. Figure 4 A circuit diagram of the memory plane configuration in a non-volatile memory device.

[0018] Figure 7 The illustration schematically shows an embodiment according to an example implementation. Figure 4 The structure of a non-volatile memory device.

[0019] Figure 8 This illustrates an example implementation. Figure 4 A block diagram of an example of a memory plane.

[0020] Figure 9 It is shown Figure 8 A circuit diagram of one of the memory blocks.

[0021] Figure 10 Show Figure 9 An example of the structure of the cell string CS in a memory block.

[0022] Figure 11 This is based on the example implementation. Figure 4 A schematic diagram of the connection between the memory plane and the page buffer circuit.

[0023] Figure 12 A page buffer according to an example implementation is shown in detail.

[0024] Figure 13 Show Figure 1 The storage medium contains four non-volatile memory devices (non-volatile memory chips).

[0025] Figure 14Show Figure 13 The CEI circuit in the two non-volatile memory devices.

[0026] Figure 15 This illustrates an example implementation. Figure 14 Timing diagram of the operation of non-volatile memory devices in the diagram.

[0027] Figure 16 Show Figure 13 The non-volatile memory devices in the memory continuously perform DMA operations.

[0028] Figure 17 Showing an example implementation Figure 4 Example operation of a non-volatile memory device.

[0029] Figure 18 This illustrates an example implementation. Figure 4 A block diagram of an example of a control circuit in a non-volatile memory device.

[0030] Figure 19 This illustrates an example implementation. Figure 4 A block diagram of an example voltage generator in a non-volatile memory device.

[0031] Figure 20 This illustrates an example implementation. Figure 3 A block diagram illustrating an example of an address decoder in a non-volatile memory device.

[0032] Figure 21 This is a flowchart illustrating an example operation of a non-volatile memory device.

[0033] Figure 22 This is a ladder diagram illustrating an example operation of a non-volatile memory device according to an example implementation.

[0034] Figure 23 This is a block diagram illustrating an electronic system including a semiconductor device according to some example embodiments. Detailed Implementation

[0035] Various exemplary embodiments will be described more fully below with reference to the accompanying drawings, some of which illustrate exemplary embodiments.

[0036] Figure 1 This is a block diagram illustrating a storage device according to an example embodiment.

[0037] Reference Figure 1The storage device 10 may include a storage controller 50 and a storage medium 90. The storage device 10 may support multiple channels (or media channels or storage channels) CHN1, CHN2, ..., CHNp (hereinafter CHN1 to CHNp), and the storage medium 90 may be connected to the storage controller 50 through multiple channels CHN1 to CHNp.

[0038] Storage medium 90 may include a plurality of non-volatile memory devices (or non-volatile memory or non-volatile memory chips) NVM11, NVM12, ..., NVM1t, NVM21, NVM22, ..., NVM2t, NVMp1, NVMp2, ..., NVMpt (hereinafter NVM11 to NVMpt, and t is an integer greater than two). Each of the non-volatile memory devices NVM11 to NVMpt may be referred to as a non-volatile memory chip.

[0039] Each of the non-volatile memory devices NVM11 to NVMpt can be connected to one of the plurality of media channels CHN1 to CHNp via a path corresponding to one of them. For example, non-volatile memory devices NVM11 to NVM1t can be connected to the first media channel CHN1 via paths W11, W12, ..., W1t; non-volatile memory devices NVM21 to NVM2t can be connected to the second media channel CHN2 via paths W21, W22, ..., W2t; and non-volatile memory devices NVMp1 to NVMpt can be connected to the p-th media channel CHNp via paths Wp1, Wp2, ..., Wpt. In some example embodiments, each of the non-volatile memory devices NVM11 to NVMpt can be implemented as an arbitrary memory cell operable according to individual commands from the memory controller 50. For example, each of the non-volatile memory devices NVM11 to NVMpt can be implemented as a chip or a die, but the example embodiments are not limited thereto.

[0040] The storage controller 50 can send signals to and receive signals from the storage medium 90 via multiple media channels CHN1 to CHNp. For example, the storage controller 50 can send commands CMDa, CMDb, ..., CMDp, addresses ADDRa, ADDRb, ..., ADDRp, and data DTAa, DTAb, ..., DTAp to the storage medium 90 via media channels CHN1 to CHNp, or it can receive data DTAa to DTAp from the storage medium 90.

[0041] The storage controller 50 can select one of the non-volatile memories NVM11 to NVMpt connected to each of the media channels CHN1 to CHNp by using a corresponding one of the media channels CHN1 to CHNp, and can send signals to the selected non-volatile memory device and receive signals from the selected non-volatile memory device.

[0042] The storage controller 50 can send signals to and receive signals from the storage medium 90 in parallel through different media channels.

[0043] Storage controller 50 can communicate with external hosts according to the Universal Flash Storage (UFS) standard.

[0044] In an example implementation, each of the storage controller 50 and the storage medium 90 may be provided in the form of a chip, package, or module. Alternatively, the storage controller 50 and the storage medium 90 may be mounted in one of various packages and may be provided with a storage device (such as a memory card).

[0045] Each of the multiple non-volatile memory devices NVM11 to NVMpt, which are associated with the memory channel CHN1, may include a chip enable interface circuit CEIC and a corresponding chip interface pin (or interface pin) IP11, IP12, ..., IP1t. The non-volatile memory devices NVM11, NVM12, ..., NVM1t can be connected together via the interface pin IP11, IP12, ..., IP1t. The first non-volatile memory device NVM11 among the non-volatile memory devices NVM11, NVM12, ..., NVM1t can perform a first direct memory access (DMA) operation in response to a first data output command from the memory controller 50 to send first read data to the memory controller 50. It can internally generate a self-termination signal indicating the completion of the first DMA operation based on an address, and can provide the self-termination signal to the non-volatile memory devices NVM12, ..., NVM1t via the chip interface pin IP11. The second non-volatile memory device NVM12, ..., NVM1t that receives the second data output command can be self-enabled based on a self-termination command, and can perform a second DMA operation associated with the second data output command without a selection chip enable command from the memory controller 50. The non-volatile memory devices NVM11, NVM12, ..., NVM1t can reduce input / output overhead by continuously performing DMA operations without selection chip termination commands and selection chip enable commands.

[0046] Similarly, each of the multiple non-volatile memory devices NVM11 to NVMpt that is coupled to the memory channel CHN2, NVM21, NVM22, ..., NVM2t may include a chip enable interface circuit CEIC and a corresponding chip interface pin IP21, IP22, ..., IP2t, and the non-volatile memory devices NVM21, NVM22, ..., NVM2t may be connected together via the interface pin IP21, IP22, ..., IP2t. Similarly, each of the multiple non-volatile memory devices NVM11 to NVMpt that is coupled to the memory channel CHNp, NVMp1, NVMp2, ..., NVMpt may include a chip enable interface circuit CEIC and a corresponding chip interface pin IPp1, IPp2, ..., IPpt, and the non-volatile memory devices NVMp1, NVMp2, ..., NVMpt may be connected together via the interface pin IPp1, IPp2, ..., IPpt. Non-volatile memory devices NVM21, NVM22, ..., NVM2t and non-volatile memory devices NVMp1, NVMp2, ..., NVMpt can operate similarly to non-volatile memory devices NVM11, NVM12, ..., NVM1t.

[0047] The storage controller 50 may include a processor 60 and an error correction code (ECC) engine 70. (See reference...) Figure 2 Describe the operation of processor 60 and ECC engine 70.

[0048] Figure 2 This illustrates an example implementation. Figure 1 A block diagram of an example storage controller in a storage device.

[0049] Reference Figure 2 The storage controller 50 may include a processor 60, an ECC engine 70, an on-chip memory 75, an Advanced Encryption Standard (AES) engine 80, a host interface 82, a ROM 84, and a memory interface 86 connected via a bus 55.

[0050] Processor 60 controls the overall operation of storage controller 50. Processor 60 controls ECC engine 70, on-chip memory 75, AES engine 80, host interface 82, ROM 84, and memory interface 86. Processor 60 may include one or more cores (e.g., homogeneous multi-core or heterogeneous multi-core). Processor 60 may be or include at least one of, for example, a central processing unit (CPU), image signal processor (ISP), digital signal processor (DSP), graphics processing unit (GPU), vision processor (VPU), and neural processor (NPU). Processor 60 can execute various applications loaded onto on-chip memory 75 (e.g., flash translation layer (FTL) 77 and firmware).

[0051] On-chip memory 75 can store various application programs that can be executed by processor 60. On-chip memory 75 can operate as a cache memory adjacent to processor 60. On-chip memory 75 can store commands, addresses, and data to be processed by processor 60, or it can store the processing results of processor 60. On-chip memory 75 can be a storage medium or working memory, such as including latches, registers, static random access memory (SRAM), dynamic random access memory (DRAM), thyristor random access memory (TRAM), tightly coupled memory (TCM), etc.

[0052] Processor 60 can execute an FTL 77 loaded onto on-chip memory 75. FTL 77 can be loaded onto on-chip memory 75 as a program or firmware stored in at least one of a plurality of non-volatile memory devices NVM11 to NVMpt. FTL 77 can manage the mapping between logical addresses provided from the host and the physical addresses of at least one of the plurality of non-volatile memory devices NVM11 to NVMpt, and may include an address mapping table manager that manages and updates the address mapping table. FTL 77 can also perform garbage collection operations, wear leveling operations, etc., and the address mapping described above. FTL 77 can be executed by processor 60 to address one or more of the following aspects of at least one of the plurality of non-volatile memory devices NVM11 to NVMpt: rewrite or in-place write-is impossible, memory cell lifetime, finite number of program-erase (PE) cycles, and erase speed slower than write speed.

[0053] The memory cells of multiple non-volatile memory devices NVM11 to NVMpt may have physical characteristics where the threshold voltage distribution varies due to factors such as programming elapsed time, temperature, programming interference, and read interference. For example, due to the above reasons, the data stored in the multiple non-volatile memory devices NVM11 to NVMpt may become corrupted.

[0054] The storage controller 50 may utilize various error correction techniques to correct such errors. For example, the storage controller 50 may include an ECC engine 70. The ECC engine 70 may correct errors occurring in data stored in a plurality of non-volatile memory devices NVM11 to NVMpt. The ECC engine 70 may include an ECC encoder 71 and an ECC decoder 73. The ECC encoder 71 may perform ECC encoding operations on data to be stored in at least one of the plurality of non-volatile memory devices NVM11 to NVMpt. The ECC decoder 73 may perform ECC decoding operations on data read from at least one of the plurality of non-volatile memory devices NVM11 to NVMpt. The ECC decoder 73 may correct errors in the hard decision data based on hard decision data and soft decision data read from at least one of the plurality of non-volatile memory devices NVM11 to NVMpt.

[0055] ROM 84 can store various information required for the operation of storage controller 50 in the firmware.

[0056] The AES engine 80 can perform at least one of encryption and decryption operations on data input to the storage controller 50 using a symmetric key algorithm. Although not shown in detail, the AES engine 80 may include an encryption module and a decryption module. For example, the encryption and decryption modules may be implemented as separate modules. As another example, a module capable of performing both encryption and decryption operations may be implemented in the AES engine 80.

[0057] The storage controller 50 can communicate with the host via the host interface 82. For example, the host interface 82 may include Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC, Peripheral Component Interconnect (PCI), PCI Express, Advanced Technology Accessory (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Mobile Industrial Processor Interface (MIPI), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), etc. The storage controller 50 can communicate with the storage medium 90 via the memory interface 86. The memory interface 86 may be referred to as the storage interface.

[0058] Figure 3 Showing an example implementation Figure 1 An example of the connection between a storage controller and one of a plurality of non-volatile memory devices in a storage device.

[0059] Reference Figure 3 The storage device 10a may include a non-volatile memory device 100 and a storage controller 50. Figure 3 The interface between the non-volatile memory device 100 and the memory controller 50 is shown in detail.

[0060] The non-volatile memory device 100 may include first to eighth pins P11, P12, P13, P14, P15, P16, P17 and P18, interface circuitry 105, control logic circuitry (or control circuitry) 480, memory cell array 200 and chip enable interface (CEI) circuitry 430. Interface circuitry 105 may be referred to as the first interface circuitry or the memory interface circuitry.

[0061] Interface circuit 105 can receive a chip enable signal nCE from memory controller 50 via first pin P11. Interface circuit 105 can send signals to and receive signals from memory controller 50 via second pin P12 to eighth pin P18 in response to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., low level), interface circuit 105 can send signals to and receive signals from memory controller 50 via second pin P12 to eighth pin P18.

[0062] Interface circuit 105 can receive command latch enable signal CLE, address latch enable signal ALE, and write enable signal nWE from memory controller 50 via pins P12 to P14. Interface circuit 105 can receive data signal DQ from memory controller 50 via pin P17, or can send data signal DQ to memory controller 50. Command CMD, address ADDR, and data DTA can be sent via data signal DQ. For example, data signal DQ can be sent via multiple data signal lines. In this case, pin P17 may include multiple pins corresponding to the multiple data signals DQ respectively.

[0063] Interface circuit 105 can obtain command CMD from data signal DQ that is received during the enable interval (e.g., high level state) of command latch enable signal CLE based on the switching time point of write enable signal nWE. Interface circuit 105 can obtain address ADDR from data signal DQ that is received during the enable interval (e.g., high level state) of address latch enable signal ALE based on the switching time point of write enable signal nWE.

[0064] In some example implementations, the write enable signal nWE may be held statically (e.g., high or low) and may toggle between high and low levels. For example, the write enable signal nWE may toggle within a range when sending command CMD or address ADDR. Therefore, the interface circuit 105 may obtain command CMD or address ADDR based on the switching timing of the write enable signal nWE.

[0065] Interface circuit 105 can receive the read enable signal nRE from memory controller 50 via pin 5 P15. Interface circuit 105 can receive the data strobe signal DQS from memory controller 50 via pin 6 P16, or it can send the data strobe signal DQS to memory controller 50.

[0066] In the data output operation of the non-volatile memory device 100, the interface circuit 105 may receive a read enable signal nRE switched via pin P15 before outputting data DTA. The interface circuit 105 may generate a data strobe signal DQS that switches based on the switching of the read enable signal nRE. For example, the interface circuit 105 may generate a data strobe signal DQS that starts switching after a predetermined delay (e.g., tDQSRE) based on the switching start time of the read enable signal nRE. The interface circuit 105 may transmit a data signal DQ including the data DTA based on the switching time of the data strobe signal DQS. Therefore, the data DTA may be aligned with the switching time of the data strobe signal DQS and may be sent to the memory controller 50.

[0067] In the data input operation of the non-volatile memory device 100, when a data signal DQ including data DTA is received from the memory controller 50, the interface circuit 105 can receive a switched data strobe signal DQS and the data DTA from the memory controller 50. The interface circuit 105 can obtain the data DTA from the data signal DQ based on the switching time point of the data strobe signal DQS. For example, the interface circuit 105 can sample the data signal DQ at the rising and falling edges of the data strobe signal DQS and obtain the data DTA.

[0068] Interface circuit 105 can send a ready / busy signal nR / B to memory controller 50 via pin 8 P18. Interface circuit 105 can also send status information of non-volatile memory device 100 to memory controller 50 via the ready / busy signal nR / B. When non-volatile memory device 100 is in a busy state (e.g., when an operation is being performed in non-volatile memory device 100), interface circuit 105 can send a ready / busy signal nR / B indicating the busy state to memory controller 50. When non-volatile memory device 100 is in a ready state (e.g., when no operation is being performed or completed in non-volatile memory device 100), interface circuit 105 can send a ready / busy signal nR / B indicating the ready state to memory controller 50.

[0069] Control circuit 480 controls the overall operation of non-volatile memory device 100. Control circuit 480 receives commands (CMD) and addresses (ADDR) from interface circuit 105. Control circuit 480 generates control signals for controlling other components of non-volatile memory device 100 in response to the received commands (CMD) and addresses (ADDR). For example, control circuit 480 generates various control signals for programming data DTA to or reading data DTA from memory cell array 200.

[0070] The memory cell array 200 can store the data DTA obtained from the interface circuit 105 under the control of the control circuit 480. The memory cell array 200 can also output the stored data DTA to the interface circuit 105 under the control of the control circuit 480.

[0071] The memory cell array 200 may include multiple non-volatile memory cells.

[0072] The CEI circuit 430 can generate a self-termination signal indicating the completion of a DMA operation based on an address, and can send the self-termination signal to another non-volatile memory device via a chip interface pin. As used herein, in some examples of this disclosure, the generated signal may include an activation signal, wherein the activation signal may indicate a change of the signal from a first level to a second level. The first level may be associated with a deactivation state of the signal, while the second level may be associated with an activation state of the signal. Note that in some other examples, the generated signal may not include an activation signal.

[0073] The storage controller 50 may include first to eighth pins P21, P22, P23, P24, P25, P26, P27, and P28, as well as interface circuitry 87. Interface circuitry 87 may be referred to as a second interface circuit or a controller interface circuit. Interface circuitry 87 may correspond to... Figure 2 The memory interface 86 in the memory. The first pin P21 to the eighth pin P28 can respectively correspond to the first pin P11 to the eighth pin P18 of the non-volatile memory device 100.

[0074] Interface circuit 87 can send the chip enable signal nCE to non-volatile memory device 100 via the first pin P21. Interface circuit 87 can send signals to and receive signals from non-volatile memory device 100 selected by chip enable signal nCE via the second pin P22 to the eighth pin P28.

[0075] Interface circuit 87 can send the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the non-volatile memory device 100 via pins P22 to P24. Interface circuit 87 can send the data signal DQ to or receive the data signal DQ from the non-volatile memory device 100 via pin P27.

[0076] Interface circuit 87 can send a data signal DQ, including command CMD or address ADDR, together with a switchable write enable signal nWE to the non-volatile memory device 100. Interface circuit 87 can also send the data signal DQ, including command CMD, to the non-volatile memory device 100 by sending a command latch enable signal CLE with an enabled state. Furthermore, interface circuit 87 can send the data signal DQ, including address ADDR, to the non-volatile memory device 100 by sending an address latch enable signal ALE with an enabled state.

[0077] Interface circuit 87 can send the read enable signal nRE to non-volatile memory device 100 via pin 5 P25. Interface circuit 87 can receive the data strobe signal DQS from non-volatile memory device 100 or send the data strobe signal DQS to non-volatile memory device 100 via pin 6 P26.

[0078] Interface circuit 87 can receive a ready / busy signal nR / B from non-volatile memory device 100 via pin 8 P28. Interface circuit 87 can determine the status information of non-volatile memory device 100 based on the ready / busy signal nR / B.

[0079] Figure 4 This illustrates an example implementation. Figure 1 A block diagram of an example of one of a plurality of non-volatile memory devices in a storage device.

[0080] Reference Figure 4 The non-volatile memory device 100a may include a memory cell array 200a and peripheral circuitry 250a.

[0081] The memory cell array 200a may include PLN1 (210), PLN2 (220), PLN3 (230) and PLN4 (240) corresponding to different bit lines.

[0082] The peripheral circuitry 250a may include multiple page buffer circuits 410a, 410b, 410c and 410d, a data input / output (I / O) circuit 420a, a CEI circuit 430a, a control circuit 480a, a voltage generator 500a and an address decoder 300a.

[0083] Memory cell array 200a can be coupled to address decoder 300 via serial select line SSL, multiple word lines WL, and ground select line GSL. Each of multiple page buffer circuits 410a, 410b, 410c, and 410d can be connected to a corresponding one of multiple memory planes 210, 220, 230, and 240 via a corresponding bit line BL. The multiple memory planes 210, 220, 230, and 240 may include multiple non-volatile memory cells coupled to multiple word lines WL and multiple bit lines BL.

[0084] Each of the plurality of memory planes 210, 220, 230, and 240 may include a plurality of memory blocks, and each of the memory blocks may have a three-dimensional (3D) structure. Each of the memory blocks may include a plurality of (vertical) cell strings, and each of the cell strings includes a plurality of memory cells stacked relative to each other. Each of the plurality of memory planes 210, 220, 230, and 240 may be referred to as a first memory plane 210, a second memory plane 220, a third memory plane 230, and a fourth memory plane 240.

[0085] Each of the multiple page buffer circuits 410a, 410b, 410c and 410d can be connected to the data I / O circuit 420a via the corresponding data line DL.

[0086] The control circuit 480a can receive commands CMD, address ADDR, and control signals CTRL from the memory controller 50, and can control the erase cycle, programming cycle, and read operation of the non-volatile memory device 100 based on the commands CMD, address ADDR, and control signals CTRL. The programming cycle may include programming operations and programming verification operations, and the erase cycle may include erase operations and erase verification operations.

[0087] In the example implementation, the control circuit 480a can generate a control signal CTL for controlling the voltage generator 500a based on the command CMD, and can provide the control signal CTL to the voltage generator 500a. It can also generate a page buffer control signal PCTL for controlling multiple page buffer circuits 410a, 410b, 410c and 410d, and can provide the page buffer control signal PCTL to the multiple page buffer circuits 410a, 410b, 410c and 410d.

[0088] Furthermore, control circuit 480a can generate row address R_ADDR and column address C_ADDR based on address signal ADDR. Control circuit 480a can provide row address R_ADDR to address decoder 300a and column address C_ADDR to data I / O circuit 420a. Control circuit 480a may include status signal generator 495a, and status signal generator 495a can generate read / busy signal (e.g., status signal) nR / B indicating the operating status of non-volatile memory device 100.

[0089] Address decoder 300a can be integrated into memory cell array 200a via serial select line SSL, multiple word lines WL, and ground select line GSL. During programming or reading operations, address decoder 300a can determine one of the multiple word lines WL as the selected word line based on row address R_ADDR, and can determine the remaining multiple word lines WL as unselected word lines.

[0090] Based on the control signal CTL from the control circuit 480a, the voltage generator 500a can use the power PWR provided from the memory controller 50 to generate a word line voltage VWL associated with the operation of the non-volatile memory device 100a. The word line voltage VWL may include a programming voltage, a read voltage, a pass voltage, an erase verification voltage, or a programming verification voltage. The word line voltage VWL can be applied to multiple word lines WL via the address decoder 300a.

[0091] For example, during an erase operation, voltage generator 500a can apply an erase voltage to the channels of the cell string of the selected memory block, and can apply a ground voltage to all word lines of the selected memory block. During an erase verification operation, voltage generator 500a can apply an erase verification voltage to all word lines of the selected memory block, or can apply an erase verification voltage to word lines of the selected memory block based on word lines.

[0092] For example, during a programming operation, voltage generator 500a can apply a programming voltage to the selected word line and a programming pass voltage to the unselected word line. Furthermore, during a programming verification operation, voltage generator 500a can apply a programming verification voltage to the selected word line and a verification pass voltage to the unselected word line. Additionally, during a reading operation, voltage generator 500a can apply a reading voltage to the selected word line and a reading pass voltage to the unselected word line.

[0093] Each of the multiple page buffer circuits 410a, 410b, 410c, and 410d may include multiple page buffers PB. Each of the multiple page buffer circuits 410a, 410b, 410c, and 410d may temporarily store data to be programmed in a selected page or data read from a selected page of the memory cell array 200a.

[0094] In the example implementation, a page buffer cell (e.g., included in each of a plurality of page buffers PB) is described. Figure 11 The first page buffer unit PBU1 to the nth page buffer unit PBUn) and the cache latches included in each of the multiple page buffers PB (e.g., Figure 11 The first cache latch (CL1) to the nth cache latch (CLn) in the cache buffer can be separated from each other and have a separate structure. Therefore, the degree of freedom of routing on the page buffer unit can be increased, and the layout complexity can be reduced. In addition, because the cache latches are adjacent to the data I / O lines, the distance between the cache latches and the data I / O lines can be reduced, and thus the data I / O speed can be improved.

[0095] Control circuitry 480a can control the operation of non-volatile memory device 100a based on control signal CTRL and command CMD. In response to a first read command, control circuitry 480a can perform a first read operation by sensing read data stored in one of a plurality of memory planes 210, 220, 230 and 240, and can perform a first DMA operation based on a first data output command from memory controller 50 to output sensed data (e.g., first read data) to memory controller 50 via data I / O circuitry 420a.

[0096] In transmit mode, CEI circuit 430a can receive a start address S_ADDR associated with the start of the first DMA operation, generate a self-termination signal indicating the completion of the first DMA operation based on the start address S_ADDR, and transmit the self-termination signal to another non-volatile memory device via chip interface pin 110a. CEI circuit 430a can provide the self-termination signal STE to control circuit 480a.

[0097] In receive mode, CEI circuit 430a can receive a self-termination signal from another non-volatile memory device through chip interface pin 110a. Based on the self-termination signal, it can generate an internal chip enable signal InCE12 for self-enabling non-volatile memory device 100a and provide the internal chip enable signal InCE12 to control circuit 480a.

[0098] Control circuit 480a can receive a chip enable signal as part of control signal CTRL, can activate internal chip enable signal InCE11 with a logic low level, and can provide the activated internal chip enable signal InCE11 to CEI circuit 430a. For example, control circuit 480a can deactivate internal chip enable signal InCE11 based on the activation of self-termination signal STE.

[0099] The CEI circuit 430a can operate in transmit mode based on the activation of the internal chip enable signal InCE11, and can operate in receive mode based on the deactivation of the internal chip enable signal InCE11.

[0100] Figure 5 This illustrates an example implementation. Figure 4 A block diagram of an example CEI circuit in a non-volatile memory device.

[0101] Reference Figure 5 The CEI circuit 430a may include a transmitting circuit 440a and a receiving circuit 460a. The transmitting circuit 440a and the receiving circuit 460a may be connected to the chip interface pin 110a.

[0102] The transmitting circuit 440a can operate in transmitting mode (can be enabled), can detect the completion of the first DMA operation of the non-volatile memory device 100a, can generate a self-termination signal STE indicating the completion of the first DMA operation, and can transmit the self-termination signal STE to another non-volatile memory device through the chip interface pin 110a.

[0103] The receiving circuit 460a can operate in receive mode (can be enabled), can receive a self-termination signal provided from another non-volatile memory device via chip interface pin 110a, can generate an internal chip enable signal InCE12 associated with the self-enablement of the non-volatile memory device 100a, and can provide the internal chip enable signal InCE12 to... Figure 4 The control circuit 480a is included.

[0104] The transmitting circuit 440a may include an address offset calculator 441a, an address counter 443a, an address comparator 445a, a signal generator 447a, and a buffer 449a.

[0105] Address offset calculator 441a can calculate the first read data (from the first start address S_ADDR and the offset information OFS_INF associated with the size of the first read data) based on the first start address S_ADDR and the offset information OFS_INF associated with the size of the first read data. Figure 4 The final address F_ADDR of the memory cell array 200a in the memory cell array 200a is read, and the final address F_ADDR can be provided to the address comparator 445a.

[0106] Address counter 443a can generate a normal address N_ADDR that increments sequentially from the first starting address S_ADDR by performing a counting operation based on the first starting address S_ADDR, and can provide the normal address N_ADDR to address comparator 445a. Address counter 443a can stop the counting operation when the normal address N_ADDR reaches a predetermined address (e.g., the final address F_ADDR).

[0107] Address comparator 445a generates a match signal MTS by comparing the final address F_ADDR and the normal address N_ADDR. Address comparator 445a outputs a match signal MTS with a logic high level based on the match between the normal address N_ADDR and the final address F_ADDR. When the normal address N_ADDR reaches the final address F_ADDR based on the match signal MTS with a logic high level, address counter 443a stops counting. Address counter 443a receives the match signal MTS (not shown) with a logic high level and stops counting until it receives a new starting address.

[0108] Signal generator 447a can generate a self-termination signal STE based on the matched signal MTS and provide the self-termination signal STE to buffer 449a. Signal generator 447a can output a self-termination signal STE that transitions to a logic high level based on the matched signal MTS transitioning to a logic high level.

[0109] Buffer 449a can receive a self-termination signal STE, which can be selectively provided to chip interface pin 110a as termination information based on an inverted internal chip enable signal InCE11b obtained by inverting the internal chip enable signal InCE11. The internal chip enable signal InCE11 can be generated based on the chip enable signal nCE. Buffer 449a can be enabled when the inverted internal chip enable signal InCE11b is at a logic high level (i.e., when the internal chip enable signal InCE11 is at a logic low level), and can transmit the self-termination signal STE to chip interface pin 110a. On the other hand, buffer 449a can be disabled when the inverted internal chip enable signal InCE11b is at a logic low level (i.e., when the internal chip enable signal InCE11 is at a logic high level). When buffer 449a is disabled, it does not transmit the self-termination signal STE to chip interface pin 110a. Therefore, by enabling or disabling buffer 449a based on whether the inverted internal chip enable signal InCE11b is at a logic high level, buffer 449a can selectively provide the self-termination signal STE to chip interface pin 110a.

[0110] The receiving circuit 460a may include a buffer 461a and a trigger FF 463a.

[0111] Buffer 461a can be connected to chip interface pin 110, receive a self-termination signal from another non-volatile memory device, and selectively provide the self-termination signal to flip-flop 463a based on an internal chip enable signal InCE11. Buffer 461a can be enabled when the internal chip enable signal InCE11 is at a logic high level, and can provide the self-termination signal from another non-volatile memory device to flip-flop 463a. Buffer 461a can be disabled when the internal chip enable signal InCE11 is at a logic low level. When buffer 461a is disabled, it does not provide the self-termination signal to flip-flop 463a. Therefore, by enabling or disabling buffer 461a based on whether the internal chip enable signal InCE11 is at a logic high level, buffer 461a can selectively provide the self-termination signal to flip-flop 463a.

[0112] The trigger 463a can generate (or activate) the internal chip enable signal InCE12 by latching and inverting the data output enable signal Dout_EN1 based on the output of the buffer 461a, and can provide the internal chip enable signal InCE12 to... Figure 4 The control circuit 480a is used in this circuit. For example, the flip-flop 463a can output an internal chip enable signal InCE12 by inverting the data output enable signal Dout_EN1 based on the rising edge transition of the output of the buffer 461a. The control circuit 480a can enable the non-volatile memory device 100a based on the transition of the internal chip enable signal InCE12.

[0113] The flip-flop 463a can generate an internal chip enable signal InCE12 with a logic low level by inverting the data output enable signal Dout_EN1 with a logic high level, based on the output of the buffer 461a being at a logic high level.

[0114] Figure 6 This illustrates an example implementation. Figure 4 A circuit diagram of the memory plane configuration in a non-volatile memory device.

[0115] Reference Figure 6The diagram illustrates a memory cell array 200a comprising multiple memory planes 210, 220, 230, and 240. Each of the multiple memory planes 210, 220, 230, and 240 may include multiple memory blocks formed on a first horizontal direction HDR1, a second horizontal direction HDR2, and a vertical direction VDR, and each memory block may include multiple cell strings. For example, a memory block of memory plane 210 may include multiple cell strings CS11, CS12, CS21, and CS22. Figure 4 For ease of explanation, the configuration of each of memory planes 210 and 220 is shown in detail, and the configuration of each of memory planes 230 and 240 may be substantially the same as that of each of memory planes 210 and 220.

[0116] Each of the memory planes (first memory plane and second memory plane) 210 and 210 may include multiple memory blocks, and one of the memory blocks may have multiple string selection lines SSL1a and SSL1b for selecting at least one of the cell strings CS11, CS12, CS21, and CS22. For example, when a selection voltage is applied to the first string selection line SSL1a, the first cell string CS11 and the second cell string CS12 can be selected. When a selection voltage is applied to the second string selection line SSL1b, the third cell string CS21 and the fourth cell string CS22 can be selected.

[0117] In some embodiments, memory planes 210 and 220 may have the same physical structure. For example, like memory plane 210, memory plane 220 may include multiple memory blocks and multiple cell strings formed within the memory blocks. Furthermore, memory plane 220 may include multiple string selection lines SSL2a and SSL2b for selecting at least one of the multiple cell strings.

[0118] Each of memory planes 210 and 220 can be associated with a corresponding word line and common-source line. The cell string in memory plane 210 can be associated with word lines WL11 to WL16, ground select line GSL1, and common-source line CSL1. The cell string in memory plane 220 can be associated with word lines WL21 to WL26, ground select line GSL2, and common-source line CSL2.

[0119] Memory planes 210 and 220 do not share bit lines. The first bit lines BL1 and BL1a are exclusively coupled to memory plane 210. The second bit lines BL2 and BL2a are exclusively coupled to memory plane 220.

[0120] although Figure 6An example is shown where each memory plane is connected to two bit lines and six word lines, but the example implementation is not limited to these features. For example, each memory plane may be connected to three or more bit lines and seven or more word lines.

[0121] Each cell string may include at least one string select transistor, memory cells, and at least one ground select transistor. For example, cell string CS31 of memory plane 220 may include a ground select transistor GST, a plurality of memory cells MC1 to MC6, and a string select transistor SST arranged in sequence perpendicular to the substrate. The remaining cell strings may be formed substantially the same as cell string CS31.

[0122] Memory planes 210 and 220 may include independent string select lines. For example, string select lines SSL1a and SSL1b are connected only to memory plane 210, and string select lines SSL2a and SSL2b are connected only to memory plane 220. String select lines can be used to select cell strings only within memory planes. Furthermore, by independently controlling the string select lines, cell strings can be selected independently in each memory plane.

[0123] For example, cell strings CS11 and CS12 can be selected independently by applying a selection voltage only to the first string select line SSL1a. When the selection voltage is applied to the first string select line SSL1a, the string select transistors of cell strings CS11 and CS12 corresponding to the first string select line SSL1a are turned on by the selection voltage. At this time, the memory cells of cell strings CS11 and CS12 can be electrically connected to the bit line. When an unselected voltage is applied to the first string select line SSL1a, the string select transistors of cell strings CS11 and CS12 corresponding to the first string select line SSL1a are turned off by the unselected voltage. At this time, the memory cells of cell strings CS11 and CS12 are electrically isolated from the bit line BL1.

[0124] Figure 7 The illustration schematically shows an embodiment according to an example implementation. Figure 4 The structure of a non-volatile memory device.

[0125] Reference Figure 7 The non-volatile memory device 100a may include a first semiconductor layer L1 and a second semiconductor layer L2, and the first semiconductor layer L1 may be stacked relative to the second semiconductor layer L2 on a vertical direction VDR. The second semiconductor layer L2 may be below the first semiconductor layer L1 on the vertical direction VDR, and therefore, the second semiconductor layer L2 may be close to the substrate.

[0126] In the example implementation, Figure 4 The memory cell array 200a can be formed (or disposed) on the first semiconductor layer L1, and Figure 4The peripheral circuitry 250a can be formed (or disposed) on the second semiconductor layer L2. Therefore, the non-volatile memory device 100a can have a structure of memory cell array 200a on the peripheral circuitry 250a (i.e., cell on peripheral (COP) structure). The COP structure can effectively reduce the area in the horizontal direction and improve the integration density of the non-volatile memory device 100a.

[0127] In an example embodiment, the second semiconductor layer L2 may include a substrate, and peripheral circuitry 250a may be formed in the second semiconductor layer L2 by forming transistors and metal patterns for wiring the transistors on the substrate. After the peripheral circuitry 250a is formed on the second semiconductor layer L2, a first semiconductor layer L1 including a memory cell array 200a may be formed, and metal patterns for connecting word lines WL and bit lines BL of the memory cell array 200a to the peripheral circuitry 250a formed in the second semiconductor layer L2 may be formed. For example, word lines WL may extend in a first horizontal direction HDR1, and bit lines BL may extend in a second horizontal direction HDR2.

[0128] As the number of memory cell stages in memory cell array 200a increases with advancements in semiconductor technology (i.e., as the number of stacked word lines WL increases), the area of ​​memory cell array 200a can be reduced, and therefore, the area of ​​peripheral circuitry 250a can also be reduced. According to one embodiment, to reduce the area occupied by page buffer circuits 410a, 410b, 410c, and 410d, each of page buffer circuits 410a, 410b, 410c, and 410d may have a structure where the page buffer cell and cache latch are separate from each other, and the sensing nodes included in each of the page buffer cells may be commonly connected to a combined sensing node. (Refer to...) Figure 11 This will be explained in detail.

[0129] Figure 8 This illustrates an example implementation. Figure 4 A block diagram of an example of a memory plane.

[0130] Reference Figure 8 The memory plane 210 may include multiple memory blocks BLK1, BLK2, ..., BLKz extending along multiple directions HDR1, HDR2, and VDR. Here, z is an integer greater than 2. In one embodiment, the memory blocks BLK1, BLK2, ..., BLKz are... Figure 4 The address decoder 300a is selected. For example, the address decoder 300a can select the memory block corresponding to the block address from memory blocks BLK1, BLK2, ..., BLKz.

[0131] Figure 9 It is shown Figure 8 A circuit diagram of one of the memory blocks.

[0132] Figure 8 The memory block BLKi can be formed on the substrate SUB in a three-dimensional (or vertical) structure. For example, multiple (memory) cell strings included in the memory block BLKi can be formed on the VDR in a vertical direction perpendicular to the substrate SUB.

[0133] Reference Figure 9 The memory block BLKi may include multiple cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 (hereinafter referred to as NS11 to NS33) coupled between bit lines BL1, BL2, and BL3 and the common-source line CSL. Each of the cell strings NS11 to NS33 may include a string select transistor SST, multiple memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7, and MC8 (hereinafter referred to as MC1 to MC8), and a ground select transistor GST. Figure 7 In the diagram, each of the cell strings NS11 to NS33 is shown as comprising eight memory cells MC1 to MC8. However, this disclosure is not limited thereto. In some example embodiments, each of the cell strings NS11 to NS33 may include any number of memory cells.

[0134] The serial select transistor SST can be connected to the corresponding serial select lines SSL1, SSL2, and SSL3 (hereinafter referred to as SSL1 to SSL3). Multiple memory cells MC1 to MC8 can be connected to their respective word lines WL1 to WL8. The ground select transistor GST can be connected to the corresponding ground select lines GSL1, GSL2, and GSL3 (hereinafter referred to as GSL1 to GSL3). The serial select transistor SST can be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common source line CSL.

[0135] Word lines with the same height (e.g., WL1) can be connected together, and ground select lines GSL1 to GSL3 and string select lines SSL1 to SSL3 can be separated.

[0136] Figure 10 Show Figure 9 An example of the structure of the cell string CS in a memory block.

[0137] Reference Figure 9 and Figure 10 The post PL is disposed on the base SUB such that the post PL extends in a direction perpendicular to the base SUB to contact the base SUB. Figure 10Each of the ground select line GSL, word lines WL1 to WL8, and string select line SSL1 shown may be formed of a conductive material (e.g., a metallic material) parallel to the substrate SUB. The post PL may be in contact with the substrate SUB through the conductive material forming the string select lines SSL, word lines WL1 to WL8, and ground select line GSL1.

[0138] The sectional view taken along line V-V' is also Figure 10 The diagram shows a cross-sectional view of a first memory cell MC1 corresponding to a first word line WL1. The pillar PL may include a cylindrical body BD. An air gap AG may be defined within the body BD.

[0139] The body BD may include P-type silicon and may be the region where the channel will be formed. The pillar PL may also include a cylindrical tunnel insulating layer TI surrounding the body BD and a cylindrical charge trapping layer CT surrounding the tunnel insulating layer TI. A barrier insulating layer BI may be disposed between the first word line WL1 and the pillar PL. The body BD, tunnel insulating layer TI, charge trapping layer CT, barrier insulating layer BI, and first word line WL1 may constitute a charge trapping transistor or be included in a charge trapping transistor, which is formed in a direction perpendicular to the substrate SUB or the upper surface of the substrate SUB. The string select transistor SST, ground select transistor GST, and other memory cells may have the same structure as the first memory cell MC1.

[0140] Figure 11 This is based on the example implementation. Figure 4 A schematic diagram of the connection between the memory plane and the page buffer circuit.

[0141] Reference Figure 11 The memory plane 210 may include a first unit string to an nth unit string NS1, NS2, NS3, ..., NSn (hereinafter referred to as NS1 to NSn). Each of the first unit string to the nth unit string NS1 to NSn may include a ground selection transistor GST connected to the ground selection line GSL, a plurality of memory cells MC connected to the first word line to the mth word line WL1, ..., WLm (hereinafter referred to as WL1 to WLm), and a string selection transistor SST connected to the string selection line SSL. The ground selection transistor GST, the plurality of memory cells MC, and the string selection transistor SST may be connected in series with each other. In this case, m may be a positive integer.

[0142] Page buffer circuit 410 may include first page buffer units to nth page buffer units PBU1, PBU2, PBU3, ..., PBUn (hereinafter referred to as PBU1 to PBUn). First page buffer unit PBU1 may be connected to first unit string NS1 via first bit line BL1, and nth page buffer unit PBUn may be connected to nth unit string NSn via nth bit line BLn. In this case, n is greater than 3. For example, n may be 8, and page buffer circuit 410 may have a structure of "eight levels of page buffer units or first page buffer units PBU1 to nth page buffer units PBUn in one row". For example, first page buffer units PBU1 to nth page buffer units PBUn may be in one row along the extension direction of first bit line BL1 to nth bit line BLn.

[0143] Page buffer circuit 410 may further include first cache latches CL1 to nth cache latches CL1, CL2, CL3, ..., CLn (hereinafter referred to as CL1 to CLn) corresponding to the first page buffer unit PBU1 to the nth page buffer unit PBUn, respectively. For example, page buffer circuit 410 may have a structure of "eight-level cache latches or first cache latches CL1 to nth cache latches CLn in one row". For example, the first cache latches CL1 to nth cache latches CLn may be in one row in the extension direction of the first bit line BL1 to the nth bit line BLn.

[0144] The sensing nodes of each of the first page buffer units PBU1 to the nth page buffer unit PBUn can be collectively connected to the combined sensing node SOC. Furthermore, the first cache latch CL1 to the nth cache latch CLn can be collectively connected to the combined sensing node SOC. Therefore, the first page buffer units PBU1 to the nth page buffer units PBUn can be connected to the first cache latch CL1 to the nth cache latch CLn via the combined sensing node SOC. The first cache latch CL1 to the nth cache latch CLn can output data DTA.

[0145] Figure 12 A page buffer according to an example implementation is shown in detail.

[0146] Reference Figure 12 The page buffer PB can correspond to Figure 4An example of a page buffer PB is provided. A page buffer PB may include a page buffer unit (PBU) and a cache unit (CU). Because the cache unit CU includes a cache latch (C-LATCH) CL, and the C-LATCH CL is connected to the global data line, the cache unit CU may be adjacent to the global data line. Therefore, the page buffer unit PBU and the cache unit CU may be separate from each other, and the page buffer PB may have a structure in which the page buffer unit PBU and the cache unit CU are separate from each other.

[0147] Page buffer unit PBU may include master unit MU. Master unit MU may include master transistors in page buffer PB. Page buffer unit PBU may also include bit line select transistor TR_hv connected to bit line BL and driven by bit line select signal BLSLT. Bit line select transistor TR_hv may include high-voltage transistor, and therefore, bit line select transistor TR_hv may be in a different well region than master unit MU (i.e., in high-voltage unit HVU).

[0148] The main unit MU may include a sense latch (S-LATCH) SL, a forced latch (F-LATCH) FL, a high-order latch (M-LATCH) ML, and a low-order latch (L-LATCH) LL. Depending on the implementation, S-LATCH SL, F-LATCH FL, M-LATCH ML, or L-LATCH LL may be referred to as a master latch or a data latch. The main unit MU may also include a precharge circuit PC capable of controlling precharge operations on the bit line BL or sense node SO based on the bit line clamping control signal BLCLAMP, and may further include a transistor PM' driven by the bit line setup signal BLSETUP.

[0149] The S-LATCH SL can store data stored in the memory cell MC or the sensing result of the threshold voltage of the memory cell MC during read or program verification operations. Furthermore, the S-LATCH SL can be used during programming operations to apply a programming bit line voltage or a programming disable voltage to the bit line BL.

[0150] The F-LATCH FL can be used to improve the threshold voltage distribution during programming operations. The F-LATCH FL can store forced data. After the forced data is initially set to "1", it can be converted to "0" when the threshold voltage of the memory cell MC enters a forced region with a lower voltage than the target region. By utilizing the forced data during programming execution operations, the bit line voltage can be controlled, and a narrower programming threshold voltage distribution can be formed.

[0151] M-LATCH ML, L-LATCH LL, and C-LATCH CL can be used to store data input externally during programming operations and can be referred to as data latches. When 3 bits of data are programmed into a memory cell MC, the 3 bits of data can be stored in M-LATCH ML, L-LATCH LL, and C-LATCH CL respectively. M-LATCH ML, L-LATCH LL, and C-LATCH CL can retain the stored data until the programming of the memory cell MC is complete. In addition, C-LATCH CL can receive data read from the memory cell MC during read operations from S-LATCH SL and output the received data to the outside via the global data line.

[0152] Furthermore, the main unit MU may also include a first transistor NM1 to a fourth transistor NM4. The first transistor NM1 may be connected between the sensing node SO and S-LATCH SL, and may be driven by the ground control signal SOGND. The second transistor NM2 may be connected between the sensing node SO and F-LATCH FL, and may be driven by the forced monitoring signal MON_F. The third transistor NM3 may be connected between the sensing node SO and M-LATCH ML, and may be driven by the high-order monitoring signal MON_M. The fourth transistor NM4 may be connected between the sensing node SO and L-LATCH LL, and may be driven by the low-order monitoring signal MON_L.

[0153] Furthermore, the main unit MU may also include a fifth transistor NM5 and a sixth transistor NM6 connected in series between the bit line selection transistor TV_hv and the sensing node SO. The fifth transistor NM5 may be driven by the bit line off signal BLSHF, and the sixth transistor NM6 may be driven by the bit line connection control signal CLBLK. Additionally, the main unit MU may also include a precharge transistor PM. The precharge transistor PM may be connected to the sensing node SO, driven by the load signal LOAD, and precharges the sensing node SO to a precharge level during the precharge period.

[0154] In one embodiment, the main unit MU may further include a pair of pass transistors connected to the sensing node SO, or a first pass transistor TR and a second pass transistor TR'. According to an embodiment, the first pass transistor TR and the second pass transistor TR' may also be referred to as a first sensing node connection transistor and a second sensing node connection transistor, respectively. The first pass transistor TR and the second pass transistor TR' may be driven in response to a pass control signal SO_PASS. According to an embodiment, the pass control signal SO_PASS may be referred to as a sensing node connection control signal. The first pass transistor TR may be connected between the first terminal SOC_U and the sensing node SO, and the second pass transistor TR' may be connected between the sensing node SO and the second terminal SOC_D.

[0155] For example, when the page buffer unit (PBU) corresponds to Figure 9 When the second page buffer unit PBU2 is in the middle, the first terminal SOC_U can be connected to one end of the through transistor included in the first page buffer unit PBU1, and the second terminal SOC_D can be connected to one end of the through transistor included in the third page buffer unit PBU3. In this way, the sensing node SO can be electrically connected to the combined sensing node SOC via the through transistor included in each of the third page buffer unit PBU3 to the nth page buffer unit PBUn.

[0156] During programming operations, the page buffer PB verifies whether programming has been completed in a selected memory cell among the memory cells included in the cell string connected to the bit line BL. The page buffer PB can store data sensed via the bit line BL during the programming verification operation in the S-LATCH SL. The M-LATCH ML and L-LATCH LL, where the target data is stored, can be set based on the sensed data stored in the S-LATCH SL.

[0157] For example, when sensed data indicates programming is complete, M-LATCH ML and L-LATCH LL can switch to a programming-disable setting for the selected memory cell in a subsequent programming cycle. C-LATCH CL can temporarily store input data provided from an external source. During programming operations, target data to be stored in C-LATCH CL can be stored in M-LATCH ML and L-LATCH LL.

[0158] Data latches and cache latches can be referred to as a latch group.

[0159] In the following text, it is assumed that the signals used to control the components in the page buffer circuit 410 are included. Figure 4 The page buffer control signal PCTL is used in the process.

[0160] Figure 13 Show Figure 1 The storage medium contains four non-volatile memory devices (non-volatile memory chips).

[0161] Reference Figure 13 Storage medium 90a may include non-volatile memory devices 100a, 100b, 100c, and 100d, and non-volatile memory devices 100a, 100b, 100c, and 100d may be accessed via, as referred to Figure 1 The described media channel CHN1 is connected to the storage controller 50.

[0162] The non-volatile memory device 100a may include a memory cell array MCA 200a, a data I / O circuit 420a, a control circuit 480a, a CEI circuit 430a, and a chip interface pin 110a. The data I / O circuit 420a can send the corresponding data DTAa1 to the memory controller 50 and receive the corresponding data DTAa1 from the memory controller 50.

[0163] The non-volatile memory device 100b may include a memory cell array 200b, a data I / O circuit 420b, a control circuit 480b, a CEI circuit 430b, and a chip interface pin 110b. The data I / O circuit 420b can send the corresponding data DTAa2 to the memory controller 50 and receive the corresponding data DTAa2 from the memory controller 50.

[0164] The non-volatile memory device 100c may include a memory cell array 200c, a data I / O circuit 420c, a control circuit 480c, a CEI circuit 430c, and a chip interface pin 110c. The data I / O circuit 420c can send the corresponding data DTAa3 to the memory controller 50 and receive the corresponding data DTAa3 from the memory controller 50.

[0165] The non-volatile memory device 100d may include a memory cell array 200d, a data I / O circuit 420d, a control circuit 480d, a CEI circuit 430d, and a chip interface pin 110d. The data I / O circuit 420d can send the corresponding data DTAa4 to the memory controller 50 and receive the corresponding data DTAa4 from the memory controller 50.

[0166] Each of the CEI circuits 430a, 430b, 430c and 430d can be connected to a corresponding one of the chip interface pins 110a, 110b, 110c and 110d, and the chip interface pins 110a, 110b, 110c and 110d are connected together.

[0167] Figure 14 Show Figure 13The CEI circuit in the two non-volatile memory devices.

[0168] exist Figure 14 In this context, it is assumed that non-volatile memory device 100a is selected and non-volatile memory device 100b is not selected. Furthermore, non-volatile memory device 100a may be referred to as a first non-volatile memory chip, and non-volatile memory device 100b may be referred to as a second non-volatile memory chip.

[0169] The non-volatile memory device 100a may include a CEI circuit 430a and a chip interface pin 110a, and the CEI circuit 430a may include a transmitting circuit 440a and a receiving circuit 460a connected to the chip interface pin 110a.

[0170] The non-volatile memory device 100b may include a CEI circuit 430b and a chip interface pin 110b, and the CEI circuit 430b may include a transmitting circuit 440b and a receiving circuit 460b connected to the chip interface pin 110b.

[0171] Reference Figure 13 and Figure 14 Because the non-volatile memory device 100a is selected, the CEI circuit 430a can operate in transmit mode. The address offset calculator 441a can calculate the first read data (from the first start address S_ADDR and the offset information OFS_INF associated with the size of the first read data) based on the first start address S_ADDR and the offset information OFS_INF associated with the size of the first read data. Figure 4 The memory cell array 200a in the memory cell array 443a is read from the final address F_ADDR, and the final address F_ADDR can be provided to the address comparator 445a. The address counter 443a can generate a normal address N_ADDR that is sequentially incremented from the first starting address S_ADDR by performing a counting operation based on the first starting address S_ADDR, and the normal address N_ADDR can be provided to the address comparator 445a.

[0172] Address comparator 445a generates a match signal MTS by comparing the final address F_ADDR and the normal address N_ADDR. Address comparator 445a outputs a match signal MTS with a logic high level based on the match between the normal address N_ADDR and the final address F_ADDR.

[0173] Signal generator 447a can generate a self-termination signal STE1 based on the matching signal MTS and provide the self-termination signal STE to buffer 449a. For example, signal generator 447a can switch from a first logic level to a second logic level based on the matching signal MTS (e.g., ...). Figure 15(As shown in the diagram) to activate the self-termination signal STE1. The signal generator 447a can output a self-termination signal STE that transitions to a logic high level based on the transition of the matched signal MTS to a logic high level. The self-termination signal STE1 can be referred to as the first self-termination signal.

[0174] Buffer 449a can be enabled when the inverting internal chip enable signal InCE11b is at a logic high level, and the self-termination signal STE1 can be transmitted to CEI circuit 430b through chip interface pins 110a and 110b.

[0175] Because the non-volatile memory device 100b is not selected, the CEI circuit 430b can operate in receive mode.

[0176] The buffer 461b can be enabled when the internal chip enable signal InCE21 is at a logic high level, and can provide the self-termination signal STE1 from the non-volatile memory device 100a to the flip-flop 463b.

[0177] The trigger 463b can generate an internal chip enable signal InCE22 by latching and inverting the data output enable signal Dout_EN2 based on the output of the buffer 461b, and can provide the internal chip enable signal InCE22 to the control circuit 480b. The control circuit 480b can self-enable the non-volatile memory device 100b based on the transition of the internal chip enable signal InCE22.

[0178] The flip-flop 463b can generate an internal chip enable signal InCE22 with a logic low level by inverting the data output enable signal Dout_EN2 with a logic high level, based on the output of the buffer 461b being at a logic high level.

[0179] The CEI circuit 430b in the self-enabled non-volatile memory device 100b can operate in transmit mode. The non-volatile memory device 100b can perform a second DMA operation to output second read data from the memory cell array 200b to the memory controller 50 via the data I / O circuit 420b. The transmit circuit 440b can generate a self-termination signal STE2 indicating the completion of the second DMA operation, and can transmit the self-termination signal STE2 to one of the other non-volatile memory devices via the chip interface pin 110b.

[0180] Figure 15 This illustrates an example implementation. Figure 14 Timing diagram of the operation of non-volatile memory devices in the diagram.

[0181] Reference Figures 13 to 15When the first non-volatile memory device 100a executes the first DMA operation DMA (LUN0) to output the first read data from the memory cell array 200a to the memory controller 50 through the I / O line IOx, the first non-volatile memory device 100a receives the second data output command LUN1Dout CMD from the memory controller 50 through the command / address lines CA[1:0].

[0182] The first read data may have a start address S_ADDR "a" and a final address F_ADDR "a+4K". The address offset calculator 441a calculates the final address F_ADDR "a+4K" by adding the address offset "4K" to the start address S_ADDR "a", and the address counter 443a generates a normal address N_ADDR that increments sequentially from the start address S_ADDR "a" by performing a counting operation based on the start address S_ADDR "a". The address counter 443a can generate the normal address N_ADDR by performing a counting operation based on the read enable signal nRE or the data strobe signal DQS. The address comparator 445a outputs a match signal MTS with a logic high level based on the match between the normal address N_ADDR and the final address F_ADDR, and the signal generator 447a outputs a self-termination signal STE1 that transitions to a logic high level based on the match signal MTS transitioning to a logic high level.

[0183] Control circuit 480a can transition the internal chip enable signal InCE1 to a logic high level based on the transition of the self-termination signal STE1. Therefore, CEI circuit 430a can operate in transmit (Tx) mode before the internal chip enable signal InCE1 transitions to a logic high level and in receive (Rx) mode after the internal chip enable signal InCE1 transitions to a logic high level.

[0184] In response to receiving the second data output command LUN1 Dout CMD, the second non-volatile memory device 100b changes the data output enable signal Dout_EN2 to a logic high level. The CEI circuit 430b in the second non-volatile memory device 100b operates in receive mode, and the receiving circuit 460b of the CEI circuit 430b receives the self-termination signal STE1 through the chip interface pin 110b.

[0185] Buffer 461b provides the self-termination signal STE1 from the non-volatile memory device 100a to flip-flop 463b. Flip-flop 463b generates an internal chip enable signal InCE22 by latching and inverting the data output enable signal Dout_EN2 based on the output of buffer 461b, and provides the internal chip enable signal InCE22 to control circuit 480b. Control circuit 480b can self-enable the non-volatile memory device 100b based on the transition of the internal chip enable signal InCE22.

[0186] The first non-volatile memory device 100b performs a second DMA operation (LUN1) to output second read data from the memory cell array 200b to the memory controller 50 via I / O line IOx. The transmitting circuit 440b can generate a self-termination signal STE2 indicating the completion of the second DMA operation, and can transmit the self-termination signal STE2 to one of the other non-volatile memory devices via chip interface pin 110b.

[0187] Therefore, in the storage device according to the example embodiment, a first non-volatile memory device (e.g., a first non-volatile memory chip) can perform a first DMA operation based on a first data output command to output first read data to the storage controller 50, can internally (e.g., self-centeredly) generate a self-termination signal indicating the completion of the first DMA operation based on an address, and can send the self-termination signal to a second non-volatile memory device (e.g., a second non-volatile memory chip). The second non-volatile memory device can self-enable based on the self-termination signal provided from the first non-volatile memory device, and (e.g., then) can perform a second DMA operation (as associated with a second data output command) to output second read data to the storage controller 50 without a select chip enable command from the storage controller 50. Therefore, non-volatile memory devices 100a, 100b, 100c, and 100d can continuously perform DMA operations without select chip enable and select chip terminate commands from the storage controller 50, and thus reduce I / O overhead.

[0188] Figure 16 Show Figure 13 The non-volatile memory devices in the memory continuously perform DMA operations.

[0189] Reference Figures 13 to 16 The first non-volatile memory device 100a performs a first DMA operation DMA11 (LUN0) based on the first data output command DoutCMD11 to output the first read data to the memory controller 50, and the CEI circuit 430a of the first non-volatile memory device 100a can change the first self-termination signal STE1 to a logic high level.

[0190] When the first non-volatile memory device 100a executes the first DMA operation DMA11 (LUN0), the second non-volatile memory device 100b can receive the second data output command Dout CMD12, can be self-enabled based on the first self-termination signal STE1 received through the chip interface pin 110b, and can execute the second DMA operation DMA12 (LUN1) based on the second data output command Dout CMD12 to output the second read data to the memory controller 50. The CEI circuit 430b of the second non-volatile memory device 100b can change the second self-termination signal STE2 to a logic high level.

[0191] When the second non-volatile memory device 100b executes the second DMA operation DMA12 (LUN1), the third non-volatile memory device 100c can receive a third data output command Dout CMD13, can be self-enabled based on the second self-termination signal STE2 received through the chip interface pin 110c, and can execute a third DMA operation DMA13 (LUN2) based on the third data output command Dout CMD13 to output the third read data to the memory controller 50. The CEI circuit 430c of the third non-volatile memory device 100c can change the third self-termination signal STE3 to a logic high level.

[0192] When the third non-volatile memory device 100c executes the third DMA operation DMA13 (LUN2), the fourth non-volatile memory device 100d can receive the fourth data output command Dout CMD14, can be self-enabled based on the third self-termination signal STE3 received through the chip interface pin 110d, and can execute the fourth DMA operation DMA14 (LUN3) based on the fourth data output command Dout CMD14 to output the fourth read data to the memory controller 50. The CEI circuit 430d of the fourth non-volatile memory device 100d can change the fourth self-termination signal STE4 to a logic high level.

[0193] In the example implementation, the first read data, second read data, third read data, and fourth read data output from non-volatile memory devices 100a, 100b, 100c, and 100d, respectively, may have different logical unit numbers (LUNs). A LUN may be the smallest unit capable of independently executing a command.

[0194] Figure 17 Showing an example implementation Figure 4 Example operation of a non-volatile memory device.

[0195] Reference Figure 4 and Figure 17When the data stored in the first memory plane to the fourth memory plane 210, 220, 230 and 240 have the same LUN (i.e., the data stored in the first memory plane to the fourth memory plane 210, 220, 230 and 240 have LUN0), the CEI circuit 430a can repeatedly self-terminate and self-enable, and the first read data, second read data, third read data and fourth read data read from the first memory plane to the fourth memory plane 210, 220, 230 and 240 respectively can be continuously output to the memory controller 50.

[0196] Refer to together Figure 5 The non-volatile memory device 100a executes a first DMA operation DMA21 (LUN0 PLN1) based on a first data output command Dout CMD21 to output first read data from the first memory plane 210 to the memory controller 50. The CEI circuit 430a can internally generate a self-termination signal indicating the completion of the first DMA operation DMA21 (LUN0 PLN1) based on the start address associated with the first read data, and can generate a self-enable signal based on the self-termination signal.

[0197] When the first DMA operation DMA21 (LUN0 PLN1) is being executed, the control circuit 480a may receive the second data output command Dout CMD22. The non-volatile memory device 100a executes the second DMA operation DMA22 (LUN0 PLN2) based on the self-enable signal and the second data output command Dout CMD22 to output the second read data from the second memory plane 220 to the memory controller 50. The CEI circuit 430a may internally generate a self-termination signal indicating the completion of the second DMA operation DMA22 (LUN0 PLN2) based on the start address associated with the second read data, and may generate a self-enable signal based on the self-termination signal.

[0198] When the second DMA operation DMA22 (LUN0 PLN2) is being executed, the control circuit 480a can receive the third data output command Dout CMD23. The non-volatile memory device 100a executes the third DMA operation DMA23 (LUN0 PLN3) based on the self-enable signal and the third data output command Dout CMD23 to output the third read data from the third memory plane 230 to the memory controller 50. The CEI circuit 430a can internally generate a self-termination signal indicating the completion of the third DMA operation DMA23 (LUN0 PLN3) based on the start address associated with the third read data, and can generate a self-enable signal based on the self-termination signal.

[0199] When the third DMA operation DMA23 (LUN0 PLN3) is being executed, the control circuit 480a can receive the fourth data output command Dout CMD24, and the non-volatile memory device 100a executes the fourth DMA operation DMA24 (LUN0 PLN4) based on the self-enable signal and the fourth data output command Dout CMD24 to output the fourth read data from the fourth memory plane 240 to the memory controller 50.

[0200] Figure 18 This illustrates an example implementation. Figure 4 A block diagram of an example of a control circuit in a non-volatile memory device.

[0201] Reference Figure 18 The control circuit 480a may include a command decoder 485a, an address buffer 487a, a control signal generator 490a, and a status signal generator 495a.

[0202] The command decoder 485a can decode the command CMD and provide the decoded command D_CMD to the control signal generator 490a and the status signal generator 495a.

[0203] Address buffer 487a can receive address signal ADDR, provide row address R_ADDR to address decoder 300a and column address C_ADDR to data I / O circuit 420a.

[0204] The control signal generator 490a can receive the decoding command D_CMD and can generate control signal CTL and page buffer control signal PCTL based on the operation pointed to by the decoding command D_CMD. The control signal CTL can be provided to the voltage generator 500a, and the page buffer control signal PCTL can be provided to the page buffer circuits 410a, 410b, 410c and 410d.

[0205] The status signal generator 495a can receive the decoding command D_CMD, monitor the operation pointed to by the decoding command D_CMD, and change the status signal nR / B to one of the ready state and busy state based on whether the operation pointed to by the decoding command D_CMD has been completed.

[0206] Figure 19 This illustrates an example implementation. Figure 4 A block diagram of an example voltage generator in a non-volatile memory device.

[0207] Reference Figure 19 The voltage generator 500a may include a high-voltage HV generator 510 and a low-voltage LV generator 530. The voltage generator 500a may also include a negative-voltage NV generator 550.

[0208] The high voltage generator 510 can be referred to as the first voltage generator, the low voltage generator 530 can be referred to as the second voltage generator, and the negative voltage generator 550 can be referred to as the third voltage generator.

[0209] The high voltage generator 510 can respond to the first control signal CTL1 to generate the programming voltage PGM, the pass voltage VPASS, the high voltage VPPH, and the erase voltage VERS according to the operation indicated by the command CMD.

[0210] The programming voltage PGM is applied to the selected word line, the voltage VPASS can be applied to the unselected word line, and the erase voltage VERS can be applied to the channels of the cell string included in the selected memory block. The high voltage VPPH can be applied to each gate of the transistor coupled to the word line, string select line, and ground select line. The first control signal CTL1 may include multiple bits indicating the operation pointed to by the decode command D_CMD.

[0211] The low voltage generator 530 can respond to the second control signal CTL2 to generate a programming verification voltage VPV and a read voltage VRD according to the operation pointed to by the command CMD. The second control signal CTL2 may include multiple bits indicating the operation pointed to by the decoding command D_CMD.

[0212] The negative voltage generator 550 can generate a negative voltage VNEG with a negative level in response to a third control signal CTL3, according to the operation pointed to by the command CMD. The third control signal CTL3 may include multiple bits indicating the operation pointed to by the decoding command D_CMD. The negative voltage VNEG can be applied to the selected word line and the unselected word line during the programming recovery period, and can be applied to the unselected word line during the bit line setting period.

[0213] Figure 20 This illustrates an example implementation. Figure 3 A block diagram illustrating an example of an address decoder in a non-volatile memory device.

[0214] Reference Figure 20 The address decoder 300a may include a driver circuit 310 and switching circuits (or transistor circuits) 360a and 360b.

[0215] Driver circuit 310 can transmit voltage supplied from voltage generator 500a to memory cell array 200a in response to a block address. Driver circuit 310 may include block select driver BWLWL DRIVER 320, serial select driver SSDRIVER 330, drive line driver SI DRIVER 340, and ground select driver GS DRIVER 350.

[0216] The block select driver 320 can supply a high voltage VPPH from the voltage generator 500 to the pass transistor circuits 360a and 360b in response to a block address. The block select driver 320 can supply the high voltage VPPH to the block word line BLKWL1, which is connected to the gates of multiple pass transistors GPT1, PT11 to PT1m and SSPT1 in the pass transistor circuit 360a, and can supply the high voltage VPPH to the block word line BLKWL2, which is connected to the gates of multiple pass transistors GPT2, PT21 to PT2m and SSPT2 in the pass transistor circuit 360b. The block select driver 320 can control the application of various voltages (such as pass voltage, programming voltage, and read voltage) to the memory cell array 200a.

[0217] Transistors GPT1, PT11 to PT1m and SSPT1 are connected to memory plane 210 via ground select line GSL1, multiple word lines WL11 to WL1m and serial select line SSL1, and transistors GPT2, PT21 to PT2m and SSPT2 are connected to memory plane 220 via ground select line GSL2, multiple word lines WL21 to WL2m and serial select line SSL2.

[0218] The string select driver 330 can supply voltage (e.g., via voltage VPASS) from voltage generator 500a to string select lines SSL1 and SSL2 as string select signals SS1 and SS2 via transistors SSPT1 and SSPT2. During programming operation, the string select driver 330 can supply select signals SS1 and SS2 to turn on all string select transistors in the selected memory block.

[0219] The drive line driver 340 can supply the programming voltage VPGM, pass voltage VPASS, verification voltage VPV, read voltage VRD, and negative voltage VNEG from the voltage generator 500a to the word lines WL11 to WL1m via drive lines S11 to S1m and via transistors PT11 to PT1m, and can supply the programming voltage VPGM, pass voltage VPASS, verification voltage VPV, read voltage VRD, and negative voltage VNEG to the word lines WL21 to WL2m via drive lines S21 to S2m and via transistors PT21 to PT2m.

[0220] The ground selection driver 350 can supply voltage (e.g., via voltage VPASS) from voltage generator 500a to ground selection lines GSL1 and GSL2 as ground selection signals GS1 and GS2 via transistors GPT1 and GPT2.

[0221] Transistors GPT1, PT11 to PT1m, and SSPT1 are configured such that ground select line GSL1, word lines WL11 to WL1m, and serial select line SSL1 are electrically connected to their respective drive lines in response to activation of a high voltage VPPH on block word line BLKWL2. In an example embodiment, each of transistors GPT1, PT11 to PT1m, and SSPT1 may include a high-voltage transistor capable of withstanding high voltages. Transistors GPT2, PT21 to PT2m, and SSPT2 are configured such that ground select line GSL2, word lines WL21 to WL2m, and serial select line SSL2 are electrically connected to their respective drive lines in response to activation of a high voltage VPPH on block word line BLKWL2. In an example embodiment, each of transistors GPT2, PT21 to PT2m, and SSPT2 may include a high-voltage transistor capable of withstanding high voltages.

[0222] Figure 21 This is a flowchart illustrating an example operation of a non-volatile memory device, and Figure 22 This is a ladder diagram illustrating an example operation of a non-volatile memory device according to an example implementation.

[0223] Reference Figure 1 and Figures 4 to 22 The first non-volatile memory device (NVM) 100a may receive the start address S_ADDR associated with the first read data from the memory controller 50 (operation S110).

[0224] The CEI circuit 430a of the first non-volatile memory device 100a can calculate the final address F_ADDR of the first read data based on the start address S_ADDR and the address offset indicating the size of the first read data (operation S120).

[0225] When the first non-volatile memory device 100a performs a first read operation based on a first data output command to output the first read data to the memory controller 50, the second non-volatile memory device 100b receives a second data output command from the memory controller 50 (operation S130).

[0226] The CEI circuit 430a of the first non-volatile memory device 100a generates a sequentially increasing normal address N_ADDR by performing a counting operation based on the start address S_ADDR, and enables self-termination (operation S140) based on the normal address N_ADDR matching the final address F_ADDR.

[0227] The CEI circuit 430a of the first non-volatile memory device 100a can send self-termination information to the CEI circuit 430b of the second non-volatile memory device 100b via chip interface pins 110a and 110b (operation S150).

[0228] The second non-volatile memory device 100b may be self-enabled based on self-termination information provided from the first non-volatile memory device 100a (operation S160), and the second non-volatile memory device 100b may perform a second DMA operation based on a second data output command to output the second read data to the memory controller 50 (operation S170).

[0229] Figure 22 Operations S130a and S130b in the middle can be combined with Figure 21 The operation S130 in the middle corresponds to this.

[0230] Therefore, in the storage device according to the example embodiment, a first non-volatile memory device (e.g., a first non-volatile memory chip) can perform a first DMA operation based on a first data output command to output first read data to the storage controller 50, can internally (e.g., self-centrically) generate a self-termination signal indicating the completion of the first DMA operation based on an address, and can transmit the self-termination signal to a second non-volatile memory device (e.g., a second non-volatile memory chip). The second non-volatile memory device can self-enable based on the self-termination signal provided from the first non-volatile memory device, and can perform a second DMA operation (as associated with a second data output command) to output second read data to the storage controller 50 without a select chip enable command from the storage controller 50. Therefore, non-volatile memory devices 110a, 110b, 100c, and 110d can continuously perform DMA operations without select chip enable and select chip terminate commands from the storage controller 50, and thus reduce I / O overhead.

[0231] Figure 23 This is a block diagram illustrating an electronic system including a semiconductor device according to some example embodiments.

[0232] Reference Figure 23 Electronic system 3000 may include semiconductor device 3100 and controller 3200 electrically connected to semiconductor device 3100. Electronic system 3000 may be a storage device including one or more semiconductor devices 3100 or an electronic device including a storage device. For example, electronic system 3000 may be a solid-state drive (SSD) device, universal serial bus (USB), computing system, medical device, or communication device that may include one or more semiconductor devices 3100.

[0233] Semiconductor device 3100 may be or may include a non-volatile memory device (e.g., see reference 3100). Figures 4 to 20 (The non-volatile memory device shown). Semiconductor device 3100 may include a first structure 3100F and a second structure 3100S on the first structure 3100F. The first structure 3100F may be a peripheral circuit structure including a decoder circuit 3110, a page buffer circuit (PBC) 3120, and a logic circuit 3130. The second structure 3100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0234] In the second structure 3100S, each of the memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary according to the example implementation.

[0235] In some example implementations, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Lower gate lines LL1 and LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. Word lines WL may be the gate electrodes of memory cell transistors MCT, respectively, and upper gate lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0236] In some example implementations, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 that can be connected in series with each other. The upper transistors UT1 and UT2 may include a series select transistor UT1 and an upper erase control transistor UT2. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation for erasing data stored in the memory cell transistor MCT via the gate-induced drain leakage (GIDL) phenomenon.

[0237] The common-source line CSL, the first lower gate line LL1 and the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 3110 via a first connection wiring 3115 extending from the first structure 3100F to the second structure 3110S. The bit line BL can be electrically connected to the page buffer circuit 3120 via a second connection wiring 3125 extending from the first structure 3100F to the second structure 3100S.

[0238] In the first structure 3100F, the decoder circuit 3110 and the page buffer circuit 3120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 3110 and the page buffer circuit 3120 can be controlled by logic circuit 3130. The semiconductor device 3100 can communicate with the controller 3200 via an input / output pad 3101 electrically connected to the logic circuit 3130. The input / output pad 3101 can be electrically connected to the logic circuit 3130 via an input / output connection wiring 3135 extending from the first structure 3100F to the second structure 3100S.

[0239] The controller 3200 may include a processor 3210, a NAND controller 3220, and a host interface (I / F) 3230. The electronic system 3000 may include a plurality of semiconductor devices 3100, and in this case, the controller 3200 may control the plurality of semiconductor devices 3100.

[0240] Processor 3210 controls the operation of electronic system 3000, including controller 3200. Processor 3210 is firmware-operable and controls NAND controller 3220 to access semiconductor device 3100. NAND controller 3220 may include NAND interface (I / F) 3221 for communicating with semiconductor device 3100. Through NAND interface 3221, control commands for controlling semiconductor device 3100, data to be written to memory cell transistors (MCTs) of semiconductor device 3100, and data to be read from memory cell transistors (MCTs) of semiconductor device 3100 can be transmitted. Host interface 3230 provides communication between electronic system 3000 and external host. When a control command is received from external host through host interface 3230, processor 3210 can control semiconductor device 3100 in response to the control command.

[0241] The non-volatile memory device or storage device according to the example implementation can be packaged using various package types or package configurations.

[0242] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting them. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications may be made to the exemplary embodiments without substantially departing from the novel teachings and advantages of this disclosure. Therefore, all such modifications are intended to be included within the scope of this disclosure as defined in the claims.

Claims

1. A storage device, comprising: Multiple non-volatile memory chips, including a first non-volatile memory chip and a second non-volatile memory chip; as well as A storage controller is configured to control the plurality of non-volatile memory chips. The first non-volatile memory chip includes: First memory cell array; The first chip enables the interface circuit; The first chip interface pin is connected to the first chip enable interface circuit; and The first control circuit is configured to control the operation of the first non-volatile memory chip. The first non-volatile memory chip is configured to: perform a first direct memory access operation based on a first data output command from the memory controller to send first read data from the first memory cell array to the memory controller. The first chip enable interface circuit is configured to generate a first self-termination signal indicating the completion of a first direct memory access operation based on a first start address associated with the first read data, and to provide the first self-termination signal to the second non-volatile memory chip via a first chip interface pin. The second non-volatile memory chip includes: a second chip interface pin configured to receive a first self-termination signal; and a second chip enable interface circuit connected to the second chip interface pin. The second non-volatile memory chip is configured to self-enable based on a first self-termination signal from the first non-volatile memory chip.

2. The storage device as claimed in claim 1, wherein, The first control circuit is configured as follows: Receive the first chip enable signal from the storage controller; The internal chip's enable signal is activated based on the first chip's enable signal; and The internal chip enable signal is provided to the first chip enable interface circuit. The first chip enable interface circuit is configured to operate in the transmission mode and activate the first self-termination signal based on the activation of the internal chip enable signal.

3. The storage device as claimed in claim 2, in, The first control circuit is configured to activate the internal chip enable signal based on the activation of the first self-termination signal, and The first chip enable interface circuit is configured to operate in receive mode based on the internal chip enable signal being deactivated.

4. The storage device as claimed in claim 1, wherein, The first chip enable interface circuit includes a transmitting circuit and a receiving circuit connected to the interface pins of the first chip. The transmitting circuit is configured to operate based on the internal chip enable signal being at a logic low level, and The receiving circuit is configured to operate based on the internal chip enable signal being at a logic high level.

5. The storage device as claimed in claim 4, wherein, The transmitting circuit includes: The address offset calculator is configured to calculate the final address of the first read data based on a first start address and offset information associated with the size of the first read data; The address counter is configured to generate normal addresses that increment sequentially from the first starting address by performing a counting operation based on the first starting address; The address comparator is configured to generate a match signal by comparing the final address with the normal address; The signal generator is configured to generate a first self-terminating signal based on the matched signal; and The buffer is configured to selectively provide a first self-termination signal to a first chip interface pin based on an inverted internal chip enable signal obtained by inverting an internal chip enable signal, the internal chip enable signal being based on the first chip enable signal.

6. The storage device as claimed in claim 5, wherein, The address comparator is configured to activate the matching signal based on a match between the normal address and the final address. The signal generator is configured to activate the first self-terminating signal based on the activation of the matched signal; and The buffer is configured to provide a first self-termination signal to the first chip interface pin based on the inverted internal chip enable signal having a logic high level.

7. The storage device as claimed in claim 5, wherein, The first control circuit is configured as follows: The internal chip enable signal is activated based on the first chip enable signal, and the internal chip enable signal is then provided to the first chip enable interface circuit; and The internal chip enable signal is activated based on the activation of the first self-termination signal.

8. The storage device as claimed in claim 1, wherein, The second non-volatile memory chip includes a second memory cell array and a second control circuit, the second control circuit being configured to control the operation of the second non-volatile memory chip. The second non-volatile memory chip is configured to: receive a second data output command from the memory controller based on a first direct memory access operation performed by the first non-volatile memory chip, and activate a data output enable signal based on the second data output command. The second non-volatile memory chip is configured to: self-activate based on a first self-termination signal from the first non-volatile memory chip and a data output enable signal; and perform a second direct memory access operation to send second read data from the second memory cell array to the memory controller.

9. The storage device as claimed in claim 8, wherein, The second chip's enable interface circuit is configured as follows: The second internal chip enable signal is activated based on the activation of the first self-termination signal; and The second internal chip enable signal is provided to the second control circuit, and The second control circuit is configured to activate the second non-volatile memory chip upon activation of the second internal chip enable signal.

10. The storage device of claim 9, wherein, The second chip enable interface circuit includes a transmitting circuit and a receiving circuit connected to the second chip interface pins. The receiving circuit is configured to operate based on the first internal chip enable signal being at a logic high level, and The transmitting circuit is configured to operate based on the first internal chip enable signal being at a logic low level.

11. The storage device of claim 10, wherein, The receiving circuit includes: A buffer, connected to a second chip interface pin, is configured to receive a first self-termination signal; and The trigger is configured to output a second internal chip enable signal by latching a data output enable signal based on the output of the buffer.

12. The storage device of claim 11, wherein, The buffer is configured to provide a first self-termination signal to the trigger based on the activation of a first internal chip enable signal.

13. The storage device of claim 11, wherein, The trigger is configured to output a second internal chip enable signal by inverting the data output enable signal through a rising edge transition based on the output of the buffer.

14. The storage device as claimed in claim 8, in, The second non-volatile memory chip is configured to perform a second direct memory access operation after the second non-volatile memory chip is enabled. The second chip's enable interface circuit is configured as follows: Based on the second start address associated with the second read data, a second self-termination signal indicating the completion of the second direct memory access operation is generated; and The second self-termination signal is provided to the non-volatile memory chip in the first group of non-volatile memory chips in the plurality of non-volatile memory chips through the second chip interface pin, wherein the first group of non-volatile memory chips excludes the second non-volatile memory chip.

15. The storage device of claim 14, wherein, The non-volatile memory chips in the first group are configured to self-enable based on a second self-termination signal.

16. The storage device of claim 14, wherein, The first and second read data have different logical unit numbers.

17. A non-volatile memory device, comprising: A memory cell array, comprising multiple memory planes, wherein the multiple memory planes include a first memory plane and a second memory plane; Multiple page buffer circuits, corresponding to the multiple memory planes, each of the multiple page buffer circuits being connected to a corresponding one of the multiple memory planes via a corresponding bit line; The data input / output circuit is connected to the multiple page buffer circuits via corresponding data lines; Chip enable interface circuit; The chip interface pins are connected to the chip's enable interface circuit. as well as The control circuit is configured to control the operation of the non-volatile memory device. The control circuit is configured to: base its data output on a first data output command from the storage controller. Perform a first direct memory access operation to output first read data from the first memory plane to the memory controller via data input / output circuitry; and Based on the fact that a first direct memory access operation is being executed, a second data output command is received from the memory controller. The chip enable interface circuit is configured to: generate a self-termination signal indicating the completion of a first direct memory access operation based on a first start address associated with the first read data, and generate a self-enable signal based on the self-termination signal. The control circuit is configured to perform a second direct memory access operation in response to a second data output command and a self-enable signal, so as to output the second read data from the second memory plane to the memory controller through the data input / output circuit.

18. The non-volatile memory device of claim 17, wherein, The chip enable interface circuit includes transmitting and receiving circuits connected to the chip interface pins. The transmitting circuit is configured to generate a self-termination signal indicating the completion of a first direct memory access operation based on a first start address, and transmit the self-termination signal to the receiving circuit via a chip interface pin. The receiving circuit is configured to generate a self-enabled signal based on a self-termination signal and provide the self-enabled signal to the control circuit.

19. The non-volatile memory device of claim 17, wherein, The first and second read data have the same logical unit number.

20. A storage device, comprising: Multiple non-volatile memory chips, including at least a first non-volatile memory chip and a second non-volatile memory chip; A storage controller is configured to control the plurality of non-volatile memory chips. The first non-volatile memory chip includes a first memory cell array, a first chip enable interface circuit, a first chip interface pin connected to the first chip enable interface circuit, and a first control circuit configured to control the operation of the first non-volatile memory chip. The first non-volatile memory chip is configured to: perform a first direct memory access operation based on a first data output command from the memory controller to send first read data from the first memory cell array to the memory controller. The first chip enable interface circuit is configured to generate a first self-termination signal indicating the completion of a first direct memory access operation based on a first start address associated with the first read data, and to provide the first self-termination signal to the second non-volatile memory chip via a first chip interface pin. The second non-volatile memory chip includes a second memory cell array and a second chip interface pin configured to receive a first self-termination signal. The second non-volatile memory chip is configured as follows: Self-enabled based on a first self-termination signal from the first non-volatile memory chip; and A second direct memory access operation is executed based on a second data output command to send second read data from the second memory cell array to the memory controller, wherein the second non-volatile memory chip is configured to receive the second data output command from the memory controller during the execution of the first direct memory access operation by the first non-volatile memory chip.

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