Capacitor, semiconductor device including the capacitor, and method of manufacturing the semiconductor device

Abstract

A capacitor, a semiconductor device including the capacitor, and a method of manufacturing the semiconductor device are provided. The capacitor includes a first electrode, a second electrode opposite the first electrode, and a dielectric layer disposed between the first electrode and the second electrode and including a rutile crystalline phase. The first electrode includes a metal nitride, and the metal nitride includes a group VB element, or a group VB element and a group IVB element.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2024-0138623 filed with the Korean Intellectual Property Office on October 11, 2024, and Korean Patent Application No. 10-2025-0092582 filed with the Korean Intellectual Property Office on July 9, 2025, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to capacitors, semiconductor devices including said capacitors, and methods of manufacturing said semiconductor devices. Background Technology

[0004] Each memory cell, which can be a basic unit of Dynamic Random Access Memory (DRAM), may include a transistor that controls charge transfer and a capacitor that stores charge. To meet the demand for higher integration, the size of DRAM memory cells has been continuously reduced, and as a result of this miniaturization, the charge storage capacity of DRAM capacitors can be reduced. Therefore, methods and materials for increasing the dielectric constant of the capacitor's dielectric layer are being explored to improve the capacitor's charge storage capacity while compensating for this size reduction. Summary of the Invention

[0005] Provided a capacitor, a semiconductor device including said capacitor, and a method of manufacturing said semiconductor device.

[0006] Other aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments presented in this disclosure.

[0007] According to one aspect of this disclosure, the capacitor includes: a first electrode comprising a metal nitride, the metal nitride comprising a nitride of a group VB element (also known as a group 5B element) or a nitride of the group VB element and a group IVB element (also known as a group 4B element); a second electrode opposite to the first electrode; and a dielectric layer between the first electrode and the second electrode, the dielectric layer comprising a rutile phase.

[0008] The dielectric layer can be in direct contact with the first electrode.

[0009] The dielectric layer may include TiO2.

[0010] The dielectric layer may include the rutile crystal phase as the main phase (primary phase).

[0011] The dielectric layer may have a thickness of 100 Å or less.

[0012] The Group VB element may include at least one of V, Nb, Ta, or Db.

[0013] The Group IVB element may include at least one of Ti, Zr, Hf, or Rf.

[0014] The metal nitride may be represented by MN or M x M' 1-x N, where 0 < x < 1, M refers to the Group VB element, M' refers to the Group IVB element, and N refers to nitrogen.

[0015] According to another aspect of the present disclosure, a semiconductor device includes a capacitor, the capacitor including: a first electrode including a metal nitride including a nitride of a Group VB element or a nitride of a Group VB element and a Group IVB element; a second electrode opposite to the first electrode; and a dielectric layer between the first electrode and the second electrode, the dielectric layer including a rutile crystal phase.

[0016] The dielectric layer may be in direct contact with the first electrode.

[0017] The dielectric layer may include TiO2.

[0018] The dielectric layer may include the rutile crystal phase as a main phase.

[0019] The dielectric layer may have a thickness of 100 Å or less.

[0020] The Group VB element may include at least one of V, Nb, Ta, or Db.

[0021] The Group IVB element may include at least one of Ti, Zr, Hf, or Rf.

[0022] The metal nitride may be represented by MN or M x M' 1-x N, where 0 < x < 1, M refers to the Group VB element, M' refers to the Group IVB element, and N refers to nitrogen.

[0023] The first electrode may include an oxide interface region that may contact the dielectric layer and contain a metal oxide of the Group VB element.

[0024] The oxide interface region may have a thickness of 12 Å or less.

[0025] The metal oxide of the Group VB element may be represented by M n O 2n-1 or MO 2n-1 where n is a natural number, M refers to the Group VB element, and O refers to oxygen.

[0026] According to another aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device including a capacitor, the method including manufacturing the capacitor by: forming a first electrode including a metal nitride, the metal nitride including a Group VB element, or the Group VB element and a Group IVB element; forming a dielectric layer on the first electrode such that the dielectric layer includes a rutile crystal phase; and forming a second electrode on the dielectric layer.

[0027] The Group VB element may include at least one of V, Nb, Ta, or Db.

[0028] The Group IVB element may include at least one of Ti, Zr, Hf, or Rf.

[0029] The metal nitride may be represented by MN or M x M' 1-x N, where 0 < x < 1, M refers to the Group VB element, M' refers to the Group IVB element, and N refers to nitrogen.

[0030] The dielectric layer may include TiO2.

[0031] The formation of the dielectric layer may include directly depositing TiO2 on the first electrode by an atomic layer deposition (ALD) process.

[0032] The dielectric layer may include the rutile crystal phase as a main phase.

[0033] The formation of the dielectric layer may include forming the dielectric layer such that the dielectric layer has a thickness of 100 Å or less.

[0034] Forming a dielectric layer on the first electrode may include: forming an oxide interface region at a surface of the first electrode, and then forming the dielectric layer on the oxide interface region. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The above and other aspects, features, and advantages of some embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0036] Figure 1 is a cross-sectional view schematically showing a capacitor according to at least one example embodiment;

[0037] Figures 2A to 2C is a diagram showing a method of manufacturing the capacitor of the at least one example embodiment shown in Figure 1 ;

[0038] Figure 3This is a transmission electron microscope (TEM) image showing a rutile TiO2 layer deposited on a VN electrode according to at least one exemplary embodiment;

[0039] Figure 4 The figure shows the following simulation results: the simulation results show the changes in interfacial energy based on the heat treatment of oxynitrides and oxides of group VB elements (M);

[0040] Figure 5 This diagram shows the crystal phases observed when TiO2 dielectric layers are grown on layers of oxides of group VB elements (M) using atomic layer deposition (ALD) technology.

[0041] Figure 6 This is a graph showing the results of measuring the leakage current density (J) and equivalent oxide thickness (Toxeq.) of a comparative capacitor and a capacitor of at least one example embodiment;

[0042] Figure 7 It is a circuit diagram schematically illustrating the circuit configuration and operation of a semiconductor device employing a capacitor according to at least one exemplary embodiment;

[0043] Figure 8 It is a schematic diagram illustrating a semiconductor device according to at least one exemplary embodiment;

[0044] Figure 9 It is a schematic diagram illustrating a semiconductor device according to at least one exemplary embodiment;

[0045] Figure 10 It is a plan view illustrating a semiconductor device according to at least one exemplary embodiment;

[0046] Figure 11 It is along Figure 10 A cross-sectional view taken by line A-A';

[0047] Figure 12 This is a cross-sectional view showing a semiconductor device according to at least one exemplary embodiment; and

[0048] Figure 13 and 14 This is a conceptual diagram illustrating a device architecture that can be applied to an electronic device according to an implementation. Detailed Implementation

[0049] The embodiments will now be described in detail, examples of which are shown in the accompanying drawings. In this regard, the embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below only with reference to the accompanying drawings to illustrate aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of" modify the entire list of elements when preceding or following it, without modifying any individual element of the list.

[0050] In the following description, embodiments will be illustrated with reference to the accompanying drawings. In the drawings, the same reference numerals refer to the same elements, and the dimensions of the elements may be enlarged for clarity of illustration. The embodiments described herein are for illustrative purposes only and various modifications may be made therein. Furthermore, when the terms “about” or “substantially” are used in this specification with respect to numerical and / or geometric terms, it is intended that the relevant numerical values ​​include manufacturing tolerances (e.g., ±10%) around the stated values. Moreover, regardless of whether numerical and / or geometric terms are modified with “about” or “substantially,” it will be understood that these values ​​should be interpreted to include manufacturing or operational tolerances (e.g., ±10%) around the stated numerical values ​​and / or geometry.

[0051] In the following description, when an element is referred to as "above" or "on" another element, it may be directly above, below, to the left, or to the right of the other element while in contact with it, or it may be above, below, to the left, or to the right of the other element without contacting it. Singular terms may include plural forms unless otherwise specified. It will be further understood that the terms "comprising" and / or "including" as used herein indicate the presence of the stated features or elements, but do not exclude the presence or addition of one or more other features or elements. Additionally, spatially related (relative) terms such as "above," "below," etc., are described herein based on the orientation shown in the accompanying drawings and may be described otherwise when the orientation of the corresponding object changes. In other words, such spatially related terms are intended to cover different orientations of the device in use or operation, in addition to those depicted in the accompanying drawings, such that the device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related terms used herein are interpreted accordingly.

[0052] An element referred to by a definite article or demonstrative determiner may be interpreted as one or more elements, even if it has a singular form. The operations of a method may be performed in an appropriate order, unless explicitly described in order or vice versa, and are not limited to the order in which they are stated.

[0053] In this disclosure, terms such as "unit" or "module" used to refer to a functional unit having at least one function or operation are implemented (and / or via) processing circuitry systems, such as hardware, software, or a combination of hardware and software. For example, processing circuitry systems may more particularly include, but are not limited to, central processing units (CPUs), arithmetic logic units (ALUs), digital signal processors, microcomputers (microcomputers), field-programmable gate arrays (FPGAs), system-on-a-chip (SoCs), programmable logic units, microprocessors, application-specific integrated circuits (ASICs), etc.

[0054] Furthermore, the line connections or connecting components between the elements depicted in the accompanying drawings represent functional connections and / or physical or electrical connections as examples, and in practical applications, they may be replaced or embodied (implemented) by a variety of other functional connections, physical connections, or electrical connections.

[0055] Examples or terms are used only to describe technical ideas in this document and should not be considered for limiting purposes unless defined by the claims.

[0056] Figure 1 This is a schematic cross-sectional view of a capacitor 100 according to at least one exemplary embodiment.

[0057] refer to Figure 1 The capacitor 100 may include a first electrode 110, a second electrode 120 opposite to the first electrode 110, and a dielectric layer 130 disposed (provided) between the first electrode 110 and the second electrode 120. Here, the dielectric layer 130 may include a dielectric material having a rutile crystal phase that is stable at relatively high temperatures and relatively high pressures.

[0058] A first electrode 110, also known as a lower electrode, may be disposed on a substrate (not shown). The substrate may be part of a structure that physically supports the capacitor 100 and / or part of a device (equipment) connected to the capacitor 100. The substrate may include a semiconductor material pattern, an insulating material pattern, a conductive material pattern, and / or the like. For example, the substrate may include semiconductor materials such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP), and / or may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0059] The first electrode 110 may be conductive and may include a metal nitride. For example, the first electrode 110 may include a metal nitride containing a group VB element and nitrogen. In these cases, the first electrode 110 may include a nitride denoted as MN (where M refers to a group VB element and N refers to nitrogen). Group VB elements may include, for example, vanadium (V), niobium (Nb), tantalum (Ta), etc. (Db), and / or the like. The first electrode 110 may include a metal nitride in which a Group IVB element is added to a Group VB element. In other words, in addition to the Group VB element, the metal nitride may further contain a Group IVB element. In this case, the first electrode 110 may include a nitride represented as M x M' 1-x N (where 0 < x < 1, M refers to a Group VB element, M' refers to a Group IVB element, and N refers to nitrogen). The Group IVB element may include, for example, titanium (Ti), zirconium (Zr), hafnium (Hf), (Rf), or the like.

[0060] The first electrode 110 may be formed by depositing the above-described metal nitride on a substrate (e.g., by an atomic layer deposition (ALD) process). Since the first electrode 110 includes a nitride of a Group VB element, a dielectric layer 130 having a rutile crystal phase can be formed on the first electrode 110 via forming an oxide interface region including an oxide of the Group VB element at the surface of the first electrode 110.

[0061] The second electrode 120, which may also be referred to as the upper electrode, may be opposite to the first electrode 110 at a certain distance from the first electrode 110. The second electrode 120 may include various conductive materials. The second electrode 120 may include, for example, a metal, a metal nitride, a metal oxide, and / or a combination thereof. For example, the second electrode 120 may include at least one metal (e.g., selected from titanium (Ti), nickel (Ni), aluminum (Al), tantalum (Ta), tungsten (W), platinum (Pt), palladium (Pd), gold (Au), iridium (Ir), rhodium (Rh), molybdenum (Mo), vanadium (V), niobium (Nb), ruthenium (Ru), cobalt (Co), and / or the like), a conductive metal oxide (including at least one of the metals), and / or a conductive metal nitride (including at least one of the metals). For example, the conductive metal oxide may include platinum oxide (PtO), iridium oxide (IrO2), ruthenium oxide (RuO2), strontium ruthenate (SrRuO3), barium strontium ruthenate ((Ba,Sr)RuO3), calcium ruthenate (CaRuO3), lanthanum strontium cobaltate ((La,Sr)CoO3), or the like. For example, the conductive metal nitride may include titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), cobalt nitride (CoN), tungsten nitride (WN), and / or the like.

[0062] The second electrode 120 may include a metal nitride denoted as HH'N. Here, H refers to a metallic element, H' refers to an element other than H, and N refers to nitrogen. For example, H may include at least one element selected from Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and / or U. For example, H' may include at least one element selected from H, Li, As, Se, N, O, P, S, Be, B, Na, Mg, Al, Si, K, Ca, Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn, Ga, Ge, Rb, Sr, Y, Zr, Nb, Mo, Tc, Ru, Rh, Pd, Ag, Cd, In, Sn, Sb, Te, Cs, Ba, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, Hf, Ta, W, Re, Os, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, Ra, Ac, Th, Pa, and / or U. Here, the term "metal" refers to both metals and metalloids.

[0063] A dielectric layer 130 is disposed between the first electrode 110 and the second electrode 120. The dielectric layer 130 may comprise a dielectric material having a relatively high dielectric constant. For example, the dielectric layer 130 may have a dielectric constant of approximately 100 or greater, but is not limited thereto. The dielectric layer 130 may comprise a dielectric material having a rutile crystalline phase (e.g., TiO2), which is a crystalline phase stable at relatively high temperatures and relatively high pressures. Here, the dielectric layer 130 may comprise the rutile crystalline phase as the main phase. The statement "the dielectric layer 130 comprises the rutile crystalline phase as the main phase" means that when the dielectric layer 130 includes other crystalline phases (e.g., anatase, brookite, or similar) and / or amorphous phases besides the rutile crystalline phase, the dielectric layer 130 comprises the rutile crystalline phase in the largest possible quantity. Because the dielectric layer 130 comprises the rutile crystalline phase as the main phase, the dielectric layer 130 can exhibit a high dielectric constant.

[0064] The dielectric layer 130 having a rutile crystal phase can be formed, for example, by depositing TiO2 on the first electrode 110 using an ALD process. In at least one exemplary embodiment, the dielectric layer 130 having a rutile crystal phase can be in direct contact with the first electrode 110. For example, the dielectric layer 130 can have a thickness of about 100 Å or less. For example, the dielectric layer 130 can have a thickness of about 50 Å to about 100 Å, but is not limited thereto.

[0065] An oxide interface region may be formed on the surface of the first electrode 110 near (e.g., in contact with) the dielectric layer 130 (also referred to as the upper surface). As described below, the oxide interface region may be formed when a dielectric layer 130 having a rutile crystal phase is deposited on the upper surface of the first electrode 110. The oxide interface region may be provided on at least a portion (e.g., the entire upper surface) of the upper surface of the first electrode 110 facing the dielectric layer 130.

[0066] The oxide interface region may include a metal oxide. For example, the oxide interface region may include a metal oxide containing a group VB element. In these cases, the oxide interface region may include an oxide denoted as M. n O 2n-1 or MO 2n-1 (Where n is a natural number (e.g., 1, 2, or 3), M refers to a Group VB element, and O refers to oxygen) oxides. For example, Group VB elements may include vanadium (V), niobium (Nb), tantalum (Ta), (Db), and / or similar.

[0067] As described below, the oxide interface region comprising oxides of group VB elements can promote or induce the formation of the rutile phase of dielectric layer 130 during the ALD process used to form dielectric layer 130. For example, the oxide interface region can be thin, having a thickness of about 12 Å or less. For example, the oxide interface region can have a thickness of about 5 Å to about 12 Å, but is not limited thereto.

[0068] Figures 2A to 2C This is a diagram illustrating a method for manufacturing a capacitor 100 according to at least one exemplary embodiment.

[0069] refer to Figure 2A A first electrode 110 is formed on a substrate (not shown). As described above, the substrate may include a semiconductor material pattern, an insulating material pattern, a conductive material pattern, and / or the like. For example, the substrate may include semiconductor materials such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP), and / or may include insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0070] The formation of the first electrode 110 may include, for example, an atomic layer deposition (ALD) process. For example, the first electrode 110 may be formed by depositing a metal nitride including a Group VB element on a substrate through an ALD process. In these cases, the first electrode 110 may include a nitride represented as MN (where M refers to a Group VB element and N refers to nitrogen). The first electrode 110 may also be formed by depositing a metal nitride in which a Group IVB element is added to a Group VB element (i.e., a metal nitride including a Group VB element and a Group IVB element) on the substrate. In this case, the first electrode 110 may include a nitride represented as M x M' 1-x N (0 < x < 1, M refers to a Group VB element, M' refers to a Group IVB element, and N refers to nitrogen).

[0071] Reference Figure 2B , a dielectric layer 130 is formed on the first electrode 110 through an ALD process. During the ALD process, the dielectric layer 130 may be formed on the first electrode 110 including a nitride of a Group VB element such that the dielectric layer 130 may have a rutile crystal phase.

[0072] During the formation of the dielectric layer 130, an oxide interface region may be formed at the surface of the first electrode 110 close to (e.g., in contact with) the dielectric layer 130. For example, by exposing the surface of the first electrode 110 to oxygen included in air, an oxide film may be naturally formed at the surface of the first electrode 110.

[0073] After that, an ALD process is performed to form a dielectric layer 130 (e.g., a TiO2 layer) on the first electrode 110. First, when the dielectric layer 130 (e.g., a TiO2 layer) is initially formed on the oxide film (e.g., an M2O5 film, where M refers to a Group VB element and O refers to oxygen) naturally formed on the surface of the first electrode 110, oxygen may escape from the oxide film, and thus, an oxide interface region having a reduced phase such as M2O3 may be formed on at least a part of the surface of the first electrode 110. Here, the oxide interface region may include a metal oxide containing a Group VB element. In this case, the oxide interface region may include a representation of M n O 2n-1 or MO 2n-1 (n is a natural number, M refers to a Group VB element, and O refers to oxygen). The oxide interface region may have a thickness of, for example, about 12 Å or less. For example, the oxide interface region may have a thickness of about 5 Å to 12 Å, but is not limited thereto.

[0074] Next, as the ALD process for forming the dielectric layer 130 (e.g., TiO2 layer) continues, a dielectric layer 130 (e.g., TiO2 layer) having a rutile crystal phase can grow from the upper surface of the first electrode 110. The dielectric layer 130 (e.g., TiO2 layer) can have a thickness of about 100 Å or less. For example, the dielectric layer 130 can have a thickness of about 50 Å to 100 Å, but is not limited thereto. Additionally, after the ALD process is completed, an additional heat treatment can be performed to make the rutile crystal phase of the dielectric layer 130 more robust.

[0075] Reference Figure 2C , a second electrode 120 is deposited on the dielectric layer 130. As described above, the second electrode 120 can include various conductive materials. For example, the second electrode 120 can include a metal, a metal nitride, a metal oxide, or a combination thereof. For example, the second electrode 120 can include at least one metal (e.g., selected from titanium (Ti), nickel (Ni), aluminum (Al), tantalum (Ta), tungsten (W), platinum (Pt), palladium (Pd), gold (Au), iridium (Ir), rhodium (Rh), molybdenum (Mo), vanadium (V), niobium (Nb), ruthenium (Ru), cobalt (Co), and / or the like), a conductive metal oxide (e.g., including at least one of the metals), and / or a conductive metal nitride (e.g., including at least one of the metals). For example, the conductive metal oxide can include platinum oxide (PtO), iridium oxide (IrO2), ruthenium oxide (RuO2), strontium ruthenate (SrRuO3), barium strontium ruthenate ((Ba,Sr)RuO3), calcium ruthenate (CaRuO3), lanthanum strontium cobaltate ((La,Sr)CoO3), or the like. For example, the conductive metal nitride can include titanium nitride (TiN), tantalum nitride (TaN), niobium nitride (NbN), molybdenum nitride (MoN), cobalt nitride (CoN), tungsten nitride (WN), or the like. The second electrode 120 can include a metal nitride represented as HH'N. Here, H refers to a metal element, H' refers to an element different from H, and N refers to nitrogen.

[0076] As described above, in the ALD process for forming the dielectric layer 130 (e.g., TiO2 layer), a dielectric layer 130 (e.g., TiO2 layer) including a rutile crystal phase can be formed on the upper surface of the first electrode 110, and the first electrode 110 includes a metal nitride of a Group VB element or a metal nitride of a Group VB element and a Group IVB element (e.g., a nitride represented as MN or M x M' 1-x N, where 0 < x < 1, M refers to a Group VB element, M' refers to a Group IVB element, and N refers to nitrogen).

[0077] When the ALD process is initially performed to form the dielectric layer 130 (e.g., TiO2 layer), an oxide interface region including a metal oxide of group VB elements (e.g., represented as M n O 2n-1 or MO 2n-1 where n refers to a natural number, M refers to a group VB element, and O refers to oxygen) can be formed at the upper surface of the first electrode 110. Then, when the ALD process continues, the dielectric layer 130 (e.g., TiO2 layer) including the rutile crystal phase can grow on the oxide interface region. For example, without being limited to a specific theory, based on the lattice interaction between the dielectric layer 130 and the oxide interface region, the formation of the dielectric layer 130 including the rutile crystal phase can be promoted.

[0078] When a TiO2 dielectric layer is disposed between general metal electrodes to form a capacitor having a metal-insulator-metal (MIM) structure, the TiO2 dielectric layer does not have the rutile crystal phase that is stable at relatively high temperatures and relatively high pressures, but instead has anatase crystal phase that exhibits a low dielectric constant. However, in the capacitor 100 of the at least one example embodiment, the first electrode 110 includes a nitride of a group VB element or a nitride of a group VB element and a group IVB element (e.g., represented as MN or M x M' 1-x N nitride, where 0 < x < 1, M refers to a group VB element, M' refers to a group IVB element, and N refers to nitrogen), and TiO2 is directly grown on the first electrode 110 to form a dielectric layer 130 having a rutile crystal phase with a high dielectric constant. As described above, the capacitor 100 of the embodiment includes a dielectric material (e.g., rutile phase TiO2) having a rutile crystal phase with a high dielectric constant. Therefore, the capacitance of the capacitor 100 can be improved, and the charge storage capacity of a semiconductor device (e.g., dynamic random access memory (DRAM)) including the capacitor 100 can be enhanced.

[0079] Figure 3 Shows a transmission electron microscope (TEM) image of a dielectric layer (rutile TiO2 layer) having a rutile crystal phase formed by depositing TiO2 on a first electrode (VN electrode) according to at least one example embodiment. Although not clearly shown in Figure 3 a V2O3 oxide interface region having a very small thickness can be formed at the surface of the VN electrode close to (in contact with) the rutile crystal phase TiO2 layer. Figure 4 is a graph showing the following simulation results: The simulation results show the change in the interfacial energy according to the heat treatment of the oxynitride and oxide containing a group VB element (M). In Figure 4In this context, MON refers to the oxynitrides of Group VB elements, and M₂O₃, MO₂, and M₂O₅ refer to the oxides of Group VB elements. M can be, for example, V, Nb, Ta, or Db. Figure 4 In the diagram, ■ represents the interface energy before heat treatment, and ▲ represents the interface energy after heat treatment. For example, heat treatment can be performed during the ALD process used to form the dielectric layer (TiO2 layer).

[0080] refer to Figure 4 It can be seen that in oxides containing group VB elements (M), the condition M satisfies n O 2n-1 or MO 2n-1 The oxide of M2O3 (where n is a natural number, M is a group VB element, and O is oxygen) shows the greatest improvement in stability due to heat treatment.

[0081] Figure 5 This diagram illustrates the crystal phases observed when TiO2 dielectric layers are grown on layers of oxides of group VB elements (M) using an ALD process. M can be, for example, V, Nb, Ta, or Db.

[0082] refer to Figure 5 When MO is in oxides containing group VB elements (M) 1.825 When TiO2 is grown on an oxide layer, a TiO2 layer with an anatase crystal phase can be formed. This is achieved when the oxide contains a group VB element (M) satisfying M... n O 2n-1 or MO 2n-1 When TiO2 is grown on an oxide layer (where n is a natural number, M is a group VB element, and O is oxygen), that is, when TiO2 is grown on an M2O3 oxide layer, a TiO2 layer with a rutile crystal phase can be formed.

[0083] Figure 6 This is a graph showing the results of measuring the leakage current density (J) and equivalent oxide thickness (Toxeq.) of the capacitor in the comparative example and the capacitor in the embodiment. The leakage current density was measured at an applied voltage of 1V.

[0084] exist Figure 6 In the text, "C1" represents the capacitor of the comparative example, and "C2" represents the capacitor of the embodiment. A capacitor comprising a TiO2 dielectric layer having anatase phase between metal electrodes is used as the capacitor of the comparative example, and... Figure 1 The capacitor 100 shown in the embodiment includes a TiO2 dielectric layer having a rutile crystal phase.

[0085] refer to Figure 6As can be seen, due to the rutile crystal phase with a high dielectric constant, the capacitor of the embodiment exhibits an improvement of approximately 31% in equivalent oxide thickness and a reduction of approximately 37.8% in leakage current density compared to the capacitor of the comparative example.

[0086] As described above, the capacitor 100 of the at least one example embodiment includes a dielectric layer 130 (e.g., a TiO2 dielectric layer) having a rutile crystal phase with a high dielectric constant, and therefore, the capacitance of the capacitor 100 can be improved. Additionally, the charge storage capability of the semiconductor device (e.g., a DRAM device or the like) including the capacitor 100 can be improved.

[0087] Capacitor 100 can be used in various semiconductor devices. For example, capacitor 100 can be used together with transistors to form a DRAM device. However, the implementation is not limited to this. For example, capacitor 100 can be used together with other semiconductor units to form various semiconductor devices. In addition, capacitor 100 can be used together with other circuit elements to form part of the electronic circuitry constituting an electronic device.

[0088] Figure 7 This is a circuit diagram schematically illustrating the circuit configuration and operation of a semiconductor device 1000 employing a capacitor 100 according to at least one exemplary embodiment.

[0089] refer to Figure 7 The circuit diagram of semiconductor device 1000 shows a memory cell of a DRAM device, which includes a transistor TR, a capacitor CA, a word line WL, and a bit line BL. The capacitor CA may be the capacitor 100 described above according to the embodiment.

[0090] Data is written to a DRAM device as follows: A gate voltage (high) is applied to the gate electrode of transistor TR through word line WL to turn on transistor TR. Then, VDD (hereinafter referred to as "high voltage") or 0 (hereinafter referred to as "low voltage"), which is the data voltage value to be input, is applied to bit line BL. When both word line WL and bit line BL are high, capacitor CA is charged, and data "1" is written. When word line WL is high and bit line BL is low, capacitor CA is discharged, and data "0" is written.

[0091] When reading data, a high voltage is applied to the word line WL to turn on the transistor TR of the DRAM device, and a voltage of VDD / 2 is applied to the bit line BL. When the DRAM data is "1", that is, when the voltage across capacitor CA is VDD, the charge in capacitor CA slowly moves to the bit line BL, causing the voltage of the bit line BL to rise slightly above VDD / 2. Conversely, when the data across capacitor CA is "0", the charge moves from the bit line BL to capacitor CA, causing the voltage of the bit line BL to drop slightly below VDD / 2. This potential difference in the bit line BL can be detected and amplified by a sense amplifier to determine whether the data is "0" or "1".

[0092] Figure 8 This is a schematic diagram illustrating a semiconductor device 1001 according to at least one exemplary embodiment.

[0093] refer to Figure 8 Semiconductor device 1001 may include a structure in which capacitor CA1 and transistor TR are electrically connected to each other via contacts 20. Capacitor CA1 may include a first electrode 110, a second electrode 120 opposite to the first electrode 110, and a dielectric layer 130 disposed between the first electrode 110 and the second electrode 120. Capacitor CA1 may be a reference. Figure 1 The capacitor 100 is described, and therefore the description of capacitor CA1 is not presented here.

[0094] The transistor TR can be a field-effect transistor. The transistor TR includes a semiconductor substrate SU and a gate stack GS. The semiconductor substrate SU includes a source region SR, a drain region DR, and a channel region CH. The gate stack GS is disposed on the semiconductor substrate SU facing the channel region CH. The gate stack GS includes a gate insulating layer GI and a gate electrode GA.

[0095] A channel region CH is disposed between and electrically connected to the source region SR and the drain region DR. The source region SR may be electrically connected to or in contact with one end portion of the channel region CH, and the drain region DR may be electrically connected to or in contact with the other end portion of the channel region CH. The channel region CH may be a substrate region defined within the semiconductor substrate SU between the source region SR and the drain region DR.

[0096] The semiconductor substrate SU may include semiconductor materials. For example, the semiconductor substrate SU may include semiconductor materials such as silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). Alternatively, the semiconductor substrate SU may include a silicon-on-insulator (SOI) substrate.

[0097] The source region SR, drain region DR, and channel region CH can be formed by independently implanting dopants into different regions of the semiconductor substrate SU. In this case, the source region SR, channel region CH, and drain region DR may include the material of the semiconductor substrate SU as the base material. The source region SR and drain region DR may include conductive materials. In this case, the source region SR and drain region DR may include, for example, metals, metal compounds, or conductive polymers.

[0098] Alternatively, with Figure 8 Unlike the illustrations shown, the channel region CH can be implemented as a separate material layer (thin film). In this case, for example, the channel region CH may include at least one selected from Si, Ge, SiGe, III-V group semiconductors, oxide semiconductors, nitride semiconductors, oxynitride semiconductors, two-dimensional (2D) materials, quantum dots (QDs), and organic semiconductors. For example, oxide semiconductors may include InGaZnO, 2D materials may include transition metal dichalcogenides (TMDs) or graphene, and QDs may include colloidal QDs or nanocrystalline structures.

[0099] The gate electrode GA may be disposed above the semiconductor substrate SU and may be opposite the channel region CH at a certain distance from the semiconductor substrate SU. The gate electrode GA may include at least one selected from metals, metal nitrides, metal carbides, and polycrystalline silicon. For example, the metal may include at least one selected from aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), and / or the like. The metal nitride may include at least one selected from titanium nitride (TiN), tantalum nitride (TaN), and / or the like. The metal carbide may include at least one selected from metal carbides doped with (or containing) aluminum or silicon. For example, the metal carbide may include TiAlC, TaAlC, TiSiC, TaSiC, and / or the like.

[0100] The gate electrode (GA) may have a structure in which multiple materials are stacked. For example, the gate electrode (GA) may include a stacked structure of metal nitride layers / metal layers such as TiN / Al, or a stacked structure of metal nitride layers / metal carbide layers / metal layers such as TiN / TiAlC / W. However, the materials mentioned above are merely examples.

[0101] A gate insulating layer GI may be further disposed between the semiconductor substrate SU and the gate electrode GA. The gate insulating layer GI may comprise a paraelectric material or a high-k dielectric material and may have a dielectric constant of approximately 20 to approximately 70.

[0102] The gate insulating layer GI may include silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, or the like, or may include a 2D insulator such as hexagonal boron nitride (h-BN). For example, the gate insulating layer GI may include silicon oxide (SiO2), silicon nitride (SiN), etc.x Hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO3), zirconium oxide (ZrO2), hafnium zirconium oxide (HfZrO2), zirconium silicon oxide (ZrSiO4), tantalum oxide (Ta2O5), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (PbSc) 0.5 Ta 0.5 O3), lead zinc niobate (PbZnNbO3), or similar. Additionally, the gate insulating layer GI may include: metal oxynitrides such as aluminum oxynitride (AlON), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), lanthanum oxynitride (LaON), or yttrium oxynitride (YON); silicates such as ZrSiON, HfSiON, YSiON, or LaSiON; or aluminates such as ZrAlON or HfAlON. The gate insulating layer GI may form a gate stack GS together with the gate electrode GA.

[0103] One of the first electrode 110 and the second electrode 120 of capacitor CA1 is electrically connected to one of the source region SR and the drain region DR of transistor TR via contact 20. Here, contact 20 may include a conductive material such as tungsten, copper, aluminum, or polycrystalline silicon.

[0104] The arrangement of capacitor CA1 and transistor TR can be modified in various ways. For example, capacitor CA1 can be positioned above semiconductor substrate SU or embedded in semiconductor substrate SU.

[0105] although Figure 8 The illustration shows a semiconductor device 1001 including a capacitor CA1 and a transistor TR, but this is merely an example. The semiconductor device 1001 may include multiple capacitors and multiple transistors.

[0106] Figure 9 A semiconductor device 1002 is shown according to at least one example embodiment.

[0107] refer to Figure 9 Semiconductor device 1002 may include a structure in which capacitor CA2 and transistor TR are electrically connected to each other via contact 21. Transistor TR includes a semiconductor substrate SU and a gate stack GS. Semiconductor substrate SU includes a source region SR, a drain region DR, and a channel region CH. Gate stack GS is disposed on semiconductor substrate SU facing channel region CH. Gate stack GS includes a gate insulating layer GI and a gate electrode GA.

[0108] An interlayer insulating layer 25 may be disposed on a semiconductor substrate SU to cover the gate stack GS. The interlayer insulating layer 25 may include an insulating material. For example, the interlayer insulating layer 25 may include silicon oxide (e.g., SiO2), aluminum oxide (e.g., Al2O3), or a high-k dielectric material (e.g., HfO2). A contact 21 extends through the interlayer insulating layer 25 and electrically connects the transistor TR and the capacitor CA2 to each other.

[0109] The capacitor CA2 may include a first electrode 110, a second electrode 120 opposite to the first electrode 110, and a dielectric layer 130 disposed between the first electrode 110 and the second electrode 120. The first electrode 110 and the second electrode 120 are shaped to increase the contact area with the dielectric layer 130. In other aspects, the capacitor CA2 may be related to a reference... Figure 1 The capacitor described is the same as (and / or substantially similar to) capacitor 100, and therefore, the description of capacitor CA2 need not be presented here.

[0110] Figure 10 This is a plan view showing a semiconductor device 1003 according to at least one exemplary embodiment.

[0111] refer to Figure 10 The semiconductor device 1003 has a structure in which a plurality of capacitors CA3 and a plurality of field-effect transistors are repeatedly arranged. (Reference) Figure 10 The semiconductor device 1003 may include: a semiconductor substrate 11' including a source, a drain, and a channel; a field-effect transistor including a gate stack 12; a contact structure 20' disposed on the semiconductor substrate 11' without overlapping the gate stack 12; and a capacitor CA3 disposed on the contact structure 20'. The semiconductor device 1003 may further include a bit line structure 13 electrically connecting the field-effect transistors to each other.

[0112] although Figure 10 An example is shown in which the contact structure 20' and capacitor CA3 are repeatedly arranged in the X and Y directions, but the implementation is not limited thereto. For example, the contact structure 20' may be arranged in the X and Y directions, and the capacitor CA3 may be arranged in a hexagonal shape, such as a honeycomb shape.

[0113] Figure 11 It is along Figure 10 A cross-sectional view taken from the A-A' line.

[0114] refer to Figure 11The semiconductor substrate 11' may have a shallow trench isolation (STI) structure including a device isolation layer 14. The device isolation layer 14 may have a single-layer structure formed of one type of insulating layer or a multilayer structure formed of a combination of two or more types of insulating layers. The device isolation layer 14 may include device isolation trenches 14T in the semiconductor substrate 11', and the device isolation trenches 14T may be filled with an insulating material. The insulating material may include at least one selected from fluorosilicate glass (FSG), undoped silicate glass (USG), borosilicate glass (BPSG), phosphosilicate glass (PSG), flowable oxide (FOX), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), and Tonen silazene (TOSZ). However, the exemplary embodiments are not limited thereto.

[0115] The semiconductor substrate 11' may further include a channel region CH defined by a device isolation layer 14, and a gate line trench 12T disposed parallel to the upper surface of the semiconductor substrate 11' and extending in the X direction. The channel region CH may have a relatively long island shape, having a long axis and a short axis. Figure 10 As shown, the long axis of the channel region CH can be parallel to the upper surface of the semiconductor substrate 11' and aligned with direction D3.

[0116] The gate line trench 12T may intersect the channel region CH at a predetermined depth from the upper surface of the semiconductor substrate 11', or it may be disposed within the channel region CH. The gate line trench 12T may be disposed inside the device isolation trench 14T. For example, the bottom surface of the gate line trench 12T disposed inside the device isolation trench 14T may be lower than the bottom surface of the gate line trench 12T disposed inside the channel region CH. The first source / drain 11'ab and the second source / drain 11''ab may be disposed on both sides of the gate line trench 12T in the upper portion of the channel region CH.

[0117] Gate stack 12 may be disposed in each of the gate line trenches 12T. For example, a gate insulating layer 12a, a gate electrode 12b, and a gate capping layer 12c may be sequentially disposed in each of the gate line trenches 12T. The gate insulating layer 12a and the gate electrode 12b can be understood by referring to the description given above. The gate capping layer 12c may include at least one selected from silicon oxide, silicon oxynitride, and silicon nitride. The gate capping layer 12c may be disposed on the gate electrode 12b to fill the remaining portion of the gate line trench 12T.

[0118] Bit line structure 13 may be disposed on the first source / drain 11'ab. Bit line structure 13 may be disposed parallel to the upper surface of semiconductor substrate 11' and may extend in the Y direction. Bit line structure 13 may be electrically connected to the first source / drain 11'ab. Bit line structure 13 may sequentially include bit line contact 13a, bit line 13b, and bit line capping layer 13c starting from semiconductor substrate 11'. For example, bit line contact 13a may include polysilicon, bit line 13b may include a metallic material, and bit line capping layer 13c may include an insulating material such as silicon nitride or silicon oxynitride.

[0119] Figure 11 An example is shown in which the bit line contact 13a has a bottom surface at the same level as the upper surface of the semiconductor substrate 11', but this is merely illustrative and not limiting. In at least one exemplary embodiment, for example, a recess may be formed to a predetermined depth from the upper surface of the semiconductor substrate 11', and the bit line contact 13a may extend into the recess such that the bottom surface of the bit line contact 13a may be lower than the upper surface of the semiconductor substrate 11'.

[0120] The bit line structure 13 may further include an intermediate layer (not shown) between the bit line contact 13a and the bit line 13b. The intermediate layer may include a metal silicide such as tungsten silicide, or a metal nitride such as tungsten nitride. Additionally, bit line spacers (not shown) may be formed on the sidewalls of the bit line structure 13. The bit line spacers may have a single-layer or multi-layer structure and may include an insulating material such as silicon oxide, silicon oxynitride, or silicon nitride. The bit line spacers may further include an air gap (not shown).

[0121] The contact structure 20' may be disposed on the second source / drain 11''ab. The contact structure 20' and the bit line structure 13 may be disposed on different sources / drains of the semiconductor substrate 11'. The contact structure 20' may be provided by sequentially stacking a lower contact pattern (not shown), a metal silicide layer (not shown), and an upper contact pattern (not shown) on the second source / drain 11''ab. In addition, the contact structure 20' may further include a barrier layer (not shown) surrounding the side surface and bottom surface of the upper contact pattern. For example, the lower contact pattern may include polysilicon, the upper contact pattern may include a metallic material, and the barrier layer may include a conductive metal nitride.

[0122] The capacitor CA3 is electrically connected to the contact structure 20' and disposed above the semiconductor substrate 11'. For example, the capacitor CA3 includes a first electrode 110 electrically connected to the contact structure 20', a second electrode 120 disposed separately from the first electrode 110, and a dielectric layer 130 disposed between the first electrode 110 and the second electrode 120.

[0123] The first electrode 110 may have a cup shape or a cylindrical shape having a closed bottom interior space. The second electrode 120 may have a comb shape having teeth extending into the interior space of the first electrode 110 and in the region between adjacent first electrodes 110. A dielectric layer 130 may be disposed between the first electrode 110 and the second electrode 120 in a direction parallel to the surfaces of the first and second electrodes 110 and 120. In other aspects, the capacitor CA3 may be related to a reference... Figure 1 The capacitor described is the same as and / or substantially similar to capacitor 100, and therefore, the description of capacitor CA3 is not presented here.

[0124] An interlayer insulating layer 15 may be further disposed between the capacitor CA3 and the semiconductor substrate 11'. The interlayer insulating layer 15 may be disposed in the space between the capacitor CA3 and the semiconductor substrate 11', in which no other structures are arranged. For example, the interlayer insulating layer 15 may cover wiring and / or electrode structures disposed on the semiconductor substrate 11', such as bit line structure 13, contact structure 20', and gate stack 12. For example, the interlayer insulating layer 15 may surround the wall of the contact structure 20'. The interlayer insulating layer 15 may include a first interlayer insulating layer 15a surrounding the bit line contact 13a, and a second interlayer insulating layer 15b covering the side surfaces and / or top surfaces of the bit line 13b and the bit line capping layer 13c.

[0125] The first electrode 110 of capacitor CA3 can be disposed on the interlayer insulating layer 15, for example, on the second interlayer insulating layer 15b of the interlayer insulating layer 15. When multiple capacitors CA3 are arranged, the bottom surfaces of the first electrodes 110 can be separated from each other by an etch stop layer 16. In other words, the etch stop layer 16 may include an opening 16T, and the bottom surfaces of the first electrodes 110 of capacitor CA3 can be disposed within the opening 16T. Figure 11 As shown, the first electrode 110 may have a cup shape or a cylindrical shape with a closed bottom interior space. The capacitor CA3 may further include a support (not shown) to prevent the first electrode 110 from tilting or collapsing, and the support may be disposed on the side wall of the first electrode 110.

[0126] Figure 12 This is a cross-sectional view showing a semiconductor device 1004 according to at least one exemplary embodiment.

[0127] The semiconductor device 1004 in the current embodiment utilizes and along Figure 10 The cross-sectional view corresponding to the section cut by line A-A' is shown, and is consistent with... Figure 11The semiconductor device 1003 shown differs only in the shape of the capacitor CA4. The capacitor CA4 is electrically connected to the contact structure 20' and disposed above the semiconductor substrate 11'. The capacitor CA4 includes a first electrode 110 electrically connected to the contact structure 20', a second electrode 120 disposed separately from the first electrode 110, and a dielectric layer 130 disposed between the first electrode 110 and the second electrode 120.

[0128] The first electrode 110 may have a cylindrical shape, such as a cylindrical, rectangular, or polygonal cylindrical shape extending in the vertical direction (Z direction). The second electrode 120 may have a comb shape, having teeth extending into the region between adjacent first electrodes 110. A dielectric layer 130 may be disposed between the first electrode 110 and the second electrode 120 in a direction parallel to the surfaces of the first and second electrodes 110 and 120. In other aspects, the capacitor CA4 may be associated with a reference... Figure 1 The capacitor 100 described is the same as or substantially similar to the capacitor 100, and therefore, the description of capacitor CA4 is not presented here.

[0129] The capacitors and semiconductor devices described above in the embodiments can be used in a variety of application areas. For example, the semiconductor devices of the embodiments can be used as logic devices or memory devices. The semiconductor devices of the embodiments can be used in devices such as mobile devices, computers, laptops, sensors, network devices, and neuromorphic devices for tasks such as arithmetic operations, program execution, or temporary data retention. In addition, the semiconductor devices of the embodiments can be used in electronic devices involving large amounts of data transmission and continuous data transmission.

[0130] Figure 13 and 14 This is a conceptual diagram illustrating an electronic device architecture that can be applied to an electronic device according to an implementation.

[0131] refer to Figure 13 The electronic device architecture 1100 may include a memory unit 1010, an arithmetic logic unit (ALU) 1020, and a control unit 1030. The memory unit 1010, ALU 1020, and control unit 1030 may be electrically connected to each other. For example, the electronic device architecture 1100 may be implemented as a single chip including the memory unit 1010, ALU 1020, and control unit 1030.

[0132] Storage unit 1010, ALU 1020, and control unit 1030 may be interconnected on-chip via metal wires for direct communication with each other. Storage unit 1010, ALU 1020, and control unit 1030 may be monolithically integrated on a single substrate to form a single chip. Input / output device 2000 may be connected to electronic device architecture 1100 (e.g., chip). Additionally, storage unit 1010 may include main memory and cache memory. Electronic device architecture 1100 (e.g., chip) may be an on-chip memory processing unit. Storage unit 1010 may include one or more of the capacitors and / or semiconductor devices described above. ALU 1020 and control unit 1030 may each include one or more of the capacitors and / or semiconductor devices described above.

[0133] refer to Figure 14 The cache memory 1510, ALU 1520, and control unit 1530 may form a central processing unit (CPU) 1500. The cache memory 1510 may include static random access memory (SRAM). The main memory 1600 and auxiliary memory 1700 may be provided separately from the CPU 1500. The main memory 1600 may include DRAM devices, which include one or more of the capacitors and / or semiconductor devices described above. In some cases, the electronic device architecture may be implemented in a manner where computing unit devices and storage unit devices are adjacent to each other on a single chip without any distinction between sub-units.

[0134] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and are not intended for limiting purposes. The descriptions of features or aspects in each embodiment should typically be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. Capacitors, including: A first electrode, comprising a metal nitride, wherein the metal nitride comprises a nitride of a group VB element or a nitride of a group VB element and a group IVB element; A second electrode opposite to the first electrode; as well as A dielectric layer between the first electrode and the second electrode, the dielectric layer comprising a rutile phase.

2. The capacitor according to claim 1, wherein the dielectric layer is in direct contact with the first electrode.

3. The capacitor according to claim 1, wherein the dielectric layer comprises TiO2.

4. The capacitor according to claim 1, wherein the dielectric layer comprises the rutile phase as the main phase.

5. The capacitor of claim 1, wherein the dielectric layer has a thickness of 100 Å or less.

6. The capacitor of claim 1, wherein the VB group element includes at least one of V, Nb, Ta, or Db.

7. The capacitor of claim 1, wherein the group IVB element includes at least one of Ti, Zr, Hf, or Rf.

8. The capacitor according to claim 1, wherein the metal nitride is represented by MN or M x M' 1-x N, where 0 < x < 1, M refers to the group VB element, M' refers to the group IVB element, and N refers to nitrogen.

9. The capacitor of claim 2, wherein the first electrode includes an oxide interface region that contacts the dielectric layer and contains a metal oxide of the group VB element.

10. The capacitor of claim 9, wherein the oxide interface region has a thickness of 12 Å or less.

11. The capacitor according to claim 9, wherein the metal oxide of the group VB element is made of M n O 2n-1 or MO 2n-1 The expression indicates that n is a natural number, M is an element of the VB group, and O is oxygen.

12. A semiconductor device, including a capacitor according to any one of claims 1 to 11.

13. A method of manufacturing a semiconductor device comprising a capacitor according to any one of claims 1 to 11, the method comprising: A first electrode comprising a metal nitride is formed, wherein the metal nitride comprises a group VB element, or a group VB element and a group IVB element; A dielectric layer is formed on the first electrode, such that the dielectric layer comprises a rutile crystal phase; and A second electrode is formed on the dielectric layer.

14. The method of claim 13, wherein the formation of the dielectric layer comprises directly depositing TiO2 on the first electrode by an atomic layer deposition process.

15. The method of claim 13, wherein forming a dielectric layer on the first electrode comprises: An oxide interface region is formed on the surface of the first electrode, and then the dielectric layer is formed on the oxide interface region.

Images