Optimized regulation and control method and system for modularized multi-level direct-current converter

Abstract

The invention discloses an optimized regulation and control method and system for a modular multi-level direct current converter, and the method comprises the steps: selecting a redundant sub-module according to a preset dynamic rotation strategy in each control period, and generating a zero-level pulse signal for the redundant sub-module; aiming at the non-redundant sub-module, calculating the capacitance voltage variation of the non-redundant sub-module and the previous control period; generating a voltage sequence and a voltage deviation value sequence; redistributing the original pulse signal corresponding to the jth non-redundant sub-module in the voltage deviation value sequence to the jth non-redundant sub-module in the voltage sequence; and integrating the zero-level pulse signal of the redundant sub-module and the pulse signal of the non-redundant sub-module, generating a final driving signal sequence corresponding to all the sub-modules of the bridge arm, and outputting the final driving signal sequence. On the fundamental premise of not changing the external characteristics of the output voltage and current of the converter port, the active equalization of the capacitor voltage and the optimization of loss and thermal stress are realized.

Description

Technical Field

[0001] This invention belongs to the field of power electronic control technology, and relates to the optimization technology of modular multilevel DC-DC converters, specifically to an optimization control method and system for modular multilevel DC-DC converters. Background Technology

[0002] Modular multilevel DC-DC converters (MMC-DC / DC converters) have gained widespread attention and application in modern power electronics fields such as submarine observation networks, flexible DC distribution networks, and urban rail transit DC traction networks due to their significant advantages, including modular structure, easy expansion of voltage levels, and low switching losses. In these application scenarios, the system typically requires the converter to possess extremely high operational reliability and long-term stability. However, the numerous submodules used in the system are potential weak points in its reliability.

[0003] To improve system reliability, redundant submodules are commonly used in engineering practice. In existing technologies, especially in AC / DC conversion applications such as high-voltage flexible DC transmission, the common "hot standby" redundant submodule modulation strategy mainly relies on real-time sorting of submodule capacitor voltages, achieving voltage balancing and redundancy replacement through the direction of bridge arm currents and capacitor voltage sorting. However, in pure DC conversion applications, the switching frequency is typically much higher than in traditional HVDC systems, and pulse changes are more frequent. Completely sorting all submodule capacitor voltages in each high-frequency control cycle would place enormous pressure on the computational resources and processing speed of the digital controller, making real-time performance difficult to guarantee. Therefore, for high-frequency DC modular multilevel converters, the completely sorted redundancy control strategy derived from high-voltage AC / DC scenarios cannot be directly and simply applied.

[0004] When the DC-DC converter topology is a DAB or LLC resonant type, the control and modulation issues become more complex. On the one hand, to ensure that the key electrical characteristics such as the output voltage and current of the system port containing redundant submodules remain strictly unchanged, any adjustment to the modulation strategy must be made without altering the equivalent output level and duty cycle. On the other hand, LLC resonant converters operate in a resonant state, and their loop current exhibits a significant resonant peak. The switching timing of the submodules not only affects capacitor voltage balance but also directly determines the switching losses and thermal stress distribution of the switching devices. If the redundancy or modulation strategy is inappropriate, some submodules can easily overheat due to prolonged high losses, accelerating device aging and ultimately weakening the reliability improvement effect expected from redundancy. Summary of the Invention

[0005] Purpose of the invention: To address the shortcomings of existing technologies in high-frequency DC applications, such as heavy computational burden, difficulty in loss optimization, and inflexible redundancy management, this invention provides a modular multilevel DC-DC converter optimization and control method and system. This method avoids the need for complete high-frequency sequencing of submodule capacitor voltages for each cycle without altering the strict constraints of the converter's external port characteristics. Simultaneously, it proactively and intelligently manages the switching and pulse distribution of submodules to achieve balanced control of capacitor voltages and dynamic uniform distribution of switching losses and thermal stress. This truly leverages the reliability-enhancing effect of redundancy design and extends the overall lifespan of the converter.

[0006] Technical Solution: To achieve the above objectives, this invention provides an optimized control method for a modular multilevel DC-DC converter, comprising the following steps:

[0007] S1: In each control cycle, according to the preset dynamic rotation strategy, select R sub-modules from the N sub-modules of each bridge arm and configure them as redundant sub-modules for this cycle, and generate a zero-level pulse signal for the redundant sub-modules so that they are in a bypass state without switching action in this cycle.

[0008] S2: Real-time acquisition of capacitor voltage Vci of each submodule; for non-redundant submodules, calculate the capacitor voltage change ΔVci(k) = |Vci(k) - Vci(k-1)| of each non-redundant submodule compared to the previous control cycle; sort all non-redundant submodules according to their current capacitor voltage value Vci to generate a voltage sequence, and sort them according to their capacitor voltage change ΔVci(k) to generate a voltage deviation sequence;

[0009] S3: Establish a one-to-one mapping relationship between the voltage deviation sequence and the voltage sequence; redistribute the original pulse signal corresponding to the j-th non-redundant sub-module in the voltage deviation sequence to the j-th non-redundant sub-module in the voltage sequence, where j=1, 2, …, NR;

[0010] S4: Integrate the zero-level pulse signals of the redundant sub-modules in step S1 with the pulse signals of the non-redundant sub-modules after redistribution in step S3 to generate the final drive signal sequence corresponding to all sub-modules of the bridge arm, and output the drive signal sequence to control the operation of the converter.

[0011] Furthermore, in step S1, before the start of each control cycle, an initialization operation is performed to initialize the ranking index and update the submodule capacitor voltage and the switching state of the previous cycle.

[0012] Furthermore, in step S1, the number R of redundant submodules is determined based on system reliability design indicators and cost constraints, and satisfies 1≤R < N / 2; the upper and lower bridge arms are configured with the same number of redundant submodules.

[0013] Further, the calculation method of the capacitor voltage change ΔVci(k) in step S2 includes: at the end of each control cycle, recording the instantaneous capacitor voltage value of each non-redundant submodule; at the beginning of the next control cycle, calculating the difference between the voltage value and the recorded value of the previous cycle, and using it as the capacitor voltage change ΔVci(k); ΔVci(k) = |Vci(k) -Vci(k-1)|, where Vci(k) and Vci(k-1) represent the capacitor voltage values ​​of the k-th control cycle and the (k-1)-th control cycle, respectively.

[0014] Further, in step S2, the current capacitor voltage values ​​Vci of all non-redundant submodules are sorted in ascending order to generate a voltage sequence, and then sorted in descending order according to their voltage change ΔVci(k) to generate a voltage deviation sequence.

[0015] This invention also provides a modular multilevel DC-DC converter optimization and control system based on dynamic redundancy and loss equalization, comprising:

[0016] The dynamic redundancy configuration module is used to select R sub-modules from the N sub-modules of each bridge arm and configure them as redundant sub-modules for the current cycle according to the preset dynamic rotation strategy, and generate a zero-level pulse signal for the redundant sub-modules so that they are in a bypass state without switching action during the current cycle.

[0017] The voltage status information processing module collects the capacitor voltage Vci of each sub-module in real time. For non-redundant sub-modules, it calculates the change in capacitor voltage ΔVci(k) of each non-redundant sub-module compared to the previous control cycle.

[0018] The pulse sequence generation module sorts the current capacitor voltage values ​​Vci of all non-redundant sub-modules to generate voltage sequences, and sorts them according to their voltage change ΔVci(k) to generate voltage deviation sequences.

[0019] The non-redundant pulse signal dynamic allocation module establishes a one-to-one mapping relationship between the voltage deviation sequence and the voltage sequence; it reassigns the original pulse signal corresponding to the j-th non-redundant sub-module in the voltage deviation sequence to the j-th non-redundant sub-module in the voltage sequence, where j=1, 2, …, NR.

[0020] The drive signal synthesis and output module integrates the zero-level pulse signals of redundant submodules and the pulse signals of non-redundant submodules to generate the final drive signal sequence corresponding to all submodules of the bridge arm, and outputs the drive signal sequence to control the operation of the converter.

[0021] Beneficial Effects: Compared with existing technologies, this invention, without fundamentally altering the external characteristics of the converter port output voltage and current, achieves active equalization of capacitor voltage and optimization of losses and thermal stress by periodically and regularly changing the position of redundant sub-modules and dynamically allocating working pulses based on the historical and current state information of the sub-modules. This invention possesses the following advantages:

[0022] 1. The pulse dynamic allocation mechanism proposed in this invention transforms the traditional voltage sorting problem into two voltage sorting and pulse mapping operations. Furthermore, it allows for voltage sampling and control over multiple control cycles. This method, while ensuring control accuracy, avoids the enormous computational burden of performing a full sort of all submodule capacitor voltages in each control cycle, as is common in traditional solutions. This makes the control system easier to implement, especially in high-frequency switching DC applications, effectively improving the real-time performance and reliability of the control.

[0023] 2. This invention constructs an active loss and thermal stress balancing mechanism by using the capacitance voltage variation of submodules as a characterization of their historical state and incorporating it into the pulse allocation decision loop. During pulse remapping, this mechanism systematically and dynamically allocates pulses from high-loss modules to modules with low current capacitance voltage and relatively less thermal stress accumulation. This overcomes the limitation of traditional modulation strategies where loss distribution is determined by a fixed topology, promoting a more consistent long-term thermal stress statistical distribution across all submodules. This effectively delays performance degradation caused by thermal fatigue in individual devices, thereby achieving proactive management and optimization of power device aging rates at the system level.

[0024] 3. The dynamic redundancy rotation and pulse dynamic allocation coordination mechanism proposed in this invention enhances the efficiency of redundancy design at the system operation level. Periodic rotation ensures that all submodules experience both "working" and "bypass" states, guaranteeing that the standby module is in a good "hot standby" state when redundancy needs to be switched. Global dynamic balancing of losses and voltage improves the consistency of the operating state of each submodule. This synergy not only enhances the system's seamless fault tolerance under single module failure, but also reduces the risk of common failures in all submodules by actively managing operational stress, thereby systematically enhancing the long-term operational reliability and availability of the converter from both preventative maintenance and fault tolerance dimensions. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the topology of a modular multilevel resonant converter;

[0026] Figure 2 This is a control block diagram of a modular multilevel resonant converter.

[0027] Figure 3 Pulse waveform diagram of a modular multilevel resonant converter submodule;

[0028] Figure 4 The waveform diagram of pulse superposition for a modular multilevel resonant converter submodule;

[0029] Figure 5 A comparison chart of junction temperatures of semiconductor devices with and without redundant sub-modules in a modular multilevel resonant converter;

[0030] Figure 6 This is a waveform diagram of the capacitor voltage of a modular multilevel resonant converter submodule. Detailed Implementation

[0031] The present invention will be further illustrated below with reference to the accompanying drawings and specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. After reading this invention, any modifications of the invention in various equivalent forms by those skilled in the art will fall within the scope defined by the appended claims.

[0032] Example 1:

[0033] This embodiment provides an optimized control method for a modular multilevel DC-DC converter based on dynamic redundancy and loss equalization. Specifically, this optimized control method is applied to a modular multilevel resonant converter, such as... Figure 1 As shown, the modular multilevel resonant converter includes a DC voltage source (DC), a modular multilevel circuit (MMC), a resonant circuit, a medium-to-high frequency transformer, a rectifier circuit, and an output capacitor (C). o and output equivalent load R L The modular multilevel circuit is divided into upper and lower bridge arms, each consisting of N identical half-bridge sub-modules SM1~SM2. N and one redundant half-bridge submodule and one bridge arm inductor L p (L) n The bridge arms are connected in series, and the upper and lower arms can be wound in a coupled manner to ensure that the inductance of the upper and lower arms is the same, and that the equivalent inductance of the bridge arm inductance in AC measurement is zero, thus decoupling the bridge arm inductance from the inductance in the resonant circuit. The resonant circuit consists of a resonant capacitor C. r Transformer leakage inductance L k And excitation inductance L m Composition. The secondary rectifier circuit of the transformer adopts a full-bridge structure with D1~D4 to reduce the voltage and current stress on individual switching devices.

[0034] Reference Figure 2 The optimization and control method for the modular multilevel resonant converter in this embodiment includes the following steps:

[0035] 1) Initialize the ranking index, update the submodule capacitor voltage and the switching state of the previous cycle;

[0036] 2) In each control cycle, according to the preset dynamic rotation strategy, R sub-modules are selected from the N sub-modules of each bridge arm and configured as redundant sub-modules for this cycle. A zero-level pulse signal is generated for the redundant sub-modules so that they are in a bypass state without switching action in this cycle.

[0037] The number of redundant submodules R is determined based on system reliability design indicators and cost constraints, and satisfies 1≤R < N / 2; the upper and lower bridge arms are configured with the same number of redundant submodules.

[0038] In this embodiment, the set of zero-level drive pulses for the current cycle is first extracted, and the zero-level pulses are sequentially distributed to the redundant sub-modules using a sequential polling method. Then, non-zero-level drive pulses are selected from the remaining sub-modules of each bridge arm.

[0039] 3) Real-time acquisition of capacitor voltage Vci of each submodule. For non-redundant submodules, the capacitor voltage data of the submodule in the previous control cycle is called up, and the capacitor voltage change of each non-redundant submodule compared with the previous control cycle is calculated as ΔVci(k) = |Vci(k) - Vci(k-1)|, where Vci(k) and Vci(k-1) represent the capacitor voltage values ​​in the k-th and (k-1)-th control cycles, respectively. The current capacitor voltage values ​​Vci of all non-redundant submodules are sorted in ascending order to generate a voltage sequence M, and then sorted in descending order according to their capacitor voltage change ΔVci(k) to generate a voltage deviation sequence P.

[0040] 4) Establish a one-to-one mapping relationship between the voltage deviation sequence and the voltage sequence; convert the original pulse signal P corresponding to the i-th non-redundant submodule in the voltage deviation sequence P. i The non-redundant submodule M at the i-th position in the voltage sequence M is reassigned. i , where j=1, 2, …, NR, to balance the capacitor voltage of each module;

[0041] 5) Integrate the zero-level pulse signals of the redundant sub-modules in step 2) with the pulse signals of the non-redundant sub-modules after redistribution in step 4) to generate the final drive signal sequence corresponding to all sub-modules of the bridge arm, and output the drive signal sequence to control the operation of the converter; the trigger signal enters the next control cycle to form a complete closed loop.

[0042] The above steps are repeated in the next control cycle to achieve active balancing of capacitor voltages in all sub-modules while ensuring that the overall output voltage and current waveforms of the converter remain unchanged, and to dynamically and uniformly distribute switching losses and thermal stress among all sub-modules.

[0043] The core of this invention's optimized control method lies in constructing a dynamic redundant submodule mechanism. This mechanism achieves balanced capacitor voltage and optimized loss distribution across all submodules without affecting the converter's port voltage and current characteristics. First, the position of the redundant submodule at each moment is determined through a sequential rotation, ensuring its pulse signal is zero. The pulses for the remaining submodules are dynamically allocated based on their capacitor voltage values. Second, for the pulse allocation strategy of non-redundant submodules, dynamic allocation is performed by combining the capacitor voltage change of the submodule at the previous moment with the current moment's capacitor voltage ranking. The pulse corresponding to the submodule with the largest capacitor voltage change in adjacent control cycles is allocated to the submodule with the lowest capacitor voltage in the current cycle, and so on.

[0044] Example 2:

[0045] This embodiment provides a modular multilevel DC-DC converter optimization and control system based on dynamic redundancy and loss equalization, including:

[0046] The dynamic redundancy configuration module is used to select R sub-modules from the N sub-modules of each bridge arm and configure them as redundant sub-modules for the current cycle according to the preset dynamic rotation strategy, and generate a zero-level pulse signal for the redundant sub-modules so that they are in a bypass state without switching action during the current cycle.

[0047] The voltage status information processing module collects the capacitor voltage Vci of each sub-module in real time. For non-redundant sub-modules, it calculates the change in capacitor voltage ΔVci(k) of each non-redundant sub-module compared to the previous control cycle.

[0048] The pulse sequence generation module sorts the current capacitor voltage values ​​Vci of all non-redundant sub-modules to generate voltage sequences, and sorts them according to their voltage change ΔVci(k) to generate voltage deviation sequences.

[0049] The non-redundant pulse signal dynamic allocation module establishes a one-to-one mapping relationship between the voltage deviation sequence and the voltage sequence; it reassigns the original pulse signal corresponding to the j-th non-redundant sub-module in the voltage deviation sequence to the j-th non-redundant sub-module in the voltage sequence, where j=1, 2, …, NR.

[0050] The drive signal synthesis and output module integrates the zero-level pulse signals of redundant submodules and the pulse signals of non-redundant submodules to generate the final drive signal sequence corresponding to all submodules of the bridge arm, and outputs the drive signal sequence to control the operation of the converter.

[0051] Example 3:

[0052] To verify the effectiveness and effects of the present invention, this embodiment will test and analyze the method of Example 1, as follows:

[0053] Figure 3 To illustrate the pulse waveforms of the submodules in the modular multilevel resonant converter, the bridge arm of the modular multilevel resonant converter has a total of 5 submodules, one of which is redundant. It can be observed that the pulses of each submodule sequentially include a zero-level pulse period, i.e. Figure 3 The blank interval with zero voltage is precisely the embodiment of the redundant pulse polling strategy. Zero-drive pulses are allocated sequentially, allowing different sub-modules to bear zero switching losses at different times, thus preventing any one sub-module from operating in a bypass position for extended periods. Simultaneously, the non-zero-level pulses exhibit a staggered distribution, with pulses from different sub-modules complementing each other in time. This corresponds to a voltage difference balancing strategy. By combining the capacitor voltage change from the previous cycle with the current capacitor voltage, the pulses are redistributed, ultimately resulting in the effect of alternating start and stop of sub-module pulses.

[0054] Figure 4 This is a waveform display of the pulse superposition of submodules in a modular multilevel resonant converter, specifically the sum of pulses from all submodules in the upper and lower arms of the converter. Each bridge arm has five submodules, one of which is redundant. Since each submodule within the bridge arm takes turns handling the zero pulse, meaning only four submodules are active at any given time, and only the redundant submodule is active, the superposition of the pulses from the five submodules results in a stepped wave. Furthermore, the stepped waves from the upper and lower arms are complementary.

[0055] Figure 5 The diagram shows a comparison of semiconductor device junction temperatures with and without redundant submodules. The converter design has 5 submodules in the upper arm, including 1 redundant submodule; the lower arm has 4 submodules and no redundant submodules. That is, the upper arm adopts the modular multilevel DC-DC converter optimization and control method based on dynamic redundancy and loss balancing provided by this invention, while the lower arm only adopts the voltage difference balancing control strategy. Under the same conditions, the junction temperatures of semiconductor devices are analyzed. The results show that the junction temperatures of semiconductor devices IGBT1 and IGBT2 in the upper arm are lower than those of semiconductor devices IGBT11 and IGBT12 in the lower arm. This verifies that the method of this invention can reduce device temperature, effectively alleviate thermal stress of the device, thereby extending device life and improving system reliability.

[0056] Figure 6 To determine the submodule capacitor voltage waveform using dynamic redundancy and loss balancing control methods, the converter input voltage is designed to be 3200V, with only 4 submodules conducting at any given time. Figure 6 As can be seen, the voltage of the submodule capacitors is concentrated around 800V, with very small fluctuations and the four voltage values ​​are very close, indicating that the dynamic redundancy and loss balancing control method provided by this invention can achieve precise voltage balancing of each submodule.

[0057] As can be seen, by dynamically adjusting the redundant positions and pulse dynamic adjustment, the loss and thermal stress of each sub-module are evenly distributed. This not only ensures that the voltage and current output characteristics of the converter remain unchanged, but also effectively reduces the thermal stress of the original sub-modules, significantly improving the operational reliability and overall lifespan of the modular multilevel DC-DC converter.

Claims

1. A method for optimizing control of a modular multilevel DC converter, characterized in that, It includes the following steps: S1: In each control period, according to a preset dynamic rotation strategy, select R sub-modules from the N sub-modules of each arm to configure as the redundant sub-modules of this period, and generate pulse signals with zero level for the redundant sub-modules to make them in a bypass state without switching actions within this period; S2: Real-time collect the capacitor voltages Vci of each sub-module. For non-redundant sub-modules, calculate the capacitor voltage change ΔVci(k) of each non-redundant sub-module compared with the previous control period; sort according to the current capacitor voltage values Vci of all non-redundant sub-modules respectively to generate a voltage sequence, and sort according to its capacitor voltage change ΔVci(k) to generate a voltage deviation sequence; S3: Establish a one-to-one mapping relationship between the voltage deviation sequence and the voltage sequence; reassign the original pulse signal corresponding to the j-th non-redundant sub-module in the voltage deviation sequence to the j-th non-redundant sub-module in the voltage sequence, where j = 1, 2, …, N - R; S4: Integrate the zero-level pulse signals of the redundant sub-modules in step S1 and the pulse signals of the non-redundant sub-modules after redistribution in step S3 to generate a final drive signal sequence corresponding to all sub-modules of the arm, and output the drive signal sequence to control the operation of the converter.

2. The method of claim 1, wherein, Before the start of each control period in step S1, perform an initialization operation, initialize the ranking index, and update the capacitor voltage of the sub-module and the switching state of the previous period.

3. The method of claim 1, wherein, The dynamic rotation strategy in step S1 is: according to the physical connection order of the sub-modules in the arm, sequentially and cyclically specify R continuously distributed sub-modules as the redundant sub-modules of the current period; when a rotation period ends, all N sub-modules are equally rotated into the redundant state at least once.

4. The method of claim 3, wherein, The number R of the redundant sub-modules in step S1 is determined according to the system reliability design index and cost constraint, and satisfies 1 ≤ R < N / 2; the upper and lower arms are configured with the same number of redundant sub-modules.

5. The method of claim 1, wherein, The calculation method of the capacitor voltage change ΔVci(k) in step S2 includes: at the end of each control period, record the instantaneous capacitor voltage value of each non-redundant sub-module; at the start of the next control period, calculate the difference between the voltage value and the recorded value of the previous period, and take it as the capacitor voltage change ΔVci(k); ΔVci(k) = |Vci(k) - Vci(k - 1)|, where Vci(k) and Vci(k - 1) respectively represent the capacitor voltage values of the k-th control period and the (k - 1)-th control period.

6. The method of claim 1, wherein, In step S2, sort in ascending order according to the current capacitor voltage values Vci of all non-redundant sub-modules to generate a voltage sequence, and sort in descending order according to its voltage change ΔVci(k) to generate a voltage deviation sequence.

7. A modular multilevel DC converter optimized control system, characterized in that, A system for implementing the method described in claim 1 includes: The dynamic redundancy configuration module is used to select R sub-modules from the N sub-modules of each bridge arm and configure them as redundant sub-modules for the current cycle according to the preset dynamic rotation strategy, and generate a zero-level pulse signal for the redundant sub-modules so that they are in a bypass state without switching action during the current cycle. The voltage status information processing module collects the capacitor voltage Vci of each sub-module in real time. For non-redundant sub-modules, it calculates the change in capacitor voltage ΔVci(k) of each non-redundant sub-module compared to the previous control cycle. The pulse sequence generation module sorts the current capacitor voltage values ​​Vci of all non-redundant sub-modules to generate voltage sequences, and sorts them according to their voltage change ΔVci(k) to generate voltage deviation sequences. The non-redundant pulse signal dynamic allocation module establishes a one-to-one mapping relationship between the voltage deviation sequence and the voltage sequence; it reassigns the original pulse signal corresponding to the j-th non-redundant sub-module in the voltage deviation sequence to the j-th non-redundant sub-module in the voltage sequence, where j=1, 2, …, NR. The drive signal synthesis and output module integrates the zero-level pulse signals of redundant submodules and the pulse signals of non-redundant submodules to generate the final drive signal sequence corresponding to all submodules of the bridge arm, and outputs the drive signal sequence to control the operation of the converter.

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