Method for overcoming synchronous phase shift defect of EPWM module in TICC2000 series DSP

Abstract

The invention provides a method for solving a synchronous phase shift defect of an EPWM (Enhanced Pulse Width Modulation) module in a TICC2000 series DSP (Digital Signal Processor), which is used for solving the technical problems that when a phase shift value of the EPWM module in the TICC2000 series DSP crosses a CMPA value or a CMPB value, the output of the EPWM module has a normally high or normally low defect, and the existing scheme of adding a direct connection prevention circuit can only relieve the normally high output defect of the EPWM module and cannot cope with the normally low output defect of the EPWM module. According to the method for solving the synchronous phase shift defect of the EPWM module in the TICC2000 series DSP, when a target phase shift value downwards crosses a CMP value, an active intervention strategy is adopted, the CMP value is temporarily set at a safe position through the safe position CMP value, so that the overturning action of an action restrictor triggers the overturning of a driving signal prior to the target phase shift value, and the synchronous phase shift defect of the EPWM module in the TICC2000 series DSP is overcome. Therefore, the driving signal can be normally increased or decreased; the strategy ensures that the driving signal can also be definitely overturned even when the phase is greatly adjusted, and the problem that the output of the EPWM module is normally high or normally low is effectively avoided.

Description

Technical Field

[0001] This invention relates to synchronous phase shifting, and more particularly to a method for solving the synchronous phase shifting defect of the EPWM module in the TI C2000 series DSP. Background Technology

[0002] Digital signal processors (DSPs) possess significant advantages in power electronics due to their high processing power, high-precision control (ADC and PWM), dedicated peripheral support, real-time performance and reliability (hardware protection mechanisms), flexibility, and programmability. Currently, in power electronics fields such as motor control, high-frequency digital switching power supplies, and grid-connected inverters, the TI C2000 series DSPs, such as the TMS chip, are primarily used. Examples of EPWM chips include 320F28035, TMS320F28335, TMS320F2812, TMS320F280049, TMS320F280039, and TMS320F28377. Taking the TMS320F28035 chip as an example, it includes two EPWM modules, denoted as EPWM1 ​​and EPWM2. The specific camera-shifting mechanism is as follows: each EPWM module has one synchronization input and one synchronization output. The synchronization input signal for EPWM2 comes from the synchronization output signal of EPWM1. Both EPWM modules can be configured to enable or ignore the synchronization input signal. When enabled and a synchronization input pulse is detected, the value of the phase register is automatically loaded into the CTR counter of the TB time base module. The direction of the CTR counter can be configured to increment or decrement. Action flipping mechanism: The TB time base module transmits the count value to the count comparison module. The count comparison module stores the CMPA and CMPB values. When the count comparison module compares the carrier counter's count value with the CMPA or CMPB value, it generates a pulse signal and transmits it to the action limiter (AQ). The action limiter synchronously receives two types of signals: one is the counting direction transmitted by the TB time base module, and the other is the pulse signal when the count value reaches zero and the period maximum value. Based on the set action, it flips the output level of the EPWM1 ​​and EPWM2 modules.

[0003] Currently, although the EPWM module in the TI C2000 series DSP supports a phase shift range of 0-180° and can flexibly configure the synchronization pulse to achieve precise phase shift, its phase shifting method has the following defects: when the phase shift value crosses the CMPA or CMPB values, the output of the EPWM module will exhibit a constant high or constant low output; when the EPWM module output is constantly high, the upper and lower bridge arms of the full bridge will shoot through, leading to damage to the power transistors; when the EPWM module output is constantly low, the upper and lower bridge arms of the full bridge will stop working, resulting in abnormal power supply output voltage and failure to operate normally. The current solution to this problem is to add an anti-shoot-through circuit, but this only alleviates the defect of a constantly high output of the EPWM module and cannot address the defect of a constantly low output. Summary of the Invention

[0004] The purpose of this invention is to solve the defect that the EPWM module in the TI C2000 series DSP will have a constant high or constant low output when the phase shift value crosses the CMPA or CMPB value. Existing solutions that add anti-shoot-through circuits can only alleviate the constant high output defect of the EPWM module, but cannot solve the technical problem of its constant low output defect. This invention provides a method to solve the synchronous phase shift defect of the EPWM module in the TI C2000 series DSP.

[0005] To achieve the above objectives, the inventive concept of this invention is as follows: First, analyze the reasons for the EPWM module's output signal being constantly high or low: such as Figure 1 The diagram shows a full-bridge LLC topology. Switches Q1 and Q3 form the leading arm, and switches Q2 and Q4 form the lagging arm. The two outputs EPWM1A and EPWM1B of the EPWM1 ​​module drive switches Q3 and Q1, respectively. The two outputs EPWM2A and EPWM2B of the EPWM2 module drive switches Q4 and Q2, respectively. Figure 2 The diagram shows a shadow register mode where the driving carrier is a triangular carrier, and EPWM1A, EPWM1B, EPWM2A, and EPWM2B are updated when the CTR counter value is 0. The phase shift is implemented by keeping the driving carrier of the leading arm fixed, while the driving carrier of the lagging arm shifts to the left until it is in phase with the driving carrier of the leading arm. The phase shift value of the EPWM2 module takes effect when the CTR counter of the EPWM1 ​​module returns to zero. During testing, when the phase shift value of the EPWM2 module crosses the CMPA or CMPB value, the outputs of EPWM2A and EPWM2B exhibit abnormally high or low values.

[0006] like As shown, when the phase shift value of the fill is greater than the CMPA value, the process of the CTR counter decrementing to 0 will pass through the CMPA value, and the toggle event will occur normally. At this time, the pulse width of EPWM2B will become wider. When the phase shift value of the fill is less than the CMPA value, the process of the CTR counter decrementing to 0 will not pass through the CMPA value, and the toggle event will not occur. At this time, EPWM2B will maintain the high level state of the previous moment, causing the output of the EPWM module to be constantly high.

[0007] In summary, the fundamental reason why the output is constantly high or low during the phase shifting process of the EPWM module is that when a new value is directly loaded through the synchronization signal to change the instantaneous phase of the CTR counter, if the loaded count value skips the CMPA or CMPB value of the current cycle, the counting comparison module will not be able to generate a matching event of CTR=CMP. Consequently, the action limiter will not receive the expected flip pulse, and the output signal will remain in its original state and will not flip normally, maintaining the high or low level state of the previous moment.

[0008] Based on the above analysis, when the target phase shift value crosses the CMPA or CMPB value downwards, the present invention temporarily sets the CMPA or CMPB value to a safe position by using the safe position CMP value, so that the flipping action of the action limiter takes precedence over the target phase shift value to trigger the flipping of the drive signal to achieve phase shift, thereby ensuring that the drive signal is pulled up or down normally.

[0009] To achieve the above-mentioned technical concept, the present invention provides the following technical solution: A method for resolving the synchronous phase-shifting defect of the EPWM module in the TI C2000 series DSP, wherein the EPWM1 ​​and EPWM2 modules are configured in shadow register mode, and the parameter values ​​in the period register and the count comparison module are loaded when the CTR counter count value is 0; the method is characterized by including the following steps: Step 1: Initialize the default values ​​for phase shift and CMP values; Step 2: Calculate the target phase shift value based on the power control loop; Step 3: Determine whether the CMP value of the current cycle in the EPWM2 module is between the phase shift value of the current cycle and the target phase shift value calculated in Step 2. If yes, proceed to Step 4; otherwise, proceed to Step 5. Step 4: Update the CMP value of the current cycle to the safe position CMP value and fill it in; after the updated CMP value takes effect, update the phase shift value of the current cycle to the target phase shift value and fill it in; after the updated phase shift value and CMP value take effect, restore the CMP value to the default value and fill it in; after the filling takes effect, return to Step 2 to process the synchronous phase shift of the next cycle. Step 5: Keep the CMP value of the current cycle unchanged, update the phase shift value of the current cycle to the target phase shift value and fill it in; after the CMP value and phase shift value filling take effect, return to step 2 to process the synchronous phase shift of the next cycle.

[0010] Furthermore, in steps 1 to 5, the CMP value is either the CMPA value or the CMPB value.

[0011] Further, in step 4, the safe position CMP value = the phase shift value of the current cycle + the fixed offset; Alternatively, the safe position CMP value = the phase shift value of the current period + (PRD - the phase shift value of the current period) / 2, where PRD represents the peak value of the triangular carrier. Alternatively, the safe position CMP value = the phase shift value of the current cycle + 10% * PRD.

[0012] Meanwhile, this invention also provides another method to solve the synchronous phase shift defect of the EPWM module in the TI C2000 series DSP. The EPWM1 ​​module is configured in shadow register mode, and the parameter values ​​in the period register and the count comparison module are loaded when the CTR counter count value is 0; the EPWM2 module directly loads the parameter values ​​in the period register and the count comparison module; its special feature is that it includes the following steps: Step 1: Initialize the default values ​​for phase shift and CMP values; Step 2: Calculate the target phase shift value based on the power control loop; Step 3: Determine whether the CMP value of the current cycle in the EPWM2 module is between the phase shift value of the current cycle and the target phase shift value. If yes, proceed to step 4; otherwise, proceed to step 5. Step 4: When the target phase shift value crosses the CMP value of the current cycle, during the falling edge of the current triangular carrier of the EPWM1 ​​module, and before the CTR counter of the EPWM2 module decrements to the phase shift value of the current cycle, the CMP value of the current cycle is updated to the safe position CMP value, and the phase shift value of the current cycle is updated to the target phase shift value. The updated CMP value and phase shift value are then filled. After the filling of the CMP value and phase shift value takes effect, during the falling edge of the next triangular carrier of the EPWM1 ​​module, and before the CTR counter of the EPWM2 module decrements to the safe position CMP value, the CMP value is restored to the default value and filled. After the filling takes effect, return to Step 2 to process the synchronous phase shift of the next cycle. Step 5: Keep the CMP value of the current cycle unchanged, update the phase shift value of the current cycle to the target phase shift value and fill it in; after the CMP value and phase shift value filling take effect, return to step 2 to process the synchronous phase shift of the next cycle.

[0013] Furthermore, in steps 1 to 5, the CMP value is either the CMPA value or the CMPB value.

[0014] Further, in step 4, the safe position CMP value = the phase shift value of the current cycle + the fixed offset; Alternatively, the safe position CMP value = the phase shift value of the current period + (PRD - the phase shift value of the current period) / 2, where PRD represents the peak value of the triangular carrier. Alternatively, the safe position CMP value = the phase shift value of the current cycle + 10% * PRD.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The method provided by this invention for solving the synchronous phase shift defect of the EPWM module in the TI C2000 series DSP adopts an active intervention strategy when the target phase shift value crosses the CMPA or CMPB value downward. By temporarily setting the CMPA or CMPB value to a safe position through the safe position CMP value, the flipping action of the action limiter takes precedence over the target phase shift value to trigger the flipping of the drive signal, so as to ensure that the drive signal is pulled high or low normally. This strategy ensures that even when the phase is adjusted significantly, the drive signal can flip deterministically, effectively avoiding the problem of constant high or low output of the EPWM module, thereby avoiding the risk of shoot-through damage to power devices in the upper and lower bridge arms, improving the reliability of phase shift of the EPWM module in the TI C2000 series DSP, and thus improving the stability and reliability of the power supply system.

[0016] 2. Compared with the solution of adding anti-shoo-through circuit, the present invention not only solves the problem of constant high and constant low output of EPWM module through software optimization, but also saves a lot of hardware costs.

[0017] 3. The present invention provides two methods for solving the synchronous phase shift defect. One method is complex and requires consideration of timing issues, but has a wide range of applications. The other method is simple but limited to fixed-frequency phase shift. The two methods can be adapted to different applications. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a full-bridge LLC topology; Figure 2 A schematic diagram of the phase-shifting power transistor drive for a full-bridge LLC topology; Figure 3 This diagram illustrates how the output of the EPWM2 module becomes constantly high when the phase shift value of the EPWM2 module crosses the CMPA or CMPB values ​​in a TI C2000 series DSP. Figure 4This is a flowchart of a first embodiment of the method for solving the synchronous phase shift defect of the EPWM module in the TI C2000 series DSP according to the present invention; Figure 5 This is a schematic diagram illustrating the driving mechanism for solving phase-shifting defects according to Embodiment 1 of the present invention; Figure 6 This is a schematic diagram illustrating the driving mechanism for solving phase-shifting defects according to Embodiment 2 of the present invention. Detailed Implementation

[0019] To make the advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0020] Example 1 In this embodiment, the EPWM1 ​​and EPWM2 modules are configured in shadow register mode, and the parameter values ​​in the period register and the count comparison module are loaded when the CTR counter count value is 0. Figure 4 As shown, the method proposed in this embodiment for solving the synchronous phase shift defect of the EPWM module in the TI C2000 series DSP specifically includes the following steps: Step 1: Initialize the default values ​​for the phase shift value and CMPA value.

[0021] Step 2: Calculate the target phase shift value based on the power control loop.

[0022] Step 3, as follows Figure 5 As shown, determine whether the CMPA value of the current cycle in the EPWM2 module is between the phase shift value of the current cycle and the target phase shift value. If yes, it means that the target phase shift value has crossed the CMPA value of the current cycle, and then proceed to step 4. Otherwise, it means that the target phase shift value has not crossed the CMPA value of the current cycle, and then proceed to step 5.

[0023] Step 4: When the target phase shift value crosses the CMPA value of the current cycle, update the CMPA value of the current cycle to the safe position CMP value and fill it; after the updated CMPA value takes effect, update the phase shift value of the current cycle to the target phase shift value and fill it; after the updated phase shift value and CMPA value take effect, restore the CMPA value to the default value and fill it. After the filling takes effect, the phase shift crossing of the current cycle is completed. At this time, return to step 2 to process the synchronous phase shift of the next cycle.

[0024] Step 5: When the target phase shift value does not cross the CMPA value of the current cycle, keep the CMPA value of the current cycle unchanged, update the phase shift value of the current cycle to the target phase shift value and fill it in; after the CMPA value and phase shift value filling take effect, the EPWM2B of the EPWM2 module will maintain the high-level state or low-level state of the previous moment. At this time, return to step 2 to process the synchronous phase shift of the next cycle.

[0025] The safe position CMP value in step 4 of this invention needs to be calculated based on the counting direction of the triangular carrier and the driving flip direction of the two EPWM modules, such as... Figure 5 As shown, the phase shift of the EPWM2 module occurs at the falling edge of its triangular carrier count. The flip action of EPWM2B at CMPA is to pull it low, so its safe position is between the peak value of the triangular carrier and the phase shift value of the current cycle.

[0026] The calculation strategy for the CMP value capacitance at the safe location in this invention includes the following three methods: (1) Fixed offset: Safe position CMP value = phase shift value of the current cycle + fixed offset; (2) Midpoint: Safe position CMP value = phase shift value of the current period + (PRD - phase shift value of the current period) / 2, where PRD represents the peak value of the triangular carrier, which is the maximum count value of the CTR counter; (3) Percentage offset: Safe position CMP value = phase shift value of the current cycle + 10% * PRD.

[0027] Among them, the fixed offset strategy is simple, but the selection of the fixed offset needs to be tested in practice to avoid the problem that the function cannot be implemented due to the fixed offset being too small; the midpoint strategy is simple to calculate, has strong versatility, and can trigger 100% with high reliability; the percentage offset strategy is similar to the fixed offset strategy, but its advantage is that it can adapt to the changes in the peak value of the triangular carrier and has stronger adaptability in frequency conversion work.

[0028] It is worth noting that in this embodiment, synchronous phase shifting is performed using the CMPA value. In other embodiments, synchronous phase shifting can also be performed using the CMPB value. Either one can be chosen.

[0029] Example 2 In this embodiment, the EPWM1 ​​module is configured in shadow register mode, and loads the parameter values ​​from the period register (PRD) and the count comparison module when the CTR counter count value is 0; the EPWM2 module does not use a shadow register, and directly loads the parameter values ​​from the period register (PRD) and the count comparison module. The method for solving the synchronous phase shift defect of the EPWM module in the TI C2000 series DSP in this embodiment specifically includes the following steps: Step 1: Initialize the default values ​​for the phase shift value and CMPA value.

[0030] Step 2: Calculate the target phase shift value based on the power control loop.

[0031] Step 3, as follows Figure 6As shown, determine whether the CMPA value of the current cycle in the EPWM2 module is between the phase shift value of the current cycle and the target phase shift value. If yes, it means that the target phase shift value has crossed the CMPA value of the current cycle, and then proceed to step 4. Otherwise, it means that the target phase shift value has not crossed the CMPA value of the current cycle, and then proceed to step 5.

[0032] Step 4: When the target phase shift value crosses the CMPA value of the current cycle, during the falling edge of the triangular carrier wave in the EPWM1 ​​module, and before the CTR counter of the EPWM2 module decrements to the phase shift value of the current cycle, the CMPA value of the current cycle is updated to the safe position CMP value. Simultaneously, the phase shift value of the current cycle is updated to the target phase shift value, and the updated CMPA and phase shift values ​​are filled. After the CMPA and phase shift values ​​are filled and take effect, during the next falling edge of the triangular carrier wave in the EPWM1 ​​module, and before the CTR counter of the EPWM2 module decrements to the safe position CMP value, the CMPA value is restored to its default value and filled. After the filling takes effect, the phase shift crossing is completed. At this point, return to Step 2 to process the synchronous phase shift of the next cycle.

[0033] Step 5: When the target phase shift value does not cross the CMPA value of the current cycle, keep the CMPA value of the current cycle unchanged, update the phase shift value of the current cycle to the target phase shift value and fill it in; after the CMPA value and phase shift value filling take effect, the EPWM2B of the EPWM2 module will maintain the high-level state or low-level state of the previous moment. At this time, return to step 2 to process the synchronous phase shift of the next cycle.

[0034] The method in Example 2 eliminates the need to consider the timing issues of updating CMPA and phase shift values. However, this method is only applicable to control schemes with fixed drive frequencies, i.e., the peak value PRD of the EPWM triangular carrier is fixed. If a control scheme with varying frequencies is used, i.e., the peak value PRD of the EPWM triangular carrier varies, the method in Example 1 should be considered.

[0035] This invention addresses the issue of constantly high or low outputs in the EPWM module when the phase shift value crosses the CMPA or CMPB values. It employs an active intervention strategy: when the target phase shift value crosses the CMPA or CMPB values ​​downwards, a safe position (CMP) is temporarily set to a safe position for the CMPA or CMPB values. This ensures that the flipping action of the action limiter takes precedence over the flipping of the drive signal triggered by the target phase shift value, effectively avoiding the constantly high or low output problem of the EPWM module. This also mitigates the risk of shoot-through damage to power devices from the upper and lower bridge arms, improving the reliability of phase shifting in the EPWM module of the TI C2000 series DSP.

[0036] The above description is only used to illustrate the technical solutions of the present invention, and is not intended to limit them. For those skilled in the art, modifications can be made to the specific technical solutions described in the above embodiments, or equivalent substitutions can be made to some of the technical features. However, these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions protected by the present invention.

Claims

1. A method for resolving the synchronous phase shift defect of the EPWM module in the TI C2000 series DSP, wherein the EPWM1 ​​and EPWM2 modules are configured in shadow register mode, and the parameter values ​​in the period register and the count comparison module are loaded when the CTR counter count value is 0; characterized in that, Includes the following steps: Step 1: Initialize the default values ​​for phase shift and CMP values; Step 2: Calculate the target phase shift value based on the power control loop; Step 3: Determine whether the CMP value of the current cycle in the EPWM2 module is between the phase shift value of the current cycle and the target phase shift value calculated in Step 2. If yes, proceed to Step 4; otherwise, proceed to Step 5. Step 4: Update the CMP value of the current cycle to the safe position CMP value and fill it in; after the updated CMP value takes effect, update the phase shift value of the current cycle to the target phase shift value and fill it in; after the updated phase shift value and CMP value take effect, restore the CMP value to the default value and fill it in; after the filling takes effect, return to Step 2 to process the synchronous phase shift of the next cycle. Step 5: Keep the CMP value of the current cycle unchanged, update the phase shift value of the current cycle to the target phase shift value and fill it in; after the CMP value and phase shift value filling take effect, return to step 2 to process the synchronous phase shift of the next cycle.

2. The method for solving the synchronous phase shift defect of the EPWM module in the TI C2000 series DSP according to claim 1, characterized in that: In steps 1 to 5, the CMP value is either the CMPA value or the CMPB value.

3. The method for solving the synchronous phase shift defect of the EPWM module in the TI C2000 series DSP according to claim 2, characterized in that: In step 4, the safe position CMP value = the phase shift value of the current cycle + the fixed offset; Alternatively, the safe position CMP value = the phase shift value of the current period + (PRD - the phase shift value of the current period) / 2, where PRD represents the peak value of the triangular carrier. Alternatively, the safe position CMP value = the phase shift value of the current cycle + 10% * PRD.

4. A method for resolving the synchronous phase-shifting defect of the EPWM module in the TI C2000 series DSP, wherein the EPWM1 ​​module is configured in shadow register mode, and loads the parameter values ​​in the period register and the count comparison module when the CTR counter count value is 0; the EPWM2 module directly loads the parameter values ​​in the period register and the count comparison module; characterized in that, Includes the following steps: Step 1: Initialize the default values ​​for phase shift and CMP values; Step 2: Calculate the target phase shift value based on the power control loop; Step 3: Determine whether the CMP value of the current cycle in the EPWM2 module is between the phase shift value of the current cycle and the target phase shift value. If yes, proceed to step 4; otherwise, proceed to step 5. Step 4: When the target phase shift value crosses the CMP value of the current cycle, during the falling edge of the current triangular carrier of the EPWM1 ​​module, and before the CTR counter of the EPWM2 module decrements to the phase shift value of the current cycle, the CMP value of the current cycle is updated to the safe position CMP value, and the phase shift value of the current cycle is updated to the target phase shift value. The updated CMP value and phase shift value are then filled. After the filling of the CMP value and phase shift value takes effect, during the falling edge of the next triangular carrier of the EPWM1 ​​module, and before the CTR counter of the EPWM2 module decrements to the safe position CMP value, the CMP value is restored to the default value and filled. After the filling takes effect, return to Step 2 to process the synchronous phase shift of the next cycle. Step 5: Keep the CMP value of the current cycle unchanged, update the phase shift value of the current cycle to the target phase shift value and fill it in; after the CMP value and phase shift value filling take effect, return to step 2 to process the synchronous phase shift of the next cycle.

5. The method for solving the synchronous phase shift defect of the EPWM module in the TI C2000 series DSP according to claim 4, characterized in that: In steps 1 to 5, the CMP value is either the CMPA value or the CMPB value.

6. The method for solving the synchronous phase shift defect of the EPWM module in the TI C2000 series DSP according to claim 5, characterized in that: In step 4, the safe position CMP value = the phase shift value of the current cycle + the fixed offset; Alternatively, the safe position CMP value = the phase shift value of the current period + (PRD - the phase shift value of the current period) / 2, where PRD represents the peak value of the triangular carrier. Alternatively, the safe position CMP value = the phase shift value of the current cycle + 10% * PRD.

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