Constant on-time generating circuit with delay compensation

Abstract

The invention provides a constant on-time generation circuit with delay compensation, which is suitable for a DC-DC controller in a self-adaptive constant on-time control mode, and belongs to the technical field of integrated circuit design. According to the technical scheme, the charging current of the capacitor is mirrored through one circuit, the voltage of the charging branch and the voltage of the output voltage branch are respectively adjusted through the two compensation resistors, and the adjusted voltage is respectively supplied to the in-phase comparison end and the reverse-phase comparison end of the comparator. By means of the mode, time delay caused by the comparator in the DC-DC controller in the constant on-time control mode can be effectively compensated, the constant on-time TON is more accurate, the problem that the working frequency is unstable when input / output voltage fluctuates due to the time delay of the comparator is effectively solved, meanwhile, resistance matching can be achieved on the layout, and the reliability of the DC-DC controller in the constant on-time control mode is improved. Deviation caused by mismatch at different process corners is reduced, and stable work can be maintained at different process corners.

Description

Technical Field

[0001] This invention belongs to the field of circuit design, and in particular relates to a constant on-time generation circuit with delay compensation. Background Technology

[0002] Power management integrated circuits (PMICs) are an important component of electronic products. DC-DC controllers are widely used in various electronic products due to their advantages such as high efficiency, flexible input / output voltage range, and high integration. The mainstream control methods include traditional PWM (Pulse Width Modulation), PSM (Pulse Frequency Hopping Modulation), and PFM (Pulse Frequency Modulation). Among them, constant-on-time (COT) control mode, as a control method of PFM, has the advantages of high efficiency under light load, fast transient response, and low static power consumption.

[0003] In common COT implementations, the Buck operating frequency is f. sw =D / T ON This causes the operating frequency to fluctuate sharply with changes in the duty cycle, thus leading to the development of an adaptive constant on-time control method to achieve a constant on-time. The on-time is directly proportional to the duty cycle (i.e., directly proportional to the output voltage) and inversely proportional to the input voltage, thus stabilizing the operating frequency. A constant on-time is typically achieved by charging a capacitor with a comparison voltage to generate this constant on-time. .

[0004] However, since the actual components of the control loop will all experience some delay during signal transmission, especially the comparator's delay T... d T cannot be ignored ON Delayed delivery, for example Figure 2 The impact of the COT system shown is reflected in the actual constant conduction time T. ON_real Slightly longer than the required constant on-time This delay slows down the frequency, and in the input and output voltage combinations, it will produce different degrees of amplitude error. The actual switching frequency is still unstable, so it is necessary to compensate for the delay to improve the system stability and accuracy. Summary of the Invention

[0005] The main technical problem solved by this invention is to provide a constant on-time generation circuit with delay compensation, which can effectively solve the problem of system frequency instability caused by a series of delays such as comparators in DC-DC controllers under ACOT control mode.

[0006] The technical solution of the present invention is as follows: a constant on-time generation circuit with delay compensation, comprising: a charging current generation circuit, a capacitor charging and discharging circuit, a comparator delay compensation circuit, and a constant on-time generation circuit; The charging current generating circuit is connected to the input voltage V. IN The charging current generating circuit is connected to the capacitor charging and discharging circuit, the capacitor charging and discharging circuit is connected to the comparator delay compensation circuit and the constant conduction time generating circuit, and the comparator delay compensation circuit is connected to the constant conduction time generating circuit. The charging current generating circuit is used to generate a current that is related to the input voltage V. IN A proportional charging current is input to the capacitor charging and discharging circuit and the comparator delay compensation circuit; The capacitor charging and discharging circuit is used to charge the capacitor C according to the charging current, generate a triangular wave voltage, and output it to the constant conduction time generation circuit. The comparator delay compensation circuit is used to generate an output voltage V based on the charging current. OUT and the output voltage V OUT Step-down, the output voltage V after step-down OUT The input is given to the constant on-time generation circuit; The constant on-time generation circuit is used to generate the output voltage V after step-down. OUT The triangular wave voltage generates the output signal Duty, which controls the charging interval of capacitor C. The capacitor charging and discharging circuit is used to control the charging frequency of capacitor C according to the output signal Duty.

[0007] Furthermore, the charging current generating circuit includes: a voltage divider network, an amplifier A, a first MOSFET M1, a second MOSFET M2, and a grounding resistor R. The voltage divider network is connected to the input voltage V. IN The non-inverting input of amplifier A is connected to a voltage divider network. The source of the second MOSFET M2 is connected to the operating voltage VDD. The gate of the second MOSFET M2 is connected to the capacitor charging and discharging circuit. The drain of the second MOSFET M2 is connected to the drain of the first MOSFET M1. The gate of the first MOSFET M1 is connected to the output of amplifier A. The drain of the first MOSFET M1 is connected to the negative input of amplifier A and one end of the grounding resistor R. The other end of the grounding resistor R is grounded.

[0008] Furthermore, the voltage divider network includes a first voltage divider resistor R1 and a second voltage divider resistor R2, with one end of the first voltage divider resistor R1 connected to the input voltage V. IN The other end is connected to the non-inverting input of amplifier A and one end of the second resistor R2, and the other end of the second resistor R2 is grounded.

[0009] Further, the capacitor charging and discharging circuit includes: a third MOSFET M3, a first compensation resistor Rc1, a capacitor C, and a fifth MOSFET M5. The source of the third MOSFET M3 is connected to the operating voltage VDD. The gate of the third MOSFET is connected to the gate of the second MOSFET M2 and the comparator delay compensation circuit. The drain of the third MOSFET is connected to one end of the first compensation resistor Rc1 and the constant on-time generation circuit. The other end of the first compensation resistor Rc1 is connected to the drain of the fifth MOSFET M5 and one end of the capacitor C. The other end of the capacitor C is grounded. The source of the fifth MOSFET M5 is grounded. The gate of the fifth MOSFET M5 is connected to the constant on-time generation circuit.

[0010] Furthermore, the comparator delay compensation circuit includes a fourth MOSFET M4, a sixth MOSFET M6, a seventh MOSFET M7, and a second compensation resistor Rc2. The source of the fourth MOSFET M4 is connected to the operating voltage VDD, the gate of the fourth MOSFET M4 is connected to the gate of the third MOSFET, the drain of the fourth MOSFET M4 is connected to the drain and gate of the sixth MOSFET M6 and the gate of the seventh MOSFET M7, the source of the sixth MOSFET M6 is grounded, the source of the seventh MOSFET M7 is grounded, and the drain of the seventh MOSFET M7 is connected to one end of the second compensation resistor Rc2. The other end of the second compensation resistor Rc2 is connected to a constant on-time generation circuit.

[0011] Furthermore, the comparator, RS flip-flop, and inverter are configured such that the non-inverting input of the comparator is connected to one end of the first compensation resistor Rc1, the inverting input of the comparator is connected to the other end of the second compensation resistor Rc2, the output of the comparator is connected to the reset input R of the RS flip-flop, the set input S of the RS flip-flop is connected to the external V_CMP signal, the positive output Q of the RS flip-flop is connected to the input of the inverter, and the output of the inverter is connected to the gate of the fifth MOS transistor M5.

[0012] The beneficial effects of this invention are as follows: This invention uses a circuit to mirror the charging current of a capacitor, and two compensation resistors to adjust the voltages of the charging branch and the output voltage branch, respectively. The adjusted voltages are then supplied to the non-inverting and inverting comparison terminals of the comparator. Through this method, this invention can effectively compensate for the delay caused by the comparator in a constant on-time control mode DC-DC controller, thus ensuring a constant on-time... It is more accurate and effectively corrects the problem of unstable operating frequency caused by input / output voltage fluctuations due to comparator delay. At the same time, it can achieve resistor matching on the layout, reduce the deviation caused by mismatch at different process corners, and maintain stable operation at different process corners. Attached Figure Description

[0013] Figure 1 This is a specific circuit diagram of a constant on-time generation circuit with delay compensation according to the present invention.

[0014] Figure 2 This is a structural diagram of an adaptive constant on-time control mode DC-DC buck converter (ACOT Buck) to which this invention applies.

[0015] Figure 3 These are waveforms of important signals when the ACOT Buck DC-DC controller is working in this invention.

[0016] Figure 4 This is a comparison diagram of the effects of a constant conduction time in this invention. Detailed Implementation

[0017] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. The described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0018] In the technical solution of the invention Figure 1 This is a schematic diagram of the specific structure of a constant on-time generation circuit with delay compensation according to the present invention, as shown below. Figure 1 As shown, the present invention includes: a charging current generating circuit 1, a capacitor charging and discharging circuit 2, a comparator delay compensation circuit 3, and a constant conduction time generating circuit 4.

[0019] The charging current generating circuit 1 is connected to the input voltage V. IN The charging current generating circuit 1 is connected to the capacitor charging and discharging circuit 2. The capacitor charging and discharging circuit 2 is connected to the comparator delay compensation circuit 3 and the constant conduction time generating circuit 4. The comparator delay compensation circuit 3 is connected to the constant conduction time generating circuit 4.

[0020] The charging current generating circuit 1 is used to generate current related to the input voltage V. IN A proportional charging current is input to the capacitor charging and discharging circuit 2 and the comparator delay compensation circuit 3.

[0021] The capacitor charging and discharging circuit 2 is used to charge the capacitor C according to the charging current, generate a triangular wave voltage, and output it to the constant conduction time generating circuit 4.

[0022] The comparator delay compensation circuit 3 is used to generate an output voltage V based on the charging current. OUTand the output voltage V OUT Step-down, the output voltage V after step-down OUT The input is given to the constant on-time generation circuit 4.

[0023] The constant on-time generation circuit 4 is used to generate the output voltage V after step-down. OUT The triangular wave voltage generates the output signal Duty, which controls the charging interval of capacitor C.

[0024] The capacitor charging and discharging circuit 2 is used to control the charging frequency of capacitor C according to the output signal Duty.

[0025] Specifically, the charging current generating circuit 1 is used to generate a current that is related to the input voltage V. IN The charging current is proportional to the input voltage V. IN After voltage division by resistors, a charging current proportional to the input voltage is generated by amplifier A and NMOS transistor M1 connected to the common source. This current is then mirrored to the capacitor charging and discharging circuit 2 by current mirrors M2 and M3. The capacitor charging and discharging circuit 2 charges the capacitor C through the compensation resistor Rc1. The triangular wave generated by the charging is output to the non-inverting input of the comparator 41 in the constant on-time generation circuit 4. The switching NMOS transistor M5 that controls the charging and discharging of the capacitor C is controlled by the output signal Duty of the constant on-time generation circuit 4. The comparator delay compensation circuit 3 mirrors the charging current of M2, M4, M6, and M7 to the compensation resistor Rc2 via a current mirror, and outputs a voltage V. OUT After subtracting the voltage drop across the compensation resistor Rc2, the output is sent to the inverting input of comparator 41 in the constant on-time generation circuit 4; The signal generated by comparator 41 in the constant on-time generation circuit 4 is the constant on-time T. ON The signal output to the reset terminal of RS flip-flop 42 pulls down the duty cycle signal Duty. When the duty cycle signal Duty is reset, it is inverted by inverter 43 and then controls the switching NMOS transistor M5 in the capacitor charging and discharging circuit 2 to turn on, thereby discharging capacitor C to obtain a constant on-time T. ON .

[0026] The constant on-time generation circuit for a switching power supply with constant on-time control includes a charging current generation circuit 1, a capacitor charging and discharging circuit 2, a comparator delay compensation circuit 3, and a constant on-time generation circuit 4; wherein the current generation circuit generates current through amplifier A and the first MOSFET M1, which is related to the input voltage V. INThe proportional charging current is mirrored to the capacitor charging and discharging circuit 2 via a current mirror. The comparator delay compensation circuit adjusts the voltage of the charging branch and the output voltage branch respectively through two compensation resistors. The adjusted voltages are then supplied to the non-inverting and inverting comparison terminals of comparator 41 in the constant conduction time generation circuit 4, thereby generating a constant conduction time signal after delay compensation. Finally, the charging and discharging of the capacitor is controlled by RS flip-flop 42 and inverter 43.

[0027] Figure 2 This application describes the structure of an adaptive constant on-time control mode DC-DC buck controller. The constant on-time control DC-DC buck controller has a steady-state duty cycle of: The switching frequency during operation is: If a constant delay is used, the steady-state operating frequency will vary with the input voltage V. IN and output voltage V OUT Fluctuations require a constant on-time T to achieve a fixed frequency. ON With V IN and V OUT Adaptive regulation means that it is inversely proportional to the input voltage and directly proportional to the output voltage.

[0028] In one embodiment of the present invention, the charging current generating circuit 1 includes: a voltage divider network, an amplifier A, a first MOSFET M1, a second MOSFET M2, and a grounding resistor R. The voltage divider network is connected to the input voltage V. IN The non-inverting input of amplifier A is connected to a voltage divider network. The source of the second MOSFET M2 is connected to the operating voltage VDD. The gate of the second MOSFET M2 is connected to the capacitor charging and discharging circuit 2. The drain of the second MOSFET M2 is connected to the drain of the first MOSFET M1. The gate of the first MOSFET M1 is connected to the output of amplifier A. The drain of the first MOSFET M1 is connected to the negative input of amplifier A and one end of the grounding resistor R. The other end of the grounding resistor R is grounded.

[0029] The voltage divider network includes a first voltage divider resistor R1 and a second voltage divider resistor R2, with one end of the first voltage divider resistor R1 connected to the input voltage V. IN The other end is connected to the non-inverting input of amplifier A and one end of the second resistor R2, and the other end of the second resistor R2 is grounded.

[0030] Among them, the first MOS transistor M1 is an NMOS transistor, and the second MOS transistor M2 is a PMOS transistor.

[0031] Input voltage V INVDD is the external input voltage of the DC-DC controller, while VDD is the internal operating voltage supplied by the controller. The amplifier connected with unity negative feedback stabilizes the voltage at the inverting input to the input voltage at the non-inverting input, thereby generating a charging current. The magnitude of the charging current is: ,

[0032] In one embodiment of the present invention, the capacitor charging and discharging circuit 2 includes: a third MOSFET M3, a first compensation resistor Rc1, a capacitor C, and a fifth MOSFET M5. The source of the third MOSFET M3 is connected to the operating voltage VDD. The gate of the third MOSFET is connected to the gate of the second MOSFET M2 and the comparator delay compensation circuit 3. The drain of the third MOSFET is connected to one end of the first compensation resistor Rc1 and the constant on-time generation circuit 4. The other end of the first compensation resistor Rc1 is connected to the drain of the fifth MOSFET M5 and one end of the capacitor C. The other end of the capacitor C is grounded. The source of the fifth MOSFET M5 is grounded. The gate of the fifth MOSFET M5 is connected to the constant on-time generation circuit 4.

[0033] Among them, the third MOSFET M3 is a PMOS transistor, and the fifth MOSFET M5 is an NMOS transistor.

[0034] PMOS transistors M2, M3, and M4 form a current mirror in a proportional configuration. M3 mirrors the charging current Ichg generated by the charging current generation circuit 1 to the capacitor charging and discharging circuit 2. This current generates a voltage drop through the compensation resistor Rc1, which, when superimposed on the capacitor charging voltage, is connected to the positive comparison terminal of comparator 41 in the comparator delay compensation circuit 4. When the charging time is t, the magnitude of this voltage is: , In one embodiment of the present invention, the comparator delay compensation circuit 3 includes a fourth MOSFET M4, a sixth MOSFET M6, a seventh MOSFET M7, and a second compensation resistor Rc2. The source of the fourth MOSFET M4 is connected to the operating voltage VDD, the gate of the fourth MOSFET M4 is connected to the gate of the third MOSFET, the drain of the fourth MOSFET M4 is connected to the drain and gate of the sixth MOSFET M6 and the gate of the seventh MOSFET M7, the source of the sixth MOSFET M6 is grounded, the source of the seventh MOSFET M7 is grounded, and the drain of the seventh MOSFET M7 is connected to one end of the second compensation resistor Rc2. The other end of the second compensation resistor Rc2 is connected to the constant on-time generation circuit 4.

[0035] Among them, the fourth MOSFET M4 is a PMOS transistor, and the sixth MOSFET M6 and the seventh MOSFET M7 are NMOS transistors.

[0036] After the charging current Ichg is mirrored by the PMOS transistor M4, the NMOS transistors M6 and M7 compensate Ichg to an output voltage V. OUT Related branch, V OUT The voltage drop across the superimposed compensation resistor Rc2 is then connected to the inverting comparison terminal of comparator 41 in comparator delay compensation circuit 4. The magnitude of this voltage is: , In one embodiment of the present invention, a comparator 41, an RS flip-flop 42, and an inverter 43 are included. The non-inverting input of the comparator 41 is connected to one end of the first compensation resistor Rc1, and the inverting input of the comparator 41 is connected to the other end of the second compensation resistor Rc2. The output of the comparator 41 is connected to the reset input R of the RS flip-flop 42. The set input S of the RS flip-flop 42 is connected to an external V_CMP signal. The positive output Q of the RS flip-flop 42 is connected to the input of the inverter 43, and the output of the inverter 43 is connected to the gate of the fifth MOS transistor M5.

[0037] The signal output by the comparator is the constant on-time signal T. ON The comparator delay is T. d V_CMP is a control signal generated by comparing the feedback voltage with the reference voltage in a DC-DC controller with constant on-time control. When the feedback voltage is greater than the reference voltage, this signal is 0; when the feedback voltage is less than the reference voltage, this signal is 1, which sets the output Q of the RS flip-flop, thereby raising the duty cycle signal Duty to control the switching transistor to adjust the voltage.

[0038] V_CMP is the control signal generated by comparing the feedback voltage with the reference voltage in the adaptive constant on-time control DC-DC controller. When the feedback voltage is lower than the reference voltage, this signal is set to a high duty cycle signal (Duty), which simultaneously pulls down the gate of the NMOS switch M5 in capacitor charging / discharging circuit 2, and the capacitor begins to charge. After a constant on-time T... ON After resetting the duty cycle signal Duty, refer to the specific working logic. Figure 3 When the voltage at the non-inverting input of comparator 41 in constant conduction time generation circuit 4 is higher than the voltage at the inverting input, its output high potential is sent to the reset terminal of RS flip-flop 42, pulling down the output signal Duty. After passing through inverter 43, the gate of NMOS switch M5 in capacitor charging and discharging circuit 2 is pulled high to discharge the capacitor. Therefore, the actual constant conduction time determined by the capacitor is T. ON +T d .

[0039] The actual constant on-time, after considering the comparator delay, is calculated using the following equation: , , According to the above formula, if the comparator delay T needs to be considered... d Even delays caused by other factors can be compensated for by adjusting the values ​​of compensation resistors Rc1 and Rc2, thereby avoiding delays such as... Figure 4 As shown, due to the constant on-time delay, T ON Signal delay, actual ramp signal is higher than output voltage V OUT The resulting comparison error; the actual constant on-time is as follows: , The above formula, while compensating for delay, also allows the deviations of the two compensation resistors at different process corners on the layout to cancel each other out during the difference calculation, further improving the accuracy of the constant conduction time; at the same time, the actual constant conduction time T ON_real Eliminating T through compensation d After the effect, it is inversely proportional to the input voltage and directly proportional to the output voltage. The adaptive adjustment of the constant conduction time ensures that the frequency of the ACOT Buck DC-DC controller in steady-state operation is not affected by fluctuations in the input / output voltage, resulting in greater stability. The specific waveform diagram is shown below. Figure 3 and Figure 4 As shown.

[0040] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A constant on-time generation circuit with delay compensation, characterized in that, include: Charging current generation circuit (1), capacitor charging and discharging circuit (2), comparator delay compensation circuit (3) and constant conduction time generation circuit (4); The charging current generating circuit (1) is connected to the input voltage V. IN The charging current generating circuit (1) is connected to the capacitor charging and discharging circuit (2), the capacitor charging and discharging circuit (2) is connected to the comparator delay compensation circuit (3) and the constant conduction time generating circuit (4), and the comparator delay compensation circuit (3) is connected to the constant conduction time generating circuit (4). The charging current generating circuit (1) is used to generate current related to the input voltage V. IN A proportional charging current is input to the capacitor charging and discharging circuit (2) and the comparator delay compensation circuit (3); The capacitor charging and discharging circuit (2) is used to charge the capacitor C according to the charging current, generate a triangular wave voltage and output it to the constant conduction time generating circuit (4). The comparator delay compensation circuit (3) is used to generate an output voltage V based on the charging current. OUT and the output voltage V OUT Step-down, the output voltage V after step-down OUT Input to the constant on-time generation circuit (4); The constant on-time generation circuit (4) is used to generate the output voltage V after step-down. OUT The triangular wave voltage generates the output signal Duty, which controls the charging interval of capacitor C. The capacitor charging and discharging circuit (2) is used to control the charging frequency of capacitor C according to the output signal Duty.

2. The constant on-time generation circuit with delay compensation as described in claim 1, characterized in that, The charging current generating circuit (1) includes: a voltage divider network, an amplifier A, a first MOSFET M1, a second MOSFET M2, and a grounding resistor R. The voltage divider network is connected to the input voltage V. IN The non-inverting terminal of amplifier A is connected to a voltage divider network. The source of the second MOS transistor M2 is connected to the operating voltage VDD. The gate of the second MOS transistor M2 is connected to the capacitor charging and discharging circuit (2). The drain of the second MOS transistor M2 is connected to the drain of the first MOS transistor M1. The gate of the first MOS transistor M1 is connected to the output terminal of amplifier A. The drain of the first MOS transistor M1 is connected to the negative input terminal of amplifier A and one end of the grounding resistor R. The other end of the grounding resistor R is grounded.

3. The constant on-time generation circuit with delay compensation as described in claim 2, characterized in that, The voltage divider network includes a first voltage divider resistor R1 and a second voltage divider resistor R2, with one end of the first voltage divider resistor R1 connected to the input voltage V. IN The other end is connected to the non-inverting input of amplifier A and one end of the second resistor R2, and the other end of the second resistor R2 is grounded.

4. The constant on-time generation circuit with delay compensation as described in claim 2, characterized in that, The capacitor charging and discharging circuit (2) includes: a third MOS transistor M3, a first compensation resistor Rc1, a capacitor C and a fifth MOS transistor M5. The source of the third MOS transistor M3 is connected to the working voltage VDD. The gate of the third MOS transistor is connected to the gate of the second MOS transistor M2 and the comparator delay compensation circuit (3). The drain of the third MOS transistor is connected to one end of the first compensation resistor Rc1 and the constant conduction time generation circuit (4). The other end of the first compensation resistor Rc1 is connected to the drain of the fifth MOS transistor M5 and one end of the capacitor C. The other end of the capacitor C is grounded. The source of the fifth MOS transistor M5 is grounded. The gate of the fifth MOS transistor M5 is connected to the constant conduction time generation circuit (4).

5. The constant on-time generation circuit with delay compensation as described in claim 4, characterized in that, The comparator delay compensation circuit (3) includes a fourth MOS transistor M4, a sixth MOS transistor M6, a seventh MOS transistor M7, and a second compensation resistor Rc2. The source of the fourth MOS transistor M4 is connected to the operating voltage VDD. The gate of the fourth MOS transistor M4 is connected to the gate of the third MOS transistor. The drain of the fourth MOS transistor M4 is connected to the drain and gate of the sixth MOS transistor M6 and the gate of the seventh MOS transistor M7. The source of the sixth MOS transistor M6 is grounded. The source of the seventh MOS transistor M7 is grounded. The drain of the seventh MOS transistor M7 is connected to one end of the second compensation resistor Rc2. The other end of the second compensation resistor Rc2 is connected to the constant on-time generation circuit (4).

6. The constant on-time generation circuit with delay compensation as described in claim 5, characterized in that, The constant on-time generation circuit (4) includes: a comparator (41), an RS flip-flop (42), and an inverter (43). The non-inverting terminal of the comparator (41) is connected to one end of the first compensation resistor Rc1, and the inverting terminal of the comparator (41) is connected to the other end of the second compensation resistor Rc2. The output terminal of the comparator (41) is connected to the reset terminal R of the RS flip-flop (42). The set terminal S of the RS flip-flop (42) is connected to the external V_CMP signal. The positive output terminal Q of the RS flip-flop (42) is connected to the input terminal of the inverter (43), and the output terminal of the inverter (43) is connected to the gate of the fifth MOS transistor M5.

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