A dynamic coding method and apparatus based on parallel filters

Abstract

The application provides a dynamic encoding method and device based on parallel filters, which is applied to a Reed Solomon encoder provided with a parallel first-order filter array: a target check byte quantity value and a plurality of information data bytes are acquired; the target check byte quantity value is decoded and converted into a thermometer code vector, a parallel first-order filter array is logically cut, and an enabled first-order filter is connected to a bimodal exclusive OR tree; the information data bytes are broadcast to the first-order filter by using a prefix and the exclusive OR tree, and a Galois field multiplication and addition operation is synchronously executed by the first-order filter to iteratively update an internal register state; the internal register state of the first-order filter is iteratively processed by using a suffix and the exclusive OR tree, and a check byte is output in real time to complete a dynamic encoding process. Through the above method, real-time dynamic configuration of encoding parameters and efficient encoding operation are realized, and chip power consumption is effectively reduced, timing performance is optimized, and continuity and reliability of an encoding process are improved.

Description

Technical Field

[0001] This application relates to the field of data transmission coding technology, and in particular to a dynamic coding method and apparatus based on parallel filters. Background Technology

[0002] The Reed-Solomon (RS) encoder is an error correction coding device based on Galois domain operations. It achieves error detection and correction in data transmission and storage by adding check bytes. It plays a core role in fields such as high-speed communication, mass storage and satellite communication. With the iteration of 5G / 6G technology, the increase in bandwidth of high-speed storage devices and the expansion of software-defined storage scenarios, RS encoders urgently need to meet the requirements of ultra-high throughput, ultra-low latency and dynamic adjustment of the number of check bytes in order to balance transmission efficiency and error correction performance.

[0003] Existing RS encoders suffer from three main technical defects: First, the serial architecture based on a linear feedback shift register (LFSR) suffers from low throughput and cannot dynamically adjust the number of check bytes in real time due to its bit-by-bit serial processing, making it difficult to adapt to flexible configuration requirements. Second, while the fully parallel matrix architecture improves throughput, it leads to a significant increase in hardware area, a surge in chip costs, and a sharp increase in timing convergence difficulty, especially with a significant increase in logic latency when encoding high-order numbers. Third, the filter cascade architecture is limited by configuration granularity (only supporting even-order adjustments), has additional configuration latency, and poor adaptability to streaming buses, making it prone to encoding interruptions due to backpressure signals. Finally, existing RS encoders commonly suffer from dynamic power consumption waste, excessively long critical paths, and large fluctuations in logic latency, severely restricting their practical deployment and promotion in high-speed communication and storage devices. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a dynamic encoding method and apparatus based on parallel filters. Through a parallel Reed-Solomon encoder architecture based on atomic-level first-order decomposition, the hardware implementation of the generator polynomial of this architecture is thoroughly decomposed into multiple physically independent and structurally similar first-order filters. The target check byte count is decoded into a thermometer code vector to logically prune the parallel first-order filter array. The prefix and suffix sum modes of a dual-modal XOR tree are used to achieve parallel encoding of information bytes and generation of check bytes, respectively. This solves the core technical problems of existing RS encoders, such as the inability to achieve full-granularity dynamic seamless switching of check byte count, low encoding throughput, high latency, high chip power consumption, unstable timing performance, and poor adaptability to streaming buses. It achieves dynamic reconstruction of generator polynomials of arbitrary integer order in a single hardware core without resynthesis or circuit reset, thereby realizing real-time dynamic configuration of encoding parameters and efficient encoding operations. Simultaneously, it effectively reduces chip power consumption, optimizes timing performance, and improves the continuity and reliability of the encoding process.

[0005] This application provides a dynamic coding method based on parallel filters, which is applied to a Reed-Solomon encoder. The Reed-Solomon encoder is equipped with a parallel first-order filter array. The dynamic coding method includes:

[0006] Obtain the target verification byte count value and multiple information data bytes from external input;

[0007] The target verification byte count value is decoded into a thermometer code vector, and based on the thermometer code vector, the parallel first-order filter array is logically pruned to enable the first-order filter corresponding to the target verification byte count value, and the first-order filter is connected to a preset dual-modal XOR tree.

[0008] The information data byte is synchronously broadcast to all enabled first-order filters using the dual-modal XOR tree in prefix sum working mode. The first-order filters synchronously perform Galois field multiplication and addition operations to iteratively update the internal register state and synchronously pass the information data byte to the output of the Reed-Solomon encoder.

[0009] The internal register state of the first-order filter is iteratively processed using the bimodal XOR tree in the suffix and working mode, and the output terminal outputs the check byte in real time until the number of the output check byte is consistent with the target check byte number, so as to complete the dynamic encoding process.

[0010] Furthermore, the parallel first-order filter array is constructed through the following steps:

[0011] Based on the target order generator polynomial parameters of the Reed-Solomon encoder, the target order generator polynomial of the Galois field is determined, and the target order generator polynomial of the Galois field is factored to decompose the first-order factors corresponding to the linear terms in the Galois field of the target order.

[0012] Based on each of the first-order factors, a corresponding first-order filter is constructed; wherein, the multiplication coefficients of each first-order filter are fixed by hard-wired connections, and the multiplication coefficients correspond to the coefficients of the first-order factors.

[0013] The first-order filters are arranged in parallel to form the parallel first-order filter array.

[0014] Further, the step of decoding the target parity byte count value into a thermometer code vector, and logically pruning the parallel first-order filter array based on the thermometer code vector to enable the first-order filter corresponding to the target parity byte count value, and connecting the first-order filter to a preset dual-modal XOR tree, includes:

[0015] The target verification byte count value is decoded and converted using a preset combinational logic circuit, and the thermometer code vector used to control the parallel first-order filter array is determined according to a preset value selection rule.

[0016] The thermometer code vector is synchronously transmitted to the control terminal of each first-order filter in the parallel first-order filter array;

[0017] For each of the first-order filters, the value of each bit in the thermometer code vector is judged to determine whether the value corresponding to that bit in the thermometer code vector is a first preset value.

[0018] When the value corresponding to the bit is the first preset value, the first-order filter corresponding to the index of the bit is controlled to enter the working state, and the output of the first-order filter is connected to the preset dual-mode XOR tree; wherein, the number of enabled first-order filters matches the number of target check bytes.

[0019] When the value corresponding to the bit is not the first preset value, the first-order filter corresponding to the index of the value corresponding to the bit is controlled to enter a sleep state, and the internal register state of the first-order filter is frozen.

[0020] Furthermore, the step of decoding the target parity byte count value into a thermometer code vector, and logically pruning the parallel first-order filter array based on the thermometer code vector to enable the first-order filter corresponding to the target parity byte count value, and connecting the first-order filter to a preset dual-modal XOR tree, further includes:

[0021] While synchronously transmitting the thermometer code vector to the control terminal of each of the first-order filters, the thermometer code vector is also synchronously transmitted to the clock control unit of the parallel first-order filter array.

[0022] The clock control unit outputs a clock shutdown signal to the disabled first-order filter to shut down the clock signal corresponding to the first-order filter and stop the logic flipping inside the first-order filter.

[0023] The clock control unit is used to maintain the clock signal output of the enabled first-order filter normally, ensuring that the first-order filter can participate in the encoding operation normally.

[0024] Furthermore, the step of synchronously broadcasting the information data bytes to all enabled first-order filters using the bimodal XOR tree in prefix sum operating mode includes:

[0025] Each of the information data bytes is synchronously broadcast to all enabled first-order filters, and the broadcast information data bytes are preprocessed using the bimodal XOR tree in prefix sum working mode, and the feedback output signal of each enabled first-order filter is collected in real time.

[0026] For each enabled first-order filter, the currently input information data byte is XORed with the feedback output signal of the enabled first-order filter preceding that first-order filter to obtain the input signal of that first-order filter.

[0027] The input signal of each enabled first-order filter is input to that first-order filter.

[0028] Furthermore, the step of synchronously performing Galois field multiplication and addition operations by the first-order filter to iteratively update the internal register state includes:

[0029] The current state parameters of the internal registers of each of the first-order filters are read.

[0030] Based on the input signal and current state parameters corresponding to each first-order filter, the preset Galois domain primitives and the index value of the first-order filter in the parallel first-order filter array, Galois domain multiplication and addition operations are performed to obtain the next state parameters of the internal register of the first-order filter.

[0031] All enabled first-order filters synchronously perform the Galois field multiply-accumulate operation to iteratively update the internal register state.

[0032] Furthermore, the dynamic encoding method also includes:

[0033] The bus backpressure signal fed back by the receiver of each enabled first-order filter is monitored in real time, and when the bus backpressure signal is detected, the internal register state of all enabled first-order filters is frozen synchronously, and the encoding operation of the Reed-Solomon encoder is frozen at the same time.

[0034] When the bus back pressure signal is detected to be released, the freezing of the internal register states of all enabled first-order filters and the freezing of the encoding operation are released to seamlessly restore the encoding operation and data output of the Reed-Solomon encoder.

[0035] This application also provides a dynamic coding device based on parallel filters, the dynamic coding device comprising:

[0036] The data acquisition module is used to acquire the target verification byte count and multiple information data bytes from external input.

[0037] The logic pruning module is used to decode the target verification byte count value into a thermometer code vector, and based on the thermometer code vector, to perform logic pruning on the parallel first-order filter array, enable the first-order filter corresponding to the target verification byte count value, and connect the first-order filter to a preset dual-modal XOR tree.

[0038] The multiply-add operation module is used to synchronously broadcast the information data byte to all enabled first-order filters using the dual-modal XOR tree in the prefix sum working mode. The first-order filters synchronously perform Galois multiply-add operations to iteratively update the internal register state and synchronously pass the information data byte to the output of the Reed-Solomon encoder.

[0039] The encoding output module is used to iteratively process the internal register state of the first-order filter using the bimodal XOR tree in the suffix and working mode, and outputs the check bytes in real time from the output terminal until the number of the output check bytes is consistent with the target number of check bytes, so as to complete the dynamic encoding process.

[0040] Furthermore, the dynamic encoding device also includes a backpressure adaptation module, which is used for:

[0041] The bus backpressure signal fed back by the receiver of each enabled first-order filter is monitored in real time, and when the bus backpressure signal is detected, the internal register state of all enabled first-order filters is frozen synchronously, and the encoding operation of the Reed-Solomon encoder is frozen at the same time.

[0042] When the bus back pressure signal is detected to be released, the freezing of the internal register states of all enabled first-order filters and the freezing of the encoding operation are released to seamlessly restore the encoding operation and data output of the Reed-Solomon encoder.

[0043] This application also provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the dynamic encoding method based on parallel filters described above are performed.

[0044] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the dynamic coding method based on parallel filters as described above.

[0045] This application provides a dynamic encoding method and apparatus based on parallel filters. The dynamic encoding method is applied to a Reed-Solomon encoder, which is equipped with a parallel first-order filter array. The dynamic encoding method includes: acquiring an externally input target check byte count value and multiple information data bytes; decoding the target check byte count value into a thermometer code vector; and logically pruning the parallel first-order filter array based on the thermometer code vector to enable the first-order filter corresponding to the target check byte count value, and connecting the first-order filter to a preset dual-modal XOR tree; utilizing... In the prefix sum mode, the bimodal XOR tree synchronously broadcasts the information data byte to all enabled first-order filters. The first-order filters synchronously perform Galois field multiplication and addition operations to iteratively update the internal register state and synchronously pass the information data byte to the output of the Reed-Solomon encoder. In the suffix sum mode, the bimodal XOR tree iteratively processes the internal register state of the first-order filters, and the output terminal outputs a check byte in real time until the quantity value corresponding to the output check byte matches the target check byte quantity value, thus completing the dynamic encoding process.

[0046] Compared with existing RS encoders, this approach utilizes a parallel Reed-Solomon encoder architecture based on atomic-level first-order decomposition. This architecture's generator polynomial hardware implementation is thoroughly decomposed into multiple physically independent and structurally similar first-order filters. The target check byte count is decoded into a thermometer code vector to logically prune the parallel first-order filter array. The prefix and suffix sum modes of a dual-modal XOR tree are used to achieve parallel encoding of information bytes and generation of check bytes, respectively. This solves the core technical problems of existing RS encoders, such as the inability to achieve full-granularity dynamic seamless switching of check byte count, low encoding throughput, high latency, high chip power consumption, unstable timing performance, and poor adaptability to streaming buses. It achieves dynamic reconstruction of generator polynomials of arbitrary integer order within a single hardware core without resynthesis or circuit reset, enabling real-time dynamic configuration of encoding parameters and efficient encoding operations. Simultaneously, it effectively reduces chip power consumption, optimizes timing performance, and improves the continuity and reliability of the encoding process.

[0047] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0048] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 One of the flowcharts for a dynamic coding method based on parallel filters provided in an embodiment of this application;

[0050] Figure 2 A second flowchart illustrating a dynamic coding method based on parallel filters provided in an embodiment of this application;

[0051] Figure 3 This is one of the structural schematic diagrams of a dynamic coding device based on a parallel filter provided in an embodiment of this application;

[0052] Figure 4 This is a second schematic diagram of a dynamic coding device based on a parallel filter, provided as an embodiment of this application.

[0053] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.

[0055] Research has revealed that the Reed-Solomon (RS) encoder is a classic error correction coding device based on Galois domain operations. Its core function is to detect and correct errors during data transmission and storage by adding specific check bytes to the original information data. With its powerful error correction capabilities, it plays an irreplaceable core role in fields such as high-speed communication, mass storage, and satellite communication. With the rapid iteration of 5G / 6G communication technologies, the continuous improvement of bandwidth of high-speed storage devices (such as NVMe SSDs), and the continuous expansion of software-defined storage scenarios, more stringent requirements are placed on the performance of RS encoders. They not only need to have ultra-high throughput and ultra-low latency coding capabilities, but also need to be able to dynamically adjust the number of check bytes in real time according to actual transmission needs and channel conditions to achieve flexible adaptation of coding redundancy in order to balance transmission efficiency and error correction performance.

[0056] Currently, existing RS encoders suffer from three main technical defects, making it difficult to meet the actual needs of the aforementioned high-end application scenarios.

[0057] The Serial Linear Feedback Shift Register (LFSR) architecture uses a traditional serial operation method, requiring data to be processed bit by bit during encoding, resulting in low encoding throughput and making it difficult to adapt to high-speed data transmission scenarios. At the same time, its generator polynomial parameters are fixed, and the number of parity bytes cannot be dynamically adjusted. If the encoding redundancy needs to be changed, the hardware connections and logic circuits need to be reconstructed, making it impossible to achieve real-time seamless parameter switching. Its adaptability is extremely poor, making it difficult to meet the flexible application requirements of multiple scenarios and multiple needs.

[0058] The fully parallel matrix architecture improves the encoding throughput by using large-scale parallel computing units, which solves the speed bottleneck of the serial architecture to some extent. However, it brings a huge hardware area overhead and a significant increase in chip manufacturing costs. In addition, this architecture also cannot achieve dynamic adjustment of the number of parity bytes, and under high-order encoding configuration, the timing convergence difficulty increases sharply, the logic latency increases, and it is difficult to adapt to high-frequency operating scenarios, which limits its integration and application in high-end chips.

[0059] The filter cascade architecture, while optimizing computational efficiency through filter cascading, suffers from significant configuration granularity limitations. It can only adjust the number of parity bytes in even-number steps, failing to dynamically configure any integer number of parity bytes, thus limiting its adaptability. Furthermore, its parameter configuration process requires a separate clock cycle, resulting in noticeable configuration latency and hindering seamless parameter switching between data packets, impacting data transmission continuity. Additionally, this architecture exhibits poor streaming bus adaptability; when the receiving end sends back a reverse pressure signal, the entire encoding process must be reset, leading to encoding interruption and data loss, severely affecting encoding continuity and reliability.

[0060] In addition, existing encoding methods generally suffer from the prominent problem of dynamic power waste, with unused computing units remaining in a continuous working state, resulting in high overall chip power consumption, which does not conform to the current design trend of low-power chips. At the same time, the critical path in the encoding process is relatively long, the timing performance is unstable, and the logic delay fluctuates greatly, making it difficult to meet the design requirements of high frequency and high throughput, further limiting its promotion and application in the fields of high-speed communication and storage.

[0061] Based on this, this application provides a dynamic encoding method based on parallel filters. Using a parallel Reed-Solomon encoder architecture based on atomic-level first-order decomposition, the hardware implementation of the generator polynomial is thoroughly decomposed into multiple physically independent and structurally similar first-order filters. The target check byte count is decoded into a thermometer code vector to logically prune the parallel first-order filter array. The prefix and suffix sum modes of a dual-modal XOR tree are used to achieve parallel encoding of information bytes and generation of check bytes, respectively. This solves the core technical problems of existing RS encoders, such as the inability to achieve full-granularity dynamic seamless switching of check byte count, low encoding throughput, high latency, high chip power consumption, unstable timing performance, and poor adaptability to streaming buses. It achieves dynamic reconstruction of generator polynomials of arbitrary integer order in a single hardware core without resynthesis or circuit reset, thereby realizing real-time dynamic configuration of encoding parameters and efficient encoding operations. Simultaneously, it effectively reduces chip power consumption, optimizes timing performance, and improves the continuity and reliability of the encoding process.

[0062] Please see Figure 1 , Figure 1This is one of the flowcharts for a dynamic coding method based on parallel filters provided in an embodiment of this application. For example... Figure 1 As shown in the figure, the dynamic coding method based on parallel filters provided in the embodiments of this application is typically applied to Reed-Solomon encoders, which are equipped with a parallel first-order filter array.

[0063] Here, Reed-Solomon (RS) is a powerful carrier of forward error correction (FEC) coding technology, widely used in data storage and communication systems to detect and correct errors generated during data transmission or storage; among them, Reed-Solomon code is a non-binary cyclic code based on the mathematical theory of finite field (GF).

[0064] Specifically, the RS encoder treats the input data block as the coefficients of a polynomial and constructs a longer codeword by adding redundant check symbols. Even if some data is lost or damaged during transmission, the receiving end can use this redundant information to recover the original data. Unlike error correction codes that process single bits, RS codes process symbols. Typically, a symbol consists of m bits (e.g., m=8, i.e., one byte). This means that RS codes are particularly good at correcting burst errors, i.e., the situation where multiple consecutive bits are wrong, because as long as the erroneous bits fall within the same symbol, it is only counted as one symbol error.

[0065] In this embodiment, the core function of the Reed-Solomon encoder is to detect and correct errors during data transmission and storage by adding check bytes to the original information data. The encoder has built-in core modules such as a parallel first-order filter array, a dual-modal XOR tree, and a clock control unit. It supports dynamic configuration of any number of check bytes from 1 to 32, is adapted to high-speed streaming bus transmission, and is mainly used in high-speed NVMe SSD, 5G / 6G optical communication and other scenarios.

[0066] Among them, the parallel first-order filter array is the core hardware carrier for encoding operations. It consists of multiple first-order filters with standardized structures and fixed hard-wired multiplication coefficients arranged in parallel. In the embodiments of this application, the parallel first-order filter array includes multiple first-order filters (e.g., 32). Each filter corresponds to the operation logic of a first-order factor of a Galois domain. Precise logic pruning can be achieved through thermometer code vectors to enable filters that match the number of target parity bytes to participate in the operation, while unenabled filters enter a sleep state.

[0067] In one possible implementation of this application, the parallel first-order filter array is constructed through the following steps:

[0068] S10A. Based on the target order generator polynomial parameters of the Reed-Solomon encoder, determine the target order generator polynomial of the Galois field, and factorize the target order generator polynomial of the Galois field to decompose the first-order factors corresponding to the linear terms in the target order Galois fields.

[0069] Here, the target order generator polynomial is the core mathematical foundation of RS encoding, directly determining the error correction capability and redundancy range of the encoding. In this embodiment, to achieve dynamic configuration of any integer number of check bytes from 1 to 32, the maximum number of check bytes supported by the RS encoder is set to 32. Therefore, the target order generator polynomial is GF(2... 8 The 32nd order generator polynomial under the Galois field; by thoroughly factoring the 32nd order generator polynomial, it can be decomposed into 32 indivisible first-order factors. Each first-order factor corresponds to a linear term factor under the Galois field, and each first-order factor corresponds to an independent operation logic.

[0070] Among them, the Galois field is a finite field, also known as the Galois field, GF(2 8 ) indicates that it is composed of 2 8 =A finite field consisting of 256 elements is the standard operational field of RS coding and is widely used in error correction coding in high-speed communication and storage fields.

[0071] Among them, the primitive element of the Galois field is the core element in the Galois field, which can generate all non-zero elements in the Galois field through its own exponentiation.

[0072] S10B. Based on each of the first-order factors, a first-order filter is constructed accordingly; wherein, the multiplication coefficients of each of the first-order filters are fixed by hard-wired connections, and the multiplication coefficients correspond to the coefficients of the first-order factors.

[0073] In the embodiments of this application, the first-order filter is the core hardware unit for implementing the first-order multiplication and addition operation in the Galois field. Its structure adopts a standardized design, which facilitates parallel layout and batch integration. Each first-order filter corresponds to only one first-order factor operation logic, ensuring the specificity and accuracy of the operation.

[0074] Here, the multiplication coefficients of each first-order filter are fixed by hard-wired connections, eliminating the need for register configuration. This effectively avoids the latency and logic complexity caused by coefficient configuration in traditional architectures, while also reducing chip area overhead.

[0075] The values ​​of the multiplication coefficients are strictly consistent with the coefficients of the corresponding first-order factors. This ensures that the operation logic of each first-order filter is completely matched with the corresponding first-order factor, thus guaranteeing the accuracy of the encoding operation.

[0076] S10C. The first-order filters are arranged in parallel to form the parallel first-order filter array.

[0077] In this step, all first-order filters with standardized structures and fixed coefficients are laid out in parallel to form a parallel first-order filter array. Each filter in the array is physically independent and can be controlled individually. It can be flexibly turned on or off according to dynamic configuration requirements, providing a stable hardware carrier for subsequent logic trimming and parallel encoding operations. At the same time, the layout is optimized to reduce timing delays.

[0078] like Figure 1 As shown, the dynamic coding method includes:

[0079] S101. Obtain the target verification byte count value and multiple information data bytes from external input.

[0080] In this embodiment, the target check byte count is the redundancy parameter required for encoding, that is, the number of check bytes to be generated during the encoding process. The value ranges from 1 to 32 (which can be flexibly set according to actual error correction requirements). It is the core input parameter for realizing dynamic adaptation of encoding redundancy and can be input by an external master control chip through the AXI4 configuration bus.

[0081] The information data bytes are the raw data that needs to be processed by error correction encoding. They can be continuously input using the AXI-Stream streaming bus without prior buffering and shaping. They can be directly and synchronously broadcast to the enabled first-order filter for parallel encoding operations, and simultaneously transmitted to the encoder output to achieve zero-delay transmission.

[0082] In this step, the Reed Solomon encoder receives two core input parameters from an external system (e.g., the main control chip, transmission module, etc.): the number of target check bytes (i.e., the redundancy parameter required for encoding, which ranges from 1 to 32 and can be flexibly set according to actual error correction requirements) and multiple data bytes to be encoded (i.e., the original data that needs to be processed for error correction encoding, which is continuously input in a streaming manner without prior buffering and shaping).

[0083] In this embodiment of the application, this step provides basic input parameters for subsequent dynamic configuration and encoding operations, clarifies the redundancy requirements of the encoding process and the original data to be encoded, ensures that the encoding process has a clear goal and processing object, and lays the foundation for the orderly development of the entire encoding process.

[0084] In this way, by adopting a streaming input method, there is no need to pre-cache and reshape the information data bytes. It is natively adapted to mainstream streaming bus transmission scenarios such as AXI-Stream, effectively reducing the latency caused by data buffering and significantly improving the real-time performance of encoding. At the same time, it supports input of any integer value of the target check byte number from 1 to 32, providing the necessary prerequisite for full-granular dynamic configuration of the check byte number and adapting to the error correction requirements of different scenarios.

[0085] For example, the target check byte count value config_R=8 (binary 00001000) is received from the external master control chip via the AXI4 configuration bus. This parameter is set according to the actual error correction requirements and is used to determine the encoding redundancy. The information data bytes to be encoded (e.g., 256KB of continuous data, input in byte-stream mode without prior buffering and shaping) are received via the AXI-Stream streaming bus. The data transmission rate matches the encoder throughput to ensure no data backlog.

[0086] S102. Decode the target check byte count value into a thermometer code vector, and based on the thermometer code vector, perform logical pruning on the parallel first-order filter array to enable the first-order filter corresponding to the target check byte count value, and connect the first-order filter to a preset dual-modal XOR tree.

[0087] In this embodiment, the thermometer code vector is a binary control vector converted from the target check byte count value, and the number of bits is exactly the same as the number of filters in the parallel first-order filter array; each bit corresponds to the control signal of a first-order filter.

[0088] Here, the preset value rules for decoding and conversion include: bits with an index less than the number of target check bytes are 1, and the rest are 0, which is used to achieve precise logical trimming of the parallel first-order filter array.

[0089] Logic pruning is a dynamic control operation performed on a parallel first-order filter array based on thermometer code vectors. The core is to enable the first-order filter that matches the target parity byte count (controlling it to enter the working state and connect it to the dual-modal XOR tree), while putting the unmatched filter into a sleep state (freezing the register and setting the output to 0), avoiding the waste of invalid operation units and laying the foundation for low-power control.

[0090] A bimodal XOR tree is an XOR operation network that can flexibly switch working modes. It is the core module for implementing parallel encoding operations and supports two working modes: prefix sum and suffix sum. It can be switched uniformly through a flow control state machine (FSM) with a switching latency of 0. The prefix sum mode is used for the preprocessing and synchronous broadcasting of information data bytes, while the suffix sum mode is used for the generation and iterative processing of check bytes. This can effectively shorten the encoding critical path and optimize timing performance.

[0091] In this step, the target parity byte count value in binary form is first quickly decoded into a thermometer code vector using a pre-set pure combinational logic circuit. Then, the thermometer code vector is used to perform precise logical pruning on the parallel first-order filter array to select first-order filters that perfectly match the target parity byte count value and put them into operation. At the same time, the output of these enabled first-order filters is connected to a pre-set dual-modal XOR tree to build a stable hardware path for subsequent parallel encoding operations.

[0092] In this embodiment, the step converts the abstract target check byte count into a control signal (i.e., thermometer code vector) that can be directly recognized and executed by the hardware, thereby realizing dynamic logic pruning of the parallel first-order filter array. This effectively solves the technical problem that the existing technology cannot achieve dynamic configuration of arbitrary check byte count, and at the same time establishes the hardware foundation for parallel encoding operations, ensuring the efficient execution of subsequent encoding operations.

[0093] This enables parameter decoding and logic trimming operations to be completed within a single cycle, without the need for a separate configuration cycle or system reset, achieving zero-overhead parameter switching. Seamless parameter switching between data packets can be easily achieved, improving the continuity of data transmission. The logic trimming has high accuracy, with the number of enabled filters perfectly matching the number of target check bytes, effectively avoiding the waste of invalid operation units and laying a solid foundation for subsequent low-power control.

[0094] An example of thermometer code conversion and logic trimming includes: using a pure combinational logic decoding circuit, quickly decoding config_R=8 into a 32-bit thermometer code vector en_vec. According to a preset value rule (bits with indices less than config_R are 1, and the remaining bits are 0), the converted en_vec has the value "00000000 00000000". The conversion process of "0000000011111111" (lower 8 bits are 1, higher 24 bits are 0) is completed within one clock cycle without any delay. The en_vec is synchronously transmitted to the control terminals of 32 first-order filters via the control bus, and simultaneously transmitted to the clock control unit via the clock control bus to ensure that logic trimming and clock control are synchronized. Each bit of en_vec is evaluated. The first preset value is 1, and the corresponding bits of the filters with indices 0 to 7 are 1, controlling them to enter the working state, and the output is connected to a dual-modal XOR tree. The corresponding bits of the filters with indices 8 to 31 are 0, controlling them to enter the sleep state, the output is forcibly set to 0, and the internal register state is frozen, realizing precise logical trimming.

[0095] In one possible implementation of this application, step S102 may include:

[0096] S1021. The target verification byte quantity value is decoded and converted using a preset combinational logic circuit, and the thermometer code vector used to control the parallel first-order filter array is determined according to the preset value selection rules.

[0097] Here, the combinational logic circuit is a logic circuit that can complete signal conversion instantly without clock triggering. Its core advantage is fast response speed and no delay. It is specifically used to quickly decode the binary form of the target parity byte count value (config_R) into a thermometer code vector (en_vec). The thermometer code vector is a binary control vector. Its number of bits is exactly the same as the number of filters in the parallel first-order filter array (32 bits in this invention). Each bit corresponds to the control signal of a first-order filter. The preset value rules are used to ensure that the vector can accurately match the target parity byte count value, realize precise control of the filter, and avoid encoding errors caused by miscontrol.

[0098] For example, the preset combinational logic circuit is a pure combinational logic decoding circuit, which can complete the conversion operation in one clock cycle without additional clock cycles; the target check byte count value config_R is 5 (00000101 in binary). According to the preset value rule (bits with an index less than config_R are 1, and the rest are 0), the converted 32-bit thermometer code vector en_vec is "00000000 00000000 00000000 00011111", that is, the lower 5 bits are 1 and the higher 27 bits are 0. This vector is specifically used to control the enable state of the 32-channel parallel first-order filter array to ensure that the number of enabled filters is completely matched with config_R=5.

[0099] S1022. The thermometer code vector is synchronously transmitted to the control terminal of each first-order filter in the parallel first-order filter array.

[0100] In this step, the generated thermometer code vector is synchronously sent to the control terminals of 32 first-order filters via a dedicated control bus to ensure that all filters receive the control signal at the same time, thereby achieving synchronous control and avoiding encoding errors caused by some filters responding prematurely or lagging behind due to the transmission delay of the control signal. This ensures the synchronization and accuracy of the logic trimming.

[0101] For example, the 32-bit thermometer code vector en_vec (low 5 bits are 1) generated in step 1 is synchronously transmitted to the control terminals of 32 first-order filters through the control bus. The control terminal of each filter receives one bit of the thermometer code vector. The filter with index 0 receives the 0th bit, the filter with index 1 receives the 1st bit, and so on, to ensure that all filters receive the control signal at the same time, so as to prepare for subsequent state switching.

[0102] S1023. For each of the first-order filters, perform a value judgment on each bit in the thermometer code vector to determine whether the value corresponding to that bit in the thermometer code vector is a first preset value.

[0103] In this step, the first preset value can be set to 1 (corresponding to the enabled working state of the filter). By judging the value of each bit of the thermometer code vector in real time, the working state (enabled or sleep) of each filter can be quickly determined, providing a clear basis for subsequent logic trimming. The value judgment is implemented using combinational logic, which does not require clock triggering and can be completed in real time without any additional delay, ensuring the efficiency of logic trimming.

[0104] For example, the first preset value is set to 1. For each of the 32 first-order filters, the value of the corresponding bit of the temperature code vector received by the control terminal is determined. For example, for filters with indices 0 to 4, the received bit value is 1, which is determined to be enabled; for filters with indices 5 to 31, the received bit value is 0, which is determined to be sleep mode. The status determination of all filters is completed.

[0105] S1024. When the value corresponding to the bit is the first preset value, the first-order filter corresponding to the index of the value corresponding to the bit is controlled to enter the working state, and the output of the first-order filter is connected to the preset dual-modal XOR tree; wherein, the number of enabled first-order filters matches the number of target check bytes.

[0106] In this step, when the corresponding bit of the thermometer code vector is 1, the corresponding first-order filter is controlled to enter the working state, its internal operation logic is started, and the output of the filter is connected to the dual-modal XOR tree so that it can participate in the subsequent parallel encoding operation. The number of enabled filters is strictly consistent with the number of target check bytes to ensure that the encoding redundancy meets the preset requirements, while avoiding invalid operation units from participating in the operation and reducing power consumption.

[0107] For example, when the corresponding bit of the thermometer code vector is 1 (filters with indices 0 to 4), these filters are controlled to enter the working state, their internal Galois field multiply-add operation logic is started, and their output is connected to a dual-modal XOR tree. The number of enabled filters is 5, which is exactly matched with the target parity byte count value config_R=5. These filters will participate in the subsequent parallel encoding operation throughout the process to ensure that the encoding redundancy meets the requirements.

[0108] S1025. When the value corresponding to the bit is not the first preset value, control the first-order filter corresponding to the index of the bit to enter the sleep state and freeze the internal register state of the first-order filter.

[0109] In this step, when the corresponding bit of the thermometer code vector is 0, the corresponding first-order filter is controlled to enter a sleep state, stopping its internal operation logic and freezing its internal register state (stopping the update of register data). Its output is forcibly set to 0. By utilizing the mathematical property that XOR 0 in the Galois field equals the original value, the filter is completely separated from the encoding path from mathematical logic, avoiding any interference to the encoding result and ensuring the accuracy of logic trimming.

[0110] For example, when the corresponding bit of the thermometer code vector is 0 (filters with indices 5 to 31), these filters are controlled to enter a sleep state, their internal register states are frozen, and their outputs are forcibly set to 0. These filters do not participate in any encoding operations and will not interfere with the encoding results, achieving precise logical trimming and laying the foundation for low-power control.

[0111] Optionally, in another possible implementation of this application, step S102 further includes:

[0112] S1026. While synchronously transmitting the thermometer code vector to the control terminal of each of the first-order filters, the thermometer code vector is also synchronously transmitted to the clock control unit of the parallel first-order filter array.

[0113] Here, the clock control unit is a hardware unit specifically designed to control the clock signal of the first-order filter. It adopts a fine-grained clock gating design, which enables independent control of the clock signal of each filter.

[0114] In this step, the clock control and logic trimming are synchronized by transmitting the thermometer code vector synchronously, which avoids power waste or logic errors caused by clock signal switching delay and ensures the coordination between low power control and logic trimming.

[0115] For example, while transmitting the 32-bit thermometer code vector en_vec to the control terminals of 32 filters, the vector is synchronously transmitted to the clock control unit via a dedicated clock control bus. The clock control unit receives the vector in real time, quickly identifies the enable state of each filter, and prepares to perform precise control of the clock signal.

[0116] S1027. The clock control unit outputs a clock shutdown signal to the disabled first-order filter to shut down the clock signal corresponding to the first-order filter and stop the logic flipping inside the first-order filter.

[0117] In this step, the disabled filter (the corresponding bit of the thermometer code vector is 0) does not need to participate in the encoding operation. Its internal logic flipping will generate invalid power consumption. By turning off its clock signal through the clock control unit, its internal logic flipping can be completely stopped, which greatly reduces the dynamic power consumption of the chip and realizes fine-grained low-power control, which is in line with the design trend of low-power chips.

[0118] For example, the clock control unit identifies the bits (index 5~31) in the thermometer code vector that have a value of 0. For these disabled filters, it outputs a clock shutdown signal to shut down the corresponding clock signal, stops all logic toggling inside these filters, avoids unnecessary power consumption, and effectively reduces the overall power consumption of the chip.

[0119] S1028. The clock control unit is used to maintain the clock signal of the enabled first-order filter in normal output, so as to ensure that the first-order filter can participate in the encoding operation normally.

[0120] In this step, the enabled filter (the corresponding bit of the thermometer code vector is 1) needs to participate in the encoding operation. The clock control unit maintains its clock signal output normally to ensure that its internal logic works normally, ensures the smooth progress of the encoding operation, and avoids encoding errors caused by abnormal clock signals, thus ensuring the reliability of the encoding.

[0121] For example, the clock control unit identifies the bits (index 0~4) with a value of 1 in the thermometer code vector. For these enabled filters, the clock signal is maintained to output normally (clock frequency is 1.4GHz, which meets the high-frequency design requirements of 6nm process), ensuring that these filters can perform Galois multiplication and addition operations normally, participate stably in the encoding process, and ensure encoding efficiency and accuracy.

[0122] As an example of low-power control, for instance, after receiving en_vec, the clock control unit quickly identifies the bits with a value of 0 (indexes 8-31). For these 24 disabled filters, it outputs a clock shutdown signal to shut down their corresponding clock signals, stopping all logic toggling within these filters and avoiding unnecessary power consumption. At the same time, it maintains the normal output of the clock signals (1.4GHz) of the 8 enabled filters (indexes 0-7) to ensure their normal participation in encoding operations. In this case, the chip's dynamic power consumption is only 1 / 4 of that in the fully enabled state, achieving refined low-power control and effectively reducing chip operating costs.

[0123] S103. The information data byte is synchronously broadcast to all enabled first-order filters using the dual-modal XOR tree in the prefix sum working mode. The first-order filters synchronously perform Galois field multiplication and addition operations to iteratively update the internal register state and synchronously pass the information data byte to the output of the Reed-Solomon encoder.

[0124] In this embodiment, the prefix sum working mode is one of the two working modes of the bimodal XOR tree. It is mainly used in the information data byte encoding stage. The core function of the prefix sum working mode is to synchronously broadcast the information data bytes to all enabled first-order filters, preprocess the broadcast data, collect the feedback output signals of each filter, calculate the input signal of each enabled filter, and provide accurate input for Galois multiplication and addition operations.

[0125] Galois field multiplication and addition is the core operation of RS encoding, strictly following the Galois field operation rules. In this embodiment, the operation field is GF(2). 8 That is, a finite field of 256 elements, used to implement iterative processing of information polynomials.

[0126] The internal register state is an intermediate state parameter stored in a dedicated register set inside each first-order filter. Essentially, it is the intermediate result of the information polynomial iterative operation. The initial state is 0x00. It is iteratively updated through Galois field multiplication and addition operations. It is frozen when the bus backpressure is triggered and resumed after the backpressure is released to ensure the continuity of the encoding.

[0127] In this step, firstly, the dual-modal XOR tree is switched to the prefix sum working mode; then, each data byte of the streaming input is synchronously broadcast to all enabled first-order filters, and the broadcast data bytes are preprocessed through the prefix sum XOR tree, while the feedback output signal of each enabled first-order filter is acquired in real time; then, all enabled first-order filters synchronously perform Galois domain multiplication and addition operations, iteratively updating the state parameters of their internal registers; at the same time, the original data bytes are synchronously passed through to the encoder output to ensure that the original data is transmitted without delay.

[0128] In the embodiments of this application, the purpose of this step is to realize parallel encoding operations of information data bytes, efficiently complete the iterative processing of information polynomials, and at the same time ensure the zero-delay transmission of the original information data, effectively solve the technical problem of low throughput of existing serial architecture encoding, and greatly improve encoding efficiency and real-time performance.

[0129] In this way, by adopting a fully parallel operation method, all enabled first-order filters work synchronously, and the coding throughput is linearly positively correlated with the number of filters, which greatly improves the coding rate. The use of prefix and XOR trees effectively shortens the critical path length of the coding process, ensures stable timing performance, and avoids the timing bottleneck caused by long feedback chains in traditional architectures. Information data bytes are transmitted synchronously without any additional delay, minimizing end-to-end latency and meeting the requirements of high-speed data transmission.

[0130] In one possible implementation of this application, in specific implementation, the step S103 of synchronously broadcasting the information data bytes to all enabled first-order filters using the bimodal XOR tree in prefix sum operating mode may include:

[0131] S1031. Each of the information data bytes is synchronously broadcast to all enabled first-order filters, and the broadcast information data bytes are preprocessed using the bimodal XOR tree in prefix sum working mode, and the feedback output signal of each enabled first-order filter is collected in real time.

[0132] In this step, the prefix sum working mode is specifically used for the preprocessing of information data bytes to achieve parallel iterative operations; data synchronization broadcasting ensures that all enabled filters acquire the same information data bytes within the same clock cycle, avoiding asynchrony caused by data transmission delays and ensuring the accuracy of parallel operations; the feedback output signal refers to the operation output result of each filter, which is used for the calculation of the input signal of each subsequent filter to ensure the continuity of operations.

[0133] For example, the bimodal XOR tree switches to prefix sum mode via a flow control state machine. External information data bytes (such as 0x12, 0x34, 0x56, etc.) are input via the AXI-Stream streaming bus. Each byte is synchronously broadcast to five enable filters with indices 0 to 4 via the broadcast bus within one clock cycle. The bimodal XOR tree preprocesses the broadcast information data bytes and simultaneously acquires the feedback output signal of each enable filter in real time through a feedback acquisition circuit, providing an accurate basis for calculating the input signal of each filter.

[0134] S1032. For each enabled first-order filter, perform an XOR operation between the currently input information data byte and the feedback output signal of the enabled first-order filter preceding that first-order filter to obtain the input signal of that first-order filter.

[0135] In this step, the core function of the prefix sum XOR tree is to calculate the input signal of each enabled first-order filter. The calculation of the input signal is based on the XOR operation between the current information data byte and the feedback output signal of the previous enabled filter. This calculation method can ensure the logical correctness of parallel operation, realize the iterative processing of information polynomial, and provide accurate input signals for subsequent Galois field multiplication and addition operations.

[0136] In this embodiment of the application, the input signal of the first-order filter is determined by the following formula.

[0137] .

[0138] in, Indicates the first The input signal of a first-order filter; , , , Indicates that it is located at the th The feedback output signal of the first-order filter that is enabled before the first-order filter; This represents the currently input data bytes.

[0139] For example, for the enable filter at index 0, there are no other enable filters before it, so the input signal is the currently input information data byte (e.g., 0x12); for the enable filter at index 1, the input signal is the XOR operation result of the current information data byte (0x12) and the feedback output signal of the filter at index 0; for the enable filter at index 2, the input signal is the XOR operation result of the current information data byte (0x12) and the feedback output signals of the filters at indices 0 and 1, and so on, completing the input signal calculation for all enable filters in sequence to ensure that the input signal of each filter is accurate.

[0140] S1033. Input the input signal of each enabled first-order filter to the first-order filter.

[0141] In this step, the input signal of each enabled filter obtained from the preprocessing is synchronously input to the corresponding first-order filter through a dedicated signal bus, providing accurate input for the subsequent Galois domain multiplication and addition operations, ensuring the smooth progress of the operation, while avoiding interference and delay in the signal transmission process, and ensuring the accuracy and efficiency of the operation.

[0142] For example, the input signals of each filter with indices 0 to 4 are calculated and input to the corresponding first-order filter through a dedicated signal bus. The input signal of the filter with index 0 is 0x12, the input signal of the filter with index 1 is the XOR result of 0x12 and the feedback output of index 0, and so on. All enabled filters receive the input signals synchronously and are ready to perform multiplication and addition operations.

[0143] In one possible implementation of this application, in specific implementation, the step S103 in which the first-order filter synchronously performs Galois field multiplication and addition operations to iteratively update the internal register state may include:

[0144] S1034. Each of the first-order filters reads the current state parameters of its internal register.

[0145] In this step, each first-order filter has a dedicated register to store intermediate state parameters during the operation. These parameters are essentially intermediate results of the information polynomial iterative operation. Reading the current state parameters is a prerequisite for performing Galois field multiplication and addition operations, which can ensure the continuity and accuracy of the operation and avoid operation interruption or data corruption.

[0146] For example, the five enable filters with indices 0 to 4 each read the current state parameter (initially all are 0) of their own internal registers through the internal register read circuit. For instance, the current state parameter of the filter with index 0 is State_current=0x00, the current state parameter of the filter with index 1 is State_current=0x00, and so on, ensuring that each filter can obtain the accurate current state parameter.

[0147] S1035. Based on the input signal and current state parameter corresponding to each first-order filter, the preset Galois domain primitive and the index value of the first-order filter in the parallel first-order filter array, perform Galois domain multiplication and addition operation to obtain the next state parameter of the internal register of the first-order filter.

[0148] In this embodiment of the application, the next state parameter of the internal register of the first-order filter is determined by the following formula.

[0149] .

[0150] in, Indicates the first The next state parameters of the internal register of each first-order filter; Indicates the first The input signal of a first-order filter; This represents the pre-defined fundamental element of the Galois domain; Indicates the first The index value of each first-order filter in the parallel first-order filter array; Indicates the first The current state parameters of a first-order filter.

[0151] For example, assuming the preset Galois domain primitive is 0x02, the input signal of the filter with index i=0 is s[0]=0x12, the current state parameter State_current=0x00, and the Galois domain multiplication and addition operation is performed: State_next=0x00×0x02+0x12=0x12; the XOR result of the input signal s[1]=0x12 of the filter with index i=1 and the feedback output of index 0 (assuming it is 0x12), the current state parameter State_current=0x00, and the calculation results in State_next=0x00×0x04+0x12=0x12, and so on, each enabled filter calculates its next state parameter according to the above formula to ensure the accuracy of the calculation result.

[0152] S1036. All enabled first-order filters synchronously perform the Galois field multiply-add operation to iteratively update the internal register state.

[0153] In this step, all enabled filters synchronously perform Galois multiplication and addition operations within the same clock cycle to avoid encoding errors caused by asynchronous operations. At the same time, the internal register state is synchronously updated from the current state State_current to the next state State_next to achieve iterative state updates, ensuring the synchronization and efficiency of parallel operations and significantly improving the encoding throughput.

[0154] For example, the five enable filters with indices 0 to 4 synchronously perform Galois multiplication and addition operations within the same clock cycle. Through the internal register update circuit, the state of their respective internal registers is updated to the State_next calculated in step 2. The register state of index 0 is updated to 0x12, the register state of index 1 is updated to 0x12, and so on, completing one iteration update of the register state. As information data bytes are continuously input, this process is repeated continuously to achieve continuous iteration of the state and ensure the continuity of the encoding operation.

[0155] As an example of parallel encoding of information bytes, the Flow Control State Machine (FSM) sends control signals to switch the bimodal XOR tree to prefix sum mode, initiating the encoding operation process and ensuring that the XOR tree's operating mode matches the encoding stage. Each information data byte input from the AXI-Stream bus is synchronously broadcast to eight enable filters (indexes 0-7) within one clock cycle via the broadcast bus, ensuring that all enable filters simultaneously acquire the same information data byte and avoiding asynchronous operations. The prefix sum XOR tree preprocesses the broadcast information bytes, and the feedback output signal of each enable filter is acquired in real time through a feedback acquisition circuit to calculate the input signal of each filter: the input signal at index 0 is the current information byte, and the input signal at index 1 is the current information byte. The input signal at index 7 is the XOR result of the current information byte and the feedback outputs at indices 0-6, ensuring the accuracy of each input signal. Each enabled first-order filter reads the current state parameter of its internal register (initially 0x00), combines it with its own input signal, the preset Galois domain primitive = 0x02, and its own index value, and synchronously performs Galois domain multiplication and addition operations to calculate the next state parameter. Then, it synchronously updates the state of its internal register. During the continuous input of all information data bytes, the above steps are repeated to realize the continuous iterative operation of the information polynomial. At the same time, each input information data byte is synchronously passed through to the encoder output to ensure that the original data is transmitted without delay, preparing for the generation of subsequent check bytes.

[0156] S104. The state of the internal register of the first-order filter is iteratively processed using the dual-modal XOR tree in the suffix and working mode, and the output terminal outputs the check byte in real time until the number of the output check byte is consistent with the number of the target check byte, so as to complete the dynamic encoding process.

[0157] In this embodiment, one of the two working modes of the dual-modal XOR tree is mainly used in the check byte generation stage. Its core function is to iteratively process the internal register states of all enabled first-order filters after the information data bytes are input, generate check bytes in real time and output them until the number of output bytes is consistent with the number of target check bytes, thus completing the closed-loop encoding process.

[0158] In this step, after all the data bytes to be encoded have been input, the dual-modal XOR tree is switched to the suffix and working mode. This working mode is used to iteratively process the internal register states of all enabled first-order filters, generate check bytes in real time and output them from the encoder output. The check bytes are continuously output until the number of output check bytes is exactly the same as the target number of check bytes, thus completing a complete dynamic encoding process. Then the encoder returns to the idle state and waits for the next set of input parameters and data bytes.

[0159] In this embodiment of the application, the purpose of this step is to complete the generation and output of the check byte during the encoding process, close the entire encoding process, ensure that the output encoded data (original information byte + check byte) strictly conforms to the RS encoding standard, has reliable error detection and correction capabilities, and ensures the reliability of data transmission and storage.

[0160] In this way, the critical path of the encoding process remains logarithmic in length, even in suffix and working modes, resulting in low timing convergence difficulty and ensuring stable operation of the encoder in high-frequency scenarios. The check byte is generated and output in real time, perfectly matching the throughput of the information byte input stage without any bandwidth loss. The output check byte strictly follows the RS encoding standard, which can be directly connected to general protocols and software libraries, resulting in strong compatibility and reducing the difficulty of system integration.

[0161] Optional, please refer to Figure 2 , Figure 2 This is a second flowchart illustrating a dynamic coding method based on parallel filters provided in an embodiment of this application. Figure 2 As shown in the figure, the dynamic encoding method based on parallel filters provided in this application embodiment includes steps S105 to S106 in addition to steps S101 to S104. Specifically, steps S105 to S106 are used to explain the backpressure adaptation logic of the streaming bus, solve the problem of poor backpressure adaptability in the prior art, and ensure the continuity and reliability of the encoding process.

[0162] S105. Monitor the bus back pressure signal fed back by the receiver of each enabled first-order filter in real time, and when the bus back pressure signal is detected, freeze the internal register state of all enabled first-order filters simultaneously, and freeze the encoding operation of the Reed-Solomon encoder at the same time.

[0163] Here, the bus backpressure signal is a status signal fed back by the receiver in a streaming bus (such as the AXI-Stream bus). Essentially, it is a change in the level of the ready signal (a low ready signal indicates that backpressure is triggered, and a high ready signal indicates that backpressure is released). When the receiver cannot receive the encoded data in time (such as when the buffer is full), backpressure is triggered, and the encoder will freeze the encoding state. After the backpressure is released, it will be seamlessly restored to avoid data loss.

[0164] In this step, the bus backpressure signal is a status signal fed back by the receiver in a streaming bus (such as the AXI-Stream bus). When the receiver cannot receive the encoded data in time (such as when the receiver buffer is full), it will feed back a backpressure signal (i.e., the ready signal is pulled low). By monitoring the backpressure signal in real time, the receiver can respond to changes in its status in a timely manner. After detecting the backpressure signal, the register status and encoding operation are immediately frozen, which can effectively avoid data loss and ensure the continuity and reliability of the encoding process.

[0165] For example, throughout the entire process of information data byte input, check byte generation and output, the back pressure signal of the AXI-Stream bus is monitored in real time by the bus monitoring circuit. When the back pressure signal (ready pulled low) is detected from the receiving end, a freeze command is immediately triggered. The internal register states of the five enable filters with indices 0 to 4 are frozen synchronously through the control circuit (stop updating register data). At the same time, all encoding operations of the encoder are frozen (stop data broadcasting, multiplication and addition operations, and check byte output) to ensure that no data is lost.

[0166] S106. When the bus back pressure signal is detected to be released, the freezing of the internal register states of all enabled first-order filters and the freezing of the encoding operation are released to seamlessly restore the encoding operation and data output of the Reed-Solomon encoder.

[0167] In this step, the release of the reverse pressure signal (i.e., the ready signal going high) indicates that the receiver is ready to receive data. At this time, the frozen state is lifted, and the encoding operation is seamlessly resumed without resetting the entire encoding process. This ensures the continuity and integrity of the encoded data, avoids repeated calculations or data corruption, and improves the reliability and efficiency of the encoding process.

[0168] For example, the bus monitoring circuit continuously monitors the bus backvoltage signal. When the backvoltage signal is detected to be released (ready pulled high), a recovery instruction is immediately triggered to release the freeze of the register states of all enable filters and the freeze of encoding operations. This restores the broadcasting of information data bytes, Galois multiplication and addition operations, and the generation and output of check bytes. The encoding process can be seamlessly continued from the state before the freeze without resetting the register state or re-entering data, ensuring the continuity of encoding and data integrity.

[0169] As an example of implementing backpressure adaptation for a streaming bus, this embodiment synchronously executes the streaming bus backpressure adaptation logic throughout the entire process of parallel encoding of information bytes, generation and output of verification bytes, ensuring that the encoding process adapts to the backpressure mechanism of the AXI-Stream bus and avoiding data loss and encoding interruption.

[0170] Specifically, the bus monitoring circuit monitors the backpressure signal (ready signal) fed back from the receiving end in real time. When the ready signal is detected to be low (i.e., backpressure signal triggered), the internal register states of the eight enable filters with indices 0 to 7 are immediately frozen synchronously through the control circuit, stopping all encoding operations (including data broadcasting, Galois multiplication and addition operations, and parity byte generation) to ensure that the current encoding state is not lost. When the ready signal is detected to be high (i.e., backpressure signal released), all frozen states are immediately released, and encoding operations and data output are seamlessly restored from the register states before freezing. There is no need to reset the entire encoding process, which ensures the continuity and integrity of the encoded data and fully demonstrates the good adaptability of this invention to the streaming bus.

[0171] Based on the above, the method described in the embodiments of this application has the following significant beneficial effects.

[0172] Achieve full-granularity dynamic seamless configuration. Precise logical pruning of the parallel first-order filter array is achieved through thermometer code vectors, supporting dynamic switching of any integer target parity byte count from 1 to 32. This eliminates the need for hardware rewiring, separate configuration cycles, and system resets, enabling zero-overhead, seamless parameter switching between data packets. This effectively solves the technical challenges of limited configuration granularity and high configuration latency in existing technologies, making it adaptable to flexible applications with diverse scenarios and error correction requirements.

[0173] The encoding boasts high throughput and low latency. Employing a parallel first-order filter array and a dual-modal XOR tree architecture, all enabled filters execute operations synchronously. The encoding throughput is linearly positively correlated with the number of filters; for example, 16 cores can achieve a peak throughput of 22.4GB / s, fully meeting the design requirement of 20GB / s. Information data bytes are transmitted synchronously without any additional latency, minimizing end-to-end latency. For instance, the encoding latency for 256KB data is ≤30μs, and for 512KB data, it is ≤60μs, perfectly adapting to the needs of high-speed communication, storage, and other high-end scenarios.

[0174] Stable timing performance and low convergence difficulty. The use of bimodal XOR trees (prefix / suffix sum mode) ensures that the critical path length in the encoding process remains logarithmic, not increasing linearly with the number of target parity bytes, effectively reducing the difficulty of timing convergence. At the same time, by optimizing the layout of first-order filters, routing delay is further reduced, for example, ensuring stable operation at a 1.4GHz clock frequency under 6nm process, with stable and reliable timing performance.

[0175] Dynamic power consumption fine-grained control. Through the clock control unit, the clock signal of the disabled filter is precisely turned off, stopping its internal logic flipping. The chip's dynamic power consumption is linearly related to the actual number of filters used (i.e., the number of target parity bytes), which greatly reduces invalid power consumption, significantly improves the chip's energy efficiency ratio, conforms to the design trend of low-power chips, and reduces chip operating costs.

[0176] Natively adapts to streaming bus transmission. It has a complete bus backpressure adaptation mechanism, which quickly freezes the encoding state when encountering backpressure and seamlessly resumes encoding operations after the backpressure is released, without resetting the entire encoding process, effectively avoiding data loss. It natively adapts to mainstream streaming buses such as AXI-Stream, reducing system integration difficulty and improving overall system reliability.

[0177] Hardware area overhead is controllable. By adopting a standardized first-order filter with fixed hard-wired coefficients, the hardware area is significantly reduced compared to the traditional fully parallel matrix architecture. For example, in the 6nm process, the physical logic area of ​​the complete 32-core subsystem is only about 0.07mm², balancing high performance and small size, making it easy to integrate into commercial SoC chips and reducing chip manufacturing costs.

[0178] High compatibility. Encoding results strictly follow GF(2). 8 The RS encoding standard under Galois can quickly connect to existing software and hardware systems, improving the compatibility and practicality of the solution and facilitating its promotion and application.

[0179] The dynamic encoding method based on parallel filters provided in this application, through a parallel Reed-Solomon encoder architecture based on atomic-level first-order decomposition, thoroughly decomposes the hardware implementation of the generator polynomial of this architecture into multiple physically independent and structurally similar first-order filters, and decodes the target check byte count value into a thermometer code vector to logically prune the parallel first-order filter array. It utilizes the prefix and suffix sum modes of a dual-modal XOR tree to achieve parallel encoding of information bytes and generation of check bytes, respectively. This solves the core technical problems of existing RS encoders, such as the inability to achieve full-granularity dynamic seamless switching of check byte count, low encoding throughput, high latency, high chip power consumption, unstable timing performance, and poor adaptability to streaming buses. It achieves dynamic reconstruction of generator polynomials of arbitrary integer order in a single hardware core without resynthesis or circuit reset, thereby realizing real-time dynamic configuration of encoding parameters and efficient encoding operations, while effectively reducing chip power consumption, optimizing timing performance, and improving the continuity and reliability of the encoding process.

[0180] Please see Figure 3 , Figure 4 , Figure 3 This is one of the structural schematic diagrams of a dynamic coding device based on a parallel filter provided in an embodiment of this application. Figure 4 This is a second schematic diagram of a dynamic coding device based on a parallel filter, provided as an embodiment of this application. Figure 3 As shown, the dynamic encoding device 300 includes:

[0181] Data acquisition module 310 is used to acquire the target verification byte count value and multiple information data bytes from external input;

[0182] The logic pruning module 320 is used to decode the target verification byte count value into a thermometer code vector, and based on the thermometer code vector, to perform logic pruning on the parallel first-order filter array, enable the first-order filter corresponding to the target verification byte count value, and connect the first-order filter to a preset dual-modal XOR tree.

[0183] The multiply-add operation module 330 is used to synchronously broadcast the information data byte to all enabled first-order filters using the dual-modal XOR tree in the prefix sum working mode. The first-order filters synchronously perform Galois multiply-add operations to iteratively update the internal register state and synchronously pass the information data byte to the output of the Reed-Solomon encoder.

[0184] The encoding output module 340 is used to iteratively process the internal register state of the first-order filter using the dual-modal XOR tree in the suffix and working mode, and outputs the check bytes in real time from the output terminal until the number of the output check bytes is consistent with the target check byte number value, so as to complete the dynamic encoding process.

[0185] Furthermore, such as Figure 4 As shown, the dynamic encoding device 300 further includes a backpressure adaptation module 350, which is used for:

[0186] The bus backpressure signal fed back by the receiver of each enabled first-order filter is monitored in real time, and when the bus backpressure signal is detected, the internal register state of all enabled first-order filters is frozen synchronously, and the encoding operation of the Reed-Solomon encoder is frozen at the same time.

[0187] When the bus back pressure signal is detected to be released, the freezing of the internal register states of all enabled first-order filters and the freezing of the encoding operation are released to seamlessly restore the encoding operation and data output of the Reed-Solomon encoder.

[0188] The dynamic encoding device based on parallel filters provided in this application embodiment, through a parallel Reed-Solomon encoder architecture based on atomic-level first-order decomposition, thoroughly decomposes the hardware implementation of the generator polynomial of this architecture into multiple physically independent and structurally similar first-order filters, and decodes the target check byte count value into a thermometer code vector to logically prune the parallel first-order filter array. It utilizes the prefix sum and suffix sum modes of the dual-modal XOR tree to realize the parallel encoding of information bytes and the generation of check bytes, respectively. This solves the core technical problems of existing RS encoders, such as the inability to achieve full-granularity dynamic seamless switching of check byte count, low encoding throughput, high latency, high chip power consumption, unstable timing performance, and poor adaptability to streaming buses. It realizes the dynamic reconstruction of generator polynomials of arbitrary integer order in a single hardware core without the need for resynthesis or circuit reset, thereby achieving real-time dynamic configuration of encoding parameters and efficient encoding operations, while effectively reducing chip power consumption, optimizing timing performance, and improving the continuity and reliability of the encoding process.

[0189] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 5 As shown, the electronic device 500 includes a processor 510, a memory 520, and a bus 530.

[0190] The memory 520 stores machine-readable instructions executable by the processor 510. When the electronic device 500 is running, the processor 510 and the memory 520 communicate via the bus 530. When the machine-readable instructions are executed by the processor 510, they can perform the operations described above. Figure 1 as well as Figure 2 The steps of the dynamic coding method based on parallel filters in the method embodiment shown are specifically implemented in the method embodiment and will not be repeated here.

[0191] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the above-described actions. Figure 1 as well as Figure 2 The steps of the dynamic coding method based on parallel filters in the method embodiment shown are specifically implemented in the method embodiment and will not be repeated here.

[0192] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0193] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0194] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0195] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0196] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0197] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A dynamic coding method based on parallel filters, characterized in that, The dynamic coding method is applied to a Reed-Solomon encoder, which is equipped with a parallel first-order filter array. The dynamic coding method includes: Obtain the target verification byte count value and multiple information data bytes from external input; The target verification byte count value is decoded into a thermometer code vector, and based on the thermometer code vector, the parallel first-order filter array is logically pruned to enable the first-order filter corresponding to the target verification byte count value, and the first-order filter is connected to a preset dual-modal XOR tree. The information data byte is synchronously broadcast to all enabled first-order filters using the dual-modal XOR tree in prefix sum working mode. The first-order filters synchronously perform Galois field multiplication and addition operations to iteratively update the internal register state and synchronously pass the information data byte to the output of the Reed-Solomon encoder. The internal register state of the first-order filter is iteratively processed using the bimodal XOR tree in the suffix and working mode, and the output terminal outputs the check byte in real time until the number of the output check byte is consistent with the target check byte number, so as to complete the dynamic encoding process.

2. The method according to claim 1, characterized in that, The parallel first-order filter array is constructed using the following steps: Based on the target order generator polynomial parameters of the Reed-Solomon encoder, the target order generator polynomial of the Galois field is determined, and the target order generator polynomial of the Galois field is factored to decompose the first-order factors corresponding to the linear terms in the Galois field of the target order. Based on each of the first-order factors, a corresponding first-order filter is constructed; wherein, the multiplication coefficients of each first-order filter are fixed by hard-wired connections, and the multiplication coefficients correspond to the coefficients of the first-order factors. The first-order filters are arranged in parallel to form the parallel first-order filter array.

3. The method according to claim 1, characterized in that, The step of decoding the target parity byte count value into a thermometer code vector, and logically pruning the parallel first-order filter array based on the thermometer code vector to enable the first-order filter corresponding to the target parity byte count value, and connecting the first-order filter to a preset dual-modal XOR tree, includes: The target verification byte count value is decoded and converted using a preset combinational logic circuit, and the thermometer code vector used to control the parallel first-order filter array is determined according to a preset value selection rule. The thermometer code vector is synchronously transmitted to the control terminal of each first-order filter in the parallel first-order filter array; For each of the first-order filters, the value of each bit in the thermometer code vector is judged to determine whether the value corresponding to that bit in the thermometer code vector is a first preset value. When the value corresponding to the bit is the first preset value, the first-order filter corresponding to the index of the bit is controlled to enter the working state, and the output of the first-order filter is connected to the preset dual-mode XOR tree; wherein, the number of enabled first-order filters matches the number of target check bytes. When the value corresponding to the bit is not the first preset value, the first-order filter corresponding to the index of the value corresponding to the bit is controlled to enter a sleep state, and the internal register state of the first-order filter is frozen.

4. The method according to claim 3, characterized in that, The step of decoding the target parity byte count value into a thermometer code vector, and logically pruning the parallel first-order filter array based on the thermometer code vector to enable the first-order filter corresponding to the target parity byte count value, and connecting the first-order filter to a preset dual-modal XOR tree, further includes: While synchronously transmitting the thermometer code vector to the control terminal of each of the first-order filters, the thermometer code vector is also synchronously transmitted to the clock control unit of the parallel first-order filter array. The clock control unit outputs a clock shutdown signal to the disabled first-order filter to shut down the clock signal corresponding to the first-order filter and stop the logic flipping inside the first-order filter. The clock control unit is used to maintain the clock signal output of the enabled first-order filter normally, ensuring that the first-order filter can participate in the encoding operation normally.

5. The method according to claim 1, characterized in that, The method of synchronously broadcasting the information data bytes to all enabled first-order filters using the bimodal XOR tree in prefix sum operating mode includes: Each of the information data bytes is synchronously broadcast to all enabled first-order filters, and the broadcast information data bytes are preprocessed using the bimodal XOR tree in prefix sum working mode, and the feedback output signal of each enabled first-order filter is collected in real time. For each enabled first-order filter, the currently input information data byte is XORed with the feedback output signal of the enabled first-order filter preceding that first-order filter to obtain the input signal of that first-order filter. The input signal of each enabled first-order filter is input to that first-order filter.

6. The method according to claim 5, characterized in that, The step of synchronously performing Galois field multiplication and addition operations by the first-order filter to iteratively update the internal register state includes: The current state parameters of the internal registers of each of the first-order filters are read. Based on the input signal and current state parameters corresponding to each first-order filter, the preset Galois domain primitives and the index value of the first-order filter in the parallel first-order filter array, Galois domain multiplication and addition operations are performed to obtain the next state parameters of the internal register of the first-order filter. All enabled first-order filters synchronously perform the Galois field multiply-accumulate operation to iteratively update the internal register state.

7. The method according to claim 1, characterized in that, The dynamic coding method further includes: The bus backpressure signal fed back by the receiver of each enabled first-order filter is monitored in real time, and when the bus backpressure signal is detected, the internal register state of all enabled first-order filters is frozen synchronously, and the encoding operation of the Reed-Solomon encoder is frozen at the same time. When the bus back pressure signal is detected to be released, the freezing of the internal register states of all enabled first-order filters and the freezing of the encoding operation are released to seamlessly restore the encoding operation and data output of the Reed-Solomon encoder.

8. A dynamic coding device based on parallel filters, characterized in that, The dynamic encoding device includes: The data acquisition module is used to acquire the target verification byte count and multiple information data bytes from external input. The logic pruning module is used to decode the target verification byte count value into a thermometer code vector, and based on the thermometer code vector, to perform logic pruning on the parallel first-order filter array, enable the first-order filter corresponding to the target verification byte count value, and connect the first-order filter to a preset dual-modal XOR tree. The multiply-add operation module is used to synchronously broadcast the information data byte to all enabled first-order filters using the dual-modal XOR tree in the prefix sum working mode. The first-order filters synchronously perform Galois multiply-add operations to iteratively update the internal register state and synchronously pass the information data byte to the output of the Reed-Solomon encoder. The encoding output module is used to iteratively process the internal register state of the first-order filter using the bimodal XOR tree in the suffix and working mode, and outputs the check bytes in real time from the output terminal until the number of the output check bytes is consistent with the target number of check bytes, so as to complete the dynamic encoding process.

9. An electronic device, characterized in that, include: The device includes a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. The machine-readable instructions are executed by the processor to perform the steps of the dynamic coding method based on parallel filters as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the steps of the dynamic coding method based on parallel filters as described in any one of claims 1 to 7.

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