RFSoC low-delay optimization method for communication perception integrated system

Abstract

The invention discloses an RFSoC (radio frequency system-on-chip) low-delay optimization method oriented to a communication sensing integrated system. The method comprises the following steps: firstly, establishing a transmitting link and a receiving link of an OFDM (orthogonal frequency division multiplexing) communication system in a programmable logic PL of an RFSoC; data interaction with a processing system PS is realized by adopting an AXI-based streaming interface; a pseudo-random noise PN sequence is inserted into the initial position of a transmission link in a time division multiplexing mode, and cooperative operation of communication and sensing is achieved; carrying out pipelined delay optimization processing on the transmitting link; dMA data path optimization is carried out on a data transmission path on the PS side, and system-level data paths and signal interface modes of an OFDM transmitting link and an OFDM receiving link are optimized on the PL side. According to the method, the parameterization relationship between communication and sensing performance is constructed, so that the system can select proper PN code configuration according to application requirements, and the performance balance between the communication and sensing functions is realized.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication and environmental perception fusion technology, specifically relating to a low-latency optimization method for a radio frequency system-on-a-chip (RFSoC) for integrated communication and perception systems. This method uses the communication baseband and frame structure as the system backbone, and without changing the basic architecture of the communication system, embeds the sensing function into the communication processing link. Based on the RFSoC, it achieves a unified hardware architecture and low-latency collaborative processing for communication and sensing, suitable for applications with high real-time and bandwidth requirements such as high-speed mobile communication, robot control, vehicle-to-everything (V2X), and drone collaboration. Background Technology

[0002] With the development of 5G-A and 6G technologies, wireless systems are evolving from "communication-centric" or "sensing-centric" to "integrated communication and sensing." Integrated Sensing and Communication (ISAC) systems, by reusing spectrum and hardware resources, enable communication links and radar sensing functions to operate collaboratively on a unified platform, significantly improving spectrum efficiency and system integration. However, existing ISAC systems generally face the following key problems: high latency, fragmented links, complex analog links, and lengthy processing paths, making it difficult to meet future requirements for sub-millisecond real-time performance.

[0003] First, existing radar sensing links generally suffer from high processing latency. Traditional sensing systems often employ FMCW, Chirp, or MIMO radar architectures, whose signal processing typically includes multi-stage RF / IF down-conversion, analog filtering, multi-frame accumulation, FFT or pulse compression, and back-end peak detection and Doppler estimation. In these stages, the IF simulator introduces approximately 10-50µs of group delay, and the stabilization time of the analog-to-digital conversion link requires tens of microseconds; while Doppler estimation relies on multi-frame data accumulation, with processing latency often reaching 1-10ms. Furthermore, in traditional platforms, sensing data typically needs to be moved between the sensor front-end, processing chip, and buffer queue; the involvement of the CPU or DSP also introduces additional queuing and scheduling latency of tens to hundreds of microseconds. Therefore, the end-to-end latency of existing sensing links is generally in the range of 0.5-10ms, significantly limiting their deployment in scenarios with extremely high real-time requirements.

[0004] Secondly, the physical separation of communication and sensing links on the hardware platform further exacerbates the overall latency. Many ISAC systems employ a dual-board structure with communication FPGAs and radar DSPs / FPGAs deployed independently. Communication data must pass through a 10-100µs unidirectional delay via PCIe, a 5-50µs transmission delay via Aurora or fiber optic links, a 2-10µs delay due to serialization / deserialization, and additional overhead of tens to hundreds of microseconds caused by multi-level buffering and queue scheduling, further accumulating the overall latency of sensing collaboration to the millisecond level. Traditional OFDM (Orthogonal Frequency Division Multiplexing) communication baseband links on FPGAs or DSPs typically employ a module-serial execution structure: IFFT, cyclic prefix insertion, frame construction, and other processing units run sequentially, and data must wait for the previous module to complete before entering the next module. Therefore, there is significant processing queuing and module-level waiting within the transmission link, resulting in transmitter latency typically reaching hundreds of microseconds, making it difficult to meet the requirements of high real-time sensing systems.

[0005] In existing technologies, Xlinx RFSoC highly integrates multi-channel high-speed analog-to-digital / digital-to-analog converters (ADCs / DACs), programmable logic (PL), and processing system (PS) onto a single chip. This supports direct RF sampling, high on-chip interconnectivity, and flexible baseband processing configurations, providing a solid hardware foundation for building systems with highly integrated communication and sensing functions. However, existing technologies using RFSoC to implement OFDM communication systems employ a serial processing approach, making it difficult to achieve low-latency, multi-stage pipelined operation across modules. Furthermore, existing technologies rely on independent radar waveforms or offline processing links for sensing, failing to coordinate with the communication baseband within the same data path. Therefore, a low-latency, integrated sensing architecture based on RFSoC to implement a hardware pipelined OFDM communication system and the low-complexity sensing characteristics of PN sequences can achieve high-precision sensing while ensuring communication performance and significantly reduce end-to-end latency. This promotes the engineering application of integrated sensing technology in high real-time scenarios, demonstrating significant engineering value and application prospects. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a low-latency optimization method for RFSoC (Radio Frequency System-on-a-Chip) integrated communication and sensing systems. This method implements a low-latency pipelined OFDM communication system on an RFSoC and introduces configurable PN code sequences as sensing signals. Through a systematic analysis of the impact of different PN code lengths on communication bit error rate and sensing accuracy, this invention constructs a parameterized relationship between communication and sensing performance, enabling the system to select appropriate PN code configurations according to application requirements, thus achieving a performance trade-off between communication and sensing functions.

[0007] The technical solution of the present invention includes the following steps:

[0008] In a first aspect, embodiments of this application provide a low-latency optimization method for RFSoC (Radio Frequency Identification System) for integrated communication and sensing systems, comprising the following steps:

[0009] Step 1: Build the transmit and receive links of the OFDM communication system in the programmable logic (PL) of the RFSoC (Radio Frequency System-on-a-Chip).

[0010] Step 2: After the OFDM communication system of PL is built, data interaction with the processing system (PS) is realized based on the AXI-Stream interface.

[0011] Step 3: Insert a pseudo-random noise (PN) sequence at the beginning of the transmit link of the OFDM communication system in a time-division multiplexing manner as a sensing preamble sequence to achieve coordinated operation of communication and sensing.

[0012] Step 4: Perform pipelined delay optimization on the transmit link of the OFDM communication system containing the sensing preamble sequence in the PL.

[0013] Step 5: Optimize the data transmission path using DMA on the PS side, and further optimize the system-level data path and signal interface of the OFDM transmit and receive links by combining the on-chip integration architecture of the RFSoC on the PL side.

[0014] In one possible implementation, step 1 is as follows:

[0015] In the programming logic (PL), a complete OFDM communication system's transmit and receive links are constructed. The transmit link first performs scrambling and convolutional coding on the input bit sequence, followed by pruning and interleaving based on the convolutional coding. Then, modulation mapping is performed, mapping the interleaved bits to complex modulation symbols, and inserting pilots in the frequency domain according to a preset subcarrier structure. After these operations, the OFDM transmit link in the PL sequentially performs inverse fast Fourier transform (IFFT), cyclic prefix addition, and windowing processing to convert the frequency domain data into a time-domain baseband data stream, generating a baseband transmission sequence. This baseband transmission sequence conforms to the OFDM waveform structure requirements and consists of multiple OFDM transmission symbols containing cyclic prefixes arranged in chronological order.

[0016] The baseband transmission sequence is converted from digital to analog and then up-converted to obtain a radio frequency (RF) signal, which is propagated through a wireless channel. The RF signal is sampled and input to the OFDM receiving link for processing. First, frame detection is performed on the obtained sampled data to determine the starting position of the received data corresponding to the baseband transmission sequence in the sampled data stream. Then, the cyclic prefix is ​​removed, and the time-domain data of the valid OFDM symbols is recovered and retained from the OFDM transmission symbols containing the cyclic prefix. Next, a Fast Fourier Transform (FFT) is performed on the valid OFDM symbols to convert them into frequency-domain OFDM subcarrier symbols. Then, channel estimation is performed using pilot subcarriers, and channel equalization and compensation are performed on each subcarrier data. The compensated frequency-domain OFDM subcarrier symbols are demapped and converted into a bitstream. Finally, the demodulated data is obtained by sequentially deinterleaving, Viterbi decoding, and descrambling.

[0017] In one possible implementation, step 2 is as follows:

[0018] A data path based on AXI-Stream is adopted to achieve high-speed data interaction between the PS and PL. The specific AXI-Stream data path is as follows: the PS establishes a data path with the Direct Memory Access Unit (DMA) through the AXI-Stream interface. The DMA is responsible for continuously sending the input bit sequence stored in the PS's memory to the transmit link of the OFDM communication system in the PL; at the same time, the demodulated data output from the receive link of the OFDM communication system in the PL is also sent back to the PS for buffering through the AXI-Stream interface.

[0019] The processing system (PS) establishes a communication connection with the off-chip ultra-low jitter clock generator LMK04828 via a Serial Peripheral Interface (SPI) and writes clock configuration data to the internal register group of the LMK04828 according to a preset clock topology. Under the control of the clock configuration data, the LMK04828 is configured to output at least one low-phase-noise differential reference clock signal to provide a sampling clock reference for the RF system-on-a-chip (RFSoC). In multi-tile or multi-device synchronous application scenarios, the LMK04828 is configured to output multiple phase-consistent differential reference clock signals. Simultaneously with outputting the differential reference clock signal, the LMK04828 synchronously outputs one SYSREF pulse signal.

[0020] The differential reference clock signal is input to a dedicated clock pin of the RFSoC chip and connected to the clock distribution network inside the RFSoC chip. This differential reference clock signal serves as the main clock source for the RFSoC, providing a clock reference for the sampling clock generation units of the ADC and DAC tiles in the RF data converter (RFDC) within the RFSoC. Through the phase-locked loop (PLL) or delay-locked loop (DLL) structure integrated within the RFSoC chip, the RFSoC performs frequency multiplication and phase adjustment based on the differential reference clock signal to generate a high-speed sampling clock that meets the target sampling rate requirements.

[0021] Simultaneously, the SYSREF pulse signal serves as a global synchronization reference, being fed into the RFSoC via a dedicated input pin and distributed to all participating ADC and DAC tiles. In multi-tile operation mode, the sampling state machine within each tile synchronously resets its digital control logic and FIFO pointer upon detecting a valid edge of SYSREF.

[0022] In addition, during the process of writing clock configuration data to the internal register group of LMK04828 via PS, the phase of the SYSREF output of LMK04828 is adjusted to maintain a fixed phase relationship with the reference clock.

[0023] In one possible implementation, step 3 is as follows:

[0024] Sensing functionality is achieved by extending the frame structure of the transmission link in an OFDM communication system.

[0025] A pre-generated pseudo-random noise sequence (PN sequence) is inserted at the beginning of the baseband transmission sequence as a sensing preamble sequence. The PN sequence is transmitted together with the baseband transmission sequence and reflects off targets in the environment during wireless propagation, forming an echo signal containing target information. By configuring PN sequences of different lengths as sensing preamble sequences, different sensing ranging accuracies can be obtained.

[0026] In one possible implementation, the PN sequence is generated using a linear feedback shift register (LFSR). The LFSR has n register cells and operates with a non-zero initial state. At each discrete time step, the LFSR performs modulo-2 addition from the current states of multiple register cells according to a preset feedback polynomial to generate a feedback bit, loads the feedback bit into the first register, and shifts the states of the remaining registers sequentially.

[0027] During each register state update, the output of a predetermined register cell is taken as the sequence bits for the current moment, and these sequence bits are mapped to bipolar values. This process is repeated... Next, the generated length is PN sequence.

[0028] In one possible implementation, the accuracy of the sensing distance measurement is obtained as follows:

[0029] The generated PN sequence is inserted at the beginning of the baseband transmission sequence as a sensing preamble sequence, and time division multiplexing (TDM) is used to make it staggered in time from the subsequent baseband transmission sequence.

[0030] The baseband transmission sequence of the inserted sensing preamble sequence is reflected by the target in the environment during wireless propagation, forming an echo signal containing target information.

[0031] The echo signal is compared with the locally stored original PN sequence. Perform cross-correlation calculations to obtain correlation peaks. Related peaks Location of appearance Time delay relative to the theoretical zero point position This refers to the round-trip propagation time of the electromagnetic wave between the transmission position and the target in the baseband transmission sequence. Based on the stated time delay... Calculate the distance estimate of the target. The calculation formula is as follows:

[0032]

[0033] in The speed of light. Furthermore, the correlation peak positions obtained from the cross-correlation operation... This represents the time delay estimate. The time delay is repeatedly estimated based on multiple frames of echo signals to obtain the statistical error of the distance estimate, which is used to characterize the accuracy of the time delay estimate. The target sensing and ranging accuracy is characterized by the statistical error of the multi-frame distance estimates.

[0034] Deviations exist between different frames. By repeatedly estimating the time delay of multiple frames of echo signals, the statistical error of the distance estimate can be obtained, which is used to characterize the sensing and ranging accuracy of the system. Moreover, the sensing and ranging accuracy is linearly related to the time delay estimation accuracy.

[0035] In one possible implementation, step 4 is as follows:

[0036] Pipeline design is implemented for scrambling, convolutional coding, pruning, interleaving, modulation mapping, pilot insertion, IFFT, and cyclic prefix addition in the transmission link to achieve parallelization of data processing and minimize latency.

[0037] The data interaction method between each processing stage in the transmission link is reconstructed into a parallel transmission method based on AXI-Stream streaming data transmission. This allows processing to begin after receiving partial data even before a complete symbol is formed, and the processing results are passed to subsequent processing stages through a step-by-step handshake. This transforms the transmission link from a traditional sequential execution to an overlapping pipeline structure, thereby reducing the overall processing latency.

[0038] In one possible implementation, a valid / ready handshake mechanism is employed to time-drive the input and output of each processing stage in the transmission link. This transforms the data interaction between processing stages into AXI-Stream-based streaming data transmission, where the output of the preceding processing stage and the receiving status of the subsequent processing stage are coordinated and controlled. This allows each processing stage to dynamically adjust its data transmission rate according to its own processing speed. When a processing stage outputs valid data, it can immediately receive and continue processing as long as the ready signal of the subsequent data processing unit is valid, without waiting for all data of the same processing object to be completely output.

[0039] The AXI-Stream-based streaming data transmission refers to the following: different processing steps in the transmission link operate independently based on the handshake mechanism. Each processing step can start processing as soon as the input data is available, thus allowing multiple processing stages to overlap in time. Based on the above AXI-Stream-based streaming data transmission, the bit-level processing of communication data (scrambling, convolutional coding, pruning, interleaving) and the communication symbol generation process (modulation mapping, pilot insertion) are executed in parallel. Once the complete frequency domain data is ready, the time-domain transform processing (IFFT) can be started without waiting for all other processing stages in the transmission link to complete.

[0040] In one possible implementation, DMA data path optimization is performed on the data transmission path on the PS side, specifically as follows:

[0041] On the PS side, a data transfer method based on Direct Memory Access (DMA) is used to reconstruct the data path between the PS and PL used for transmitting the digital baseband data. Specifically, the input bit sequence used to generate the baseband transmission sequence is read directly from off-chip memory by the DMA controller and continuously fed into the PL-side processing link through the AXI-Stream data path.

[0042] In the specific implementation of the DMA controller reading from off-chip memory, the burst transfer length, AXI-Stream FIFO depth, and transfer arbitration strategy of the DMA are configured to enable DMA-based data transfer to be completed in a continuous burst manner. Accordingly, the DMA transfer delay can be expressed as:

[0043]

[0044] in, Indicates the DMA setup time; Indicates the total amount of data to be transmitted; Indicates the time required for a single burst transmission; For burst length.

[0045] In one possible implementation, the system-level data paths and signal interface methods of the OFDM transmit and receive links are optimized as follows:

[0046] On the PL side, the RF link is reconstructed using the high-speed RF-DAC and RF-ADC built into the RFSoC, combined with on-chip digital up-conversion and down-conversion processing units. The baseband transmission sequence generated in the OFDM communication system's transmit link is directly fed into the RF-DAC to achieve direct RF transmission; the baseband signal received in the OFDM communication system's receive link is directly sampled by the RF-ADC and then converted by the digital down-conversion processor.

[0047] Secondly, embodiments of this application provide a low-latency optimization device for an integrated communication and sensing system (RFSoC), comprising the following modules:

[0048] System building module: Build the transmit and receive links of the OFDM communication system in the programmable logic (PL) of the RFSoC (Radio Frequency System-on-Chip).

[0049] Data interaction module: After the OFDM communication system of PL is built, data interaction with the processing system (PS) is realized based on the AXI-Stream interface.

[0050] A data path based on AXI-Stream is adopted to achieve high-speed data interaction between the PS and PL. The specific AXI-Stream data path is as follows: the PS establishes a data path with the Direct Memory Access Unit (DMA) through the AXI-Stream interface. The DMA is responsible for continuously sending the input bit sequence stored in the PS's memory to the transmit link of the OFDM communication system in the PL; at the same time, the demodulated data output from the receive link of the OFDM communication system in the PL is also sent back to the PS for buffering through the AXI-Stream interface.

[0051] Cooperative operation module: Pseudo-random noise (PN) sequence is inserted at the beginning of the transmit link of the OFDM communication system in a time-division multiplexing manner as a sensing preamble sequence to realize the cooperative operation of communication and sensing.

[0052] Sensing functionality is achieved by extending the frame structure of the transmission link in an OFDM communication system.

[0053] A pre-generated pseudo-random noise sequence (PN sequence) is inserted at the beginning of the baseband transmission sequence as a sensing preamble sequence. The PN sequence is transmitted together with the baseband transmission sequence and reflects off targets in the environment during wireless propagation, forming an echo signal containing target information. By configuring PN sequences of different lengths as sensing preamble sequences, different sensing ranging accuracies can be obtained.

[0054] Pipeline module: Performs pipelined delay optimization on the transmit link of the OFDM communication system containing the sensing preamble sequence in the PL.

[0055] Pipeline design is implemented for scrambling, convolutional coding, pruning, interleaving, modulation mapping, pilot insertion, IFFT, and cyclic prefix addition in the transmission link to achieve parallelization of data processing and minimize latency.

[0056] The data interaction method between each processing stage in the transmission link is reconstructed into a parallel transmission method based on AXI-Stream streaming data transmission. This allows processing to begin after receiving partial data even before a complete symbol is formed, and the processing results are passed to subsequent processing stages through a step-by-step handshake. This transforms the transmission link from a traditional sequential execution to an overlapping pipeline structure, thereby reducing the overall processing latency.

[0057] Optimization module: On the PS side, the data transmission path is optimized using DMA data path optimization, and on the PL side, the system-level data path and signal interface of the OFDM transmit and receive links are further optimized by combining the on-chip integration architecture of the RFSoC.

[0058] Due to the adoption of the above technical solution, the technical progress achieved by this invention compared to the prior art is as follows:

[0059] 1. This invention introduces a multi-stage pipeline structure and a valid / ready handshake mechanism into the OFDM transmit link to achieve parallel operation of processes such as pilot insertion, IFFT, and cyclic prefix addition, reducing the waiting time between each operation and significantly reducing end-to-end latency. By transforming the overall link processing latency from the accumulated latency of the processing processes into the maximum processing latency determined by the critical processing processes, this invention significantly reduces the end-to-end latency of the OFDM transmit link and effectively improves the real-time performance of the system.

[0060] 2. This invention optimizes the data transmission path on the PS side using DMA data path optimization, enabling high-speed direct transfer of the input bit sequence within the chip. This avoids the cache overhead and scheduling delay caused by the ARM processor participating in large-scale data copying. Combined with the built-in RF analog-to-digital converter and digital-to-analog converter resources of the RFSoC, the baseband transmission sequence generated in the OFDM transmit link and the digital processing results obtained in the receive link can be directly output and sampled on the chip. This eliminates the group delay caused by traditional analog up-conversion and down-conversion circuits, thereby further compressing the overall link processing delay.

[0061] 3. This invention introduces a PN sequence for sensing processing while maintaining the communication frame structure. Utilizing the excellent autocorrelation characteristics of the PN sequence, correlation operations are performed on the received signal containing the target echo to estimate the target's round-trip time delay and Doppler shift, thereby adding the ability to sense the target environment outside the communication link. Furthermore, based on the influence of PN sequence length on sensing accuracy and communication resource consumption, this invention supports adaptive adjustment of the PN length and insertion method in different scenarios, enabling the system to achieve a dynamic trade-off between sensing performance and communication performance, thus improving the overall performance of the integrated sensing system.

[0062] In summary, this invention achieves low-latency collaborative processing of communication and sensing functions by optimizing the transmit link and DMA data path of the pipelined OFDM communication system and extending the sensing function based on PN sequence. Compared with the prior art, it significantly improves the system's real-time performance, communication efficiency and sensing capability. Attached Figure Description

[0063] Figure 1 This is a schematic diagram of the overall process of an embodiment of the present invention.

[0064] Figure 2 This is a schematic diagram of the synesthesia time frame structure of the present invention.

[0065] Figure 3 This is a schematic diagram of the OFDM communication system framework implemented in this invention.

[0066] Figure 4This invention relates to an OFDM pipelined transmit link based on a valid / ready handshake mechanism.

[0067] Figure 5 This is a schematic diagram of the OFDM receiving link of the present invention.

[0068] Figure 6 This is a board-level verification diagram of the OFDM transmit link of this invention.

[0069] Figure 7 This is a board-level verification diagram of the OFDM receiver link of the present invention.

[0070] Figure 8 This describes the sensing process of the integrated sensing system of the present invention.

[0071] Figure 9 This describes the RMSE performance of the present invention for different PN sequence lengths.

[0072] Figure 10 This relates to the impact of PN sequence length on communication system performance. Detailed Implementation

[0073] The specific implementation method of the present invention will be further described below with reference to the accompanying drawings.

[0074] This application provides a low-latency optimization method for RFSoC (Radio Frequency Identification System) in a communication-sensing integrated system, including the following steps:

[0075] Step 1: Build the transmit and receive links of the OFDM communication system in the programmable logic (PL) of the RFSoC (Radio Frequency System-on-a-Chip).

[0076] In the programming logic (PL), a complete OFDM communication system's transmit and receive links are constructed. The transmit link first performs scrambling and convolutional coding on the input bit sequence, followed by pruning and interleaving based on the convolutional coding to improve the sequence's time and frequency domain distribution characteristics. Then, modulation mapping is performed, mapping the interleaved bits to complex modulation symbols, and pilots are inserted in the frequency domain according to a preset subcarrier structure for channel estimation and compensation in the receive link. After these operations, the OFDM transmit link in the PL sequentially performs inverse fast Fourier transform (IFFT), cyclic prefix addition, and windowing processing to convert the frequency domain data into a time-domain baseband data stream, generating a baseband transmission sequence. This baseband transmission sequence conforms to the OFDM waveform structure requirements and consists of multiple OFDM transmission symbols containing cyclic prefixes arranged in chronological order.

[0077] The baseband transmission sequence is converted from digital to analog and then up-converted to obtain a radio frequency (RF) signal, which is propagated through a wireless channel. The RF signal is sampled and input to the OFDM receiving link for processing. First, frame detection is performed on the obtained sampled data to determine the starting position of the received data corresponding to the baseband transmission sequence generated by the transmit link in the sampled data stream. Then, the cyclic prefix is ​​removed, and the time-domain data of the valid OFDM symbols is recovered and retained from the OFDM transmission symbols containing the cyclic prefix. Next, a Fast Fourier Transform (FFT) is performed on the valid OFDM symbols to convert them into frequency-domain OFDM subcarrier symbols. Then, channel estimation is performed using pilot subcarriers, and channel equalization and compensation are performed on each subcarrier data. The compensated frequency-domain OFDM subcarrier symbols are demapped and converted into a bit stream. Finally, the demodulated data is obtained by deinterleaving, Viterbi decoding, and descrambling.

[0078] Step 2: After the OFDM communication system of PL is built, data interaction with the processing system (PS) is realized based on the AXI-Stream interface.

[0079] After establishing the transmit and receive links of the OFDM communication system in the PL, this invention employs an AXI-Stream-based data path to achieve high-speed data interaction between the PS and PL. The AXI-Stream-based data path is as follows: the PS establishes a data path with the Direct Memory Access Unit (DMA) via the AXI-Stream interface. The DMA is responsible for continuously transmitting the input bit sequence stored in the PS's memory to the transmit link of the OFDM communication system in the PL. Simultaneously, the demodulated data output from the receive link of the OFDM communication system in the PL is also transmitted back to the PS for buffering via the AXI-Stream interface. This AXI-Stream-based data path uses a streaming transmission method, avoiding full-frame buffering and multiple data copies, thereby reducing data interaction latency between the PS and PL and improving system throughput.

[0080] To ensure the timing stability of the AXI-Stream-based data path and the transmit and receive links of the OFDM communication system within the PL, the processing system (PS) further establishes a communication connection with the off-chip ultra-low jitter clock generator LMK04828 via the Serial Peripheral Interface (SPI), and writes clock configuration data to the internal register group of the LMK04828 according to a preset clock topology. The clock configuration data includes the reference clock output frequency setting, division ratio, phase offset, output enable control parameters, and the enable mode and timing parameters of the SYSREF signal. Under the control of the clock configuration data, the LMK04828 is configured to output at least one low-phase-noise differential reference clock signal to provide a sampling clock reference for the RF System-on-a-Chip (RFSoC); in multi-tile or multi-device synchronous application scenarios, the LMK04828 is configured to output multiple phase-consistent differential reference clock signals. While outputting the differential reference clock signal, the LMK04828 synchronously outputs a SYSREF pulse signal as a global synchronization reference across ADC / DAC tiles to achieve multi-tile sampling timing alignment.

[0081] The differential reference clock signal is input to the dedicated clock pin of the RFSoC chip via differential traces on the PCB where the PS is located, and is connected to the clock distribution network inside the RFSoC chip. This differential reference clock signal serves as the main clock source for the RFSoC, providing a clock reference for the sampling clock generation units of the ADC and DAC tiles in the RF data converter (RFDC) within the RFSoC. Through the phase-locked loop (PLL) or delay-locked loop (DLL) structure integrated within the RFSoC chip, the RFSoC performs frequency multiplication and phase adjustment based on the differential reference clock signal to generate a high-speed sampling clock that meets the target sampling rate requirements, ensuring high accuracy and timing stability during the analog-to-digital / digital-to-analog conversion process.

[0082] Simultaneously, the SYSREF pulse signal serves as a global synchronization reference, being fed into the RFSoC via a dedicated input pin and distributed to all participating ADC and DAC tiles. In multi-tile operation mode, upon detecting a valid edge of SYSREF, the sampling state machine within each tile synchronously resets its digital control logic and FIFO pointer, thereby achieving cross-tile sampling phase alignment. This mechanism is a prerequisite for applications such as multi-channel coherent signal acquisition or beamforming.

[0083] Furthermore, to ensure synchronization accuracy, this invention finely adjusts the phase of the SYSREF output of the LMK04828 during the process of writing clock configuration data to the internal register group of the LMK04828 via the PS, ensuring a fixed phase relationship with the reference clock. Simultaneously, the LMK04828 employs an equal-length, impedance-matched differential routing strategy in its hardware design to minimize the path delay deviation between the SYSREF and the reference clock. This effectively suppresses sampling mismatch caused by clock skew, significantly improving the signal-to-noise ratio and phase consistency of the multi-channel system.

[0084] Step 3: Insert a pseudo-random noise (PN) sequence at the beginning of the transmit link of the OFDM communication system in a time-division multiplexing manner as a sensing preamble sequence to achieve coordinated operation of communication and sensing.

[0085] This step, based on the OFDM communication system described in step 1, expands the frame structure of the OFDM communication system's transmission link to achieve sensing functionality without changing the communication modulation method and demodulation process.

[0086] Based on the baseband transmission sequence described in step 1, a pre-generated pseudo-random noise sequence (PN sequence) is inserted at the beginning of the baseband transmission sequence as a sensing preamble sequence. The PN sequence is transmitted together with the baseband transmission sequence and reflects off targets in the environment during wireless propagation, forming an echo signal containing target information. By configuring PN sequences of different lengths as sensing preamble sequences, different sensing ranging accuracies can be obtained. Since target distance is one of the most fundamental physical parameters in a sensing system, ranging accuracy can serve as an important indicator for evaluating the performance of the sensing function. The specific steps are as follows:

[0087] A fixed-length pseudo-random noise sequence (PN sequence) is pre-generated and used as a sensing leader sequence. The generated PN sequence is as follows:

[0088]

[0089] in, The length of the PN sequence is indicated by a linear feedback shift register (LFSR), which is generated using a linear feedback shift register. The LFSR has n register cells and operates with a non-zero initial state. At each discrete moment, the LFSR performs modulo-2 addition on the current states of multiple register cells according to a preset feedback polynomial to generate a feedback bit, loads the feedback bit into the first register, and shifts the states of the remaining registers sequentially.

[0090] During each register state update, the output of a predetermined register cell is taken as the sequence bits for the current moment, and these sequence bits are mapped to bipolar values. This process is repeated... Next, the generated length is PN sequence.

[0091] Based on the baseband transmission sequence generated in step 1, the PN sequence is inserted into the beginning of the baseband transmission sequence as a sensing preamble sequence. Time division multiplexing (TDM) is used to make it staggered in time from the subsequent baseband transmission sequence.

[0092] The baseband transmission sequence of the inserted sensing preamble sequence is reflected by a target in the environment during wireless propagation, forming an echo signal containing target information; considering the wireless Ricean channel effect and the spatial response of the array antenna, the echo signal is in the... The received signal at each discrete sampling time can be modeled as:

[0093]

[0094] in The equivalent complex channel coefficients of the direct path represent the propagation loss and phase characteristics of the main reflecting target. and These represent the signals at the angle of incidence. and Array space response upon arrival at the array; This indicates that the echo signal experiences a propagation delay. The corresponding delay; The total number of effective transmission paths; Indicates the first Complex channel coefficients of each scattering path; This indicates the delay formed after the echo signal propagates through multiple paths; Indicates the first Additive noise at each discrete sampling time point; Indicates the discrete sampling time index of the echo signal; This represents the total number of discrete sampling points used to process the echo signal during the sensing process.

[0095] The echo signal is compared with the locally stored original PN sequence. Perform cross-correlation calculations to obtain correlation peaks. Related peaks Location of appearance Time delay relative to the theoretical zero point position This refers to the round-trip propagation time of the electromagnetic wave between the transmission position of the baseband transmission sequence in the inserted sensing preamble sequence and the target. Based on the time delay... Calculate the distance estimate of the target. The calculation formula is as follows:

[0096]

[0097] in The speed of light. The correlation peak positions obtained from the cross-correlation calculation. The distance estimate is a time delay value. Due to the influence of noise, multipath propagation, and system processing errors, the distance estimate deviates between different frames. The time delay is repeatedly estimated based on multiple frames of echo signals to obtain the statistical error of the distance estimate, which is used to characterize the accuracy of the time delay estimation. The target sensing and ranging accuracy is characterized by the statistical error of the multi-frame distance estimate.

[0098] In this way, the cross-correlation calculation and time delay estimation based on the echo signal are completed without affecting the normal operation of the downstream communication receiving equipment, thereby realizing the coordinated operation of communication and sensing under the same wireless channel conditions.

[0099] Step 4: Perform pipelined delay optimization on the transmit link of the OFDM communication system containing the sensing preamble sequence in the PL.

[0100] Based on the OFDM transmit link constructed in step 1, in order to solve the problems of large cumulative delay and fixed and unhidden waiting time between modules caused by the traditional serial structure in multi-level modulation processing, this step performs pipelined design on the scrambling code, convolutional coding, pruning, interleaving, modulation mapping, pilot insertion, IFFT and cyclic prefix addition of the transmit link, so as to achieve parallelization of data processing and minimize delay.

[0101] In traditional implementations, processing modules typically operate serially in a "whole frame input - whole frame output" manner. This means that subsequent modules cannot start until the preceding module has completed the entire symbol processing, resulting in a linearly accumulating total link latency. To address this structural bottleneck, this step reconstructs the data interaction between processing stages in the transmit link into a parallel transmission method based on AXI-Stream streaming data transmission. This allows processing to begin after receiving partial data even before a complete symbol is formed, and the processing results are passed to subsequent processes via a step-by-step handshake. This transforms the transmit link from a traditional sequential execution to an overlapping pipeline structure, thereby reducing overall processing latency.

[0102] In its implementation, a valid / ready handshake mechanism is used to time-drive the input and output of each processing stage in the transmission link. This transforms the data interaction between processing stages into AXI-Stream-based streaming data transmission, where the output of the preceding processing stage and the receiving status of the subsequent processing stage are coordinated and controlled. This allows each processing stage to dynamically adjust its data transmission rate according to its own processing speed. When a processing stage outputs valid data, it can immediately receive and continue processing as long as the ready signal of the subsequent data processing unit is valid, without waiting for all data of the same processing object to be completely output. The AXI-Stream-based streaming data transmission means that different processing stages in the transmission link operate independently based on the handshake mechanism. Each processing stage can start processing as soon as the input data availability condition is met, thus allowing multiple processing stages to overlap in time. Based on the above AXI-Stream-based streaming data transmission, the bit-level processing of communication data (scrambling, convolutional coding, pruning, interleaving) and the communication symbol generation process (modulation mapping, pilot insertion) are executed in parallel. Once the complete frequency domain data is ready, the time-domain transformation process (IFFT) can be started without waiting for all other processing stages in the transmission link to be completed.

[0103] Through pipelined processing, this invention transforms the multi-stage processing delay of the original serial link from item-by-item accumulation to a delay determined by the critical module with the longest execution time. For the OFDM transmit chain, the IFFT processing procedure typically has the highest computational complexity; therefore, under pipelined conditions, the end-to-end processing delay of the OFDM communication system transmit chain can be expressed as:

[0104]

[0105] in, This refers to the scrambling processing time. This refers to the processing time for convolutional encoding and pruning; For the processing time of interleaving; The modulation processing time; The processing time for inserting pilot signals; This refers to the processing time for IFFT; Processing time for adding and windowing to the loop prefix.

[0106] Compared to traditional structures

[0107]

[0108] The pipelined architecture significantly reduces module-level cumulative latency and reconstructs a low-latency signal generation path dominated by key computing units.

[0109] Furthermore, thanks to the parallel operation of modules generated by pipelined architecture, when there are differences in the processing speed of different modules, the system can effectively avoid additional latency caused by cache blocking, data accumulation, or inter-stage waiting by utilizing valid / ready, so that the launch chain can still maintain a stable timing relationship under high throughput conditions.

[0110] Through the above-described pipelined design, this step significantly reduces the symbol-level processing latency of the OFDM transmit link, laying the foundation for the sub-millisecond end-to-end performance of the integrated sensing system of this invention.

[0111] Step 5: Based on the completion of the OFDM transmit link pipeline processing in Step 4, perform DMA data path optimization on the PS side, and further optimize the system-level data path and signal interface mode of the OFDM transmit link and receive link by combining the on-chip integration architecture of the RFSoC on the PL side.

[0112] After completing the pipelined processing of the OFDM transmit link, the data transmission path is optimized by DMA on the PS side, and the high-speed analog-to-digital converter and digital-to-analog converter resources integrated on the RFSoC are used on the PL side to enable the transmit link and receive link to be directly connected to the sampling and output process of the radio frequency signal. This further reduces the end-to-end processing latency of the system while keeping the processing process described in step 1 unchanged.

[0113] On the PS side, to address the additional latency introduced by the need for baseband data in traditional communication systems to undergo multi-level buffering, interrupt scheduling, and multiple memory copies before entering the PL-side processing link, this step employs a data transfer method based on Direct Memory Access (DMA) to reconstruct the data path between the PS and PL used for transmitting the digital baseband data. Specifically, the input bit sequence used to generate the baseband transmission sequence is directly read from off-chip memory by the DMA controller and continuously fed into the PL-side processing link through the AXI-Stream data path, achieving zero-copy transmission of the input bit sequence from the storage unit to the processing unit, thereby avoiding data movement and interrupt response processes involving the PS side.

[0114] In the specific implementation of the DMA controller reading from off-chip memory, the burst transfer length, AXI-Stream FIFO depth, and transfer arbitration strategy of the DMA are configured to enable DMA-based data transfer to be completed in a continuous burst manner. Accordingly, the DMA transfer delay can be expressed as:

[0115]

[0116] in, Indicates the DMA setup time; Indicates the total amount of data to be transmitted; Indicates the time required for a single burst transmission; The burst length is specified; proper configuration of the burst length can significantly reduce cache blocking and scheduling wait on the PL side.

[0117] On the PL side, the high-speed RF digital-to-analog converter (RF-DAC) and RF analog-to-digital converter (RF-ADC) built into the RFSoC, combined with on-chip digital up-conversion and down-conversion processing units, are used to reconstruct the RF link that traditionally relies on external analog up-conversion and down-conversion devices. The baseband transmission sequence generated in the OFDM communication system's transmit link is directly fed into the RF-DAC to achieve direct RF transmission; the baseband signal received in the OFDM communication system's receive link is directly sampled by the RF-ADC and converted by the digital down-conversion processor, thus avoiding the fixed group delay introduced by traditional analog mixing and filtering structures.

[0118] By introducing DMA data path optimization on the PS side and optimizing the system-level data path and signal interface of the OFDM transmit and receive links on the PL side, this step simultaneously reduces the data transfer delay across processing units and the analog RF link delay at the system level. This makes the overall latency of the OFDM transmit and receive links mainly determined by the on-chip digital processing, thereby further reducing the system end-to-end latency.

[0119] Figure 1 This is an overall flowchart of a low-latency optimization method for an integrated communication and sensing system according to the present invention. The present invention sequentially performs the following steps on the RFSoC: parameter design, frame structure scheduling, insertion of PN sequence as sensing preamble sequence, pipelined processing of OFDM transmit link, radio frequency signal transmission, wireless channel propagation, radio frequency signal reception, and processing of communication and sensing results, thereby realizing the coordinated operation of communication and sensing functions on the same hardware platform.

[0120] Specifically, the first step is to design and configure the operational parameters required for communication and sensing. These operational parameters include at least frame structure parameters, PN sequence length, and sensing time slots. Communication time slots The modulation scheme and synchronization-related parameters are configured. Based on these parameters, time frames are scheduled and controlled to switch between sensing time slots and communication time slots, providing a unified timing control basis for subsequent transmission and reception processes.

[0121] Under the control of frame structure scheduling, the PN sequence is used as a sensing preamble sequence and inserted into the beginning of the OFDM communication transmission link in a time-division multiplexing manner, so that the sensing preamble and communication data are sent sequentially in the same transmission data stream according to a predetermined timing sequence.

[0122] A wireless channel contains both a direct path for communication data and an echo signal formed by target reflection. The sensing processing step performs cross-correlation calculations between the echo signal and the local PN sequence to achieve correlation detection, time delay estimation, and Doppler analysis; the communication processing step demodulates the communication data.

[0123] Finally, the communication processing results and the sensing processing results are comprehensively analyzed and evaluated to characterize the communication performance and sensing performance, thereby completing the RFSoC low-latency optimization method for integrated communication and sensing systems described in this invention.

[0124] Figure 2 This is a schematic diagram of the frame structure based on time-domain resource partitioning in this invention. This invention employs an Integrated Sensing and Communication (ISAC) frame structure based on time-domain resource partitioning. The system uses fixed-length time frames. As the basic scheduling unit, resources are divided into sensing time slots in each time frame. and communication time slots Both are executed sequentially on the same hardware platform in a time-division multiplexing (TDM) manner, thereby enabling the coordinated operation of sensing and communication functions.

[0125] Specifically, in the sensing time slot Inside, the system transmits a pre-generated PN sequence. This signal, reflected by the target, forms an echo signal. Through processes such as cross-correlation peak detection, time delay estimation, and phase difference calculation, the system obtains the target's distance and velocity information, achieving low-latency sensing processing. Within the communication time slot... Within the system, standard OFDM transmission symbols are transmitted, including pilot subcarriers, data subcarriers, and a cyclic prefix. The OFDM communication system constructed using this invention performs frame detection, FFT, and channel estimation on the receive link, thereby achieving high-throughput data communication.

[0126] The switching between sensing time slots and communication time slots is entirely controlled by on-chip programmable logic (PL). Both share the RFSoC's high-speed ADC / DAC, on-chip high-speed interconnects, and some baseband processing resources. They do not require cross-chip data transmission or rely on external coprocessors, thus achieving efficient collaboration between communication and sensing functions within a single platform.

[0127] Reference Figure 3This invention implements a low-latency OFDM communication system based on RFSOC, comprising a processing system (PS) and a programmable logic unit (PL), and uses an RF data converter to transmit and receive signals. The PS is primarily responsible for AXI-Lite parameter configuration, clock and reset management, and DMA and DDR buffer management. The PL carries a high-speed physical layer pipeline. OFDM_tx includes scrambling, convolutional coding, pruning, interleaving, modulation mapping, pilot insertion (ping-pong RAM parallel read / write), IFFT, cyclic prefix addition, and windowing before DAC input. OFDM_rx includes decimation and mixing of received AD data, frame detection, frequency offset estimation, cyclic prefix removal, FFT, pilot extraction and channel estimation, equalization and compensation, demapping, deinterleaving, Viterbi decoding, and descrambling. Data interaction between OFDM_tx processes uses a valid / ready handshake mechanism for data transmission between upper and lower levels. The PS and PL perform register-level control via AXI-Lite and batch data transfer and buffer scheduling via DMA and DDR.

[0128] Reference Figure 4 The transmit link of the OFDM communication system of the present invention includes, in sequence: scrambling code for reducing data bit correlation; convolutional coding for increasing anti-interference capability; cleavage for adjusting coding rate; interleaving for reducing the impact of burst errors; modulation mapping for mapping bit stream to complex symbols; insertion pilot for inserting known reference signals; inverse fast Fourier transform (IFFT) for realizing frequency domain to time domain conversion; cyclic prefix addition for suppressing multipath interference; and windowing processing for reducing adjacent channel leakage.

[0129] Specifically, in the transmission link of the OFDM communication system of this invention, between each processing step, the preceding processing step pulls the valid signal high after data preparation to indicate that the current data is valid; the following processing step pulls the ready signal high when reception conditions are met to indicate that data can be received. Data will only be successfully transmitted to the next processing step when both the valid signal of the upstream data and the ready signal of the downstream data are high. If the next stage is not ready due to delay or buffer fullness, ready=0 is maintained, and the previous stage will pause data output to avoid data overflow or loss. This handshake mechanism allows each processing step to work in parallel even when calculations overlap: while the IFFT of the previous frame of OFDM symbols is being calculated, the pilot insertion process can process the next frame of data simultaneously, and the cyclic prefix addition process can perform prefix concatenation while the IFFT is being output, thus forming a pipelined hardware execution path.

[0130] Reference Figure 5The OFDM communication system of this invention comprises three parts: time-domain synchronization, frequency-domain synchronization, and decoding. Time-domain synchronization detects the start position of the received frame and performs preliminary compensation for carrier frequency offset and symbol time offset, thereby ensuring the accuracy of subsequent processing. Frequency-domain synchronization utilizes pilot subcarriers to perform channel estimation and subcarrier equalization, while simultaneously tracking and correcting sampling frequency offset and residual phase error to recover the amplitude and phase information of data symbols on each subcarrier. Decoding includes steps such as symbol demapping, interleaving structure recovery, and channel decoding to recover the input bit sequence.

[0131] Reference Figure 6 and Figure 7 In the OFDM transmit and receive link loopback test based on the RFSoC platform described in this invention, the key control signals of the system were observed by an on-chip integrated logic analyzer (ILA), and the processing delays of the transmit link and the receive link were measured and analyzed respectively.

[0132] like Figure 6 As shown, during the internal processing of the transmit link, starting from the generation of the valid data signal in the transmit link, under a processing clock of 20 MHz, after multi-stage pipeline processing within the OFDM transmit link, the data takes approximately 70 clock cycles to reach the DAC output, corresponding to a time length of approximately 3.5 μs. This delay reflects the symbol-level first data crossover delay of the baseband pipeline within the transmit link PL, i.e., the shortest processing time required for the first valid data sample to go from input to output under the valid / ready streaming processing mechanism. Its value is mainly determined by the processing depth of key computation processes such as IFFT. This result demonstrates that the pipelined OFDM transmit link can complete data processing at the symbol-level granularity, avoiding the structural cumulative delay caused by the sequential execution of multi-stage processing processes in traditional serial structures.

[0133] like Figure 7 As shown, under a 100 MHz sampling clock condition, from the start of a valid input data signal in the receive link to the output of a valid result by the baseband processing module of the receive link, approximately 64,543 sampling cycles are elapsed, corresponding to a baseband processing delay of approximately 645.43 μs. This delay belongs to the total end-to-end processing delay of the receive link. Its formation is due to the fact that the receive link includes frame detection and synchronization window waiting, FFT, channel estimation and equalization, and decoding processes, while also incorporating necessary buffering and scheduling overhead. These processes are difficult to completely pipeline or hide in the architecture, thus significantly exceeding the symbol-level processing delay of the transmit link in terms of time scale.

[0134] Comprehensive analysis shows that the approximately 3.5 μs delay in the transmit link corresponds to the arrival time of the first data in the PL's internal baseband pipeline under valid / ready streaming conditions, while the approximately 645 μs delay in the receive link encompasses the complete processing from signal reception to baseband processing output. This comparison clearly demonstrates that the pipelined OFDM transmit link proposed in this invention can effectively suppress the structural cumulative delay caused by the serial processing structure, which is a key factor in achieving low-latency characteristics in the integrated sensing system.

[0135] To further quantitatively analyze the contribution of each functional module to the overall system latency, Table 1 lists the latency of the main processing modules in the OFDM integrated sensing system implemented in this invention. Compared with the millisecond-level processing latency commonly found in traditional sensing systems that employ serial processing structures or cross-board data transmission methods, the architecture proposed in this invention achieves a significant low-latency advantage while ensuring the coordinated operation of communication and sensing functions, thus verifying the effectiveness and engineering feasibility of the proposed low-latency integrated sensing architecture.

[0136] Table 1. Delay of each processing module in the OFDM communication system

[0137]

[0138] To verify the behavior of the PN sequence in the unified sensing architecture constructed in this invention, this embodiment employs the following... Figure 8 A simulation model was used to verify the impact of inserting a PN sequence as a sensing preamble on communication performance. The system channel model was a Rician channel with a Ricean factor of 10 and both transmit and receive gains of 20 dB. The signal-to-noise ratio (SNR) was set to range from −10 dB to 30 dB, and 2000 frames were simulated at different SNRs, with the average bit error rate (BER) calculated. The PN sequence lengths were 0, 7, 15, 31, and 63, and the sequences were superimposed on the received signal with a delay to simulate echo interference of the sensing signal.

[0139] Figure 9 The figure shows the variation of the root mean square error (RMSE) of distance estimation under different PN sequence lengths and various signal-to-noise ratios (SNRs). As can be seen from the figure, the RMSE of all PN sequences gradually decreases with increasing SNR. Longer PN sequences have smaller RMSEs under low SNR conditions, and their performance is better than that of shorter PN sequences. This figure demonstrates that the PN sequence length can affect sensing accuracy; longer sequences generally achieve higher ranging accuracy.

[0140] Figure 10As shown, simulation results indicate that the system BER gradually decreases as the SNR increases. When the PN sequence length increases, the impact on communication performance also increases due to the enhanced interference of the PN echo on the OFDM subcarrier. The BER is lowest when the PN sequence is not superimposed, while the BER is highest when the PN length is 63.

[0141] This embodiment verifies that the architecture proposed in this invention can achieve a significant reduction in end-to-end processing latency while maintaining the coordinated operation of communication and sensing functions, and demonstrates good technical advantages in real-time processing capabilities and sensing performance adjustment.

[0142] This application also provides a low-latency optimization device for RFSoC (Radio-Sensitive System-on-Chips) in a communication-sensing integrated system, comprising the following modules:

[0143] System building module: Build the transmit and receive links of the OFDM communication system in the programmable logic (PL) of the RFSoC (Radio Frequency System-on-Chip).

[0144] Data interaction module: After the OFDM communication system of PL is built, data interaction with the processing system (PS) is realized based on the AXI-Stream interface.

[0145] A data path based on AXI-Stream is adopted to achieve high-speed data interaction between the PS and PL. The specific AXI-Stream data path is as follows: the PS establishes a data path with the Direct Memory Access Unit (DMA) through the AXI-Stream interface. The DMA is responsible for continuously sending the input bit sequence stored in the PS's memory to the transmit link of the OFDM communication system in the PL; at the same time, the demodulated data output from the receive link of the OFDM communication system in the PL is also sent back to the PS for buffering through the AXI-Stream interface.

[0146] Cooperative operation module: Pseudo-random noise (PN) sequence is inserted at the beginning of the transmit link of the OFDM communication system in a time-division multiplexing manner as a sensing preamble sequence to realize the cooperative operation of communication and sensing.

[0147] Sensing functionality is achieved by extending the frame structure of the transmission link in an OFDM communication system.

[0148] A pre-generated pseudo-random noise sequence (PN sequence) is inserted at the beginning of the baseband transmission sequence as a sensing preamble sequence. The PN sequence is transmitted together with the baseband transmission sequence and reflects off targets in the environment during wireless propagation, forming an echo signal containing target information. By configuring PN sequences of different lengths as sensing preamble sequences, different sensing ranging accuracies can be obtained.

[0149] Pipeline module: Performs pipelined delay optimization on the transmit link of the OFDM communication system containing the sensing preamble sequence in the PL.

[0150] Pipeline design is implemented for scrambling, convolutional coding, pruning, interleaving, modulation mapping, pilot insertion, IFFT, and cyclic prefix addition in the transmission link to achieve parallelization of data processing and minimize latency.

[0151] The data interaction method between each processing stage in the transmission link is reconstructed into a parallel transmission method based on AXI-Stream streaming data transmission. This allows processing to begin after receiving partial data even before a complete symbol is formed, and the processing results are passed to subsequent processing stages through a step-by-step handshake. This transforms the transmission link from a traditional sequential execution to an overlapping pipeline structure, thereby reducing the overall processing latency.

[0152] Optimization module: On the PS side, the data transmission path is optimized using DMA data path optimization, and on the PL side, the system-level data path and signal interface of the OFDM transmit and receive links are further optimized by combining the on-chip integration architecture of the RFSoC.

[0153] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0154] The various embodiments in this specification are described in a related manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referred to each other.

[0155] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A low-latency optimization method for RFSoC (Radio Frequency Integrated System) for integrated communication and sensing systems, characterized in that, Includes the following steps: Step 1: Build the transmit and receive links of the OFDM communication system in the programmable logic (PL) of the RFSoC (Radio Frequency System-on-a-Chip). Step 2: After the OFDM communication system of PL is built, data interaction with the processing system PS is realized based on the AXI streaming interface; Step 3: Insert a pseudo-random noise PN sequence as a sensing preamble at the beginning of the transmit link of the OFDM communication system using time-division multiplexing to achieve coordinated operation of communication and sensing. Step 4: Perform pipelined delay optimization on the transmit link of the OFDM communication system containing the sensing preamble sequence in the PL. Step 5: Optimize the data transmission path using DMA on the PS side, and further optimize the system-level data path and signal interface of the OFDM transmit and receive links by combining the on-chip integration architecture of the RFSoC on the PL side.

2. The RFSoC low-latency optimization method for a communication-sensing integrated system according to claim 1, characterized in that, Step 1 is as follows: In the PL, a complete OFDM communication system transmit and receive links are constructed. The transmit link first performs scrambling and convolutional coding on the input bit sequence, and then performs pruning and interleaving on the basis of convolutional coding. Then, modulation mapping is performed, that is, the interleaved bits are mapped to complex modulation symbols, and pilots are inserted in the frequency domain according to the preset subcarrier structure. After the above operations, the OFDM transmit link performs inverse fast Fourier transform (IFFT), cyclic prefix addition and windowing processing in the PL in sequence to convert the frequency domain data into a time domain baseband data stream and generate a baseband transmission sequence. The baseband transmission sequence conforms to the OFDM waveform structure requirements and is composed of multiple OFDM transmission symbols containing cyclic prefixes arranged in chronological order. The baseband transmission sequence is converted from digital to analog and then up-converted to obtain a radio frequency (RF) signal, which is propagated through a wireless channel. The RF signal is sampled and input to the OFDM receiving link for processing. First, frame detection is performed on the obtained sampled data to determine the starting position of the received data corresponding to the baseband transmission sequence in the sampled data stream. Then, the cyclic prefix is ​​removed, and the time-domain data of the valid OFDM symbols is recovered and retained from the OFDM transmission symbols containing the cyclic prefix. Next, a Fast Fourier Transform (FFT) is performed on the valid OFDM symbols to convert them into frequency-domain OFDM subcarrier symbols. Then, channel estimation is performed using pilot subcarriers, and channel equalization and compensation are performed on each subcarrier data. The compensated frequency-domain OFDM subcarrier symbols are demapped and converted into a bit stream. Finally, the demodulated data is obtained by deinterleaving, Viterbi decoding, and descrambling.

3. The RFSoC low-latency optimization method for an integrated communication and sensing system according to claim 2, characterized in that, Step 2 is as follows: A data path based on AXI-Stream is adopted to realize high-speed data interaction between PS and PL. The specific AXI-Stream data path is as follows: the PS side establishes a data path with the Direct Memory Access Unit (DMA) through the AXI-Stream interface. The DMA is responsible for continuously sending the input bit sequence stored in the PS side memory to the transmit link of the OFDM communication system in the PL. At the same time, the demodulated data output from the receive link of the OFDM communication system in the PL is also sent back to the PS side for buffering through the AXI-Stream interface. The processing system PS establishes a communication connection with the off-chip ultra-low jitter clock generator LMK04828 through the serial peripheral interface SPI, and writes clock configuration data into the internal register group of the LMK04828 according to the preset clock topology. Under the control of the clock configuration data, the LMK04828 is configured to output at least one low phase noise differential reference clock signal to provide a sampling clock reference for the RF system-on-a-chip (RFSoC). In multi-chip or multi-device synchronous application scenarios, the LMK04828 is configured to output multiple phase-consistent differential reference clock signals. While outputting the differential reference clock signal, the LMK04828 synchronously outputs a SYSREF pulse signal; The differential reference clock signal is input to a dedicated clock pin of the RFSoC chip and connected to the clock distribution network inside the RFSoC chip. The differential reference clock signal serves as the main clock source of the RFSoC, providing a clock reference for the sampling clock generation units of the ADC and DAC Tile in the RF data converter within the RFSoC. Through the phase-locked loop or delay-locked loop structure integrated inside the RFSoC chip, the RFSoC performs frequency multiplication and phase adjustment based on the differential reference clock signal to generate a high-speed sampling clock that meets the target sampling rate requirements. Meanwhile, the SYSREF pulse signal serves as a global synchronization reference, is sent to the RFSoC through a dedicated input pin, and distributed to all participating ADC and DAC tiles. In multi-tile operation mode, the sampling state machine inside each tile synchronously resets its digital control logic and FIFO pointer after detecting a valid edge of SYSREF. In addition, during the process of writing clock configuration data to the internal register group of LMK04828 via PS, the phase of the SYSREF output of LMK04828 is adjusted to maintain a fixed phase relationship with the reference clock.

4. The RFSoC low-latency optimization method for a communication-sensing integrated system according to claim 3, characterized in that, Step 3 is as follows: Sensing functionality is achieved by extending the frame structure of the transmission link in an OFDM communication system. A pre-generated pseudo-random noise sequence, i.e., a PN sequence, is inserted at the beginning of the baseband transmission sequence as a sensing preamble sequence. The PN sequence is transmitted together with the baseband transmission sequence and is reflected by the target in the environment during wireless propagation, forming an echo signal containing target information. By configuring PN sequences of different lengths as sensing preamble sequences, different sensing ranging accuracies can be obtained.

5. The RFSoC low-latency optimization method for a communication-sensing integrated system according to claim 4, characterized in that, The PN sequence is generated by a linear feedback shift register; the linear feedback shift register has n register units and operates in a non-zero initial state; at each discrete moment, the linear feedback register performs modulo-2 addition from the current state of multiple register units according to a preset feedback polynomial to generate a feedback bit, and loads the feedback bit into the first register, while the states of the remaining registers are shifted sequentially to the next level. During each register state update, the output of a predetermined register unit is taken as the sequence bit at the current moment, and the sequence bit is mapped to a bipolar value; by repeating the above operation... Next, the generation length is PN sequence.

6. The RFSoC low-latency optimization method for a communication-sensing integrated system according to claim 5, characterized in that, The accuracy of the sensing and ranging is obtained as follows: The generated PN sequence is inserted into the beginning of the baseband transmission sequence as a sensing preamble sequence, and time-division multiplexing is used to make it staggered in time from the subsequent baseband transmission sequence. The baseband transmission sequence of the inserted sensing preamble sequence is reflected by a target in the environment during wireless propagation, forming an echo signal containing target information. The echo signal is compared with the locally stored original PN sequence. Perform cross-correlation calculations to obtain correlation peaks. Related peaks Location of appearance Time delay relative to the theoretical zero point position This refers to the round-trip propagation time of the electromagnetic wave between the transmission position and the target in the baseband transmission sequence; based on the time delay... Calculate the distance estimate of the target. The calculation formula is as follows: in The speed of light; further, the correlation peak positions obtained from the cross-correlation operation... This is the estimated time delay value; The time delay is repeatedly estimated based on multiple frames of echo signals to obtain the statistical error of the distance estimate, which is used to characterize the accuracy of the time delay estimation; the target sensing and ranging accuracy is characterized by the statistical error of the multiple frames of distance estimate. There is a discrepancy between different frames; By repeatedly estimating the time delay of multiple echo signals, the statistical error of the distance estimate can be obtained, which is used to characterize the sensing and ranging accuracy of the system. The sensing and ranging accuracy is linearly related to the time delay estimation accuracy.

7. The RFSoC low-latency optimization method for a communication-sensing integrated system according to claim 6, characterized in that, Step 4 is as follows: Pipeline design is implemented for scrambling, convolutional coding, pruning, interleaving, modulation mapping, pilot insertion, IFFT, and cyclic prefix addition in the transmission link to achieve parallelization of data processing and minimize latency. The data interaction method between each processing stage in the transmission link is reconstructed into a parallel transmission method based on AXI-Stream streaming data transmission. This allows processing to begin after receiving partial data even before a complete symbol is formed, and the processing results are passed to subsequent processing stages through a step-by-step handshake. This transforms the transmission link from a traditional sequential execution to an overlapping pipeline structure, thereby reducing the overall processing latency.

8. The RFSoC low-latency optimization method for a communication-sensing integrated system according to claim 7, characterized in that, A valid / ready handshake mechanism is adopted to drive the input and output of each processing stage in the transmission link according to the timing. The data interaction between each processing stage is transformed into a streaming data transmission based on AXI-Stream, which is based on the coordinated control of the output of the preceding processing stage and the receiving status of the subsequent processing stage. This allows each processing stage to dynamically adjust the data transmission according to its own processing rate. When each processing stage outputs valid data, as long as the ready signal of the subsequent data processing unit is valid, it can be received immediately and processing can continue without waiting for all the data of the same processing object to be completely output. The AXI-Stream-based streaming data transmission refers to the following: different processing procedures in the transmission link operate independently based on the handshake mechanism. Each processing procedure can start processing when the input data availability condition is met, thereby allowing multiple processing stages to overlap in time. Based on the above AXI-Stream-based streaming data transmission, the bit-level processing of communication data and the communication symbol generation process are executed in parallel. The bit-level processing includes scrambling, convolutional coding, pruning, and interleaving. The communication symbol generation process includes modulation mapping and pilot insertion. Once the complete frequency domain data is ready, the time domain transformation process can be started without waiting for all other processing stages in the transmit link to complete.

9. A low-latency optimization method for RFSoC in a communication-sensing integrated system according to claim 8, characterized in that, Step 5 is as follows: On the PS side, a data transmission method based on direct memory access (DMA) is adopted to reconstruct the data path between the PS and PL used to transmit the digital baseband data. Specifically, the input bit sequence used to generate the baseband transmission sequence is read directly from the off-chip memory by the DMA controller and continuously sent to the PL-side processing link through the AXI-Stream data path. In the specific implementation of the DMA controller reading from off-chip memory, the burst transfer length, AXI-Stream FIFO depth, and transfer arbitration strategy of the DMA are configured to enable DMA-based data transfer to be completed in a continuous burst manner; correspondingly, the DMA transfer delay is expressed as: in, Indicates the DMA setup time; Indicates the total amount of data to be transmitted; Indicates the time required for a single burst transmission; For burst length; On the PL side, the RF link is reconstructed by utilizing the high-speed RF-DAC and RF-ADC built into the RFSoC, combined with the on-chip digital up-conversion and down-conversion processing units. The baseband transmission sequence generated in the OFDM communication system's transmit link is directly fed into the RF-DAC to achieve direct RF transmission. The baseband signal received in the OFDM communication system's receive link is directly sampled by the RF-ADC and then converted by the digital down-conversion processor.

10. A low-latency optimization device for an integrated communication and sensing system (RFSoC), characterized in that, Includes the following modules: System building module: Build the transmit and receive links of the OFDM communication system in the programmable logic PL of the RFSoC (Radio Frequency System-on-Chip). Data interaction module: After the OFDM communication system of PL is built, data interaction with the processing system PS is realized based on the AXI-Stream interface; A data path based on AXI-Stream is adopted to realize high-speed data interaction between PS and PL. The specific AXI-Stream data path is as follows: the PS side establishes a data path with the Direct Memory Access Unit (DMA) through the AXI-Stream interface. The DMA is responsible for continuously sending the input bit sequence stored in the PS side memory to the transmit link of the OFDM communication system in the PL. At the same time, the demodulated data output from the receive link of the OFDM communication system in the PL is also sent back to the PS side for buffering through the AXI-Stream interface. Cooperative operation module: A pseudo-random noise sequence is inserted at the beginning of the transmit link of the OFDM communication system in a time-division multiplexing manner as a sensing preamble sequence to realize the cooperative operation of communication and sensing; Sensing functionality is achieved by extending the frame structure of the transmission link in an OFDM communication system. A pre-generated pseudo-random noise sequence, namely a PN sequence, is inserted at the beginning of the baseband transmission sequence as a sensing preamble sequence. The PN sequence is transmitted together with the baseband transmission sequence and is reflected by the target in the environment during wireless propagation to form an echo signal containing target information. Different sensing ranging accuracies can be obtained by configuring PN sequences of different lengths as sensing preamble sequences. Pipeline module: Performs pipelined delay optimization on the transmit link of an OFDM communication system containing a sensing preamble sequence in the PL; Pipeline design is implemented for scrambling, convolutional coding, pruning, interleaving, modulation mapping, pilot insertion, IFFT, and cyclic prefix addition in the transmission link to achieve parallelization of data processing and minimize latency. The data interaction method between each processing stage in the transmission link is reconstructed into a parallel transmission method based on AXI-Stream streaming data transmission. This allows processing to begin after receiving partial data even before a complete symbol is formed, and the processing results are passed to subsequent processing stages through a step-by-step handshake. This transforms the transmission link from a traditional sequential execution to an overlapping pipeline structure, thereby reducing the overall processing latency. Optimization module: On the PS side, the data transmission path is optimized using DMA data path optimization, and on the PL side, the system-level data path and signal interface of the OFDM transmit and receive links are further optimized by combining the on-chip integration architecture of the RFSoC.

Images