Magnetic random access memory and manufacturing method thereof
By etching notches in the substrate edge region to remove metal fragments, the defect problem caused by metal residue in magnetic random access memory is solved, thus improving the yield of MRAM arrays.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- ZHEJIANG HIKSTOR TECHOGY CO LTD
- Filing Date
- 2024-10-12
- Publication Date
- 2026-04-14
AI Technical Summary
Magnetic random access memory (MRAM) has metal residue defects in the wafer edge region, which leads to Flake defects and affects the yield of MRAM arrays.
Edge notches are etched to form the edge region of the substrate to remove metal fragments, and defects caused by metal residue are resolved by depositing a magnetic tunneling film structure.
It improves the hard failure yield of magnetic random access memory, reduces wafer surface defects, and enhances the yield of MRAM arrays.
Smart Images
Figure CN121865626A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductors, and in particular to a magnetic random access memory and a method for manufacturing the same. Background Technology
[0002] Magnetic random access memory (MRAM) is a non-volatile memory that uses magnetic tunnel junctions (MTJs) as storage cells, recording binary data by changing the magnetization direction. MTJs are composed of stacked thin films of various materials and require annealing to stabilize device performance. After annealing, defect detection equipment detects numerous flake defects on the wafer surface; these defects are larger than 1 μm and severely impact MRAM array yield.
[0003] Therefore, how to solve the above-mentioned technical problems should be a key focus for those skilled in the art. Summary of the Invention
[0004] The purpose of this application is to provide a magnetic random access memory and its manufacturing method to solve the problem of metal residue defects in the edge region of a wafer and improve yield.
[0005] To address the aforementioned technical problems, this application provides a method for manufacturing a magnetic random access memory, comprising:
[0006] Prepare a substrate with contact holes;
[0007] A metal layer is grown on the upper surface of the substrate;
[0008] Etching the metal layer produces metal fragments in the edge region of the substrate;
[0009] The edge region of the substrate is etched to form an edge notch in the edge region;
[0010] Deposited magnetic tunnel membrane structure.
[0011] Optionally, etching the metal layer to generate metal fragments in the edge region of the substrate includes:
[0012] The metal layer is etched to form a bottom electrode, generating metal fragments in the edge region of the substrate.
[0013] Optionally, etching the metal layer to generate metal fragments in the edge region of the substrate includes:
[0014] Etching the metal layer and the substrate forms a first alignment groove, generating metal fragments in the edge region of the substrate;
[0015] Correspondingly, after depositing the magnetic tunneling membrane structure, the process also includes:
[0016] The metal layer is etched to form the bottom electrode.
[0017] Optionally, after etching the edge region of the substrate to form an edge notch in the edge region, the method further includes:
[0018] The substrate is etched to form a second alignment groove.
[0019] Optionally, after growing a metal layer on the upper surface of the substrate, the method further includes:
[0020] A first hard mask layer is deposited on the metal layer;
[0021] Accordingly, etching the metal layer to form the bottom electrode includes:
[0022] The metal layer and the first hard mask layer are etched to form the bottom electrode and the first hard mask unit layer, the first hard mask unit layer being located on the upper surface of the bottom electrode.
[0023] Optionally, after growing a metal layer on the upper surface of the substrate, the method further includes:
[0024] A second hard mask layer is deposited on the metal layer;
[0025] Accordingly, etching the metal layer and the substrate to form the first alignment groove includes:
[0026] The second hard mask layer, the metal layer, and the substrate are etched to form a first alignment groove;
[0027] Etching the metal layer to form the bottom electrode includes:
[0028] The metal layer and the second hard mask layer are etched to form the bottom electrode and the second hard mask unit layer, the second hard mask unit layer being located on the upper surface of the bottom electrode.
[0029] Optionally, etching the edge region of the substrate to form an edge notch in the edge region includes:
[0030] The edge region of the substrate is etched using a dry etching method to form an edge notch in the edge region, wherein the etching power ranges from 200W to 800W and the etching time ranges from 10s to 30s.
[0031] Optionally, the width of the edge notch in the direction parallel to the upper surface of the substrate ranges from 0.8 mm to 3 mm.
[0032] Optionally, growing a metal layer on the upper surface of the substrate includes:
[0033] A metal layer is grown on the upper surface of the substrate using a sputtering method.
[0034] This application also provides a magnetic random access memory (MRM), which is manufactured using any of the above-described methods for manufacturing MRM.
[0035] The present application provides a method for fabricating a magnetic random access memory (MRM), comprising: preparing a substrate having contact holes; growing a metal layer on the upper surface of the substrate; etching the metal layer to generate metal fragments in the edge region of the substrate; etching the edge region of the substrate to form an edge notch in the edge region; and depositing a magnetic tunneling membrane structure.
[0036] As can be seen, the fabrication method in this application deposits a metal layer on the substrate, and after etching the metal layer, etches the edge region of the substrate to form an edge notch, thereby removing the metal fragments generated in the edge region of the substrate during the etching process, that is, removing the metal residue at the edge of the substrate, solving the fragment defects caused by the metal residue at the edge region, and thus improving the yield of the magnetic random access memory (MRRAM) in terms of hard failure.
[0037] In addition, this application also provides a magnetic random access memory with the above-mentioned advantages. Attached Figure Description
[0038] To more clearly illustrate the technical solutions of the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0039] Figure 1 Images showing the morphology of defects in the wafer edge region in existing technologies;
[0040] Figure 2 Images of residual defects at the edge of a wafer under an optical microscope, as seen in existing technologies.
[0041] Figure 3 Scanning electron microscope (SEM) image of residual defects in the wafer edge region in the prior art;
[0042] Figure 4 The process of fabricating a magnetic random access memory provided in the embodiments of this application. Figure 1 ;
[0043] Figures 5 to 11 The fabrication process of a magnetic random access memory provided in the embodiments of this application Figure 1 ;
[0044] Figure 12 The process of fabricating a magnetic random access memory provided in the embodiments of this application. Figure 2 ;
[0045] Figures 13 to 15 The fabrication process of a magnetic random access memory provided in the embodiments of this application Figure 2 ;
[0046] Figure 16 The process of fabricating a magnetic random access memory provided in the embodiments of this application. Figure 3 ;
[0047] Figures 17 to 18 The fabrication process of a magnetic random access memory provided in the embodiments of this application Figure 3 ;
[0048] Figure 19 The process of fabricating a magnetic random access memory provided in the embodiments of this application. Figure 4 ;
[0049] Figure 20 This is a comparison diagram of the base edge in the embodiments of this application and the base edge region in the prior art;
[0050] In the figure: 1. Substrate, 2. Contact hole, 3. Metal layer, 4. Patterned photoresist, 5. Metal residual defect, 6. Bottom electrode, 7. Edge notch, 8. Magnetic tunnel junction layer structure, 9. First alignment groove, 10. Photoresist, 11. First hard mask layer, 12. First hard mask unit layer. Detailed Implementation
[0051] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are merely some embodiments of the present application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0052] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.
[0053] As described in the background section, numerous Flake defects were found to fall onto the wafer surface after annealing of the magnetic tunnel junction, such as... Figures 1 to 3 As shown, this affects the yield of the MRAM array.
[0054] The applicant discovered that the defect originated from a 0.5mm area at the wafer edge, a region typically characterized by photolithography edge washing and lacking patterns, thus ruling out the influence of the patterning process. Further investigation revealed that the defect was caused by a lower etching rate at the wafer edge during the bottom electrode metal etching process. This resulted in numerous metal residues on the wafer surface. These residues had weak adhesion to the film layer in the subsequently fabricated magnetic tunnel junction. After annealing following the fabrication of the magnetic tunnel junction, the metal residues drifted onto the wafer surface under stress expansion, thus forming the defect.
[0055] In view of this, this application provides a method for manufacturing a magnetic random access memory (MRM). Please refer to [link / reference]. Figure 4 ,include:
[0056] Step S101: Prepare a substrate with contact holes.
[0057] The substrate can be a silicon substrate, and the material of the contact holes can be a metal, such as copper or tungsten.
[0058] Step S102: Grow a metal layer on the upper surface of the substrate.
[0059] The metal layer is used in subsequent fabrication to form the bottom electrode. The thickness of the metal layer can range from 30 Å to 1000 Å, for example, the thickness of the metal layer can be 30 Å, 100 Å, 200 Å, 300 Å, 500 Å, 800 Å, 1000 Å, etc.
[0060] It should be noted that the growth method of the metal layer is not limited in this embodiment and can be selected by the user. For example, the growth method of the metal layer can be sputtering methods such as PVD (Physical Vapor Deposition).
[0061] The material of the metal layer is not limited in this application and can be selected by the applicant. For example, the material of the metal layer can be any one or any combination of Ta, Al, Co, Ti, TaN, TiN, etc.
[0062] Step S103: Etch the metal layer to generate metal fragments in the edge region of the substrate.
[0063] The process of etching the metal layer includes: spin-coating photoresist onto the surface of the metal layer, exposing and developing the photoresist, and then etching the metal layer.
[0064] The edge area of the base is a patternless area.
[0065] Step S104: Etch the edge region of the substrate to form an edge notch in the edge region.
[0066] It should be noted that the etching depth of the substrate edge region in this embodiment is not limited and depends on the situation.
[0067] Step S105: Deposit magnetic tunneling membrane structure.
[0068] The magnetic tunneling membrane structure is etched to form a magnetic tunnel junction.
[0069] The structure of the magnetic tunneling membrane layer and the subsequent processes for fabricating magnetic random access memory can be found in relevant technologies, and will not be elaborated here.
[0070] In this embodiment, the fabrication method involves depositing a metal layer on a substrate, etching the metal layer, and then etching the edge region of the substrate to form an edge notch. This removes the metal fragments generated in the edge region of the substrate during the etching process, i.e., removes the metal residue at the edge of the substrate, thus solving the fragmentation defect caused by the metal residue at the edge region and improving the yield of the magnetic random access memory (MRRAM) in the form of a hard failure.
[0071] A comparative illustration of the etched edge region of the substrate in this application and the unetched edge region in the prior art is shown below. Figure 20 As shown, Figure 20 Image (a) shows the unetched edge of the substrate in the prior art. Figure 20 (b) Image of the etched edge region of the substrate in this application. Figure 20 It is understood that the etching of the substrate edge region in this application completely solves the defects caused by metal fragments.
[0072] Please refer to Figure 5 Based on the above embodiments, in one embodiment of this application, the method for manufacturing a magnetic random access memory may include:
[0073] Step S201: Prepare a substrate with contact holes.
[0074] like Figure 6 As shown, the substrate 1 has a contact hole 2. In this embodiment, the Critical Dimension (CD) of the contact hole 2 can range from 80nm to 120nm.
[0075] For example, the CD of contact hole 2 can be 80nm, 90nm, 100nm, 110nm, 120nm, etc.
[0076] Step S202: Grow a metal layer on the upper surface of the substrate.
[0077] like Figure 7 As shown, metal layer 3 is located on the upper surface of substrate 1.
[0078] In this embodiment, the thickness of the metal layer can range from 20 nm to 50 nm. For example, the thickness of the metal layer can be 20 nm, 30 nm, 40 nm, 50 nm, etc.
[0079] Step S203: Etch the metal layer to form the bottom electrode and generate metal fragments in the edge region of the substrate.
[0080] like Figures 8 to 9 As shown, photoresist is spin-coated onto the metal layer 3, and then the photoresist is exposed and developed to form a patterned photoresist 4. Then, etching is performed to form the bottom electrode 6. At the same time, some metal residual defects 5 exist at the edge of the wafer.
[0081] Step S204: Etch the edge region of the substrate to form an edge notch in the edge region.
[0082] like Figure 10 As shown, an edge notch 7 is formed in the edge region of the etched substrate 1 to remove residual metal defects.
[0083] It should be noted that, after etching the substrate edge and before depositing the magnetic tunneling film structure, the process also includes:
[0084] Backfill the upper surface of the substrate so that the upper surface of the substrate is flush with the upper surface of the bottom electrode.
[0085] Step S205: Deposit the magnetic tunneling membrane structure.
[0086] like Figure 11 As shown, the magnetic tunnel membrane structure 8 is located on the upper surface of the substrate 1, and magnetic tunnel membrane structures 8 are also distributed at the edge notches.
[0087] In this embodiment, the fabrication process of the magnetic random access memory (MRMH) is performed before the fabrication process of the magnetic tunnel junction.
[0088] Please refer to Figure 12 Based on the above embodiments, in one embodiment of this application, the method for manufacturing a magnetic random access memory may include:
[0089] Step S301: Prepare a substrate with contact holes.
[0090] like Figure 6 As shown, the substrate 1 has a contact hole 2.
[0091] In this embodiment, the Critical Dimension (CD) range of the contact hole 2 can be 30nm~80nm.
[0092] For example, the CD of contact hole 2 can be 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, etc.
[0093] Step S302: Grow a metal layer on the upper surface of the substrate.
[0094] like Figure 7 As shown, metal layer 3 is located on the upper surface of the substrate.
[0095] In this embodiment, the thickness of the metal layer 3 can range from 3 nm to 10 nm. For example, the thickness of the metal layer 3 can be 3 nm, 5 nm, 7 nm, 9 nm, 10 nm, etc.
[0096] Step S303: Etch the metal layer and the substrate to form a first alignment groove, generating metal fragments in the edge region of the substrate.
[0097] like Figures 13 to 14 As shown, photoresist 10 is spin-coated onto metal layer 3, and then the photoresist 10 is exposed and developed to form patterned photoresist, and then etched to form the first alignment groove 9. Metal residual defects 5 will be formed at the edge of the wafer.
[0098] The first alignment groove 9 serves as an alignment mark during subsequent etching to form a magnetic tunnel junction, preventing etching deviations.
[0099] Step S304: Etch the edge region of the substrate to form an edge notch in the edge region.
[0100] like Figure 15 As shown, edge notches 7 are formed in the edge region of the etched substrate to remove residual metal defects.
[0101] Step S305: Deposit the magnetic tunneling membrane structure.
[0102] The magnetic tunneling membrane structure is located on the upper surface of the metal layer.
[0103] Step S306: Etch the metal layer to form the bottom electrode.
[0104] In this embodiment, the fabrication process of the magnetic random access memory (MRRAM) is performed after the fabrication process of the magnetic tunnel junction.
[0105] When the fabrication process of the bottom electrode is performed before the fabrication process of the magnetic tunnel junction, based on the above embodiments, in one embodiment of this application, after etching the edge region of the substrate and forming an edge notch in the edge region, the process may further include:
[0106] The substrate is etched to form a second alignment groove.
[0107] The second alignment groove serves as an alignment mark during subsequent etching to form a magnetic tunnel junction, preventing etching deviations.
[0108] When the fabrication process of the bottom electrode is performed before the fabrication process of the magnetic tunnel junction, please refer to [reference needed]. Figure 16 Based on any of the above embodiments, in one embodiment of this application, the method for manufacturing a magnetic random access memory includes:
[0109] Step S401: Prepare a substrate with contact holes.
[0110] like Figure 6 As shown, the substrate 1 has a contact hole 2.
[0111] Step S402: Grow a metal layer on the upper surface of the substrate.
[0112] like Figure 7 As shown, metal layer 3 is located on the upper surface of substrate 1.
[0113] Step S403: Deposit a first hard mask layer on the metal layer.
[0114] like Figure 17 As shown, the first hard mask layer 11 is located on the upper surface of the metal layer 3.
[0115] The thickness of the first hard mask layer 11 can range from 20nm to 50nm, and the specific thickness can be set according to the situation.
[0116] For example, the thickness of the first hard mask layer 11 can be 20nm, 30nm, 40nm, 50nm, etc.
[0117] The material of the first hard mask layer 11 can be an oxide of Si, including but not limited to silicon dioxide, silicon oxynitride, tetraethyl orthosilicate (TEOS), etc.
[0118] It should be noted that the preparation method of the first hard mask layer 11 is not limited in this embodiment, and can be selected by the user.
[0119] As one possible implementation method, growth can be carried out using LPCVD (low pressure chemical vapor deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition).
[0120] The growth temperature of the first hard mask layer 11 can be in the range of 200℃~500℃; the deposition power can be in the range of 300W~800W.
[0121] For example, the growth temperature of the first hard mask layer 11 can be 200℃, 250℃, 300℃, 350℃, 400℃, 450℃, 500℃, etc.; the deposition power can be 300W, 400W, 500W, 600W, 700W, 800W, etc.
[0122] When directly etching the metal layer 3, etching byproducts and photoresist residues accumulate on the surface of the metal layer 3 during the etching process and photoresist removal, exhibiting strong adhesion and making them difficult to remove during subsequent cleaning. This embodiment addresses this by adding an oxide hard mask material (first hard mask layer 11) between the photoresist and the metal layer. This causes the photoresist to accumulate on the surface of the first hard mask layer 11, making it easier to remove during subsequent cleaning processes. This optimizes the removal of polymer residues (formed by direct contact between the photoresist and the metal layer) on the surface of the bottom electrode 6 after etching the metal layer 3.
[0123] Step S404: Etch the metal layer and the first hard mask layer to form the bottom electrode and the first hard mask unit layer, and generate metal fragments in the edge region of the substrate. The first hard mask unit layer is located on the upper surface of the bottom electrode.
[0124] like Figure 18 As shown, during etching, the first hard mask layer 11 and the metal layer 3 are etched simultaneously to form a patterned bottom electrode 6 and a first hard mask unit layer 12.
[0125] Step S405: Etch the edge region of the substrate to form an edge notch in the edge region.
[0126] Step S406: Deposit the magnetic tunneling membrane structure.
[0127] Please refer to the above embodiment for steps S405 and S406, which will not be described in detail here.
[0128] When the fabrication process of the bottom electrode is performed after the fabrication process of the magnetic tunnel junction, please refer to [reference needed]. Figure 19 Based on any of the above embodiments, in one embodiment of this application, the method for manufacturing a magnetic random access memory includes:
[0129] Step S501: Prepare a substrate with contact holes.
[0130] Step S502: Grow a metal layer on the upper surface of the substrate.
[0131] Step S503: Deposit a second hard mask layer on the metal layer.
[0132] The thickness of the second hard mask layer can range from 20nm to 50nm, and the specific thickness can be set according to the situation.
[0133] For example, the thickness of the second hard mask layer can be 20nm, 30nm, 40nm, 50nm, etc.
[0134] The material of the first hard mask layer can be an oxide of Si, including but not limited to silicon dioxide, silicon oxynitride, tetraethyl orthosilicate (TEOS), etc.
[0135] It should be noted that the preparation method of the first hard mask layer is not limited in this embodiment, and can be selected by the user.
[0136] As one possible implementation method, growth can be carried out using LPCVD (low pressure chemical vapor deposition) or PECVD (Plasma Enhanced Chemical Vapor Deposition).
[0137] The growth temperature range for the second hard mask layer can be 200℃~500℃; the deposition power range can be 300W~800W.
[0138] For example, the growth temperature of the second hard mask layer can be 200℃, 250℃, 300℃, 350℃, 400℃, 450℃, 500℃, etc.; the deposition power can be 300W, 400W, 500W, 600W, 700W, 800W, etc.
[0139] When directly etching the metal layer, etching byproducts and photoresist residues accumulate on the metal layer surface during etching and photoresist removal, exhibiting strong adhesion and making them difficult to remove during subsequent cleaning. This embodiment addresses this by adding an oxide hard mask material (a second hard mask layer) between the photoresist and the metal layer. This causes the photoresist to accumulate on the surface of the second hard mask layer, making it easier to remove during subsequent cleaning processes. This optimizes the removal of polymer residues (formed by direct contact between the photoresist and the metal layer) from the electrode surface after metal layer etching.
[0140] Step S504: Etch the second hard mask layer, the metal layer and the substrate to form a first alignment groove, and generate metal fragments in the edge region of the substrate.
[0141] Step S505: Etch the edge region of the substrate to form an edge notch in the edge region.
[0142] Step S506: Deposit the magnetic tunneling membrane structure.
[0143] Step S507: Etch the metal layer and the second hard mask layer to form the bottom electrode and the second hard mask unit layer, the second hard mask unit layer being located on the upper surface of the bottom electrode.
[0144] Based on any of the above embodiments, in one embodiment of this application, etching the edge region of the substrate and forming an edge notch in the edge region includes:
[0145] The edge region of the substrate is etched using a dry etching method to form an edge notch. The etching power ranges from 200W to 800W, and the etching time ranges from 10s to 30s.
[0146] For example, the etching power can be 200W, 300W, 400W, 500W, 600W, 700W, 800W, etc., and the etching time can be 10s, 15s, 20s, 25s, 30s, etc.
[0147] The etching gas can be CF4, CHF3, CCl4, etc., depending on the situation, and no specific limitation is made here.
[0148] Based on any of the above embodiments, in one embodiment of this application, the width W of the edge notch in the direction parallel to the upper surface of the substrate ranges from 0.8 mm to 3 mm.
[0149] For example, the width W of the edge notch can be 0.8mm, 1.2mm, 1.5mm, 2mm, 2.5mm, 3mm, etc.
[0150] Setting the width W of the edge notch to 0.8mm~3mm can ensure that metal defects at the base edge are completely removed and that stability is high.
[0151] Based on any of the above embodiments, in one embodiment of this application, growing a metal layer on the upper surface of the substrate includes:
[0152] A metal layer is grown on the upper surface of the substrate using a sputtering method.
[0153] Metal layers grown by sputtering have advantages such as uniform film formation, high adhesion, and environmental friendliness. However, this embodiment does not specifically limit this aspect; in other methods of this application, PVD (Physical Vapor Deposition) can also be used.
[0154] Based on any of the above embodiments, in one embodiment of this application, before preparing the substrate with contact holes, the method further includes:
[0155] Create through holes in the substrate;
[0156] A contact hole is formed by filling the through hole with metal material.
[0157] This application also provides a magnetic random access memory (MRM), which is manufactured using any of the above-described methods for manufacturing MRM.
[0158] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0159] The magnetic random access memory and its manufacturing method provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the solution and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.
Claims
1. A method for manufacturing a magnetic random access memory, characterized in that, include: Prepare a substrate with contact holes; A metal layer is grown on the upper surface of the substrate; Etching the metal layer produces metal fragments in the edge region of the substrate; The edge region of the substrate is etched to form an edge notch in the edge region; Deposited magnetic tunnel membrane structure.
2. The method for manufacturing a magnetic random access memory as described in claim 1, characterized in that, Etching the metal layer to generate metal fragments in the edge region of the substrate includes: The metal layer is etched to form a bottom electrode, generating metal fragments in the edge region of the substrate.
3. The method for manufacturing a magnetic random access memory as described in claim 1, characterized in that, Etching the metal layer to generate metal fragments in the edge region of the substrate includes: Etching the metal layer and the substrate forms a first alignment groove, generating metal fragments in the edge region of the substrate; Correspondingly, after depositing the magnetic tunneling membrane structure, the process also includes: The metal layer is etched to form the bottom electrode.
4. The method for manufacturing a magnetic random access memory as described in claim 2, characterized in that, After etching the edge region of the substrate to form an edge notch in the edge region, the method further includes: The substrate is etched to form a second alignment groove.
5. The method for manufacturing a magnetic random access memory as described in claim 2, characterized in that, After growing a metal layer on the upper surface of the substrate, the method further includes: A first hard mask layer is deposited on the metal layer; Accordingly, etching the metal layer to form the bottom electrode includes: The metal layer and the first hard mask layer are etched to form the bottom electrode and the first hard mask unit layer, the first hard mask unit layer being located on the upper surface of the bottom electrode.
6. The method for manufacturing a magnetic random access memory as described in claim 3, characterized in that, After growing a metal layer on the upper surface of the substrate, the method further includes: A second hard mask layer is deposited on the metal layer; Accordingly, etching the metal layer and the substrate to form the first alignment groove includes: The second hard mask layer, the metal layer, and the substrate are etched to form a first alignment groove; Etching the metal layer to form the bottom electrode includes: The metal layer and the second hard mask layer are etched to form the bottom electrode and the second hard mask unit layer, the second hard mask unit layer being located on the upper surface of the bottom electrode.
7. The method for manufacturing a magnetic random access memory as described in claim 1, characterized in that, Etching the edge region of the substrate to form an edge notch in the edge region includes: The edge region of the substrate is etched using a dry etching method to form an edge notch in the edge region, wherein the etching power ranges from 200W to 800W and the etching time ranges from 10s to 30s.
8. The method for manufacturing a magnetic random access memory as described in claim 1, characterized in that, The width of the edge notch in the direction parallel to the upper surface of the substrate ranges from 0.8 mm to 3 mm.
9. The method for manufacturing a magnetic random access memory as described in any one of claims 1 to 8, characterized in that, Growing a metal layer on the upper surface of the substrate includes: A metal layer is grown on the upper surface of the substrate using a sputtering method.
10. A magnetic random access memory, characterized in that, The magnetic random access memory is manufactured using the method described in any one of claims 1 to 9.