Semiconductor wafer and preparation method thereof

Abstract

The embodiment of the invention provides a semiconductor wafer and a preparation method thereof, the semiconductor wafer comprises a substrate, a polycrystalline silicon layer and a composite buffer layer arranged between the substrate and the polycrystalline silicon layer, the composite buffer layer comprises a first sub-layer used for providing a preset stress, and a second sub-layer used for providing a second stress; the average tensile stress of the polycrystalline silicon layer is at least partially counteracted; and a second sub-layer disposed between the first sub-layer and the polysilicon layer, the second sub-layer having a higher in-plane stiffness than the first sub-layer for dispersing stress generated in the polysilicon layer in a plane parallel to an interface between the first sub-layer and the second sub-layer, and transmitting the dispersed stress to the first sub-layer. Through the function-decoupled composite buffer layer structure, accurate allocation and efficient compensation of non-uniform tensile stress in the polycrystalline silicon thin film are realized, so that the problem of excessive warping of a wafer is fundamentally solved.

Description

Technical Field

[0001] This application relates to the field of semiconductor materials technology, and in particular to semiconductor wafers and methods for their fabrication. Background Technology

[0002] In the manufacturing of integrated circuits and microelectromechanical systems, chemical vapor deposition is a key process for preparing functional thin films such as polycrystalline silicon.

[0003] However, due to the inherent differences in physical properties such as the coefficient of thermal expansion between the thin film material and the substrate, thermomechanical stress inevitably accumulates inside the wafer during the cooling stage after high-temperature deposition. If this stress is not effectively controlled, it will lead to macroscopic warping deformation of the wafer. As device manufacturing processes continue to shrink, the requirements for depth of focus and surface flatness in photolithography are becoming increasingly stringent. Excessive wafer warping not only causes photolithography overlay alignment errors and focal plane shift, but in severe cases, it can also lead to wafer transport failures or thin film delamination, significantly reducing production yield.

[0004] Therefore, how to effectively manage stress in complex thin-film stacked structures to maintain wafer flatness is an important technical issue that urgently needs to be addressed in the semiconductor manufacturing field. Summary of the Invention

[0005] In view of this, embodiments of this application provide semiconductor wafers and their fabrication methods, aiming to achieve precise allocation and efficient compensation of non-uniform tensile stress in polycrystalline silicon thin films through a functionally decoupled composite buffer layer structure, thereby fundamentally solving the problem of excessive wafer warpage.

[0006] The technical solution of this application is implemented as follows: In a first aspect, embodiments of this application provide a semiconductor wafer. The semiconductor wafer includes: a substrate, a polysilicon layer, and a composite buffer layer disposed between the substrate and the polysilicon layer. The composite buffer layer includes: The first sublayer is used to provide a preset stress to at least partially offset the average tensile stress of the polysilicon layer; and A second sublayer is disposed between the first sublayer and the polysilicon layer. The second sublayer has a higher in-plane stiffness than the first sublayer. It is used to disperse the stress generated in the polysilicon layer in a plane parallel to the interface between the first and second sublayers and to transfer the dispersed stress to the first sublayer.

[0007] In some examples, the first sublayer contains silicon nitride.

[0008] In some examples, the second sublayer contains hexagonal boron nitride.

[0009] In some examples, the in-plane stiffness of the second sublayer is greater than or equal to 300 GPa.

[0010] In some examples, the first sublayer contains silicon nitride, and a Si-NB bonding interface is formed between the first and second sublayers.

[0011] In some examples, the thickness of the Si-NB bonding interface is between 1 nm and 2 nm.

[0012] In some examples, the thickness of the first sublayer is greater than the thickness of the second sublayer.

[0013] In some examples, the thickness of the first sublayer is between 250 nm and 350 nm.

[0014] In some examples, the thickness of the second sublayer is between 30 nm and 70 nm.

[0015] In some examples, the polycrystalline silicon layer includes a seed layer and a host layer, with the seed layer disposed between the second sublayer and the host layer.

[0016] In some examples, the maximum warpage of the semiconductor wafer is no greater than 37 μm.

[0017] In some examples, the uniformity of the polycrystalline silicon layer is not less than 98%.

[0018] Secondly, embodiments of this application provide a method for fabricating a semiconductor wafer. The fabrication method includes: A first sublayer is formed on the substrate, the first sublayer being used to provide a predetermined stress; A second sublayer is formed on the first sublayer, the second sublayer having a higher in-plane stiffness than the first sublayer; and A polycrystalline silicon layer is deposited on the second sublayer; The second sublayer is configured to disperse the stress generated in the polysilicon layer in a plane parallel to the interface between the first and second sublayers, and to transfer the dispersed stress to the first sublayer.

[0019] In some examples, the step of forming the first sublayer includes depositing silicon nitride; and the step of forming the second sublayer includes depositing hexagonal boron nitride.

[0020] In some examples, the step of depositing a silicon nitride layer includes forming a nitrogen-rich interface on the surface of the substrate prior to depositing the silicon nitride layer.

[0021] In some examples, the steps for depositing a hexagonal boron nitride layer include: A nucleation step is performed on the silicon nitride layer, the nucleation step including introducing a boron-containing precursor at a first flow rate to form boron nitride (BN) nucleation sites on the silicon nitride layer; and A growth step is performed at the BN nucleation site, the growth step including introducing a boron-containing precursor at a second flow rate greater than the first flow rate.

[0022] In some examples, the nucleation and growth steps cause the boron-containing precursor to react with the surface of the silicon nitride layer, thereby forming a silicon-nitrogen-boron (Si-NB) bonding interface between the silicon nitride layer and the hexagonal boron nitride layer.

[0023] In some examples, the step of depositing a polycrystalline silicon layer includes: At a first temperature, a polycrystalline silicon seed layer is deposited on the second sublayer; and On the seed layer, a polycrystalline silicon host layer is deposited at a second temperature, which is higher than the first temperature.

[0024] This application provides a semiconductor wafer and a method for fabricating the same. A composite buffer layer is introduced between the substrate and a polysilicon layer in the semiconductor wafer. This composite buffer layer is further divided into two functional sub-layers. The first sub-layer provides a preset stress to at least partially offset the average tensile stress of the polysilicon layer. The second sub-layer, disposed between the first sub-layer and the polysilicon layer, has a higher in-plane stiffness than the first sub-layer. It first intercepts localized, non-uniform stress concentrations generated by the polysilicon layer and disperses and homogenizes the stress in a plane parallel to the interface. The homogenized stress is then efficiently transferred to the first sub-layer for compensation. This synergistic mechanism of stress homogenization followed by compensation fundamentally solves the problem of non-uniform stress concentration that traditional single buffer layers cannot effectively address. This significantly reduces the maximum warpage value of the wafer while significantly reducing the proportion of stress concentration areas, thus improving the flatness of the wafer and the stress uniformity of the thin film. Attached Figure Description

[0025] Figure 1 A schematic cross-sectional view of a semiconductor wafer provided for an embodiment of this application.

[0026] Figure 2 A schematic cross-sectional view of a semiconductor wafer provided for another embodiment of this application.

[0027] Figure 3 A schematic diagram illustrating the mechanism of stress in a composite buffer layer in a semiconductor wafer, provided for embodiments of this application.

[0028] Figure 4 A schematic cross-sectional view of a semiconductor wafer provided for yet another embodiment of this application.

[0029] Figure 5 The embodiments of this application provide a flowchart of a method for fabricating a semiconductor wafer. Detailed Implementation

[0030] The technical solutions in this application will now be clearly and completely described with reference to the accompanying drawings.

[0031] The coefficient of thermal expansion of polycrystalline silicon is approximately 4.2 × 10⁻⁶. -6 / ℃, while that of a single-crystal silicon substrate is only 2.6×10. -6 / ℃, the two have a ΔCTE = 1.6 × 10 -6 Significant differences in temperature. During the cooling phase after deposition, for example, from 640°C to room temperature, the polycrystalline silicon layer exhibits a significantly stronger shrinkage tendency than the substrate, thereby inducing enormous tensile stress within the wafer. Through in-depth research and failure analysis of the wafer's warping behavior and its underlying mechanisms, it was noted that although the mismatch in thermal expansion coefficients between the polycrystalline silicon film and the monocrystalline silicon substrate is the main macroscopic driving force for tensile stress, models based solely on the difference in macroscopic thermal expansion coefficients cannot fully explain the complex deformation behavior observed in the experiments.

[0032] To address this tensile stress problem, after analysis and research, it was considered to introduce a buffer layer with compressive stress characteristics, such as a silicon nitride layer, to balance the wafer through a stress offsetting mechanism.

[0033] However, experiments and research revealed that although the warpage of wafers with a silicon nitride layer was improved compared to wafers without a buffer layer, the residual warpage value remained high, and the wafers exhibited complex, non-axisymmetric twisted shapes, such as butterfly or saddle-shaped warpage. This result indicates that a single homogeneous buffer layer cannot achieve ideal stress balance.

[0034] To address the aforementioned phenomenon, further microstructural analysis was conducted. The analysis revealed a key physical fact: the tensile stress within the polycrystalline silicon thin film is not uniformly distributed on the plane. This stress non-uniformity stems from the randomness and inhomogeneity of grain growth during polycrystalline silicon deposition.

[0035] Specifically, the grain size distribution on the surface of polycrystalline silicon grown by low-pressure chemical vapor deposition exhibits significant differences. In regions with larger and smaller grain sizes, the difference in grain boundary density leads to a microscopic gradient in the contraction force generated during cooling. This results in the polycrystalline silicon layer actually being a complex stress field composed of countless localized tensile points with varying intensities.

[0036] Based on the discovery of this microscopic non-uniformity, the fundamental mechanical cause of the failure of the traditional single solution was identified: attempting to use a macroscopically uniform planar compressive stress field, i.e., a homogeneous buffer layer, to counteract a microscopically non-uniform, multi-point concentrated tensile stress field, i.e., a polycrystalline silicon layer, inevitably leads to localized stress mismatch. In localized areas with high tensile stress, the uniform buffer layer cannot provide sufficient reverse support; while in areas with low tensile stress, the buffer layer may cause overcompensation.

[0037] To resolve this deep-seated contradiction, a composite stress regulation mechanism was conceived, which is functionally decoupled into two cooperating physical processes: first, a mechanism is needed to intercept and eliminate local stress peaks from the polysilicon layer; subsequently, a mechanism is needed to provide macroscopic reverse stress to balance the overall thermal expansion coefficient mismatch. The non-uniform stress of the polysilicon acts directly on the silicon nitride layer, causing the silicon nitride layer to collapse locally at pressure points, failing to change the non-uniformity of the pressure distribution.

[0038] However, if a high-stiffness intermediate layer is placed between the silicon nitride layer and the polysilicon layer, the intermediate layer, with its high in-plane stiffness, will rapidly disperse the pressure points of the polysilicon layer in the planar direction, transforming them into uniform surface pressure acting on the silicon nitride layer.

[0039] Based on this, this application proposes to embed a stress homogenizing layer with high in-plane stiffness between the polycrystalline silicon layer and the stress compensation layer. After screening, hexagonal boron nitride was found to be an ideal material for the aforementioned intermediate layer due to its unique two-dimensional layered structure and in-plane Young's modulus of over 300 GPa.

[0040] Subsequent experimental data verified the correctness of this theoretical model: when a hexagonal boron nitride (6h-BN) layer was introduced as an intermediate layer, in conjunction with a silicon nitride layer, the maximum warpage of the wafer was significantly reduced to 37 μm, and the stress uniformity index was reduced from 50% to 15% of the baseline.

[0041] The following section will detail the specific implementation structure based on the above findings and mechanism analysis.

[0042] See Figure 1 The diagram shows a schematic cross-sectional view of a semiconductor wafer 100 provided in an embodiment of this application. The semiconductor wafer 100 mainly includes three core parts: a substrate 10 at the bottom, a functional composite buffer layer 20 in the middle, and a polysilicon layer 30 at the top.

[0043] Substrate 10 serves as the mechanical support foundation for the entire semiconductor wafer, providing a stable substrate for the subsequent growth of various functional layers. In the embodiments of this application, substrate 10 can be a single-crystal silicon substrate, which has good mechanical strength, thermal stability, and crystal integrity, and can meet the stringent requirements of semiconductor manufacturing processes for substrate materials.

[0044] In some alternative embodiments, the substrate 10 may also be a substrate of other semiconductor materials, such as a silicon carbide substrate, as long as it can provide a compatible surface environment for the growth of the composite buffer layer 20 and the polysilicon layer 30 and meet the mechanical and thermal requirements for device manufacturing.

[0045] A polysilicon layer 30 is deposited on top of the composite buffer layer 20. In semiconductor processes, the thickness of the polysilicon layer 30 is typically on the order of micrometers, for example, 1 to 2 micrometers.

[0046] See Figure 2 The composite buffer layer 20 is disposed between the substrate 10 and the polysilicon layer 30, playing a crucial role in connecting the two layers. The composite buffer layer 20 is a heterogeneous stacked structure, which is functionally decoupled into two cooperating sublayers: the first sublayer 21 and the second sublayer 22. The two can be tightly bonded through the Si-NB bonding interface 23 to ensure smooth stress transfer and structural stability.

[0047] The first sublayer 21 is formed directly on the surface of the substrate 10, or on top of an existing thin oxide layer on the substrate surface. When a thin oxide layer is present, its thickness is typically no more than 5 nm to avoid affecting the adhesion between the first sublayer 21 and the substrate 10 and the stress transfer efficiency. The first sublayer 21 can serve as a stress compensation mechanism. Mechanically, the first sublayer 21 is fabricated to have a predetermined compressive stress state. The direction of the compressive stress is opposite to the direction of the tensile stress generated by the polysilicon layer 30. When the tensile stress above attempts to bend the wafer, the compressive stress of the first sublayer 21 generates a reverse torque, thereby macroscopically offsetting or balancing most of the average tensile stress.

[0048] In terms of specific material selection, the first sublayer 21 may contain, for example, silicon nitride (SiN). x Silicon nitride materials are deposited using specific processes, such as introducing excess ammonia gas during the initial deposition phase, resulting in an N / Si ratio greater than 1.33. This process promotes the formation of a dense Si-N network structure in the film. This structure exhibits a high atomic packing density at the microscopic level, with bond lengths of approximately 1.73 Å and bond energies of approximately 4.5 eV, thus displaying significant compressive stress characteristics at the macroscopic level.

[0049] To provide sufficient stress compensation, the first sublayer 21 typically needs to have a certain physical thickness, which can be greater than the thickness of the second sublayer 22. For example, the thickness of the first sublayer 21 can range from 250 nm to 350 nm. If the thickness is less than 250 nm, the provided compressive stress is insufficient and cannot effectively offset the tensile stress of the polysilicon layer, resulting in limited improvement in wafer warpage. If the thickness is greater than 350 nm, on the one hand, it will lead to stress accumulation in the first sublayer itself, which may cause the risk of interface delamination between the first sublayer and the substrate or the second sublayer; on the other hand, it will increase process costs and deposition time, reducing production efficiency.

[0050] In some examples, the thickness of the first sublayer 21 can be set to 300 nm. In this case, the compressive stress of the first sublayer 21 is approximately 200 MPa, which can offset about 68% of the tensile stress of the 1 μm thick polycrystalline silicon layer. The wafer warpage can be reduced from 140 μm without a buffer layer to about 65 μm (see data from control group 1 below). At the same time, the stress accumulation of the first sublayer itself is only 120 MPa, which is far lower than its bonding strength with the substrate (approximately 200 MPa), eliminating the risk of interface peeling. In addition, the deposition time corresponding to a thickness of 300 nm is relatively short, achieving a balance between production efficiency and cost, making it suitable for large-scale mass production.

[0051] The second sublayer 22 is located between the first sublayer 21 and the polysilicon layer 30, adjacent to the stress source. Functionally, the second sublayer 22 is defined as a stress homogenization mechanism. The core physical characteristic of the second sublayer 22 is its high in-plane stiffness, i.e., strong resistance to in-plane deformation. The in-plane stiffness of the second sublayer 22 is designed to be significantly higher than that of the first sublayer 21.

[0052] Figure 3 The working principle of the composite buffer layer 20 is illustrated through a mechanical transmission path. The downward arrows in the figure represent tensile stress from the polysilicon layer 30, and the uneven distribution of downward arrows represents uneven tensile stress. When these locally concentrated stresses are transmitted to the second sublayer 22, due to its higher modulus, the second sublayer 22 does not conform to local deformation like a soft material, but maintains planar rigidity. This rigidity forces the local point stresses to rapidly diffuse and redistribute in a plane parallel to the interface, as shown by the downward arrows in the figure. After filtering and homogenization by the second sublayer 22, the originally high-gradient local stress is transformed into a uniformly distributed surface stress. Subsequently, this homogenized stress is transmitted to the underlying first sublayer 21. At this point, the first sublayer 21 faces a more uniform stress field, and its originally homogeneous compressive stress can efficiently and perfectly cancel out the tensile stress across the entire plane.

[0053] In some embodiments, the second sublayer 22 may comprise hexagonal boron nitride. Hexagonal boron nitride is a typical two-dimensional layered material, whose atoms are bonded by strong covalent bonds, giving it a high in-plane Young's modulus. Experimental tests show that the in-plane stiffness of the second sublayer 22 can reach or exceed 300 GPa. Considering cost and process control, the thickness of the second sublayer 22 is, for example, between 30 nm and 70 nm, and further, 50 nm. This thickness is sufficient to establish a rigid mechanical shielding layer without introducing additional growth stress due to excessive thickness. To ensure that interlayer slippage or delamination does not occur between the first sublayer 21 and the second sublayer 22 under enormous thermal stress, the interfacial bonding strength between them is crucial. See also Figure 2This illustrates the internal interface of the composite buffer layer 20. A unique Si-NB bonding interface 23 exists between the first sublayer 21, such as a silicon nitride layer, and the second sublayer 22, such as hexagonal boron nitride. This bonding interface 23 is not an adhesive layer introduced through an additional deposition step, but rather a transition zone naturally formed during the early stages of the growth of the second sublayer 22 through an in-situ chemical reaction between the precursor gas and the substrate surface.

[0054] Specifically, the first sublayer 21 is treated as a nitrogen-rich surface during preparation, containing a large number of highly reactive nitrogen atom dangling bonds. When a boron-containing precursor, such as boron trichloride, is deposited on the second sublayer 22 and contacts this surface, boron atoms utilize their empty orbitals to undergo a strong Lewis acid-base reaction with the lone pair electrons of nitrogen atoms, forming a stable Si-NB chemical bond network. This process is accompanied by atomic-scale interdiffusion and recombination, forming a transition layer with a thickness of approximately 1 nm to 2 nm. This relatively thin Si-NB bonding interface 23 tightly binds the two layers together, ensuring that stress can be smoothly and undamagedly transferred from the second sublayer 22 to the first sublayer 21, achieving coupling of mechanical properties.

[0055] Furthermore, to further optimize the growth quality of the polysilicon layer 30 and reduce its stress non-uniformity, the polysilicon layer 30 is also designed as a double-layer structure in the vertical direction. For example... Figure 4 As shown, the polycrystalline silicon layer 30 includes a seed layer 31 and a host layer 32. The seed layer 31 is located directly above the second sublayer 22. Since the surface of the second sublayer 22, particularly hexagonal boron nitride, is chemically inert and lacks dangling bonds, it is difficult for silicon atoms to nucleate directly on it. Therefore, a thin seed layer 31, for example, 5 nm to 10 nm thick, is first deposited as a template for subsequent growth. The host layer 32 then undergoes rapid homoepitaxial growth based on the seed layer 31, forming a thicker film, for example, with a thickness of 1 μm or more. This seed-induced growth strategy effectively improves the grain uniformity of the host layer 32, reducing stress concentration at its source.

[0056] Some embodiments of this application also provide a method for fabricating the aforementioned semiconductor wafer 100. This fabrication method achieves atomic-level assembly and performance tuning of each functional layer by precisely controlling the reaction conditions. See also Figure 5 The preparation method mainly includes steps S100, S200 and S300.

[0057] In step S100, a first sublayer is formed on the substrate, the first sublayer being used to provide a preset stress.

[0058] Specifically, first, a clean substrate 10, such as a standard-sized single-crystal silicon wafer, is provided. The substrate 10 is then placed into the reaction chamber of a low-pressure chemical vapor deposition apparatus.

[0059] The goal of this step is to deposit a first sublayer 21 with compressive stress characteristics, such as a silicon nitride layer. To obtain a dense structure and excellent interface properties, this step includes a critical nitride-rich pretreatment process.

[0060] Before or at the initial stage of deposition, the temperature of the reaction chamber is set to the first process temperature, for example, 800°C. A high flow rate of nitrogen source gas, such as ammonia, is introduced into the chamber. The ammonia flow rate can be set to 600 standard cubic centimeters per minute (sccm). At the high temperature, the ammonia decomposes to produce highly reactive nitrogen atoms, which react with the silicon surface of substrate 10 to form a nitrogen-rich interface layer. This nitrogen-rich interface not only improves the adhesion of subsequent thin films but also lays the foundation for the subsequent compressive stress formation of silicon nitride. For example, this pretreatment process can last for approximately 2 minutes.

[0061] Subsequently, while maintaining the ammonia flow, a silicon source gas, such as dichlorosilane (SiH2Cl2) or silane (SH4), is introduced. The flow rate of the silicon source gas is set to 200 sccm. At this time, the pressure in the reaction chamber is maintained at approximately 0.5 Torr. During this stage, it is necessary to strictly control the gas ratio to ensure that nitrogen is in excess relative to silicon in the reaction atmosphere, for example, an N / Si ratio greater than 1.33.

[0062] Deposition continues until the first sublayer 21 reaches a preset thickness, such as 300 nanometers.

[0063] In step S200, a second sublayer is formed on the first sublayer, the second sublayer having a higher in-plane stiffness than the first sublayer.

[0064] After the first sublayer 21 is formed, a second sublayer 22 with high in-plane stiffness, such as a hexagonal boron nitride layer, is then constructed on its surface.

[0065] First, a heating operation is performed. Since high-quality crystallization of hexagonal boron nitride typically requires higher energy, the temperature of the reaction chamber is increased from 800°C to a second process temperature, such as 950°C. The heating rate can be controlled at approximately 10°C per minute. During the heating process, ammonia and argon are introduced at flow rates of, for example, 500 sccm and 1000 sccm respectively, to maintain a reducing atmosphere within the chamber and protect the surface state of the first sublayer 21.

[0066] Once the temperature stabilizes at 950℃, the deposition of hexagonal boron nitride begins. This deposition process is finely divided into nucleation and growth steps.

[0067] First, the nucleation step is performed. At this point, a boron-containing precursor, such as boron trichloride (BCl3), is introduced into the chamber. Crucially, a low initial flow rate, such as 100 sccm, is used. The influent time is also short, such as 30 seconds. The low flow rate limits the amount of reactant supplied, allowing boron atoms sufficient time to find the lowest-energy binding sites on the nitrogen-rich surface of the first sublayer 21. Since the surface of the first sublayer 21 is rich in dangling nitrogen bonds, boron atoms preferentially react with these nitrogen atoms. This reaction process not only forms the initial nucleation sites for hexagonal boron nitride, but more importantly, it constructs the aforementioned Si-NB bonding interface 23 in situ between the two layers.

[0068] Next, the growth step is performed. After the nucleation sites are formed, the flow rate of the boron-containing precursor is rapidly increased to a second flow rate, which is significantly greater than the first flow rate, for example, increased to 300 sccm. This ample supply of reactants allows the hexagonal boron nitride crystal to grow rapidly in two dimensions, centered on the nucleation sites, in a direction parallel to the substrate surface. This growth step continues until the second sublayer 22 reaches a predetermined thickness, for example, 50 nm.

[0069] In step S300, a polycrystalline silicon layer is deposited on the second sub-layer.

[0070] Finally, a polycrystalline silicon layer 30 is deposited on the second sublayer 22. This embodiment employs a variable-temperature two-step deposition method.

[0071] First, a cooling operation is performed. The temperature of the reaction chamber is reduced from 950°C to the third process temperature, for example, 620°C. The cooling rate can be controlled at approximately 15°C per minute.

[0072] At the third process temperature, a silicon source gas, such as silane (SiH4) at a flow rate of 300 sccm, is introduced, and the chamber pressure is controlled at approximately 0.1 Torr. Under these conditions, silicon atoms slowly deposit on the surface of the second sublayer 22, forming a thin and dense seed layer 31 with a thickness of approximately 5 nm to 10 nm.

[0073] Subsequently, a second heating process is performed. The temperature is slightly increased to the fourth process temperature, for example, 640°C. The heating rate can be controlled at 5°C per minute. At this temperature, silicon source gas continues to be introduced, and the host layer 32 is rapidly grown on top of the seed layer 31. By dynamically adjusting the reaction pressure, the non-uniformity caused by gas consumption can be compensated, ensuring that the thickness uniformity of the host layer 32 is within 3%.

[0074] To verify the actual effectiveness of the composite buffer layer technology proposed in this application, a series of rigorous comparative experiments were designed and implemented. Single-crystal silicon wafers of the same specifications were selected as substrates, and the same fabrication process was performed in the same equipment.

[0075] The experiment was set up with four groups of samples: Reference group: Polycrystalline silicon layer is deposited directly on the substrate.

[0076] Control group 1: Only one 300nm silicon nitride prestress layer was deposited between the substrate and the polysilicon layer.

[0077] Control group 2: Only one 50 nm hexagonal boron nitride layer was deposited between the substrate and the polysilicon layer.

[0078] Implementation Group 1: Using the technical solution of this application, a composite buffer layer consisting of a 300nm silicon nitride layer and a 50nm hexagonal boron nitride layer is deposited between the substrate and the polysilicon layer.

[0079] The experimental results are shown in the table below:

[0080] The test results are analyzed below.

[0081] Regarding stress uniformity: The baseline group: SIRD 40DU% is 50%, which means that the stress deviation in 50% of the wafer surface area exceeds 40MPa. This is due to the uneven grain size inside the polysilicon layer, which leads to local stress concentration. Furthermore, there is no buffer layer to homogenize the stress, resulting in extremely uneven stress distribution. Control group 1: When the SIRD 40DU% decreased to 30%, the compressive stress of the silicon nitride layer could partially offset the tensile stress, but it could not homogenize the non-uniform stress, and there was still a large stress deviation in 30% of the area. Control group 2: SIRD 40DU% decreased to 26%. The high in-plane stiffness of the hexagonal boron nitride layer can disperse local stress, but it lacks reverse stress compensation and cannot fundamentally solve the stress problem. Implementation Group 1: SIRD 40DU% is only 15%, the stress homogenization and stress compensation synergistic mechanism of the composite buffer layer plays a role in achieving excellent stress uniformity.

[0082] Regarding the maximum warpage value: Reference group: The maximum warpage value is 140μm, which far exceeds the process requirements because the tensile stress of the polycrystalline silicon layer is completely applied to the substrate. Control group 1: The maximum warpage value was 65μm. Although there was an improvement, it was still higher than the process requirements. A single silicon nitride layer could not completely offset the tensile stress, and the non-uniform stress caused non-axisymmetric warpage. Control group 2: The maximum warpage value was 118 μm, which was only slightly lower than the baseline group. The hexagonal boron nitride layer could not provide reverse stress compensation, and the tensile stress still caused severe warpage. Implementation Group 1: The maximum warpage value is 37μm, which is far below the process requirements. The composite buffer layer achieves efficient stress balance and has minimal residual stress.

[0083] Regarding film uniformity Reference group: Thin film uniformity 85%, no buffer layer on substrate surface, uneven silicon atom nucleation; Control group 1: The film uniformity is 90%, and the surface flatness of the silicon nitride layer is better than that of the bare substrate, but its own thickness uniformity is still affected; Control group 2: The film uniformity was 94%, and the surface roughness of the hexagonal boron nitride layer was low, providing a better surface for the growth of polycrystalline silicon layers; Implementation Group 1: Thin film uniformity of 98%, with the synergistic effect of the composite buffer layer, the hexagonal boron nitride layer ensuring uniform nucleation, and the silicon nitride layer avoiding thickness fluctuations caused by stress.

[0084] Summary and Advantages The semiconductor wafer and its fabrication method provided in this application address the shortcomings of existing technologies through innovative composite buffer layer design and precise process control. First, the synergistic mechanism of the second sublayer homogenizing stress and the first sublayer compensating stress in the composite buffer layer solves the problem of non-uniform stress concentration, significantly reducing wafer warpage and stress inhomogeneity. Furthermore, the in-situ formation of the Si-NB bonding interface enhances the interface bonding strength, improves the long-term thermal stability of the composite buffer layer, and ensures stable high-temperature process performance of the device. In addition, the structure of the seed layer and the main layer, combined with the high flatness of the hexagonal boron nitride layer, improves the uniformity of the polycrystalline silicon thin film, meeting the requirements of high-performance devices.

[0085] It should be noted that the technical solutions described in this application can be combined arbitrarily without conflict.

[0086] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor wafer, characterized in that, include: Substrate, polysilicon layer, and composite buffer layer disposed between the substrate and the polysilicon layer. The composite buffer layer includes: A first sublayer is used to provide a preset stress to at least partially offset the average tensile stress of the polysilicon layer; and A second sublayer is disposed between the first sublayer and the polysilicon layer. The second sublayer has a higher in-plane stiffness than the first sublayer. It is used to disperse the stress generated in the polysilicon layer in a plane parallel to the interface between the first sublayer and the second sublayer, and to transfer the dispersed stress to the first sublayer.

2. The semiconductor wafer according to claim 1, characterized in that, The first sublayer comprises silicon nitride; the second sublayer comprises hexagonal boron nitride.

3. The semiconductor wafer according to claim 2, characterized in that, The in-plane stiffness of the second sublayer is greater than or equal to 300 GPa.

4. The semiconductor wafer according to claim 1, characterized in that, The thickness of the first sublayer is greater than the thickness of the second sublayer.

5. The semiconductor wafer according to claim 4, characterized in that, The thickness of the first sublayer is between 250 nm and 350 nm.

6. The semiconductor wafer according to claim 4 or 5, characterized in that, The thickness of the second sublayer is between 30 nm and 70 nm.

7. The semiconductor wafer according to claim 1, characterized in that, The polycrystalline silicon layer includes a seed layer and a main layer, wherein the seed layer is disposed between the second sub-layer and the main layer.

8. The semiconductor wafer according to claim 1, characterized in that, The maximum warpage of the semiconductor wafer is no greater than 37 μm.

9. The semiconductor wafer according to claim 1, characterized in that, The uniformity of the polycrystalline silicon layer is not less than 98%.

10. A method for fabricating a semiconductor wafer, characterized in that, The preparation method includes: A first sublayer is formed on the substrate, the first sublayer being used to provide a predetermined stress; A second sublayer is formed on the first sublayer, the second sublayer having an in-plane stiffness higher than that of the first sublayer; and A polycrystalline silicon layer is deposited on the second sub-layer; The second sublayer is configured to disperse the stress generated in the polysilicon layer in a plane parallel to the interface between the first and second sublayers, and to transfer the dispersed stress to the first sublayer.

11. The method for preparing a semiconductor wafer according to claim 10, characterized in that, The step of forming the first sublayer includes depositing a silicon nitride layer; and the step of forming the second sublayer includes depositing hexagonal boron nitride.

12. The method for preparing a semiconductor wafer according to claim 11, characterized in that, The step of depositing the silicon nitride layer includes forming a nitrogen-rich interface on the surface of the substrate before depositing the silicon nitride layer.

13. The method for fabricating a semiconductor wafer according to claim 11, characterized in that, The step of depositing the hexagonal boron nitride layer includes: A nucleation step is performed on the silicon nitride layer, the nucleation step comprising introducing a boron-containing precursor at a first flow rate to form boron nitride nucleation sites on the silicon nitride layer; and A growth step is performed at the boron nitride nucleation site, the growth step including introducing the boron-containing precursor at a second flow rate greater than the first flow rate.

14. The method for preparing a semiconductor wafer according to claim 13, characterized in that, The nucleation step and the growth step cause the boron-containing precursor to react with the surface of the silicon nitride layer, thereby forming a silicon-nitrogen-boron bonding interface between the silicon nitride layer and the hexagonal boron nitride layer.

15. The method for fabricating a semiconductor wafer according to claim 10, characterized in that, The step of depositing the polycrystalline silicon layer includes: At a first temperature, a polycrystalline silicon seed layer is deposited on the second sublayer; and A polycrystalline silicon host layer is deposited on the seed layer at a second temperature, which is higher than the first temperature.

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