Solar cell and method for manufacturing solar cell

Abstract

The invention discloses a solar cell and a manufacturing method of the solar cell. The solar cell comprises a P-type doping structure located on the back face of a silicon substrate, an N-type doping structure located on the back face of the silicon substrate, a spacer region located between the P-type doping structure and the N-type doping structure, a first electrode located on the back face of the P-type doping structure and a second electrode located on the back face of the N-type doping structure. And the width of the P-type doping structure is greater than that of the N-type doping structure. According to the solar cell, the width of the P-type doping structure is designed to be larger than that of the N-type doping structure, generation, separation and collection of photon-generated carriers are facilitated, and the cell efficiency can be improved.

Description

Cross-references to related applications

[0001] This application is a divisional application of Chinese invention patent application No. 202411205043.3, filed on August 29, 2024, entitled "Solar Cell". Technical Field

[0002] This invention relates to the field of photovoltaics, and more particularly to a solar cell and a method for manufacturing a solar cell. Background Technology

[0003] Back contact (BC) batteries have both positive and negative electrodes located on the back of the battery, which reduces the current transmission path and lowers resistance; in addition, the absence of grid lines on the front improves light absorption efficiency and enhances battery performance.

[0004] The existing BC battery has poor light absorption on the back side, which hinders the improvement of battery efficiency.

[0005] In view of this, it is necessary to provide an improved solar cell to solve the above-mentioned technical problems. Summary of the Invention

[0006] This invention provides a solar cell and a method for manufacturing a solar cell, which facilitates the generation, separation, and collection of photogenerated carriers and can improve cell efficiency.

[0007] To achieve one of the aforementioned objectives, the present invention employs the following technical solution: A solar cell includes a P-type doped structure on the back side of a silicon substrate, an N-type doped structure on the back side of the silicon substrate, a spacer region between the P-type doped structure and the N-type doped structure, a first electrode on the back side of the P-type doped structure, and a second electrode on the back side of the N-type doped structure, wherein the P-type doped structure is higher than the N-type doped structure in the direction from the front side to the back side of the silicon substrate.

[0008] In an optional embodiment, the silicon substrate is an N-type silicon substrate, and the P-type doped structure forms a P-type doped structure with the N-type silicon substrate. An N-junction is formed between the N-type doped structure and the N-type silicon substrate. N+ junction, the P The area of ​​the region containing the N-junction is greater than the N-junction. The area of ​​the region containing the N+ junction.

[0009] In one alternative embodiment, the P-type doped structure is higher than the N-type doped structure in the direction from the front to the back of the silicon substrate.

[0010] In one optional embodiment, the P-type doped structure is a P-type diffusion region formed by P-type doping from the back side of the silicon substrate to the front side at a predetermined depth, and the height difference between the back surface of the N-type doped structure and the back surface of the P-type doped structure is 0.5 to 1.5 times the diffusion depth of the P-type diffusion region.

[0011] In an optional embodiment, the diffusion depth of the P-type diffusion region is 0.5 μm to 1.0 μm, and the dark saturation current density J0 of the P-type diffusion region is 2 fA / cm². 2 ~4fA / cm 2 .

[0012] In one optional embodiment, the P-type diffusion region includes a gate line region and a non-gate line region, wherein the doping concentration of the gate line region is greater than the doping concentration of the non-gate line region, and the first electrode is in contact with the gate line region.

[0013] In one optional embodiment, the sheet resistance of the gate line region is 80 ohm / sq to 130 ohm / sq, and the sheet resistance of the non-gate line region is 200 ohm / sq to 400 ohm / sq.

[0014] In one optional implementation, the diffusion depth of the gate region is greater than the diffusion depth of the non-gate region.

[0015] In one optional embodiment, the N-type doped structure is recessed from the back side of the silicon substrate toward the front side; the N-type doped structure is an N-type tunneling passivation contact structure disposed on the back side of the silicon substrate, the N-type tunneling passivation contact structure including at least one first tunneling layer and an N-type doped polycrystalline silicon layer located on the side of each first tunneling layer away from the silicon substrate.

[0016] In one optional embodiment, the N-type tunneling passivation contact structure includes at least two first tunneling layers, and the second electrode is in contact with at least one of the other N-type doped polysilicon layers except for the one closest to the silicon substrate.

[0017] In one optional embodiment, when the first tunneling layer is SiOx, the thickness is between 1.4 nm and 2.3 nm; when the first tunneling layer is SiC, the thickness is between 1 nm and 1.8 nm.

[0018] In one optional embodiment, the N-type doped structure is recessed from the back side to the front side of the silicon substrate; the N-type doped structure is an N-type diffusion region formed by diffusion from the recessed back surface to the front surface to a predetermined depth.

[0019] In one optional embodiment, the spacer region is recessed from the back side of the silicon substrate toward the front side, and the recess depth is 1 to 1.5 times the diffusion depth of the P-type diffusion region.

[0020] In one optional embodiment, the P-type doped structure is a P-type tunneling passivation contact structure located on the back side of the silicon substrate. The P-type tunneling passivation contact structure includes at least one second tunneling layer and a P-type doped polysilicon layer located on the side of each second tunneling layer facing away from the silicon substrate. The height difference between the back surface of the N-type doped structure and the back surface of the P-type doped structure is 0.5 to 1.5 times the thickness of the P-type tunneling passivation contact structure.

[0021] In one optional embodiment, the N-type doped structure is an N-type diffusion region formed by diffusion from the back side of the silicon substrate to the front side.

[0022] In one optional embodiment, the spacer region is recessed from the back side of the silicon substrate toward the front side, and the recess depth is 1 to 1.5 times the diffusion depth of the N-type diffusion region.

[0023] In an optional embodiment, the N-type doped structure is an N-type tunneling passivation contact structure disposed on the back side of the silicon substrate, the N-type tunneling passivation contact structure including at least one first tunneling layer and an N-type doped polycrystalline silicon layer located on the side of each first tunneling layer facing away from the silicon substrate.

[0024] In one optional embodiment, the height difference between the back surface of the N-type doped structure and the back surface of the P-type doped structure is 1 μm to 10 μm.

[0025] In one optional embodiment, the width of the interval region is 10μm to 150μm.

[0026] In one optional embodiment, the width of the P-type doped structure is greater than the width of the N-type doped structure.

[0027] In one optional embodiment, the back side of the solar cell is further provided with a back passivation layer and a back antireflection layer, the first electrode passes through the back antireflection layer and the back passivation layer and contacts the P-type doped structure, and the second electrode passes through the back antireflection layer and the back passivation layer and contacts the N-type doped structure.

[0028] In an optional embodiment, the solar cell further includes a front passivation layer and a front antireflection layer sequentially disposed on the front side of the silicon substrate.

[0029] To achieve one of the aforementioned objectives, the present invention also employs the following technical solution: A method for manufacturing a solar cell, characterized by comprising: providing a silicon substrate; forming a P-type doped structure on the back side of the silicon substrate, forming an N-type doped structure on the back side of the silicon substrate, wherein a spacer region is provided between the P-type doped structure and the N-type doped structure; forming a first electrode on the back side of the P-type doped structure, and forming a second electrode on the back side of the N-type doped structure.

[0030] In an optional embodiment, the P-type doped structure is a P-type diffusion region formed by diffusion from the back side of a silicon substrate to the front side to a predetermined depth, wherein the P-type diffusion region includes a gate line region and a non-gate line region; the step of forming the P-type diffusion region includes: depositing a boron source layer on the back side of the silicon substrate; performing laser scanning on a portion of the silicon substrate to form the heavily doped gate line region; and then performing diffusion in the region corresponding to the subsequently formed non-gate line region to form the P-type diffusion region including the gate line region and the non-gate line region.

[0031] In an optional embodiment, the P-type doped structure is a P-type tunneling passivation contact structure located on the back side of a silicon substrate. The P-type tunneling passivation contact structure includes at least one second tunneling layer and a P-type doped polysilicon layer located on the side of each second tunneling layer away from the silicon substrate. The step of forming the P-type doped structure includes: depositing at least one second tunneling layer on the back side of the silicon substrate, and forming intrinsic polysilicon on the side of each second tunneling layer away from the silicon substrate; and doping the intrinsic polysilicon by tubular diffusion to form the P-type doped polysilicon layer.

[0032] The beneficial effects of the present invention are: the solar cell of the present invention, by designing the width of the P-type doped structure to be greater than the width of the N-type doped structure, is conducive to the generation, separation and collection of photogenerated carriers, and can improve the cell efficiency. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention; Figure 2 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention; Figure 6 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention; Figure 7This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention; Figure 9 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention; Figure 11 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention; Figure 12 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention; Figure 13 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention; Figure 14 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention; Figure 15 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention; Figure 16 This is a schematic diagram of the structure of a solar cell according to one embodiment of the present invention.

[0034] Among them, 100-solar cell, 1-silicon substrate, 2-P-type doped structure, 21-gate region, 22-non-gate region, 23-second tunneling layer, 24-N-type doped polycrystalline silicon layer, 3-N-type doped structure, 31-first tunneling layer, 32-N-type doped polycrystalline silicon layer, 33-N-type diffusion region, 4-isolation region, 5-back passivation layer, 6-back antireflection layer, 7-front passivation layer, 8-front antireflection layer, 91-first electrode, 92-second electrode. Detailed Implementation

[0035] The present invention will now be described in detail with reference to the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional modifications made by those skilled in the art based on these embodiments are included within the scope of protection of the present invention.

[0036] In the various figures of this invention, for ease of illustration, some dimensions of structures or parts may be exaggerated relative to other structures or parts; therefore, only the basic structure of the subject matter of this invention is used to illustrate the invention.

[0037] Please refer to Figures 1-16As shown, a solar cell 100 according to a preferred embodiment of the present invention includes a silicon substrate 1, a P-type doped structure 2 located on the back side of the silicon substrate 1, an N-type doped structure 3 located on the back side of the silicon substrate 1, a spacer region 4 located between the P-type doped structure 2 and the N-type doped structure 3, a first electrode 91 located on the back side of the P-type doped structure 2, and a second electrode 92 located on the back side of the N-type doped structure 3.

[0038] The silicon substrate 1 is selected from N-type silicon wafers with a resistivity of 0.3 Ω·cm to 7 Ω·cm, preferably 2 Ω·cm to 3.5 Ω·cm. In an optional embodiment, the front side of the silicon substrate 1 has a textured structure, which has a good light-limiting effect and can further improve the light utilization rate.

[0039] The P-type doped structure 2 and the N-type doped structure 3 are alternately arranged, and the two regions are separated by the isolation region 4. Placing both the P-type doped structure 2 and the N-type doped structure 3 on the back of the solar cell reduces the current transport path between the two structures, thus lowering resistance. Furthermore, by placing both the first electrode 91 and the second electrode 92 on the back, there are no metal electrodes obstructing the front, resulting in a larger light-receiving area and improved cell efficiency.

[0040] The P-type doped structure 2 forms a PN junction with the silicon substrate 1, and the N-type doped structure 3 forms an N-N+ junction with the silicon substrate 1. When the width W1 of the P-type doped structure 2 is greater than the width W2 of the N-type doped structure, the area of ​​the PN junction region is greater than the area of ​​the N-N+ region, which is beneficial for the generation, separation, and collection of photogenerated carriers, and can improve the battery efficiency.

[0041] In this invention, the P-type doped structure 2 is higher than the N-type doped structure 3 along the direction from the front to the back of the silicon substrate 1. That is, the distance from the back surface of the P-type doped structure 2 (the wall surface of the spacer region 4 facing the front of the silicon substrate 1) to the front surface of the silicon substrate 1 is greater than the distance from the back surface of the N-type doped structure 3 to the front surface of the silicon substrate 1.

[0042] The P-type doping structure is superior to the N-type doping structure. On the one hand, it increases the surface area of ​​the entire back side, thus expanding the light-receiving area. On the other hand, the back and sides of the P-type doping structure are exposed to the outside, increasing the light-absorbing area of ​​the P-type doping structure. This enables the generation and successful collection of more charge carriers, thereby improving the battery efficiency.

[0043] In the first type of implementation, please refer to Figures 1-12 As shown, the P-type doped structure 2 is a P-type diffusion region formed by direct inward diffusion of P-type doping from the back side of the silicon substrate 1. In this case, the PN junction is located within the silicon substrate 1, which facilitates carrier separation and collection, thereby improving battery efficiency.

[0044] P-type doping sources include, but are not limited to, boron, aluminum, and gallium.

[0045] like Figure 3 , Figure 4 As shown, the diffusion concentration is uniform throughout the entire P-type diffusion region. Figure 1 , Figure 2 As shown, the P-type doped structure 2 includes a gate line region 21 and a non-gate line region 22, wherein the doping concentration of the gate line region 21 is greater than the doping concentration of the non-gate line region 22.

[0046] The high doping concentration of the gate region 21 forms an ohmic contact with the first electrode 91, reducing the series resistance of the battery and increasing the fill factor FF. Conversely, the low doping concentration of the non-gate region 22 reduces the probability of carrier surface recombination, decreasing the reverse saturation current and thus increasing the open-circuit voltage Voc and short-circuit current Isc. Furthermore, the gate region 21 and the non-gate region 22 can create a P++ / P+ or N++ / N+ high-low junction laterally, which is beneficial for improving carrier collection and further increasing the short-circuit current Isc.

[0047] In an optional embodiment, the doping concentration of the gate region 21 is 5E18cm⁻¹. -3 ~1E20cm -3 The sheet resistance is 80 ohm / sq to 130 ohm / sq; the sheet resistance of the non-gate region 22 is 200 ohm / sq to 400 ohm / sq.

[0048] The N-type doped structure 3 is recessed from the back side of the silicon substrate 1 towards the front side, that is, the N-type doped structure 3 is located in the region recessed from the back side of the silicon substrate 1 towards the front side.

[0049] In one implementation party, such as Figures 1-8 As shown, the N-type doped structure 3 is an N-type tunneling passivation contact structure.

[0050] In one embodiment, such as Figures 1-4 As shown, the N-type tunneling passivation contact structure includes at least one first tunneling layer 31, a doped polysilicon layer 32 located on the side of each first tunneling layer 31 facing away from the silicon substrate 1, and the second electrode 92 is in contact with the doped polysilicon layer 32.

[0051] The N-type passivated contact structure includes a first tunneling layer 31 and a doped polysilicon layer 32. The second electrode 92 is in contact with the doped polysilicon layer 32, which avoids direct contact between the second electrode 92 and the silicon substrate 1, thereby improving the battery efficiency.

[0052] In another embodiment, such as Figures 5-8As shown, the N-type tunneling passivation contact structure includes n first tunneling layers 31 and a doped polycrystalline silicon layer 32 located on the side of each first tunneling layer 31 facing away from the silicon substrate 1, where n ≥ 2. The multiple first tunneling layers 31 can hinder the inward diffusion of metallic silver, preventing it from contacting the silicon substrate and forming a silicon-silver alloy.

[0053] In the direction from the silicon substrate 1 toward the back side, the second electrode 92 is in contact with at least one of the 2nd to nth doped polysilicon layers 32; that is, the second electrode 92 is in contact with part or all of the other doped polysilicon layers 2 except for the doped polysilicon layer 32 closest to the silicon substrate 1, and will not reach the innermost doped polysilicon layer, thus avoiding direct contact between silver and the silicon substrate.

[0054] In one specific embodiment, the passivation contact structure includes two doped polysilicon layers, and the second electrode 92 contacts only the doped polysilicon layer 32 furthest from the silicon substrate 1.

[0055] In another specific embodiment, the passivation contact structure includes three doped polysilicon layers 32, and the second electrode 92 is in contact only with the outermost doped polysilicon layer 32, or the second electrode 92 is in contact only with the first and second doped polysilicon layers 32 counted from the outside in.

[0056] Based on the above design, the first tunneling layer 31 is selected from silicon oxide (SiOx) or silicon carbide (SiC), with a thickness of 1nm to 3nm, preferably 1nm to 2.5nm, more preferably 1nm to 2nm or 1.5nm to 2.5nm. The thickness of the first tunneling layer 31 is optimized according to its density. When the first tunneling layer 31 is SiOx, the thickness is between 1.4nm and 2.3nm; when the first tunneling layer 31 is SiC, the film is more dense, with a thickness of 1nm to 1.8nm.

[0057] The doped polysilicon layer 32 is an N-doped polysilicon layer; the following explanation will use phosphorus doping as an example. The doping concentration is 1E19cm⁻¹. -3 ~1E21cm -3 1E20cm is preferred -3 ~9E20cm -3 The thickness is 80nm~120nm, and can be set to 85nm, 90nm, 100nm, 105nm, 110nm, or 115nm.

[0058] In another embodiment, such as Figures 9-12 As shown, the N-type doped structure 3 is an N-type diffusion region 33 formed by diffusion from the back surface after the depression to the front surface to a predetermined depth.

[0059] In the first embodiment, the height difference ΔH between the back surface of the N-type doped structure and the back surface of the P-type doped structure is 0.5 to 1.5 times the diffusion depth H1 of the P-type diffusion region. The larger the height difference ΔH, the larger the area of ​​the P-type diffusion region exposed to the outside, which is more conducive to light absorption and the higher the efficiency of the battery.

[0060] The isolation region 4 separates the P-type doped structure 2 and the N-type doped structure 3 to prevent leakage problems caused by contact between the two.

[0061] In one embodiment, the width W3 of the spacer region 4 is 10 μm to 150 μm. Under the premise of isolating leakage current, the narrower the width W3 of the spacer region 4, the less recombination of charge carriers in that region, and the higher the battery efficiency. Preferably, the width W3 is 50 μm to 100 μm.

[0062] In this invention, the spacer region 4 is recessed from the back side of the silicon substrate 1 to the front side, and the recess depth H3 is 1 to 1.5 times the diffusion depth H1 of the P-type diffusion region. That is, the recess depth H3 is greater than the diffusion depth H1 of the P-type diffusion region, ensuring that the spacer region 4 completely isolates the P-type doped structure 2 and the N-type doped structure 3.

[0063] In one embodiment, the recess depth H2 at the location of the N-type doped structure 3 is greater than the recess depth H3 of the spacer region 4, which completely isolates the P-type diffusion region and the N-type tunneling passivation contact structure in both the extension direction and thickness direction of the silicon substrate 1, resulting in good isolation effect.

[0064] In one embodiment, the height difference ΔH between the back surface of the P-type doped structure 2 and the back surface of the N-type doped structure 3 in the thickness direction of the silicon substrate 1 is 1 μm to 10 μm. This not only increases the surface area of ​​the back surface but also creates a stepped shape, allowing light to undergo multiple reflections on the back surface, which is more conducive to light absorption. Preferably, the height difference ΔH is 4 μm to 10 μm.

[0065] Alternatively, the surface of the spacer region 4 facing the silicon substrate 1 is planar, which provides good passivation and can improve the cell efficiency by 0.1-0.2% while keeping other structures unchanged. Or, the surface of the spacer region 4 facing the silicon substrate 1 can be textured.

[0066] Additionally, please refer to Figures 1-12 The back side of the solar cell 100 is also provided with a back passivation layer 5 and a back anti-reflection layer 6. The first electrode 91 passes through the back anti-reflection layer 6 and the back passivation layer 5 and contacts the grid line region 21. The second electrode 92 passes through the back anti-reflection layer 6 and the back passivation layer 5 and contacts the doped polycrystalline silicon layer 32.

[0067] The back passivation layer 5 is preferably an alumina layer, providing excellent field passivation for the P-type doped structure 2 and excellent interface passivation for the N-type doped structure 3. In this invention, the thickness of the back passivation layer 5 is preferably 3 nm to 6 nm.

[0068] The back antireflection layer 6 is selected from one or more stacked films of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 60nm~130nm, which reduces reflectivity and improves light utilization.

[0069] In an optional embodiment, the solar cell 100 further includes a front passivation layer 7 and a front antireflection layer 8 sequentially disposed on the front side of the silicon substrate 1 to passivate surface defects on the front side. In this invention, the front passivation layer 7 and the back passivation layer 5 are made of the same material and have the same thickness, and can be deposited together; the front antireflection layer 8 and the back antireflection layer 6 are made of the same material and have the same thickness, and can also be deposited in the same process.

[0070] Based on the above design, the P-type doped structure 2 is a P-type diffusion region formed by the diffusion of dopant from the back side of the silicon substrate 1 inwards, and the N-type doped structure 3 is located in a region recessed from the back side to the front side of the silicon substrate 1. The N-type doped structure 3 is either an N-type tunneling passivation contact structure or an N-type diffusion region formed by diffusion into the silicon substrate 1. This structural design allows for the initial diffusion formation of the P-type doped structure 2 on the back side of the silicon substrate, followed by the removal of a portion of the diffusion junction, and then the deposition of the tunneling passivation contact structure. This design offers high compatibility with the TOPCon cell process flow and is suitable for industrialization.

[0071] The following describes a method for fabricating a solar cell, using the example of a boron-doped P-type diffusion region (P-type doped structure 2) and a phosphorus-doped N-type tunneling passivation contact structure (N-type doped structure 2).

[0072] S1 uses a boron diffusion process to form a P-type diffusion region (boron junction) and BSG on the back side of silicon substrate 1.

[0073] S11 First, a boron source is formed on the entire back side of the silicon substrate 1. The silicon substrate 1 is fixed in a quartz boat and placed in a tube furnace. The boron source and oxygen are introduced to deposit a layer of boron source (or a through-source) on the back side of the silicon substrate 1. The boron source is boron trichloride (BCl3), with a flow rate of 90 sccm to 150 sccm, an oxygen flow rate of 100 sccm to 500 sccm reacting with BCl3, and an oxygen flow rate of 1 slm to 10 slm for forming the oxide layer; or, the boron source is boron tribromide (BBr3), with a boron trichloride flow rate of 90 sccm to 150 sccm, an oxygen flow rate of 100 sccm to 500 sccm reacting with BBr3, and an oxygen flow rate of 1 slm to 10 slm for forming the oxide layer.

[0074] S12 is used to laser scan the gate region of the p-type doped structure 2 to form a heavily doped gate region 21. Laser parameters: laser gas power is 120W, using 63% power for wafer fabrication; laser frequency is 100kHz, and scan speed is 25m / s.

[0075] S13 then diffuses in the non-gate region.

[0076] In one optional embodiment, the heavily doped silicon substrate 1 is placed in a tube furnace, and oxygen is introduced into the tube furnace at a temperature of 950°C to 1000°C and an oxygen flow rate of 10 slm to 15 slm. At the high temperature, the boron source in the non-gate region diffuses inward to form a non-gate region 22, while BSG is formed on the entire surface.

[0077] In one optional embodiment, the sheet resistance after depositing the boron source is 120 ohm / sq to 170 ohm / sq; after laser scanning, the doping concentration of the gate region 21 is 5E18cm. -3 ~1E20cm -3 The sheet resistance is 80 ohm / sq to 130 ohm / sq; after high-temperature oxidation, the sheet resistance of the non-gate region 22 is 200 ohm / sq to 400 ohm / sq.

[0078] The diffusion depth of boron is 0.5 μm to 1.0 μm, and the dark saturation current density J0 of the P-type diffusion region is 2 fA / cm. 2 ~4fA / cm 2 This can achieve a balanced passivation effect with the N-type doped structure 3. The dark saturation current density J0 of the N-type doped structure 3 is 1 fA / cm². 2 ~3fA / cm 2 When this optimal passivation level is reached, a roughly fixed junction depth level will appear.

[0079] S2 removes the BSG and boron junction outside the p-type doped structure 2: S21 performs laser ablation on the p-type doped structure 2 to remove the BSG outside the p-type doped structure 2. The laser power is 50W~120W, preferably ultraviolet picosecond or green picosecond lasers, which have low damage and low cost; femtosecond lasers can also be used.

[0080] S22 removes the boron junction outside the p-type doped structure 2: First, the BSG on the front and sides of the silicon substrate 1 is removed using an HF solution with a concentration of 5% to 20% (volume concentration). In an optional embodiment, this step is performed in a chain machine.

[0081] The material is then polished to remove the boron junction outside the P-type doped structure 2, as well as the boron junction wrapped around the front side. The boron junction of the P-type doped structure 2 and the BSG are retained. In an optional embodiment, this step is performed in a tank mill.

[0082] This step removes the boron junction outside the P-type doped structure 2, as well as the BSG on the front and sides and the boron junction expanded on the front. The process is simple and lays a good foundation for subsequent processes.

[0083] S3 Backside Tunneling Passivation Contact Structure and Mask Layer: A first tunneling layer 31 and a phosphorus-doped amorphous silicon layer are grown on the entire backside using PECVD in-situ doping, and a mask layer is grown on the outermost side. Here, by alternatingly depositing multiple layers of the first tunneling layer 31 and the phosphorus-doped amorphous silicon layer, a tunneling passivation contact structure including multiple layers of the first tunneling layer 31 and the doped polycrystalline silicon layer 32 can be formed.

[0084] In one embodiment, the first tunneling layer 31 is SiOx, and the thickness is preferably 1.4nm~2.3nm.

[0085] In another embodiment, the first tunneling layer 31 is SiC, which is more dense and preferably has a thickness of 1 nm to 1.8 nm.

[0086] The thickness of the N-poly layer is preferably 80nm~120nm.

[0087] The mask layer is preferably a silicon oxide layer, with a thickness controlled in the range of 10nm to 50nm.

[0088] S4 uses a high-temperature annealing furnace, and the annealing temperature can be matched according to the tunneling conditions. The first tunneling layer 31 has a large thickness, requiring a high annealing temperature. In an optional embodiment, the annealing temperature is 850℃~950℃, which can be optimally matched with the conventional first tunneling layer 31, ensuring a doping concentration of 1E19cm³ for the n-poly region electrochemical doping concentration test (ECV test). -3 ~1E21cm -3 .

[0089] During this process, the first tunneling layer 31 of the N-type doped structure 3 retains a BSG layer, which hinders the inward expansion of phosphorus; while outside the P-type doped structure 2, phosphorus penetrates the first tunneling layer 31 and expands into the silicon substrate 1 to form a phosphorus doped region.

[0090] The annealing temperature is related to the density and thickness of the first tunneling layer 31. In an optional embodiment, when the first tunneling layer 31 is silicon oxide, the thickness is 1.4 nm to 2.3 nm and the annealing temperature is 880 °C to 950 °C; when the first tunneling layer 31 is silicon carbide, the thickness is 1 nm to 1.8 nm and the annealing temperature is 850 °C to 900 °C, so as to ensure that the phosphorus outside the P-type doped structure 2 diffuses inward to the silicon substrate 1.

[0091] S5 removes the mask layer, doped polysilicon layer 32, and first tunneling layer 31, which are separated from the N-type doped structure 3 by the P-type doped structure 2: S51 uses a laser process to remove the mask layer outside the N-type doped structure 3, exposing the underlying doped polycrystalline silicon layer 32. Laser parameters: laser power 50W~120W, preferably ultraviolet picosecond or green picosecond laser; the less damaging the laser, the better for film opening.

[0092] The S52 uses a chain machine and HF solution to remove the mask layer that has been wrapped around the front side.

[0093] S53 then uses a tank etcher and alkaline solution to remove the doped polysilicon layer 32 and the first tunneling layer 31 outside the N-type doped structure 3 on the back side; at the same time, alkaline etching is performed on the front side of the silicon substrate 1 to form a pyramid structure on the exposed silicon substrate 1, and finally it is cleaned.

[0094] In step S5, the film layers at the location of the N-type doped structure 3 and the location of the spacer region 4 can be removed in a patterned manner, so that the depression depth H2 at the location of the N-type doped structure 3 and the depression depth H3 at the location of the spacer region 4 are different.

[0095] Compared to related technologies that "first form a textured structure on the surface of silicon substrate 1 and then prepare other films", this invention forms a pyramid structure on the front side after the important structures and films of P-type doped structure 2 and N-type doped structure 3 are prepared. On the one hand, there is no need to polish the back side before boron diffusion; on the other hand, step S53 removes the back-doped polysilicon layer 32 and the first tunneling layer 31 while forming a pyramid structure on the front side, achieving multiple benefits at once; furthermore, when the front side is flat, it is more conducive to the deposition and cleaning of films in the above steps.

[0096] In addition, the boron junction, the first tunneling layer 31, and the doped polysilicon layer 32 between the P-type doped structure 2 and the N-type doped structure 3 have all been removed to form an isolation region 4, thereby preventing leakage between the P-type doped structure 2 and the N-type doped structure 3.

[0097] In this invention, the width W3 and depth of the isolation zone 4 are as described above, and will not be repeated here.

[0098] S6 Double-sided passivation. Using the ALD process, aluminum oxide is deposited on both the front and back sides, with a preferred thickness of 3nm~6nm. Al2O3 provides excellent field passivation for the P-type doped structure 2 and excellent interface passivation for the N-type doped structure 3. In this invention, the double-sided passivation layer is not a mandatory process step.

[0099] S7 Double-sided antireflective layer: can be a stacked film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 60nm~130nm. In this invention, the double-sided antireflective layer is not a necessary process step.

[0100] S8 electrode fabrication: The electrode is fabricated by screen printing and sintering, including the fabrication of the back main gate electrode and the fabrication of the back P-type doped structure 2 and N-type doped structure 3 sub-gate electrodes.

[0101] The S9 uses laser-assisted contact optimization (LECO) technology to laser sinter the first electrode 91 and the second electrode 92, which can improve the contact between silver and silicon in the electrodes, thereby increasing the battery efficiency by more than 0.2% to 0.3%. It can also change the electrode paste, such as using silver-coated copper paste with low silver content, to save costs.

[0102] The laser wavelength is 1064nm or 532nm, and the laser width is 100 micrometers or 1mm~2mm.

[0103] In the second type of embodiment, please refer to Figures 13-14 As shown, the P-type doped structure 2 is a P-type tunneling passivated contact structure located on the back side of the silicon substrate 1. The difference between the second embodiment and the first embodiment lies only in the following description; other details will not be repeated.

[0104] The P-type tunneling passivation contact structure includes at least one second tunneling layer 23 and a P-type doped polysilicon layer 24 located on the side of each second tunneling layer 23 facing away from the silicon substrate. In this case, the height difference ΔH between the back surface of the N-type doped structure and the back surface of the P-type doped structure is 0.5 to 1.5 times the thickness H4 of the P-type tunneling passivation contact structure.

[0105] Please refer to Figures 13-14 As shown, the N-type doped structure 3 is an N-type diffusion region 33 formed by diffusion from the back side of the silicon substrate 1 to the front side.

[0106] Accordingly, the spacer region 4 is recessed from the back side of the silicon substrate 1 to the front side, and the recess depth H3 is 1 to 1.5 times the diffusion depth H5 of the N-type diffusion region, which can completely isolate the P-type doped structure 2 and the N-type doped structure 3.

[0107] Please refer to Figures 15-16 As shown, the N-type doped structure 3 is an N-type tunneling passivation contact structure disposed on the back side of the silicon substrate 1. The N-type tunneling passivation contact structure includes at least one first tunneling layer 31 and an N-type doped polysilicon layer 32 located on the side of each first tunneling layer 31 facing away from the silicon substrate 1.

[0108] This type of embodiment can be prepared using the following method: first, a P-type tunneling passivation contact structure is fabricated on the entire back side of the silicon substrate, and then the... In this type of embodiment, the P-type doped structure 2 is a P-type tunneling passivation contact structure formed on the surface of the silicon substrate 1, and the N-type doped structure 3 is located on the surface of the silicon substrate 1 after the P-type tunneling passivation contact structure has been removed. The N-type doped structure 3 is either an N-type tunneling passivation contact structure or an N-type diffusion region formed by diffusion into the silicon substrate 1. This structural design allows for the first diffusion formation of the P-type doped structure 2 on the back side of the silicon substrate, followed by the removal of a portion of the P-type tunneling passivation contact structure, and then the formation of the N-type doped structure 3. This design offers high compatibility with the process flow of TOPCON cells and is suitable for industrialization.

[0109] The following provides a specific preparation method for explanation.

[0110] S1 polishing: Alkaline polishing is performed using KOH or NaOH and additives; or the surface of silicon substrate 1 is first textured and then polished, with the base of the region where the P-type doped structure 2 is located being 3μm~15μm.

[0111] S2 preparation of P-type doped structure 2: S21LPCVD method for depositing tunneling layers / i-Poly: First, a second tunneling layer 23 with a thickness of 1.2~2nm is grown on the back side; then an i-poly layer with a thickness of 200~400nm is grown. 0, 1, 2....n second tunneling layers 23 can be grown in the middle of the poly layer.

[0112] S22 boron doping: can be achieved through tubular diffusion, using BCl3 or BBr3 as the diffusion source, with the temperature controlled at 900℃~1100℃, sheet resistance of 50 ohm / sq~500 ohm / sq, BSG thickness of 30~200 nm, and surface concentration of 1E18 cm⁻¹. -3 ~1E20cm -3 .

[0113] S3 Laser Removal of BSG: Laser treatment is performed on the back side, removing BSG in a patterned manner. A UV picosecond laser with a spot power of 3W~20W, a spot size of 100μm~150μm, a frequency of 500kHz~600kHz, and a scan rate of 40m / s~80m / s can be used. Alternatively, a green picosecond laser with a spot power of 5W~50W, a spot size of 100μm~500μm, a frequency of 500kHz~600kHz, and a scan rate of 40m / s~80m / s can be used.

[0114] S4 wet chain machine + tank machine: The chain machine uses HF solution to remove BSG from the front side and the side of the silicon wafer; the tank machine performs texturing to remove the poly spread on the front side and the poly in the laser area on the back side, forming a uniform textured structure on the front side of the silicon substrate.

[0115] S5 diffusion: A high-temperature diffusion furnace is used, with a temperature of 850℃~950℃, to ensure that the doping concentration of the n-poly region ECV test is 1E15~1E21cm-3. This step can also be double-sided diffusion, so that an n+ field can be formed on the front side and an N+ field can be formed in the N region on the back side.

[0116] S6 laser delamination for PSG removal: PSG at position 4, the space between the P and N areas on the back side, is removed according to the pattern.

[0117] The S7 tank etching machine is used to prepare the spacer region 4 by alkaline etching, and finally cleaning is performed.

[0118] S8 Double-sided passivation. Using the ALD process, aluminum oxide is deposited on both the front and back sides, with a preferred thickness of 3nm~6nm. Al2O3 provides excellent field passivation for the P-type doped structure 2 and excellent interface passivation for the N-type doped structure 3. In this invention, the double-sided passivation layer is not a mandatory process step.

[0119] S9 double-sided antireflective layer: can be a stacked film composed of one or more of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 60nm~130nm. In this invention, the double-sided antireflective layer is not a necessary process step.

[0120] S10 electrode fabrication: The electrode was fabricated by screen printing and sintering, including the fabrication of the back main gate electrode and the fabrication of the back P-type doped structure 2 and N-type doped structure 3 sub-gate electrodes.

[0121] S11 uses laser-assisted contact optimization (LECO technology, also known as laser-enhanced contact optimization) to laser sinter the first electrode 91 and the second electrode 92, which can improve the contact between silver and silicon in the electrodes, thereby increasing the battery efficiency by more than 0.2% to 0.3%; it can also change the electrode paste, such as using silver-coated copper paste with low silver content, to save costs.

[0122] The laser wavelength is 1064nm or 532nm, and the laser width is 100 micrometers or 1mm~2mm.

[0123] In summary, the solar cell 100 of the present invention improves cell efficiency by placing both the first electrode 91 and the second electrode 92 on the back side, eliminating metal electrode obstruction on the front side, resulting in a large light-receiving area and high light conversion efficiency. Furthermore, by incorporating an SE structure in the P-type doped structure 2, the open-circuit voltage and short-circuit current of the cell are improved; and by incorporating a passivated contact structure in the N-type doped structure 3 to passivate its surface, the short-circuit current is increased, thus enhancing overall cell efficiency.

[0124] It should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This way of describing the specification is only for clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0125] The detailed descriptions listed above are merely specific descriptions of feasible embodiments of the present invention, and are not intended to limit the scope of protection of the present invention. All equivalent embodiments or modifications made without departing from the spirit of the present invention should be included within the scope of protection of the present invention.

Claims

1. A solar cell, comprising a P-type doped structure on the back side of a silicon substrate, an N-type doped structure on the back side of the silicon substrate, a spacer region between the P-type doped structure and the N-type doped structure, a first electrode on the back side of the P-type doped structure, and a second electrode on the back side of the N-type doped structure, characterized in that, The width of the P-type doped structure is greater than the width of the N-type doped structure.

2. The solar cell according to claim 1, characterized in that, The silicon substrate is an N-type silicon substrate, and the P-type doped structure forms a P-type doped structure with the N-type silicon substrate. An N-junction is formed between the N-type doped structure and the N-type silicon substrate. N+ junction, the P The area of ​​the region containing the N-junction is greater than that of the N-junction. The area of ​​the region containing the N+ junction.

3. The solar cell according to claim 1 or 2, characterized in that, Along the direction from the front to the back of the silicon substrate, the P-type doped structure is higher than the N-type doped structure.

4. The solar cell according to claim 1, characterized in that, The P-type doped structure is a P-type diffusion region formed by the diffusion of P-type doping from the back side of the silicon substrate to the front side to a predetermined depth. The height difference between the back surface of the N-type doped structure and the back surface of the P-type doped structure is 0.5 to 1.5 times the diffusion depth of the P-type diffusion region.

5. The solar cell according to claim 1, characterized in that, The diffusion depth of the P-type diffusion region is 0.5 μm to 1.0 μm, and the dark saturation current density J0 of the P-type diffusion region is 2 fA / cm. 2 ~4fA / cm 2 .

6. The solar cell according to claim 4, characterized in that, The P-type diffusion region includes a gate line region and a non-gate line region, wherein the doping concentration of the gate line region is greater than that of the non-gate line region, and the first electrode is in contact with the gate line region.

7. The solar cell according to claim 6, characterized in that, The sheet resistance of the gate line region is 80 ohm / sq to 130 ohm / sq, and the sheet resistance of the non-gate line region is 200 ohm / sq to 400 ohm / sq.

8. The solar cell according to claim 6, characterized in that, The diffusion depth of the gate line region is greater than the diffusion depth of the non-gate line region.

9. The solar cell according to claim 4, characterized in that, The N-type doped structure is recessed from the back side of the silicon substrate toward the front side; the N-type doped structure is an N-type tunneling passivation contact structure disposed on the back side of the silicon substrate, and the N-type tunneling passivation contact structure includes at least one first tunneling layer and an N-type doped polycrystalline silicon layer located on the side of each first tunneling layer away from the silicon substrate.

10. The solar cell according to claim 9, characterized in that, The N-type tunneling passivation contact structure includes at least two first tunneling layers, and the second electrode is in contact with at least one of the other N-type doped polysilicon layers except for the one closest to the silicon substrate.

11. The solar cell according to claim 9, characterized in that, When the first tunneling layer is SiOx, its thickness is between 1.4 nm and 2.3 nm; when the first tunneling layer is SiC, its thickness is between 1 nm and 1.8 nm.

12. The solar cell according to claim 4, characterized in that, The N-type doped structure is recessed from the back side to the front side of the silicon substrate; the N-type doped structure is an N-type diffusion region formed by diffusion from the recessed back surface to the front surface to a predetermined depth.

13. The solar cell according to any one of claims 4 to 12, characterized in that, The spacer region is recessed from the back side of the silicon substrate to the front side, and the recess depth is 1 to 1.5 times the diffusion depth of the P-type diffusion region.

14. The solar cell according to claim 1, characterized in that, The P-type doped structure is a P-type tunneling passivation contact structure located on the back side of the silicon substrate. The P-type tunneling passivation contact structure includes at least one second tunneling layer and a P-type doped polysilicon layer located on the side of each second tunneling layer away from the silicon substrate. The height difference between the back surface of the N-type doped structure and the back surface of the P-type doped structure is 0.5 to 1.5 times the thickness of the P-type tunneling passivation contact structure.

15. The solar cell according to claim 14, characterized in that, The N-type doped structure is an N-type diffusion region formed by diffusion from the back side to the front side of the silicon substrate.

16. The solar cell according to claim 15, characterized in that, The spacer region is recessed from the back side of the silicon substrate toward the front side, and the recess depth is 1 to 1.5 times the diffusion depth of the N-type diffusion region.

17. The solar cell according to claim 14, characterized in that, The N-type doped structure is an N-type tunneling passivation contact structure disposed on the back side of the silicon substrate. The N-type tunneling passivation contact structure includes at least one first tunneling layer and an N-type doped polycrystalline silicon layer located on the side of each first tunneling layer away from the silicon substrate.

18. The solar cell according to claim 1, characterized in that, The height difference between the back surface of the N-type doped structure and the back surface of the P-type doped structure is 1 μm to 10 μm.

19. The solar cell according to claim 1, characterized in that, The width of the interval is 10μm to 150μm.

20. The solar cell according to claim 1, characterized in that, The back side of the solar cell is further provided with a back passivation layer and a back antireflection layer. The first electrode passes through the back antireflection layer and the back passivation layer and contacts the P-type doped structure. The second electrode passes through the back antireflection layer and the back passivation layer and contacts the N-type doped structure.

21. The solar cell according to claim 1, characterized in that, It also includes a front passivation layer and a front antireflection layer sequentially disposed on the front side of the silicon substrate.

22. A method for manufacturing a solar cell, characterized in that, include: Provide silicon substrates; A P-type doped structure is formed on the back side of the silicon substrate, and an N-type doped structure is formed on the back side of the silicon substrate, with a spacer region between the P-type doped structure and the N-type doped structure. A first electrode is formed on the back side of the P-type doped structure, and a second electrode is formed on the back side of the N-type doped structure.

23. The method for manufacturing a solar cell according to claim 22, characterized in that, The P-type doped structure is a P-type diffusion region formed by P-type doping from the back side of the silicon substrate to the front side at a predetermined depth. The P-type diffusion region includes a gate line region and a non-gate line region. The steps for forming the P-type diffusion region include: A boron source layer is deposited on the back side of the silicon substrate; A portion of the silicon substrate is laser-scanned to form the heavily doped gate region; Then, diffusion is performed in the region corresponding to the non-gate area that is subsequently formed to form the P-type diffusion region that includes the gate area and the non-gate area.

24. The method for manufacturing a solar cell according to claim 22, characterized in that, The P-type doped structure is a P-type tunneling passivation contact structure located on the back side of the silicon substrate. The P-type tunneling passivation contact structure includes at least one second tunneling layer and a P-type doped polycrystalline silicon layer located on the side of each second tunneling layer away from the silicon substrate. The steps for forming the p-type doped structure include: At least one second tunneling layer is deposited on the back side of the silicon substrate, and intrinsic polycrystalline silicon is formed on the side of each second tunneling layer opposite to the silicon substrate. The intrinsic polycrystalline silicon is doped by tubular diffusion to form the P-type doped polycrystalline silicon layer.

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