Process method for thinning poly layer of photovoltaic cell by using patterned mask
By employing patterned masking and acid etching processes, the problems of thermal damage and uneven etching during the thinning or removal of the poly layer in the non-metallic electrode region of topcon cells were solved, achieving efficient and precise poly layer processing and improving the photoelectric conversion efficiency and yield of the cells.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-31
- Publication Date
- 2026-04-14
AI Technical Summary
Existing processes, when thinning or removing the poly layer in the non-metallic electrode area on the back of a topcon cell, can easily lead to thermal damage such as microcracks in the poly layer, as well as insufficient or excessive corrosion, resulting in a decrease in cell efficiency and yield.
A patterned mask combined with acid etching is used to selectively etch the non-metallic electrode area with a mixture of hydrofluoric acid and nitric acid. By controlling the concentration and temperature of the etching solution, and combining it with cleaning and drying steps, high-precision poly layer thinning or removal can be achieved.
This avoids thermal damage caused by laser processing, improves the precision and uniformity of etching, reduces leakage and contact failure of solar cells, and improves the photoelectric conversion efficiency and yield of solar cells.
Smart Images
Figure CN121865733A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the fields of photovoltaic and semiconductor technology, and more particularly to a process method for thinning or removing the poly layer of the non-metallic electrode region on the back of a topcon cell. Background Technology
[0002] With the increasing demand for higher photoelectric conversion efficiency in monocrystalline silicon solar cells, TOPCon cells, as an advanced solar cell technology, have gradually gained an important position in the market. Crystalline silicon TOPCon is a cell technology with a tunneling oxide layer passivated contact on the back side. Its main structure uses an N-type monocrystalline silicon wafer as a substrate, with an ultrathin silicon oxide layer fabricated on the back side of the cell, and a phosphorus-doped amorphous silicon layer (N+ layer) deposited on top of the silicon oxide layer. This structure enables selective tunneling of charge carriers and provides excellent field passivation for the cell, thereby improving the photoelectric conversion efficiency.
[0003] However, the poly in topcon cells exhibits strong parasitic absorption of light, and the thicker the poly layer, the greater the light loss, thus reducing the cell's photoelectric conversion efficiency. However, heavily phosphorus-doped poly can tunnel to improve passivation and avoid direct contact between the metal electrode and the silicon substrate, reducing recombination. Therefore, a process solution is needed to retain the poly in the metal electrode region while thinning or removing the poly in the non-metal electrode region. Currently, the main process for thinning the poly in the non-metal electrode region of topcon cells involves using a high-power laser to selectively treat the PSG (phosphosilicate glass) on the surface of the poly layer, and then using the positive etching function of RCA to remove the poly in the non-metal electrode region. This method has several risks: 1. During laser treatment, excessively high energy density may cause thermal damage such as microcracks in the poly layer; 2. Precisely processing the poly thickness in the non-metal electrode region using RCA positive etching is difficult, and the process window is small, easily leading to insufficient or over-etching. These problems can easily lead to fatal defects such as leakage and contact failure, significantly reducing the cell's efficiency and yield.
[0004] Therefore, how to overcome the defects such as microcracks and thermal damage to the poly layer, as well as insufficient or excessive corrosion, that easily occur when thinning or removing the non-metallic electrode area poly layer on the back of the topcon battery using existing processes is a problem that needs to be solved in this technical field. Summary of the Invention
[0005] In order to solve the technical problems that existing processes may cause thermal damage such as microcracks in the poly layer of the non-metallic electrode region on the back of a topcon battery, as well as insufficient or excessive corrosion, the present invention provides a process method for thinning or removing the poly layer of the non-metallic electrode region on the back of a topcon battery.
[0006] This invention provides a process method for thinning the poly layer of a photovoltaic cell using a patterned mask, comprising the following steps: Step 1: Pattern the metal electrode area on the back side of the polysilicon wafer using a mask; Step 2: Use an acid etching mixture to etch the PSG layer and poly layer in the non-mask area of the silicon wafer to achieve thinning or removal of the poly layer in the non-metallic electrode area. Step 3: Perform subsequent processing on the silicon wafer after acid etching.
[0007] Preferably, the poly-coated silicon wafer is a PE-poly-coated silicon wafer or an LP-poly-coated silicon wafer.
[0008] Preferably, the acid etching solution is a mixture of hydrofluoric acid, nitric acid, and deionized water.
[0009] Preferably, in step 2, the volume ratio of HF to HNO3 in the acid etching mixture is 1.5:3; the acid etching temperature is controlled at 3-10℃; and the reaction time of immersing the silicon wafer in the acid etching mixture is 60-80 seconds.
[0010] Preferably, in step 1, the PSG layer deposited on both sides and the front side of the silicon wafer after Poly is removed first, and then the patterned mask is applied.
[0011] Preferably, the PSG layer is removed using an HF solution with a volume ratio of HF to deionized water of 1:4.8, and the treatment is carried out at 25°C for 100-120 seconds.
[0012] Preferably, in step 2, the volume ratio of HF to HNO3 in the acid etching mixture is 1:3, the acid etching temperature is controlled at 3-10℃, and the reaction time of immersing the silicon wafer in the acid etching solution is 40-60 seconds.
[0013] Preferably, step 3 includes the following procedures: The silicon wafer after acid etching is cleaned once using overflow water; the silicon wafer is then cleaned with an alkaline mixture; the silicon wafer is cleaned a second time using overflow water; the silicon wafer is cleaned with hydrofluoric acid solution; the silicon wafer is cleaned a third time using overflow water; the silicon wafer is slowly pulled up to pre-dehydrate its surface; and the pre-dehydrated silicon wafer is then dried.
[0014] Preferably, the washing time is 120s; the alkaline solution is a mixture of NaOH, H2O2 and deionized water, wherein the volume ratio of NaOH to H2O2 is 1:4, the temperature of the subsequent alkaline wash is 70℃, and the time is 90s; the solubility of the hydrofluoric acid solution is: the volume ratio of HF to water = 1:4.8, the temperature of the HF acid wash is 25℃, and the time is 280s; the speed of slowly lifting the deionized water is 3mm / s, the temperature during pre-dehydration is 48-50℃; the drying temperature is 95℃, and the time is 600s.
[0015] This invention provides a novel process for thinning or removing poly in the non-metallic electrode region of a topcon battery. It primarily utilizes a patterned mask + acid etching thinning method. Specifically, a mask pattern is applied as a protective layer to the PSG layer of the metal electrode region on the back of the silicon wafer, and an acidic solution is used to selectively etch the PSG and poly in the non-masked areas of the topcon silicon wafer, thereby achieving the thinning or removal of the poly in the non-metallic electrode region.
[0016] Patterned masking combined with acid etching enables high-resolution and high-precision pattern transfer. By selecting an appropriate etchant and controlling its concentration and process conditions, the etching rate and anisotropy of polysilicon can be precisely controlled. This also avoids the thermal damage caused by laser during surface treatment and solves problems such as cell leakage caused by excessive thinning or poor etching uniformity due to improper laser thinning control. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the process flow for the first preparation scheme, which involves removing PSG, patterning mask, acid etching, and subsequent processing of the silicon wafer after PE-poly. Figure 2 This is a schematic diagram of the process flow for the first preparation scheme, which involves removing PSG, patterning mask, acid etching, and subsequent processing of the silicon wafer after LP-poly. Figure 3 This is a schematic diagram of the process flow for the second preparation method, which involves patterning a silicon wafer after PE-poly, acid etching, and subsequent processing. Figure 4 This is a schematic diagram of the process flow for the second preparation method, which involves patterning a mask, acid etching, and subsequent processing steps on a silicon wafer after LP-poly. Detailed Implementation
[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the following specific embodiments are only used to explain the invention and do not constitute a limitation thereof.
[0019] This invention provides a process method for thinning the poly layer of a photovoltaic cell using a patterned mask, which has two fabrication schemes. The first fabrication scheme includes the following steps: Step 1: Remove the PSG (phosphosilicate glass) layer (coated around the sides and front of the polysilicon wafer). HF is used. The PSG layer was removed by a solution with a volume ratio of HF to deionized water of 1:4.8, and the solution was used at 25°C for 100-120 seconds.
[0020] The poly-coated silicon wafer is either a PE-poly-coated silicon wafer or an LP-poly-coated silicon wafer.
[0021] Step 2: Apply a patterned mask to the metal electrode area on the back side of the polysilicon wafer.
[0022] Step 3: The PSG layer and poly layer in the non-mask area of the silicon wafer are etched using an acid etching mixture to thin or remove the poly layer in the non-metallic electrode area. Wherein: The acid etching solution can be a mixture of hydrofluoric acid, nitric acid, and deionized water.
[0023] Step 4: Perform subsequent processing on the silicon wafer after acid etching. The process includes: The silicon wafer after acid etching is cleaned once using overflow water; then, it is cleaned again using an alkaline mixture; followed by a second cleaning using overflow water; then a third cleaning using hydrofluoric acid solution; finally, the wafer is slowly pulled up to pre-dehydrate its surface; and finally, the pre-dehydrated wafer is dried. Wherein: The three washing cycles each lasted 120 seconds; the alkaline solution was a mixture of NaOH, H2O2, and deionized water, with a NaOH:H2O2 volume ratio of 1:4; the subsequent alkaline wash was performed at 70°C for 90 seconds; the hydrofluoric acid solution had a HF:water volume ratio of 1:4.8; the HF acid wash was performed at 25°C for 280 seconds; the deionized water was slowly lifted at a speed of 3 mm / s; the pre-dehydration temperature was 48-50°C; and the drying temperature was 95°C for 600 seconds.
[0024] The second preparation method of the present invention includes the following steps: Step 1: Apply a patterned mask to the metal electrode area on the back side of the poly-coated silicon wafer. The poly-coated silicon wafer is either a PE-poly-coated or LP-poly-coated silicon wafer.
[0025] Step 2: The PSG layer and poly layer in the non-mask area of the silicon wafer are etched using an acid etching mixture to thin or remove the poly layer in the non-metallic electrode area. Wherein: The acid etching solution can be a mixture of hydrofluoric acid, nitric acid, and deionized water.
[0026] Step 3: Perform subsequent processing on the silicon wafer after acid etching. The process includes: The silicon wafer after acid etching is cleaned once using overflow water; then, it is cleaned again using an alkaline mixture; followed by a second cleaning using overflow water; then a third cleaning using hydrofluoric acid solution; finally, the wafer is slowly pulled up to pre-dehydrate its surface; and finally, the pre-dehydrated wafer is dried. Wherein: The three washing cycles each lasted 120 seconds; the alkaline solution was a mixture of NaOH, H2O2, and deionized water, with a NaOH:H2O2 volume ratio of 1:4; the subsequent alkaline wash was performed at 70°C for 90 seconds; the hydrofluoric acid solution had a HF:water volume ratio of 1:4.8; the HF acid wash was performed at 25°C for 280 seconds; the deionized water was slowly lifted at a speed of 3 mm / s; the pre-dehydration temperature was 48-50°C; and the drying temperature was 95°C for 600 seconds.
[0027] In the N-TopCon battery manufacturing process, the PE-poly battery is a semi-finished product that undergoes the following processes: 1. Texturing: Utilizing the anisotropic corrosion of silicon in a low-concentration alkaline solution, a "pyramid"-shaped light-trapping structure is formed, reducing the reflectivity of the silicon wafer and increasing light absorption.
[0028] 2. Front-side boron diffusion: P-type impurities are diffused onto an N-type substrate to form a PN junction, achieving a suitable doping concentration ρ / sheet resistance R. This yields the junction depth, doping concentration ρ, and sheet resistance R required for a solar cell PN junction.
[0029] 3. BSG Removal + Backside Polishing: BSG Removal – Using HF to remove the borosilicate glass (BSG) on the back of the silicon wafer. Backside polishing - removes the PN junction on the back and edges to prevent short circuits; backside polishing improves long-wavelength response.
[0030] 4. PECVD-poly (Backside Tunneling Oxide Layer + Doped Amorphous Silicon Layer Deposition): This technique uses plasma-enhanced chemical vapor deposition. It's a technique that deposits a thin film on a substrate surface at a relatively low temperature through a plasma-assisted chemical reaction. Tunneling Oxide Layer: An extremely thin (~1-2 nm) silicon dioxide (SiO2) film. Its main function is to allow charge carriers (electrons) to selectively pass through via quantum tunneling, while effectively blocking another type of charge carrier (holes), thus achieving excellent passivation. Doped Amorphous Silicon Layer: A phosphorus-doped (n-type) amorphous silicon film is deposited on top of the tunneling oxide layer. This film will be converted into polycrystalline silicon in subsequent processes.
[0031] 5. Annealing and crystallization - The silicon wafer with the deposited amorphous silicon layer is annealed in a high-temperature furnace tube; Crystallization – High temperatures rearrange amorphous silicon atoms, transforming them from a disordered amorphous state to an ordered polycrystalline state, forming polycrystalline silicon (Poly-Si). This is the origin of the "poly" in "PECVD-poly". Activation Doping – High temperatures simultaneously activate phosphorus impurity atoms in the amorphous silicon, making them effective carrier providers. Enhanced Passivation – The resulting "tunneling oxide / polycrystalline silicon layer" structure (i.e., the TOPCon structure) provides excellent surface passivation for the back of the silicon wafer, significantly reducing carrier recombination and thus improving the open-circuit voltage and conversion efficiency of the solar cell.
[0032] After completing this process step, the PE-poly silicon wafer is obtained.
[0033] 6. PSG+RCA Removal: Utilize HF to remove edge and front-side phosphor bronze (PSG). RCA – Front etching, removing the Poly Si wrap-around plating on the front and edges; removing the oxide layer on the front and back.
[0034] The term LE-poly refers to a semi-finished product after undergoing the following process: 1. Texturing: Utilizing the anisotropic corrosion of silicon in a low-concentration alkaline solution, a "pyramid"-shaped light-trapping structure is formed, reducing the reflectivity of the silicon wafer and increasing light absorption.
[0035] 2. Front-side boron diffusion: P-type impurities are diffused onto an N-type substrate to form a PN junction, achieving a suitable doping concentration ρ / sheet resistance R. This yields the junction depth, doping concentration ρ, and sheet resistance R required for a solar cell PN junction.
[0036] 3. BSG Removal + Backside Polishing: BSG Removal -- Using HF to remove the borosilicate glass (BSG) on the back of the silicon wafer; Backside polishing – removes the PN junction on the back and edges to prevent short circuits; achieves backside polishing to improve long-wavelength response.
[0037] 4. LPCVD-poly (back-side tunneling oxide + intrinsic polysilicon deposition): Using heating, gaseous compounds are reacted on the silicon wafer surface under low pressure and deposited into a solid thin film (i.e., tunneling oxide layer and intrinsic polysilicon).
[0038] 5. Backside phosphorus diffusion: The purpose of phosphorus diffusion is to form an N+ layer on the backside.
[0039] After completing this process step, the LP-poly silicon wafer is obtained.
[0040] 6. PSG Removal + RCA: PSG removal - using HF to remove edge and front phosphor bronze (PSG); RCA - Front etching, removing the Poly Si wrap-around plating on the front and edges; removing the oxide layer on the front and back.
[0041] The present invention will be described below through specific embodiments.
[0042] Example 1 Using the first fabrication method, the silicon wafer after PE-poly processing undergoes PSG removal, patterning masking, acid etching, and subsequent steps, such as... Figure 1 The process flow shown is as follows.
[0043] 1. PSG Removal: The PE-poly silicon wafer is fed into a chain-type PSG removal device. A mixed solution of HF and deionized water at a volume ratio of 1:4.8 is used, and the wafer is treated at 25°C for 100-120 seconds to remove the PSG layer (phosphosilicate glass) deposited on both sides and the front side of the silicon wafer. The BSG layer (borosilicate glass) on the front side is retained as a mask layer for subsequent protection. The degree of PSG removal is checked by observing the dehydration of the silicon wafer surface; complete dehydration indicates that the PSG has been completely removed.
[0044] 2. Patterned Mask: A patterned mask is applied to the PSG (Power Seal) area on the back side of the silicon wafer after PSG removal. This is done by spraying mask material onto the back of the silicon wafer using a spray printing method to form a mask pattern. The printed grid lines have a height of 15-18µm and a width of 100-120µm. Mask materials mainly include one or more of the following: paraffin wax, ink, resin, or adhesive film.
[0045] 3. Acid Etching: The silicon wafer with the patterned mask is subjected to acid etching. An acid etching solution of HF + HNO3 or additive + deionized water is used, where the volume ratio of HF to HNO3 is 1:3. The temperature is controlled at 3-10℃. The silicon wafer is immersed in the acid etching solution for 40-60 seconds. By suppressing the reaction rate at low temperature, the PSG layer and poly layer exposed in the non-patterned mask areas are removed, including the PSG layers on both sides of the silicon wafer and those extending to the front side, in order to achieve a controllable poly layer etching depth.
[0046] 4. First water rinse: Use overflow water to rinse for 120 seconds to remove impurities and residual acid solution from the silicon wafer surface, ensuring the silicon wafer surface is clean.
[0047] 5. Post-alkaline wash: A mixed solution of NaOH + H2O2 + deionized water is mainly used. The volume ratio of NaOH to H2O2 is 1:4. The temperature is 70℃ and the process time is 90s. This wash cleans the silicon wafer after acid etching, neutralizes the residual acid etching solution on the silicon wafer, removes the porous silicon generated by the acid etching reaction, and removes the patterned mask layer.
[0048] 6. Secondary water rinse: Use overflow water to rinse for 120 seconds to remove impurities and residual alkaline solution from the silicon wafer surface, ensuring the silicon wafer surface is clean.
[0049] 7. HF Wash: Perform a final HF wash to remove the front BSG and back PSG. The HF:water ratio is 1:4.8, the washing temperature is 25℃, and the washing time is 280 seconds.
[0050] 8. Three-stage water rinse: Rinse with overflow water for 120 seconds to remove impurities and residual acid solution from the silicon wafer surface, ensuring the silicon wafer surface is clean. 9. Slow lifting: Deionized water (lifting speed 3mm / s, working temperature 48-50℃) is used to pre-dehydrate the surface of the monocrystalline silicon wafer to avoid watermarks during drying.
[0051] 10. Drying: Dry the cleaned silicon wafers. The temperature is 95℃ and the time is 600 seconds.
[0052] Example 2 Using the first fabrication method, the silicon wafer after LP-poly processing undergoes PSG removal, patterning masking, acid etching, and subsequent steps, such as... Figure 2 The process flow shown is as follows: The processing method for the silicon wafer after LP-poly etching—PSG removal, patterning masking, acid etching, and subsequent processes—is basically the same as the process in Example 1. The difference is that a poly layer is also deposited on the BSG on the front side of the silicon wafer after LP-poly etching. Therefore, during the acid etching process after patterning masking, in addition to removing the PSG and poly layers exposed in the non-patterned mask areas of the silicon wafer, as well as the PSG and poly layers on both sides of the silicon wafer and those extending to the front side, the poly layer covering the BSG on the front side of the silicon wafer must also be removed to achieve a controllable poly layer etching depth. The subsequent processing of the silicon wafer after acid etching is the same as in Example 1.
[0053] The first fabrication method requires first removing the PSG layer deposited around the sides and front of the poly-coated silicon wafer, and then performing the patterning mask-acid etching + subsequent processing. This fabrication method is suitable for manufacturers' existing equipment; that is, the "chain-type PSG removal" equipment in the current Topcon conventional process flow can be used to remove the PSG layer deposited around the sides and front of the poly-coated silicon wafer. Only the patterning equipment and the tank required for acid etching need to be added to realize the fabrication method of this invention. Production line modification is convenient, saving time and costs.
[0054] The second preparation method provided by this invention is used below to achieve thinning of the poly layer in photovoltaic cells.
[0055] Example 3 The second fabrication method involves patterning the silicon wafer after PE-poly etching, followed by acid etching and subsequent processing steps, such as... Figure 3 The process flow shown is as follows.
[0056] 1. Patterned Mask: A patterned mask is applied to the PSG (Power Photocell) on the metal electrode area of the back side of the silicon wafer after PE-polymerization. This involves spraying mask material onto the back of the silicon wafer using a spray printing method to form a mask pattern. The printed grid lines have a height of 15-18µm and a width of 100-120µm. Mask materials mainly include one or more of the following: paraffin wax, ink, resin, or adhesive film.
[0057] 2. Acid Etching: The silicon wafer with the patterned mask is subjected to acid etching. An acid etching solution of HF + HNO3 + deionized water is used, where the volume ratio of HF to HNO3 is 1.5:3. The temperature is controlled at 3-10℃. The silicon wafer is immersed in the acid etching solution for 60-80 seconds. By suppressing the reaction rate at low temperature, the PSG layer and poly layer exposed in the non-patterned mask areas are removed, including the PSG layers on both sides of the silicon wafer and those extending to the front side, in order to achieve a controllable poly layer etching depth.
[0058] 3. First water rinse: Use overflow water to rinse for 120 seconds to remove impurities and residual acid solution from the silicon wafer surface, ensuring the silicon wafer surface is clean.
[0059] 4. Post-alkaline washing: mainly using a mixed solution of NaOH + H2O2 + deionized water, with a volume ratio of NaOH:H2O2 of 1:4, a temperature of 70℃, and a process time of 90s, to clean the silicon wafer after acid etching, neutralize the residual acid etching solution on the silicon wafer, remove the porous silicon generated by the acid etching reaction, and remove the patterned mask layer at the same time.
[0060] 5. Secondary water rinse: Use overflow water to rinse for 120 seconds to remove impurities and residual alkaline solution from the silicon wafer surface, ensuring the silicon wafer surface is clean.
[0061] 6. HF Wash: Perform a final HF wash to remove the front BSG and back PSG. The HF:water ratio is 1:4.8, the washing temperature is 25℃, and the washing time is 280 seconds.
[0062] 7. Three-stage water rinse: Rinse with overflow water for 120 seconds to remove impurities and residual acid solution from the silicon wafer surface, ensuring the silicon wafer surface is clean. 8. Slow lifting: Deionized water (lifting speed 3mm / s, working temperature 48-50℃) is used to pre-dehydrate the surface of the monocrystalline silicon wafer to avoid watermarks during drying.
[0063] 9. Drying: Dry the cleaned silicon wafers at 95℃ for 600 seconds.
[0064] Example 4 The second fabrication method involves patterning the silicon wafer after LP-poly etching, followed by acid etching and subsequent processing steps, such as... Figure 4 The process flow shown is as follows: The processing method for patterning masking, acid etching, and subsequent steps on the silicon wafer after LP-poly etching is basically the same as that in Example 3. The difference is that a poly layer is also deposited on the front side of the silicon wafer in addition to the BSG layer. Therefore, during the acid etching process after patterning masking, in addition to removing the PSG and poly layers exposed in the non-patterned mask areas of the silicon wafer, as well as the PSG and poly layers on both sides of the silicon wafer and those extending to the front side, the poly layer covering the BSG on the front side of the silicon wafer must also be removed to achieve a controllable poly layer etching depth. The subsequent processing of the silicon wafer after acid etching is the same as in Example 3.
[0065] The second fabrication scheme, considering process optimization, integrates the first scheme's process of first removing the PSG layers on both sides and the front of the silicon wafer using a chain-type device, and then removing the PSG and poly layers in non-patterned mask areas via acid etching, into a single step. This involves directly applying a patterned mask to the back of the silicon wafer after POLY etching, followed by a one-step acid etching process to remove the PSG and poly layers. This eliminates the need for the existing chain-type PSG removal equipment, saving process steps. The only difference is the removal of the patterning equipment and the etching tank required for acid etching, which allows for the etching of the non-gateline poly areas on the back.
[0066] The above description is merely a specific embodiment of the present invention. It should be noted that any modifications, equivalent substitutions, and variations made within the spirit and framework of the present invention should be included within the protection scope of the present invention.
Claims
1. A process for thinning the poly layer of a photovoltaic cell using a patterned mask, comprising the following steps: Step 1: Pattern the metal electrode area on the back side of the polysilicon wafer using a mask; Step 2: Use an acid etching mixture to etch the PSG layer and poly layer in the non-mask area of the silicon wafer to achieve thinning or removal of the poly layer in the non-metallic electrode area. Step 3: Perform subsequent processing on the silicon wafer after acid etching.
2. The process method as described in claim 1, characterized in that, The poly-coated silicon wafer is either a PE-poly-coated silicon wafer or an LP-poly-coated silicon wafer.
3. The process method as described in claim 1, characterized in that, The acid etching solution is a mixture of hydrofluoric acid, nitric acid, and deionized water.
4. The process method as described in claim 3, characterized in that, In step 2, the volume ratio of HF to HNO3 in the acid etching mixture is 1.5:3; the acid etching temperature is controlled at 3-10℃; and the silicon wafer is immersed in the acid etching mixture for 60-80 seconds.
5. The process method as described in claim 1, characterized in that, In step 1, the two sides of the silicon wafer after Poly are removed and the PSG layer on the front side is coated before the patterned mask is applied.
6. The process method as described in claim 5, characterized in that, The PSG layer was removed using an HF solution with a volume ratio of HF to deionized water of 1:4.8, and the treatment was carried out at 25°C for 100-120 seconds.
7. The process method as described in claim 5, characterized in that, In step 2, the acid etching solution is a mixture of hydrofluoric acid, nitric acid and deionized water, wherein the volume ratio of HF to HNO3 is 1:3, the acid etching temperature is 3-10℃, and the silicon wafer is immersed in the acid etching solution for 40-60 seconds.
8. The process method as described in claim 1, characterized in that, Step 3 includes the following procedures: The silicon wafer after acid etching is cleaned once using overflow water; the silicon wafer is then cleaned with an alkaline mixture; the silicon wafer is cleaned a second time using overflow water; the silicon wafer is cleaned with hydrofluoric acid solution; the silicon wafer is then cleaned a third time using overflow water; the silicon wafer is then slowly pulled up to pre-dehydrate its surface. The pre-dehydrated silicon wafers are then dried.
9. The process method as described in claim 8, characterized in that, The cleaning time for each step is 120 seconds; the alkaline solution is a mixture of NaOH, H2O2, and deionized water, with a NaOH:H2O2 volume ratio of 1:4; the subsequent alkaline washing temperature is 70°C and the time is 90 seconds; the hydrofluoric acid solution has a HF:water volume ratio of 1:4.8; the HF acid washing temperature is 25°C and the time is 280 seconds; the deionized water is slowly lifted at a speed of 3 mm / s; the pre-dehydration temperature is 48-50°C; and the drying temperature is 95°C and the time is 600 seconds.