Solar cell and photovoltaic module

Abstract

The invention relates to a solar cell and a photovoltaic module, and the solar cell comprises a silicon substrate, a first semiconductor layer and a second semiconductor layer. The silicon substrate comprises a first region, a second region, a platform region and a slope region; the first semiconductor layer is deposited on the first area, the platform area and the slope area in a conformal manner; the second semiconductor layer is deposited on the second region in a shape follow-up manner; the slope area is located between the first area and the platform area; the electrical properties of the first semiconductor layer and the second semiconductor layer are different; the platform area is provided with a texture structure, the slope area is provided with a plurality of vertical textures and a plurality of arc-shaped textures, and the arc-shaped textures are overlaid on the vertical textures. According to the scheme, the light trapping effect of the solar cell can be improved, and the adhesive force of a subsequently deposited structural layer is enhanced. In addition, the arc-shaped textures are overlapped on the vertical textures, and the structure can block the etching paste, so that the excessive expansion of the etching paste is avoided.

Description

Technical Field

[0001] This invention relates to the field of solar photovoltaic technology, and in particular to a solar cell and a photovoltaic module. Background Technology

[0002] Solar cells are devices that directly convert light energy into electrical energy. Related technologies involve first fabricating a patterned passivation layer and a doped polycrystalline silicon layer on the surface of the solar cell, then depositing another passivation layer and a doped amorphous silicon layer on the entire back side of the solar cell. Next, the partially doped amorphous silicon layer above the doped polycrystalline silicon is opened up, and then a transparent conductive layer and electrodes are used to conduct electricity of different electrical properties, thus enabling the solar cell to generate electricity.

[0003] Currently, the polycrystalline silicon layer on the surface of solar cells has a transition region on its side. The relatively smooth surface of the transition region results in poor light trapping properties of the cell. In addition, when etching is performed in the transition region, the smooth surface makes it easy for the etching paste to spread to other parts, thereby adversely affecting the structure of other parts. Summary of the Invention

[0004] In view of this, the present invention proposes a solar cell and a photovoltaic module, which aims to partially or completely solve the technical problems of existing transition regions having relatively smooth surfaces, resulting in poor light trapping properties of the cell and making it easy for etching paste to spread to other parts, thereby adversely affecting the structure of other parts.

[0005] To achieve the above objectives, the technical solution of the present invention is implemented as follows: In a first aspect, embodiments of the present invention provide a solar cell, the solar cell comprising... A silicon substrate, a first semiconductor layer, and a second semiconductor layer; The silicon substrate includes: a first region, a second region, a plateau region, and a ramp region; The first semiconductor layer is conformally deposited on the first region; the second semiconductor layer is conformally deposited on the second region; the slope region is located between the first region and the platform region; the first semiconductor layer and the second semiconductor layer have different electrical properties; The platform area has a textured structure, and the slope area has multiple vertical textures and multiple arc-shaped textures, with the arc-shaped textures superimposed on the vertical textures; the extension direction of the arc-shaped textures is a first direction, which is the length extension direction of the current collector electrode of the solar cell, and the extension direction of the vertical textures is perpendicular to the first direction.

[0006] In a second aspect, embodiments of the present invention provide a photovoltaic module, the photovoltaic module including a cover plate, a back plate, and a solar cell disposed between the cover plate and the back plate; the solar cell includes the solar cell as described above.

[0007] In this embodiment of the invention, the platform region has a textured structure, meaning its surface is not a smooth plane. This textured structure increases the surface roughness of the platform region, thereby improving its light-trapping effect and increasing the light utilization rate of the solar cell, significantly enhancing its optical performance. Furthermore, the rough surface of the platform region helps to enhance the adhesion of subsequently deposited structural layers. The slope region has multiple vertical and multiple arc-shaped textures, with the arc-shaped textures superimposed on the vertical textures. This textured surface morphology also has the aforementioned effects of increasing surface roughness, improving light-trapping effect, and enhancing the adhesion of subsequently deposited structural layers. Additionally, during subsequent etching operations, the arc-shaped textures superimposed on the vertical textures form a barrier against the etching paste, thus preventing excessive spread of the etching paste.

[0008] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments will be briefly introduced below.

[0010] Figure 1 A schematic diagram of the cross-sectional structure of a solar cell according to an embodiment of the present invention is shown; Figure 2 A schematic diagram of a partial surface structure of a solar cell according to an embodiment of the present invention is shown; Figure 3 A schematic diagram of a partial surface structure of another solar cell according to an embodiment of the present invention is shown; Figure 4 A schematic diagram of a partial surface structure of another solar cell according to an embodiment of the present invention is shown; Figure 5 A schematic diagram of a partial surface structure of another solar cell according to an embodiment of the present invention is shown; Figure 6 A schematic diagram of a partial surface structure of another solar cell according to an embodiment of the present invention is shown; Figure 7 A schematic diagram of the cross-sectional structure of another solar cell according to an embodiment of the present invention is shown; Figure 8 A schematic diagram of the cross-sectional structure of another solar cell according to an embodiment of the present invention is shown.

[0011] Explanation of reference numerals in the attached figures: 10-First semiconductor layer; 20-Second semiconductor layer; 30-Silicon substrate; 31-First region; 32-Second region; 33-Plateau region; 34-Slope region; 35-Isolation region; 36-Third region; 52-Surface passivation layer; 60-Electrode; 70-Conductive layer; 21-Doped polycrystalline silicon layer; 331-Texture structure; 41-Vertical texture; 42-Arc texture; 43-Pyramid structure; 51-Passivation layer; A-Isolation trench; X-First direction; Y-Second direction. Detailed Implementation

[0012] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the invention and to fully convey the scope of the invention to those skilled in the art.

[0013] Reference Figure 1 The diagram shows a cross-sectional structural schematic of a solar cell provided in an embodiment of the present invention. The embodiment discloses a solar cell comprising a silicon substrate 30, a first semiconductor layer 10, and a second semiconductor layer 20. The silicon substrate 30 includes a first region 31, a second region 32, a plateau region 33, and a ramp region 34. The first semiconductor layer 10 is conformally deposited on the first region 31. The second semiconductor layer 20 is conformally deposited on the second region 32. The ramp region 34 is located between the first region 31 and the plateau region 33. The first semiconductor layer 10 and the second semiconductor layer 20 have different electrical properties. Further reference... Figure 2 The platform area 33 has a textured structure, and the slope area 34 has multiple vertical textures 41 and multiple arc textures 42. The arc textures 42 are superimposed on the vertical textures 41. The extension direction of the arc textures 42 is the first direction X, which is the length extension direction of the current collector electrode of the solar cell. The extension direction of the vertical textures 41 is perpendicular to the first direction X.

[0014] In this embodiment of the invention, reference is made to Figure 1The solar cell can be a hybrid heterojunction back-contact (HIBC) cell. Specifically, in the solar cell, one of the first surface and the second surface is the front side of the silicon substrate 30, and the other of the first surface and the second surface is the back side of the silicon substrate 30. One of the first semiconductor layer 10 and the second semiconductor layer 20 can be an N-type semiconductor layer, and the other of the first semiconductor layer 10 and the second semiconductor layer 20 can be a P-type semiconductor layer. The first semiconductor layer 10 and the second semiconductor layer 20 are disposed on the same surface of the silicon substrate 30 (such as the first surface). In some embodiments, the first semiconductor layer 10 is a P-type doped microcrystalline silicon layer, and the second semiconductor layer 20 is an N-type doped polycrystalline silicon layer, as an example.

[0015] Reference Figure 1 In some embodiments, a first semiconductor layer 10 and a second semiconductor layer 20 are disposed on a first surface of a silicon substrate 30. Since the first semiconductor layer 10 and the second semiconductor layer 20 have different electrical properties, alternating N-regions and P-regions can be formed on the first surface of the solar cell. The N-region is the electron transport region of the solar cell, corresponding to the second region 32 in this embodiment; the P-region is the hole transport region of the solar cell, corresponding to the first region 31 in this embodiment. The current collector electrode is typically a fine grid electrode, used to extract charge carriers from the solar cell. The bus electrode is typically a main grid electrode, used to combine the charge carriers transported by multiple current collector electrodes together.

[0016] N-regions and P-regions are alternately arranged on the first surface of the solar cell. Due to the presence of a platform region 33 and a ramp region 34 between the N-regions and P-regions, insulation isolation between the P-regions and N-regions can be achieved. In this embodiment of the invention, the platform region 33 and the ramp region 34 are located between the N-regions and P-regions, and the ramp region 34 is located between the first region 31 and the platform region 33. The first semiconductor layer 10 is conformally deposited on the silicon substrate surface of the platform region 33 and the ramp region 34.

[0017] The height of the platform region 33 relative to the height of the silicon substrate 30 is greater than that of the slope region 34 relative to the height of the silicon substrate 30. In other words, the thickness of the platform region 33 corresponding to the silicon substrate 30 is greater than that of the slope region 34 corresponding to the thickness of the silicon substrate 30. This creates a height difference between the platform region 33 and the slope region 34. The height of the slope region 34 can decrease uniformly along the second direction Y (perpendicular to the first direction X), thus forming a slope surface.

[0018] Specifically, the platform region 33 has a textured structure, meaning its surface is not a smooth plane. This textured structure increases the surface roughness of the platform region 33, thereby improving its light-trapping effect and increasing the light utilization rate of the solar cell, significantly enhancing its optical performance. Furthermore, the rough surface of the platform region 33 helps to strengthen the adhesion of subsequently deposited structural layers (such as the first semiconductor layer 10).

[0019] Furthermore, the slope region 34 has multiple vertical textures 41 and multiple arc-shaped textures 42, with the arc-shaped textures 42 superimposed on the vertical textures 41; the extension direction of the arc-shaped textures 42 is perpendicular to the extension direction of the vertical textures 41. This textured surface morphology, firstly, also has the aforementioned effects of increasing surface roughness, improving light-trapping effect, and enhancing the adhesion of subsequently deposited structural layers, thereby improving the passivation effect of the structural layers on the silicon substrate.

[0020] In addition, regarding Figure 1 In HIBC batteries, when etching the conductive layer between the N-region and P-region using etching paste, if the area between the N-region and P-region is smooth, the etching paste easily spreads along the second direction Y to the N-region and P-region, leading to over-etching of the conductive layer and affecting the solar cell's current collection. However, in this embodiment of the invention, the arc-shaped texture 42 extending along the first direction X is superimposed on the vertical texture 41 extending along the second direction Y. This structure can form a barrier against the etching paste, thereby preventing excessive spread of the etching paste.

[0021] In some embodiments, multiple vertical textures 41 are spaced apart along the second direction Y, and multiple arc-shaped textures 42 extending along the first direction X are superimposed on the vertical textures 41, and the multiple superimposed arc-shaped textures 42 are spaced apart along the second direction Y.

[0022] In the back-contact solar cell fabrication process of this invention, a wet texturing process can be used to texturize the front side of the silicon substrate, within the P-region opening (first region), forming a pyramid-shaped textured surface structure. Furthermore, this process creates the slope region and plateau region of this invention, as well as vertical textures on the slope region. A secondary texturing process can then be used to further superimpose arc-shaped textures onto the vertical textures in the slope region, while simultaneously forming a textured structure on the plateau region. The secondary texturing refers to etching using two texturing methods.

[0023] In some embodiments, refer to Figure 3 and Figure 4 The diagram shows the platform region 33 and the sloping region 34 after wet texturing. The platform region 33 has a smooth surface, while the sloping region 34 has vertical textures 41. Further reference... Figure 5 and Figure 6The diagram shows the platform region 33 and the slope region 34 after secondary texturing. It can be seen that the platform region 33 has a texture structure 331, and the slope region 34 has an arc-shaped texture 42 superimposed on the vertical texture.

[0024] Optional, refer to Figure 2 The texture structure of platform region 33 includes raised particles and a first recessed structure between the raised particles; the height difference between the raised particles and the first recessed structure is 1nm~15nm.

[0025] In this embodiment of the invention, the textured structure of the platform region 33 includes protruding particles and a first recessed structure. The height difference between the protruding particles and the first recessed structure is 1 nm to 25 nm. This creates an uneven surface structure in the platform region 33, which serves as a light-trapping effect for the solar cell, increasing the light utilization rate of the solar cell and significantly improving its optical performance. Furthermore, this uneven surface structure increases the surface roughness of the platform region 33, which helps to enhance the adhesion of subsequently deposited structural layers (such as the intrinsic amorphous silicon layer and the first semiconductor layer 10), thereby improving the passivation effect of the structural layers on the silicon substrate.

[0026] Optionally, the height of the protruding particles can be 1 nm to 20 nm.

[0027] In practical applications, the height of the protruding particles can be selected according to actual needs. For example, the height of the protruding particles can be any value among 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, and 20nm.

[0028] Optionally, in some embodiments, the surface roughness of the solar cell in the platform region 33 is less than the surface roughness of the solar cell in the slope region 34.

[0029] The roughness of the platform region is smaller than that of the slope region, according to reference... Figure 1 HIBC batteries in Figure 7 The tunnel oxide passivated back contact (TBC, TOPCon BC) solar cell is designed to prevent defects in the silicon substrate caused by excessive roughness gradient during the transition from the second region 32 to the first region 31. Therefore, the surface roughness of the platform region 33 is designed to be less than that of the solar cell in the slope region 34. In this application, roughness is quantified statistically by the number of textures per unit area under an electron microscope. For example, a higher texture count results in a higher roughness than a lower texture count.

[0030] In some embodiments, the surface roughness of the solar cell in platform region 33 is greater than the surface roughness of the solar cell in second region 32. Also refer to... Figure 1 HIBC batteries in Figure 7 The TBC cell in this design is mainly intended to increase the surface roughness gradient during the transition from the second region 32 to the first region 31, and to avoid the formation of defects in the silicon substrate caused by excessive differences. Therefore, the surface roughness of the platform region 33 is designed to be greater than that of the solar cell in the second region 32.

[0031] In some embodiments, the surface roughness of the solar cell in platform region 33 is greater than the surface roughness of the solar cell's sidewalls. The sidewalls of the solar cell include the four sides of the solar cell excluding the first and second surfaces. (See reference...) Figure 1 HIBC batteries in Figure 7 TBC batteries in Figure 8 The Poly-finger TOPCON cell has a roughness on the four sides of the cell that is less than that of the platform region 33, which can reduce defects at the edges of the silicon substrate on the four sides and reduce recombination at the edges of the cell.

[0032] Optional, refer to Figure 2 The height difference between the arc-shaped texture 42 on the vertical texture 41 and the second recessed structure between the arc-shaped texture 42 and the second recessed structure is 1nm-20nm. Alternatively, refer to... Figure 2 The vertical texture 41 has multiple spaced arc-shaped textures 42, and there is a second recessed structure between the arc-shaped textures 42. The height difference between the arc-shaped textures 42 and the second recessed structure is 1nm-20nm.

[0033] In this embodiment of the invention, the height difference between the arc-shaped texture 42 and the second recessed structure is 1nm-20nm, which can form an uneven surface structure in the slope region 34, which can achieve the light trapping effect of solar cells and enhance the adhesion of the subsequently deposited structural layer, and achieve a better insulation effect between the N region and the P region.

[0034] Furthermore, in HIBC cells, a first semiconductor layer 10 can be deposited on the surface of the slope region 34. The uneven structure formed by the arc-shaped texture 42 and the second recessed structure can improve the crystallinity of the first semiconductor layer 10 at the stacking position. The crystallinity of the structural layer is a key indicator of solar cells, describing the degree of order in the crystal structure within the structural layer. Simply put, a higher crystallinity indicates a more complete crystal structure, while a lower crystallinity indicates more defects or disordered regions in the crystal structure.

[0035] In practical applications, the height difference between the arc-shaped texture 42 on the vertical texture 41 and the second recessed structure between the arc-shaped texture 42 and the arc-shaped texture 42 can be selected according to actual needs. For example, the height difference can be any value among 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm, 9nm, 10nm, 11nm, 12nm, 13nm, 14nm, 15nm, 16nm, 17nm, 18nm, 19nm, and 20nm.

[0036] Optional, refer to Figure 5 In the sloping area 34, near the first area 41, there are multiple pyramid structures 43; the pyramid structures 43 have arc-shaped textures 42.

[0037] In some embodiments, the first region 41 has a plurality of pyramid structures 43, and the pyramid structures 43 have arc-shaped textures 42.

[0038] In this embodiment of the invention, the first region 41 undergoes a texturing process to form a surface structure with multiple pyramidal structures 43. Combined with a subsequent secondary texturing process, an arc-shaped texture 42 can be superimposed on the pyramidal structures 43 of the first region 41. This improves the light-trapping effect of the solar cell and enhances the adhesion of the first region 41 to the subsequently deposited structural layers. Furthermore, the superposition of the arc-shaped texture 42 and the pyramidal edges of the pyramidal structures 43 in the first region 41 can also improve the crystallinity of the first semiconductor layer 10 at the superposition location.

[0039] Furthermore, during the texturing process in the first region 41 to form multiple pyramid structures 43, some reagents will extend to the slope region 34 near the first region 41, thereby forming multiple pyramid structures 43 in the slope region 34 near the first region 41. After subsequent secondary texturing, arc-shaped textures 42 can be superimposed on the pyramid structures 43 in the slope region 34 near the first region 41. This superimposed structure helps to improve the crystallinity of the first semiconductor layer 10.

[0040] Optionally, the slope region has multiple pyramid structures located near the first region; the height of the texture structure on the platform region is less than the height of the arc texture structure on the slope region; and / or; the height of the texture structure on the platform region is less than the height of the arc texture on the pyramid; and / or; the height of the arc texture structure on the slope region is less than the height of the arc texture on the pyramid.

[0041] In this embodiment of the invention, the above-described settings can increase the passivation effect of the platform region and create a height gradient change in the texture from the platform region to the slope region and then to the pyramid structure, thereby reducing surface defects on the silicon substrate.

[0042] Optional, for HIBC batteries, refer to Figure 1 The first region 31, the second region 32, the platform region 33, and the slope region 34 are located on the first surface of the silicon substrate 30; the first region 31 and the second region 32 are arranged alternately; the platform region 33 and the slope region 34 are located between adjacent first regions 31 and second regions 32; the first semiconductor layer 10 includes an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer stacked sequentially; the intrinsic amorphous silicon layer is in contact with the silicon substrate; the second semiconductor layer 20 includes a passivation layer 51 disposed on the silicon substrate 30, a doped polycrystalline silicon layer 21 disposed on the passivation layer 51, and a portion of the first semiconductor layer 11 disposed on the doped polycrystalline silicon layer 21.

[0043] In this HIBC cell, a first region 31, a second region 32, a plateau region 33, and a ramp region 34 are located on the first surface of a silicon substrate 30. The first region 31 and the second region 32 are arranged alternately, and the plateau region 33 and the ramp region 34 are located between adjacent first regions 31 and second regions 32. The first semiconductor layer 10 includes an intrinsic amorphous silicon layer and a doped amorphous silicon layer stacked sequentially. The doped amorphous silicon layer can also be replaced by a nanocrystalline silicon layer or a microcrystalline silicon layer. The first semiconductor layer is conformally deposited on the silicon substrate surface of the first region 31, the plateau region 33, and the ramp region 34. The second semiconductor layer 20 includes a passivation layer 51 and a doped polycrystalline silicon layer 21 stacked sequentially. A conductive layer 70 is disposed on at least a portion of the first semiconductor layer 10 and at least a portion of the second semiconductor layer. Additionally, the solar cell may include electrodes and the conductive layer 70. The electrodes are disposed on the conductive layer 70, and the electrodes, together with the conductive layer 70 disposed below them, form a system for collecting and transporting charge carriers. The passivation layer 51 can perform a passivation function. The material of the passivation layer 51 is any one or more combinations of silicon oxide, aluminum oxide, silicon nitride, silicon carbide, and magnesium oxide.

[0044] Reference Figure 1 During the process, an isolation trench A needs to be formed on the first semiconductor layer 10. The isolation trench A is the trench structure generated after the conductive layer 70 is removed. Since the platform area has a textured structure and the slope area has a superposition structure of vertical texture and arc texture, the adhesion of the first semiconductor layer 10 deposited on the platform area and the slope area can be improved, resulting in good adhesion of the first semiconductor layer 10. Therefore, the first semiconductor layer 10 is not easily damaged during the formation of the isolation trench A, ensuring the passivation effect of the passivation layer at the location of the isolation trench A.

[0045] Optional, refer to Figure 1 The second surface, first region 31, platform region 33 and ramp region 34 of silicon substrate 30 have multiple pyramid structures; the pyramid structures have multiple arc-shaped textures.

[0046] In this embodiment of the invention, the second surface, first region 31, plateau region 33, and slope region 34 of the silicon substrate 30 can all be texturized to create surface structures with multiple pyramidal structures. The pyramidal structures, superimposed with the arcuate textures created by secondary texturing, can enhance the light-trapping effect of the second surface of the silicon substrate 30, as well as the first region 31, plateau region 33, and slope region 34 of the first surface of the silicon substrate 30, thereby improving the light utilization rate of the solar cell and increasing its power generation efficiency. Furthermore, the superposition of the pyramidal structures and the arcuate textures can also increase the adhesion of these regions to subsequently deposited structural layers.

[0047] Optionally, the first semiconductor layer 10 deposited on the pyramid structure in the first region 31 has a crystallinity at the arcuate texture 42 of the pyramid structure that is greater than the crystallinity at the non-arcuate texture of the pyramid structure.

[0048] In some embodiments, the crystallinity of the first semiconductor layer 10 deposited on the pyramid structure in the first region 31 is greater than that of the first semiconductor layer 10 deposited on the pyramid structure in the platform region 33 and the slope region 34 at the pyramid structure.

[0049] In this embodiment of the invention, the first semiconductor layer 10 with high crystallinity can effectively improve the conductivity of the solar cell, while the first semiconductor layer 10 with low crystallinity has better passivation performance and less parasitic absorption. This alternating arrangement of the first semiconductor layer 10 with high crystallinity and the first semiconductor layer 10 with low crystallinity can significantly improve the overall conversion efficiency of the cell.

[0050] Optionally, the conductive layer 70 deposited on the pyramid structure in the first region 31 has a higher crystallinity at the arcuate texture 42 of the pyramid structure than at the non-arcuate texture of the pyramid structure.

[0051] And / or, the crystallinity of the conductive layer 70 deposited on the pyramid structure in the first region 31 is greater than that of the conductive layer 70 deposited on the pyramid structure in the platform region 33 and the slope region 34 at the pyramid structure.

[0052] In this embodiment of the invention, the conductive layer 70 with a high crystallinity can effectively improve the conductivity of the solar cell, while the conductive layer 70 with a low crystallinity has better passivation performance and less parasitic absorption. This alternating arrangement of the conductive layer 70 with a high crystallinity and the conductive layer 70 with a low crystallinity can significantly improve the overall conversion efficiency of the cell.

[0053] Optionally, the plane of the ramp region is tilted at an angle of 20°-30° relative to the silicon substrate; The height difference between the first region and the second region is 1 μm to 10 μm, and / or, optionally, the height difference between the first region and the second region is 1 μm to 5 μm.

[0054] In practical applications, the tilt angle of the plane of the slope region relative to the silicon substrate can be selected according to actual needs. For example, the tilt angle of the plane of the slope region relative to the silicon substrate can be any value among 20°, 21°, 22°, 23°, 24°, 25°, 26°, 27°, 28°, 29°, and 30°.

[0055] In practical applications, the height difference between the first region and the second region can be selected according to actual needs. For example, the height difference between the first region and the second region can be any value among 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, 8μm, 9μm, and 10μm.

[0056] Optional, refer to Figure 1 The width w1 of the slope region is 0.3μm to 8μm, preferably 1μm to 3μm.

[0057] Specifically, the width of the slope region cannot be too narrow, as this will affect the subsequent deposition and passivation effect on the slope region. Within the aforementioned width range of the slope region, the deposition of the first semiconductor layer exhibits better conformal characteristics, thereby improving the passivation effect. Furthermore, the width of the slope region cannot be too wide, as this will affect the light-trapping effect of the battery.

[0058] In practical applications, the width of the slope region can be selected according to actual needs. For example, the width of the slope region can be any value among 0.3μm, 1μm, 2μm, 3μm, 4μm, 5μm, 6μm, 7μm, and 8μm.

[0059] Optionally, the width of the platform region is 50nm~600nm, and preferably, the width of the platform region is 150nm~400nm.

[0060] Specifically, the width of the platform region cannot be too narrow, as this will affect the subsequent passivation effect. Within the aforementioned width range of the platform region, the deposition of the first semiconductor layer exhibits better conformal characteristics, thereby improving the passivation effect. Secondly, the width of the platform region cannot be too wide, as this will negatively impact the light-trapping effect of the battery.

[0061] In practical applications, the width of the platform area can be selected according to actual needs. For example, the width of the platform area can be any value among 50nm, 10nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, and 600nm.

[0062] In TBC solar cells, refer to Figure 7 The first region 31, the second region 32, the platform region and the slope region are located on the first surface of the silicon substrate; the first region 31 and the second region 32 are arranged alternately; the platform region and the slope region are located between adjacent first regions 31 and second regions 32; a surface passivation layer 52 is deposited on the platform region and the slope region.

[0063] In this embodiment of the invention, for TBC batteries, refer to Figure 7 In the TBC battery, the first region 31, the second region 32, the platform region, and the ramp region are located on the first surface of the silicon substrate 30. The first region 31 and the second region 32 are arranged alternately, and there is an isolation region 35 between the first region 31 and the second region 32. The platform region 33 and the ramp region 34 can be located in the isolation region 35, and the platform region 33 is located close to the first region 31 (P region). A surface passivation layer 52 is deposited conformally on the platform region 33 and the ramp region 34. The surface passivation layer 52 is any one or any multiple layers of aluminum oxide, silicon nitride, and silicon oxynitride. For example, the surface passivation layer 52 can be a superposition structure of aluminum oxide layer and silicon nitride layer, or it can be a superposition structure of aluminum oxide layer and silicon oxynitride layer.

[0064] Because the platform region 33 has a textured structure and the slope region 34 has a superimposed structure of vertical and arc-shaped textures, the adhesion of the surface passivation layer 52 deposited on the platform region 33 and the slope region 34 can be improved. This results in good adhesion of the surface passivation layer 52, making it less prone to damage and less likely to experience film bursting, thus ensuring the passivation effect of the surface passivation layer 52 in the isolation region 35. By setting a textured structure in the platform region 33 and setting vertical and arc-shaped textures in the slope region 34, the surface roughness of these regions can be increased, thereby improving the light-trapping effect of the solar cell. In addition, the structure of arc-shaped texture superimposed on vertical texture in this embodiment of the invention can also form a barrier against the etching paste, thereby preventing excessive spread of the etching paste.

[0065] The TBC battery also includes a passivation layer 51, which can be a tunneling oxide layer. The passivation layer 51 is in contact with the silicon substrate 30. The first semiconductor layer 10 includes a doped polycrystalline silicon layer of one polarity (e.g., P-type); the second semiconductor layer 20 includes a doped polycrystalline silicon layer of another polarity (e.g., N-type). The surface passivation layer 52 is disposed on the platform region 33 and the ramp region 34 between the first region 31 and the second region 32. Additionally, the TBC battery also includes battery structures such as electrodes 60. Electrodes 60 of different polarities are alternately disposed, and the electrodes 60 pass through the surface passivation layer 52 and are in contact with the surface of the first semiconductor layer 10 or the second semiconductor layer 20.

[0066] In bifacial Topcon solar cells (Poly-finger TOPCON cells), refer to... Figure 8 The silicon substrate further includes: a third region 36; a first region 31, a third region 36, a platform region and a ramp region are located on the first surface of the silicon substrate 30, and a second region 32 is located on the second surface of the silicon substrate 30; the third region 36 is located on opposite sides of the first region 31 in the length extension direction; and the platform region 33 and the ramp region 34 are located between adjacent first regions 31 and third regions 36.

[0067] In this embodiment of the invention, the solar cell can be a Topcon bifacial cell with a polyfinger structure, as shown in the reference. Figure 8 In the Topcon bifacial solar cell with a polyfinger structure, the first region 31, the plateau region 33, and the ramp region 34 are located on the first surface of the silicon substrate 30, and the second region 32 is located on the other side of the silicon substrate. The plateau region 33 and the ramp region 34 are located on either side of the adjacent first region 31. The Topcon bifacial solar cell with a polyfinger structure also has a passivation layer 51, which can be a tunneling oxide layer. The passivation layer 51 is in contact with the silicon substrate 30. The first semiconductor layer 10 includes a doped polycrystalline silicon layer. The second semiconductor layer 20 includes a boron-doped layer. The electrode 60 on the second surface penetrates the surface passivation layer 52 and contacts the boron-doped layer. The electrode 60 on the first surface penetrates the surface passivation layer 52 and contacts the first semiconductor layer 10. The electrodes 60 on the first surface and the electrodes 60 on the second surface have different polarities.

[0068] The surface passivation layer 52 is disposed on the surface of the platform region 33 and the slope region 34, and can play a passivation role. The material of the surface passivation layer 52 is any one or more combinations of silicon oxide, aluminum oxide, silicon nitride, silicon carbide and magnesium oxide.

[0069] In this embodiment of the invention, the platform region 33 has a textured structure, and the slope region 34 has a superimposed structure of vertical texture and arc texture. This can improve the adhesion of the first semiconductor layer 10 deposited on the platform region 33 and the slope region 34, as well as increase the light trapping effect. In addition, this structure of arc texture superimposed on vertical texture can also form a barrier to the etchant, thereby preventing the etchant from being over-expanded.

[0070] This invention also provides a photovoltaic module, which includes a cover plate, a back sheet, and a solar cell disposed between the cover plate and the back sheet; the solar cell includes the solar cell described above.

[0071] The embodiments of the present invention do not specifically limit whether the photovoltaic module includes other structures. For example, the photovoltaic module may also include: a first encapsulating film disposed between the cover plate and the solar cell, and a second encapsulating film disposed between the back sheet and the solar cell.

[0072] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0073] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. For embodiments of devices, electronic devices, computer-readable storage media, and computer program products containing instructions, the descriptions are relatively simple because they are basically similar to the method embodiments; relevant parts can be referred to the descriptions of the method embodiments.

[0074] The above are merely preferred embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A solar cell, characterized in that, The solar cell includes a silicon substrate, a first semiconductor layer, and a second semiconductor layer; The silicon substrate includes: a first region, a second region, a plateau region, and a ramp region; The first semiconductor layer is conformally deposited on the first region; the second semiconductor layer is conformally deposited on the second region; the slope region is located between the first region and the platform region; the first semiconductor layer and the second semiconductor layer have different electrical properties; The platform area has a textured structure, and the slope area has multiple vertical textures and multiple arc-shaped textures, with the arc-shaped textures superimposed on the vertical textures; the extension direction of the arc-shaped textures is a first direction, which is the length extension direction of the current collector electrode of the solar cell, and the extension direction of the vertical textures is perpendicular to the first direction.

2. The solar cell according to claim 1, characterized in that, The texture structure of the platform area includes raised particles and a first recessed structure between the raised particles. The height difference between the protruding particles and the first recessed structure is 1 nm to 25 nm.

3. The solar cell according to claim 1, characterized in that, The surface roughness of the solar cell in the platform region is less than that in the slope region; and / or; The surface roughness of the solar cell in the platform region is greater than the surface roughness of the solar cell in the second region; and / or; The surface roughness of the solar cell in the platform region is greater than the surface roughness of the sidewall of the solar cell.

4. The solar cell according to claim 1, characterized in that, The vertical texture has multiple spaced arc-shaped textures, and there is a second recessed structure between the arc-shaped textures. The height difference between the arc-shaped textures and the second recessed structure is 1nm-20nm.

5. The solar cell according to claim 2, characterized in that, The height of the protruding particles is 1nm-20nm.

6. The solar cell according to claim 1, characterized in that, The slope region has multiple pyramid structures located near the first region; The pyramid structure has the aforementioned arc-shaped texture; And / or, the first region has multiple pyramid structures, on which the arc-shaped texture is present.

7. The solar cell according to claim 6, characterized in that, The height of the texture structure on the platform area is less than the height of the arc-shaped texture structure on the slope area. And / or; the height of the texture structure on the platform area is less than the height of the arc-shaped texture on the pyramid; And / or; the height of the arc-shaped texture structure on the slope region is less than the height of the arc-shaped texture on the pyramid.

8. The solar cell according to claim 1, characterized in that, The first region, the second region, the platform region, and the ramp region are located on the first surface of the silicon substrate; the first region and the second region are arranged alternately; the platform region and the ramp region are located between adjacent first regions and second regions; The first semiconductor layer includes a passivation layer and a doped polysilicon layer on the passivation layer; A surface passivation layer is deposited conformally on the platform area and the slope area.

9. The solar cell according to claim 1, characterized in that, The first region, the second region, the platform region, and the ramp region are located on the first surface of the silicon substrate; the first region and the second region are arranged alternately; the platform region and the ramp region are located between adjacent first regions and second regions; The first semiconductor layer comprises an intrinsic amorphous silicon layer and a doped amorphous silicon layer stacked sequentially; the first semiconductor layer contacts the silicon substrate in the first region and extends onto the silicon substrate in the platform region and the slope region. The second semiconductor layer includes a passivation layer disposed on the silicon substrate, a doped polysilicon layer disposed on the passivation layer, and a portion of the first semiconductor layer disposed on the doped polysilicon layer.

10. The solar cell according to claim 1, characterized in that, The silicon substrate further includes: a third region; The first region, the third region, the platform region, and the ramp region are located on the first surface of the silicon substrate, and the second region is located on the second surface of the silicon substrate; The third region is located on opposite sides of the first region in the length extension direction; the platform region and the slope region are located between the adjacent first region and the third region; The first semiconductor layer includes a passivation layer and a doped polysilicon layer on the passivation layer; A surface passivation layer is formed on the silicon substrate in the platform region, the slope region, and the third region.

11. The solar cell according to claim 9, characterized in that, The second surface of the silicon substrate, the first region, the platform region, and the slope region all have multiple pyramid structures; The pyramid structure has multiple of the aforementioned arc-shaped textures.

12. The solar cell according to claim 11, characterized in that, The crystallinity of the first semiconductor layer deposited on the pyramid structure in the first region is greater at the arcuate texture of the pyramid structure than at the non-arcuate texture of the pyramid structure. And / or, the crystallinity of the first semiconductor layer deposited on the pyramid structure in the first region at the pyramid structure in the first region is greater than the crystallinity of the first semiconductor layer deposited on the pyramid structure in the platform region and the slope region at the pyramid structure in the platform region and the slope region.

13. The solar cell according to claim 11, characterized in that, The conductive layer deposited on the pyramid structure in the first region has a higher crystallinity at the arc-shaped texture of the pyramid structure than at the non-arc-shaped texture of the pyramid structure. And / or, the conductive layer deposited on the pyramid structure in the first region has a crystallinity at the pyramid structure in the first region that is greater than the crystallinity of the conductive layer deposited on the pyramid structure in the platform region and the slope region that is at the pyramid structure in the platform region and the slope region.

14. The solar cell according to claim 1, characterized in that, The slope region is located at an angle of inclination of 20°-30° relative to the silicon substrate. The height difference between the first region and the second region is 1 μm to 10 μm, and / or; Optionally, the height difference between the first region and the second region is 1μm to 5μm.

15. The solar cell according to claim 1, characterized in that, The width of the slope region is 0.3μm to 8μm, preferably 1μm to 3μm.

16. The solar cell according to claim 1, characterized in that, The width of the platform region is 50nm~600nm, preferably 150nm~400nm.

17. A photovoltaic module, characterized in that, The photovoltaic module includes a cover plate, a back sheet, and a battery string disposed between the cover plate and the back sheet, the battery string including a plurality of solar cells connected in series by interconnecting elements; the solar cells include the solar cells as described in any one of claims 1 to 16.

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