Light emitting diode and light emitting device
By introducing a current blocking region into the light-emitting diode and utilizing the reverse cutoff characteristic of the PN junction, the problem of bridging electrode bending and breakage is solved, achieving higher device reliability and carrier cutoff function, and improving the lifespan of the light-emitting diode.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-08
- Publication Date
- 2026-04-14
AI Technical Summary
The bridging electrodes of existing high-voltage chips are prone to breakage in the bending area within the isolation trench, leading to reduced device reliability.
The reverse cutoff property of the PN junction is used to replace physical isolation. By forming a current blocking region between adjacent light-emitting units, electrical isolation is achieved by utilizing the reverse cutoff characteristic of the PN junction, reducing the bending degree of the bridging electrode and avoiding breakage.
This improves the reliability and carrier cutoff performance of light-emitting diodes, avoids device failure caused by bridging electrode breakage, and extends the device's lifespan.
Smart Images
Figure CN121865781A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor device technology, and specifically to a light-emitting diode and a light-emitting device. Background Technology
[0002] As consumers' demands for picture quality in display devices such as LCD TVs continue to rise, especially with the emergence of Mini-LED TVs and monitors, which are essentially still LCD products but utilize Mini-LEDs as backlights, the TVs achieve better display effects by creating more backlight zones. For example, Local Dimming technology is highly favored by TV manufacturers and is currently the mainstream technology for improving contrast ratio. This technology can effectively improve the dynamic contrast ratio of the display screen. Currently, backlight zones are composed of a large number of LED chips. The design of the LED chips, their associated electronic components, and circuit board solder joints are important factors affecting the cost of the display screen. In optimizing the backlight zones, considering both cost and picture quality, using LED chips (high-voltage chips) with multiple LED chips connected in series is the main approach. This chip can effectively improve the integration of the display panel and is also an effective way to simplify circuit design and reduce power consumption.
[0003] Existing high-voltage chips comprise multiple light-emitting regions connected in series, with adjacent regions linked by bridging electrodes. However, these bridging electrodes are typically formed within isolation trenches between adjacent light-emitting units. These bridging electrodes contain bending areas within the isolation trenches, which are prone to breakage, leading to high-voltage chip failure and reducing device reliability. Summary of the Invention
[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a light-emitting diode and a light-emitting device to reduce the failure or leakage problem of the light-emitting diode and improve the reliability of the device.
[0005] To achieve the above and other related objectives, the present invention provides a light-emitting diode, comprising:
[0006] The first semiconductor layer includes N mesa regions and N-1 current blocking regions disposed between adjacent mesa regions, where N≥2 and N is a positive integer. The conductivity type of the mesa regions is a first conductivity type, and the conductivity type of the current blocking regions is a second conductivity type opposite to the first conductivity type.
[0007] N mesa structures are disposed one-to-one on the N mesa regions of the first semiconductor layer, and each mesa structure includes at least an active layer and a second semiconductor layer.
[0008] Each mesa structure and the first semiconductor layer below it constitute a single light-emitting unit. Adjacent light-emitting units are electrically connected through bridging electrodes and electrically isolated through current blocking regions.
[0009] According to one aspect of the present invention, the present invention also provides a light-emitting device, including an encapsulation substrate and at least one light-emitting diode disposed on the encapsulation substrate, wherein the light-emitting diode is the aforementioned light-emitting diode.
[0010] Compared with the prior art, the light-emitting diode and light-emitting device described in this invention have at least the following beneficial effects:
[0011] The light-emitting diode of the present invention includes a first semiconductor layer and N mesa structures. The first semiconductor layer includes N mesa regions and N-1 current-blocking regions disposed between adjacent mesa regions, where N ≥ 2, and N is a positive integer. The conductivity type of the mesa regions is a first conductivity type, and the conductivity type of the current-blocking regions is a second conductivity type opposite to the first conductivity type. The current-blocking regions are used to electrically isolate adjacent mesa structures. The N mesa structures are disposed one-to-one on the N mesa regions of the first semiconductor layer. Each mesa structure includes at least an active layer and a second semiconductor layer. Each mesa structure and the first semiconductor layer below it constitute a single light-emitting unit. Adjacent light-emitting units are electrically connected through bridging electrodes, and the current-blocking regions block the flow of charge carriers between adjacent light-emitting units. Since the conductivity types of the current-blocking regions and the mesa regions are opposite, a PN junction is formed between their interfaces. The reverse cutoff performance of the PN junction is used to replace different methods of physical isolation, electrically isolating adjacent light-emitting units. This isolation method can reduce the bending degree of the bridging electrodes and simultaneously achieve better carrier cutoff function, improving the reliability of the device.
[0012] The light-emitting device of the present invention includes the above-mentioned light-emitting diode and similarly possesses the above-mentioned technical effects. Attached Figure Description
[0013] Figure 1 This is a top view of an existing high-voltage chip.
[0014] Figure 2 for Figure 1 A schematic diagram of the cross-sectional structure;
[0015] Figure 3 This is a top view of the structure of the light-emitting diode in an embodiment of the present invention;
[0016] Figure 4 This is a schematic diagram of the cross-sectional structure of the light-emitting diode in an embodiment of the present invention;
[0017] Figure 5 This is a schematic diagram of the cross-sectional structure of the light-emitting diode in an embodiment of the present invention;
[0018] Figure 6 This is a schematic diagram of the cross-sectional structure of a light-emitting diode in an embodiment of the present invention.
[0019] Illustration of reference numerals in the attached diagram:
[0020] 001, Light-emitting area; 002, Channel; 003, Metal bridging structure; 004, Bending.
[0021] 100, Light-emitting unit; 110, First semiconductor layer; 111, Mesa region; 112, Current blocking region; 113, First sub-layer; 114, Second sub-layer; 120, Mesa structure; 121, Active layer; 122, Second semiconductor layer; 130, Insulating layer; 140, Bridging electrode; 151, First electrode; 152, Second electrode; 160, Substrate. Detailed Implementation
[0022] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.
[0023] It should be understood that the illustrations provided in the embodiments of this invention are merely schematic representations of the basic concept of the invention. Although the illustrations only show components relevant to the invention and are not drawn according to the actual number, shape, and size of components in implementation, the shape, quantity, and proportion of each component can be arbitrarily changed in actual implementation, and the component layout may also be more complex. The structures, proportions, sizes, etc., shown in the accompanying drawings are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which this application can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the invention can produce, should still fall within the scope of the technical content disclosed in this application.
[0024] Reference Figure 1 and Figure 2In the design of high-voltage chips, multiple independent light-emitting regions 001 are integrated into a single LED chip. Each light-emitting region 001 has its own independent PN junction. Each high-voltage chip integrating multiple light-emitting regions 001 ultimately leaves one N-terminal and one P-terminal for wire bonding. Within the same light-emitting region 001 of the high-voltage chip, electrons must flow normally from the N-terminal to the P-terminal of the PN junction, and normal conduction of charge carriers must be achieved between different light-emitting regions 001. In this way, different light-emitting regions 001 within the same high-voltage chip emit light independently. Different light-emitting regions 001 are typically electrically connected using a metal bridge structure 003 (Inter Connect). This metal bridge structure 003 is the only connection channel for charge carriers between different light-emitting regions 001.
[0025] The light-emitting area 001 of a high-voltage chip is usually etched with ICP (Inductively Coupled Plasma Etching) to create a channel 002 for physical isolation. When the metal bridging structure 003 connects different light-emitting areas 001 through the channel 002, there will be many bends 004. These bends 004 place high demands on the mechanical strength and conductivity of the metal bridging structure 003. This is especially true for small-size multi-series structure designs, because the light-emitting area 001 is small and the bridging interface of the light-emitting area 001 cannot be designed with a large slope, resulting in a greater degree of bend. However, the metal bridging structure 003 at the bend 004 is prone to breakage, delamination, and other phenomena, which can lead to the failure of the high-voltage chip.
[0026] In view of the technical problems mentioned above and in the background section, we will continue to refer to... Figure 1 and 2 Current solutions typically involve adding an insulating material filling layer (not shown in the figure) within the ICP-etched channel 002, or skipping channel 002 etching and forming an insulating region (not shown in the figure) through ion implantation within the semiconductor layer between adjacent light-emitting regions 001. This physically isolates multiple light-emitting regions 001 while preventing severe bending 004 of the metal bridging structure 003, which could lead to breakage. However, the current solution of adding an insulating material filling layer within the ICP channel 002 suffers from a mismatch between the filling material and the thermal expansion system of the semiconductor layer. This mismatch can easily cause chip failure during end-user use. While the solution of forming an insulating region through ion implantation within the semiconductor layer achieves consistency in the connecting materials of adjacent light-emitting regions 001, ion implantation can still disrupt the crystal lattice, creating tiny leakage channels that ultimately affect device reliability.
[0027] To address the background technology and the aforementioned technical problems, this embodiment provides a light-emitting diode and a light-emitting device. This light-emitting diode can reduce light-emitting diode failure or leakage problems, thereby improving device reliability.
[0028] Specifically, this embodiment provides a light-emitting diode, including:
[0029] The first semiconductor layer includes N mesa regions and N-1 current blocking regions disposed between adjacent mesa regions, where N≥2 and N is a positive integer. The conductivity type of the mesa regions is a first conductivity type, and the conductivity type of the current blocking regions is a second conductivity type opposite to the first conductivity type.
[0030] N mesa structures are disposed one-to-one on the N mesa regions of the first semiconductor layer, and each mesa structure includes at least an active layer and a second semiconductor layer.
[0031] In this embodiment, each mesa structure and its underlying first semiconductor layer constitute a single light-emitting unit. Adjacent light-emitting units are electrically connected via bridging electrodes and electrically isolated via current-blocking regions. A PN junction is formed at the interface between the current-blocking region and the mesa region, electrically isolating adjacent light-emitting units. This embodiment utilizes the reverse cutoff characteristic of the PN junction. During ion implantation, through ion selection and process improvement, the polarity of the semiconductor material in the implanted region is reversed, forming a PN junction at the interface between different light-emitting units. The reverse cutoff performance of the PN junction replaces different methods of physical isolation, thereby reducing the bending degree of the bridging electrodes, improving the breakage of the bridging electrodes, and achieving better carrier cutoff performance, thus improving the reliability of client applications.
[0032] Optionally, the first semiconductor layer is an N-type semiconductor layer, the second semiconductor layer is a P-type semiconductor layer, and the current blocking region is doped with P-type impurity ions.
[0033] Optionally, the first semiconductor layer is a P-type semiconductor layer, the second semiconductor layer is an N-type semiconductor layer, and the current blocking region is doped with N-type impurity ions.
[0034] Optionally, the surface of the platform area is flush with the surface of the current blocking area.
[0035] Optionally, the mezzanine area includes a flat portion and a raised portion, the surface of the flat portion is flush with the surface of the current blocking region, the surface of the raised portion is higher than the surface of the flat portion, and the mezzanine structure is formed on the surface of the raised portion.
[0036] Optionally, the first semiconductor layer includes a first sublayer and a second sublayer, wherein the first sublayer is formed as a flat portion and the second sublayer is formed as a protrusion.
[0037] Optionally, the first sub-layer is a first current extension layer.
[0038] Optionally, the impurity ion doping concentration of the first semiconductor layer is between 1E16 atcoms / cm². 3 ~5E20 atcoms / cm 3.
[0039] Optionally, the impurity ion doping concentration in the current blocking region is between 1E16 atcoms / cm². 3 ~5E20 atcoms / cm 3 .
[0040] Optionally, the current blocking region extends from the surface of the first semiconductor layer into the interior of the first semiconductor layer, and the depth of the current blocking region is greater than or equal to the thickness of the first semiconductor layer, so as to avoid leakage of adjacent light-emitting units.
[0041] Optionally, the bridging electrode extends from the mesa region of the first semiconductor layer of one of the adjacent light-emitting units through the surface of the current blocking region to the surface of the second semiconductor layer on the mesa structure of another adjacent light-emitting unit, and the current blocking region is electrically isolated from the bridging electrode.
[0042] Optionally, the light-emitting diode includes a substrate that is attached to the side of the first semiconductor layer facing away from the mesa structure.
[0043] Optionally, the substrate is a growth substrate or a bonding substrate.
[0044] Optionally, the width of the current blocking region along the direction parallel to the surface of the first semiconductor layer is 0.0001μm to 1000μm. Since the current blocking region in this embodiment blocks the current by forming a PN junction with the mesa region, its width can be set to be smaller. This is not only beneficial for reducing the size of the high voltage chip, but also beneficial for saving the functional area of the first semiconductor layer and improving the light-emitting performance of the light-emitting diode.
[0045] Optionally, the light-emitting diode also includes:
[0046] The first electrode is electrically connected to the first semiconductor layer;
[0047] The second electrode is electrically connected to the second semiconductor layer.
[0048] This embodiment also provides a light-emitting device, which includes a packaging substrate and at least one light-emitting diode disposed on the packaging substrate, wherein the light-emitting diode is the aforementioned light-emitting diode. Furthermore, the light-emitting device in this embodiment can avoid device failure caused by bridging electrode breakage and can also avoid leakage between adjacent light-emitting units, thus improving the reliability and lifespan of the device.
[0049] The present invention will now be described in detail with reference to specific embodiments.
[0050] Example 1
[0051] This embodiment provides a light-emitting diode, as shown in the reference. Figure 3 or Figure 4 The light-emitting diode includes a first semiconductor layer 110 and a plurality of mesa structures 120 spaced apart on the first semiconductor layer 110.
[0052] Among them, reference Figure 4 The first semiconductor layer 110 can be an N-type semiconductor layer intentionally doped with N-type impurities, or a P-type semiconductor layer intentionally doped with P-type impurities. The N-type semiconductor layer provides electrons, and the P-type semiconductor layer provides holes. Optionally, the N-type impurities can be Si, Ge, Sn, Se, and Te. The P-type impurities can be Mg, Zn, Ca, Sr, and Ba. In this embodiment, the first semiconductor layer 110 is an N-type semiconductor layer. Optionally, the material of the first semiconductor layer 110 is Al. x Ga 1-x InP, 0≤x≤0.1.
[0053] Reference Figure 3 or Figure 4 The first semiconductor layer 110 includes N mesa regions 111 and N-1 current blocking regions 112 disposed between adjacent mesa regions 111, where N ≥ 2 and N is a positive integer. The mesa regions 111 have a first conductivity type, and the current blocking regions 112 have a second conductivity type opposite to the first conductivity type. In this embodiment, the first semiconductor layer 110 is doped with impurity ions of the opposite conductivity type to form the N-1 current blocking regions 112, and the portions separated by the N-1 current blocking regions 112 are formed as mesa regions 111. Optionally, the current blocking regions 112 extend from the surface of the first semiconductor layer 110 into the interior of the first semiconductor layer 110, with an extension depth greater than or equal to the thickness of the first semiconductor layer 110, to completely electrically isolate adjacent mesa regions 111. In this embodiment, the mesa regions 111 are N-type semiconductor layers with N-type conductivity. The current blocking regions 112 are P-type semiconductor layers doped with P-type impurities with P-type conductivity. Of course, it is also possible to set the platform area 111 to P-type conductivity and the current blocking area 112 to N-type conductivity.
[0054] The surface of the platform area 111 can be flush with the surface of the current blocking area 112, or it can have a protrusion that extends above the current blocking area 112. In this embodiment, referring to... Figure 4The surface of the mesa region 111 is flush with the surface of the current blocking region 112. In other embodiments, the mesa region 111 may include a flat portion flush with the surface of the current blocking region 112 and a raised portion extending above the flat portion. The material of the flat portion may be the same as, different from, or partially the same as the material of the raised portion. Optionally, the first semiconductor layer 110 can be understood as including multiple doped layers with different functions, such as a current spreading layer or an ohmic contact layer, etc., and this embodiment does not impose any limitations on this.
[0055] Reference Figure 4 N mesa structures 120 are disposed one-to-one on the N mesa regions 111 of the first semiconductor layer 110. Each mesa structure 120 includes at least an active layer 121 and a second semiconductor layer 122. A current blocking region 112 electrically isolates adjacent mesa structures 120 by means of a conductivity type opposite to that of the mesa regions 111. Optionally, each mesa structure 120 includes at least an active layer 121 and a second semiconductor layer 122, the second semiconductor layer 122 having a conductivity type opposite to that of the first semiconductor layer 110. The active layer 121 is formed above the first semiconductor layer 110 and provides a region for providing light radiation to facilitate electron-hole recombination. Different materials can be selected depending on the emission wavelength. The active layer 121 can be a periodic structure of a single quantum well or multiple quantum wells. The active layer 121 includes a well layer and a barrier layer, wherein the barrier layer has a larger band gap than the well layer. By adjusting the composition ratio of the semiconductor material in the active layer 121, it is desired to radiate light of different wavelengths. In this embodiment, the active layer 121 is a multi-quantum-well layer, and the repetition period of the well layer and the barrier layer is between 1 and 60. The material of the active layer 121 is Al. x Ga 1-x InP, 0≤x≤1. The second semiconductor layer 122 can be an N-type semiconductor layer intentionally doped with N-type impurities, or a P-type semiconductor layer intentionally doped with P-type impurities. The N-type semiconductor layer provides electrons, and the P-type semiconductor layer provides holes. Optionally, the N-type impurities can be Si, Ge, Sn, Se, and Te. The P-type impurities can be Mg, Zn, Ca, Sr, and Ba. In this embodiment, the second semiconductor layer 122 is a P-type semiconductor layer. Optionally, the material of the second semiconductor layer 122 is Al. x Ga 1-x In P , 0.5≤x≤1.
[0056] Reference Figure 4The mesa structure 120 is formed on the mesa region 111 of the first semiconductor layer 110. When the mesa region 111 includes a protrusion, the mesa structure 120 is formed on the protrusion of the mesa region 111. In this embodiment, the first semiconductor layer 110 is an N-type semiconductor layer, the second semiconductor layer 122 is a P-type semiconductor layer, and the current blocking region 112 is doped with P-type impurity ions. Thus, a PN junction is formed between the interface between the current blocking region 112 and the mesa region 111. The reverse cutoff performance of the PN junction is used to replace different methods of physical isolation, electrically isolating adjacent light-emitting units 100. This isolation method can reduce the bending degree of the bridging electrode 140 and simultaneously achieve better carrier cutoff function, improving the reliability of client applications. Optionally, the impurity ion doping concentration of the first semiconductor layer 110 is between 1E16 atcoms / cm³. 3 ~5E20 atcoms / cm 3 Optionally, the doping concentration of impurity ions in the current blocking region 112 is between 1E16 atcoms / cm². 3 ~5E20 atcoms / cm 3 .
[0057] Reference Figure 4 Each mesa structure 120 and its underlying first semiconductor layer 110 constitute a single light-emitting unit 100, and adjacent light-emitting units 100 are electrically connected via a bridging electrode 140. The bridging electrode 140 extends from the mesa region 111 of the first semiconductor layer 110 of one of the adjacent light-emitting units 100 through the surface of the current blocking region 112 to the surface of the second semiconductor layer 122 of the mesa structure 120 of the other adjacent light-emitting unit 100, and the current blocking region 112 is electrically isolated from the bridging electrode 140. Optionally, at least an insulating layer 130 is provided between the current blocking region 112 and the bridging electrode 140 to achieve electrical insulation between the current blocking region 112 and the bridging electrode 140. Optionally, the material of the insulating layer 130 can be silicon dioxide or silicon nitride.
[0058] Optionally, refer to Figure 4 The light-emitting diode also includes a substrate 160, which is attached to one side of the mesa structure 120 opposite to the first semiconductor layer 110. Optionally, the substrate 160 can be a growth substrate or a base plate. The growth substrate can be sapphire, gallium nitride, or gallium arsenide. Optionally, the substrate 160 can be a sapphire base plate. When the substrate is a bonding base plate, the growth substrate used in epitaxial growth has been removed during the process, and the bonding base plate is bonded to the first semiconductor layer 110 through a bonding layer.
[0059] Optionally, refer to Figure 4The width W of the current blocking region 112 along the direction parallel to the surface of the first semiconductor layer 110 is between 0.0001 μm and 1000 μm. Since the current blocking region 112 in this embodiment blocks current by forming a PN junction with the mesa region 111, its width can be smaller. This not only helps to reduce the size of the high-voltage chip but also saves functional areas of the first semiconductor layer 110, thus improving the light-emitting performance of the LED. In existing solutions that use an insulating material filling layer to physically isolate adjacent light-emitting units 100, dopant ions from the semiconductor layer adjacent to the insulating material filling layer diffuse into the insulating material filling layer during the manufacturing process, weakening or even eliminating the physical isolation effect. It is necessary to increase the size of the insulating material filling layer to prevent dopant ions from completely diffusing into the insulating material filling layer and causing leakage. However, this embodiment utilizes the reverse non-conducting characteristic of the PN junction, which can greatly improve the current blocking effect. Even with a small size of the current blocking region 112, its cutoff performance can be achieved, reducing the leakage performance of the device and thus improving the reliability of the high-voltage chip.
[0060] Optionally, refer to Figure 3 and Figure 4 The light-emitting diode also includes a first electrode 151 and a second electrode 152. The first electrode 151 is electrically connected to the first semiconductor layer 110. In this embodiment, the first electrode 151 is formed on the mesa region 111 of the first semiconductor layer 110. The second electrode 152 is electrically connected to the second semiconductor layer 122 of the mesa structure 120. In this embodiment, the second electrode 152 is formed on the mesa structure 120 and electrically connected to the second semiconductor layer 122 on the mesa structure 120. In this embodiment, the first electrode 151 is an N-electrode and the second electrode 152 is a P-electrode.
[0061] Example 2
[0062] This embodiment provides a light-emitting diode (LED). The similarities between this LED and that in Embodiment 1 will not be repeated here. The differences are as follows:
[0063] Reference Figure 5 In this embodiment, the first semiconductor layer 110 is a P-type semiconductor layer, the second semiconductor layer 122 is an N-type semiconductor layer, and the current blocking region 112 is doped with N-type impurity ions. At this time, the first electrode 151 is a P-type electrode, and the second electrode 152 is an N-type electrode. Thus, a PN junction is formed at the interface between the current blocking region 112 and the mesa region 111. The reverse cutoff performance of the PN junction is used to replace different methods of physical isolation, electrically isolating adjacent light-emitting units 100. This isolation method can reduce the bending degree of the bridging electrode 140 and simultaneously achieve better carrier cutoff function, improving the reliability of client applications.
[0064] Example 3
[0065] This embodiment provides a light-emitting diode (LED). The similarities between this LED and that in Embodiment 1 will not be repeated here. The differences are as follows:
[0066] Reference Figure 6 In this embodiment, the first semiconductor layer 110 is a P-type semiconductor layer, the second semiconductor layer 122 is an N-type semiconductor layer, and the current blocking region 112 is doped with N-type impurity ions. In this case, the first electrode 151 is a P-type electrode, and the second electrode 152 is an N-type electrode. The first semiconductor layer 110 may include a first sub-layer 113 and a second sub-layer 114. The first sub-layer 113 may be a first current spreading layer, mainly used for current spreading. Optionally, the first sub-layer 113 is a P-type current spreading layer, and its material may be GaP; the second sub-layer 114 is a P-type confinement layer, and its material may be AlGaInP or AlInP. In other embodiments, the first semiconductor layer 110 may be an N-type semiconductor layer, in which case the first sub-layer 113 is an N-type current spreading layer. For example, its material may be AlGaInP, and the second sub-layer 114 is an N-type confinement layer, and its material may be AlInP.
[0067] In this embodiment, the mezzanine area 111 includes a flat portion and a raised portion. The surface of the flat portion is flush with the surface of the current blocking region 112, and the surface of the raised portion is higher than the surface of the flat portion. The mezzanine structure 120 is formed on the raised portion of the mezzanine area 111. Optionally, referring to... Figure 6 The flat portion of the first semiconductor layer 110 is formed as a first sublayer 113, and the raised portion is formed as a second sublayer 114. A first electrode 151 is formed on the flat portion of the first semiconductor layer 110, that is, on the first sublayer 113, and a second electrode 152 is formed on the second semiconductor layer 122 of the mesa structure 120.
[0068] Similarly, in this embodiment, a PN junction is formed at the interface between the current blocking region 112 and the mesa region 111. This PN junction has reverse cutoff performance, which can achieve carrier cutoff between adjacent light-emitting units 100, which is beneficial to the reliability of the device.
[0069] Example 4
[0070] This embodiment provides a light-emitting device, which includes a packaging substrate and at least one light-emitting diode (LED) disposed on the packaging substrate. The LED is any one of the LEDs described in embodiments 1 to 3. When there are multiple LEDs, they are spaced apart on the packaging substrate. The multiple LEDs can be fixed to the packaging substrate by wire bonding or wire bonding. The light-emitting device in this embodiment can avoid device failure caused by broken bridging electrodes and can also avoid leakage between adjacent light-emitting units, which is beneficial to the reliability and lifespan of the device.
[0071] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.
Claims
1. A light-emitting diode, characterized in that, include: A first semiconductor layer, comprising N mesa regions and N-1 current blocking regions disposed between adjacent mesa regions, where N≥2 and N is a positive integer, the mesa regions are of a first conductivity type, and the current blocking regions are of a second conductivity type opposite to the first conductivity type. N mesa structures are disposed one-to-one on the N mesa regions of the first semiconductor layer, and each mesa structure includes at least an active layer and a second semiconductor layer. Each of the mesa structures and the first semiconductor layer below it constitute a single light-emitting unit. Adjacent light-emitting units are electrically connected through bridging electrodes and electrically isolated through the current blocking region.
2. The light-emitting diode according to claim 1, characterized in that, A PN junction is formed between the interface between the current blocking region and the mesa region, and the PN junction electrically isolates adjacent light-emitting units.
3. The light-emitting diode according to claim 1, characterized in that, The first semiconductor layer is an N-type semiconductor layer, the second semiconductor layer is a P-type semiconductor layer, and the current blocking region is doped with P-type impurity ions.
4. The light-emitting diode according to claim 1, characterized in that, The first semiconductor layer is a P-type semiconductor layer, the second semiconductor layer is an N-type semiconductor layer, and the current blocking region is doped with N-type impurity ions.
5. The light-emitting diode according to claim 1, characterized in that, The surface of the platform area is flush with the surface of the current blocking area.
6. The light-emitting diode according to claim 1, characterized in that, The platform area includes a flat portion and a raised portion. The surface of the flat portion is flush with the surface of the current blocking region, and the surface of the raised portion is higher than the surface of the flat portion. The platform structure is formed on the surface of the raised portion.
7. The light-emitting diode according to claim 6, characterized in that, The first semiconductor layer includes a first sublayer and a second sublayer, wherein the first sublayer is formed as the flat portion and the second sublayer is formed as the protruding portion.
8. The light-emitting diode according to claim 7, characterized in that, The first sub-layer is the first current extension layer.
9. The light-emitting diode according to claim 1, characterized in that, The impurity ion doping concentration of the first semiconductor layer is between 1E16 atcoms / cm 3 ~5E20 atcoms / cm 3 .
10. The light-emitting diode according to claim 1, characterized in that, The impurity ion doping concentration in the current blocking region is between 1E16 atcoms / cm² 3 ~5E20 atcoms / cm 3 .
11. The light-emitting diode according to claim 1, characterized in that, The current blocking region extends from the surface of the first semiconductor layer into the interior of the first semiconductor layer, and the depth of the current blocking region is greater than or equal to the thickness of the first semiconductor layer.
12. The light-emitting diode according to claim 1, characterized in that, The bridging electrode extends from the mesa region of the first semiconductor layer of one of the adjacent light-emitting units through the surface of the current blocking region to the surface of the second semiconductor layer on the mesa structure of another adjacent light-emitting unit, wherein the current blocking region is electrically isolated from the bridging electrode.
13. The light-emitting diode according to claim 1, characterized in that, The light-emitting diode includes a substrate, which is attached to the side of the first semiconductor layer opposite to the mesa structure.
14. The light-emitting diode according to claim 13, characterized in that, The substrate is a growth substrate or a bonding substrate.
15. The light-emitting diode according to claim 1, characterized in that, The width of the current blocking region along the direction parallel to the surface of the first semiconductor layer is 0.0001 μm to 1000 μm.
16. The light-emitting diode according to claim 1, characterized in that, The light-emitting diode also includes: The first electrode is electrically connected to the first semiconductor layer; The second electrode is electrically connected to the second semiconductor layer.
17. A light-emitting device, characterized in that, It includes a packaging substrate and at least one light-emitting diode disposed on the packaging substrate, wherein the light-emitting diode is the light-emitting diode according to any one of claims 1 to 16.