Phase change memory device based on scandium-tellurium binary alloy

Abstract

The invention discloses a phase change memory device based on a scandium-tellurium binary alloy. The phase change memory device structurally comprises a bottom electrode, a phase change layer, a buffer layer, a gating layer and a top electrode in sequence from bottom to top, wherein the gating layer and the phase change layer are both made of scandium-tellurium (Sc-Te) binary alloy, the chemical formula of the material of the gating layer is Sc < x > Te < 100-x >, and 0 lt; x is less than or equal to 8 and is atomic percent of elements; the chemical formula of the material of the phase change layer is ScyTe100-y, wherein 8lt; y is less than or equal to 40 and is atomic percent of elements. The scandium element doped tellurium material is used for alloying, and the scandium element can effectively regulate and control the crystallization behavior of the alloy in a specific proportion range, so that the conversion of volatile and non-volatile switch functions is realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more specifically to a phase-change memory device based on a scandium-tellurium binary alloy. Background Technology

[0002] Phase-change memory (PCM) has become one of the key technologies for next-generation storage-class memory (SCM) due to its non-volatility, high read / write speed, and excellent scalability. Its principle is to store information by utilizing the reversible conversion between high-resistivity amorphous and low-resistivity crystalline states of chalcogenides under electrical pulse drive. When constructing high-density 3DX-point memory arrays, to suppress leakage current between cells, each non-volatile PCM memory cell typically needs to be vertically connected in series with a volatile gating cell, forming a gating transistor and a memory cell (1S1R) structure. The octonic threshold switch (OTS) is a volatile switch based on chalcogenides. Due to its highly nonlinear current-voltage (IV) characteristics and good compatibility with PCM technology, it is considered an ideal gating device.

[0003] However, the traditional 1S1R structure requires the integration of two chalcogenide materials with different compositions and properties. For example, a germanium-antimony-tellurium (Ge-Sb-Te, GST) alloy can be used as the PCM layer, while another specific chalcogenide glass (such as the As-Te-Ge-Si system) can be used as the OTS layer. This integration of heterogeneous materials not only increases the complexity of the material system and the difficulty of the manufacturing process (such as requiring multiple different functional layer thin film deposition processes), but also can cause elemental diffusion or phase separation between different layers under long-term high-frequency cycling, leading to device performance degradation or even failure.

[0004] Therefore, there is an urgent need in the field for a new and simplified material system that can simultaneously meet the performance requirements of both OTS and PCM units by controlling the composition of a single material system, thereby simplifying the manufacturing process and improving the long-term reliability of the device. Summary of the Invention

[0005] To overcome the shortcomings of the existing technology, the present invention provides a phase change memory device based on a scandium-tellurium binary alloy. This device utilizes scandium doping to alloy tellurium materials. Scandium can effectively control the crystallization behavior of the alloy within a specific ratio range, thereby realizing the switching between volatile and non-volatile switching functions.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A phase change memory device based on a scandium-tellurium binary alloy, with a structure from bottom to top being a bottom electrode, a phase change layer, a buffer layer, a select gate layer, and a top electrode in sequence; Among them, both the select gate layer and the phase change layer are composed of a scandium-tellurium (Sc-Te) binary alloy. The chemical formula of the select gate layer material is Sc x Te 100-x , where 0 < x ≤ 8 and x is the atomic percentage of the element; the chemical formula of the phase change layer material is Sc y Te 100-y , where 8 < y ≤ 40 and y is the atomic percentage of the element.

[0007] The select gate layer exhibits volatile threshold switching (OTS) characteristics; under this composition,; Sc x Te 100-x The material is crystalline at room temperature, at this time it is in a high-resistance state, and the device circuit is in an off state; when an electrical pulse is applied, it becomes a molten state, at this time it is in a low-resistance state, realizing circuit conduction. The range of the applied pulse voltage is 0.5 - 5V, and the pulse width is 10 - 1000ns; after the pulse stops; Sc x Te 100-x The material recrystallizes, at this time it is in a high-resistance state, and the circuit is in an off state.

[0008] The phase change layer exhibits non-volatile phase change memory (PCM) characteristics; under this composition, Sc y Te 100-y There is a significant resistance difference (more than 3 orders of magnitude) between the crystalline state and the amorphous state of the material, realizing reliable data storage; Sc y Te 100-y The material is amorphous at room temperature, at this time it is in a high-resistance state, serving as the logic state "0"; after applying an electrical pulse, Sc y Te 100-y The material changes to a crystalline state, at this time it is in a low-resistance state, serving as the logic state "1", and it can remain in the crystalline state after the pulse stops; after applying an electrical pulse again, Sc y Te 100-y The material changes to an amorphous state, at this time it is in a high-resistance state, serving as the logic state "0", and it can remain in the amorphous state after the pulse stops.

[0009] The phase change memory device based on the scandium-tellurium binary alloy controls the opening and closing of the circuit through the select gate layer, and controls the storage and erasure of data through the phase change layer; In the initial state of the device, the gating layer is crystalline, the circuit is off, and the phase change layer is amorphous, which is logic state "0". When a write pulse is applied, the gating layer material is molten, the circuit is turned on, and the electrical pulse is further applied to the phase change layer, causing it to change from amorphous to crystalline, becoming logic state "1". When the pulse ends, the gating layer material becomes crystalline again, the circuit is off, and the phase change layer material remains crystalline, maintaining logic state "1". When an erase pulse is applied, the gating layer material is molten, the circuit is turned on, and the electrical pulse is further applied to the phase change layer, causing it to change from crystalline to amorphous, becoming logic state "0".

[0010] The thickness of the gate layer is 10-50 nm, and the thickness of the phase change layer is 10-50 nm. A buffer layer is disposed between the phase change layer and the gated layer, and its material is carbon (C), with a thickness of 2-10 nm. The materials of the bottom electrode and the top electrode are one or a combination of common electrode materials such as W, TiN, and Pt.

[0011] The phase change layer is prepared by one of the following methods: magnetron sputtering, vacuum evaporation, atomic layer deposition, or chemical vapor deposition.

[0012] The device is used to construct high-density cross-point memory arrays, storage-class memory, and embedded non-volatile memory chips.

[0013] The beneficial effects of this invention are: This invention is the first to propose that, using only a single Sc-Te binary system, the ratio of Sc to Te can be changed during the manufacturing process (e.g., adjusting the power ratio of the co-sputtering target) to fabricate both a volatile gated layer (OTS) and a non-volatile phase change layer (PCM) in the same device. This greatly simplifies the material selection for different functional layers in 3D integrated memory processes, reducing manufacturing complexity and cost.

[0014] The device provided by this invention has a simple structure and compact size, which can effectively improve the chip integration density. Moreover, its fabrication process (magnetron sputtering) is compatible with existing CMOS processes and is easy to carry out large-scale integrated production. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the phase-change electronic device in an embodiment of the present invention.

[0016] Figure 2 For Sc x Te 100-x The resistance-temperature curve of the alloy thin film, with x ranging from 0 to 1. <x≤8。

[0017] Figure 3 For Sc y Te100-y The resistance-temperature curve of the alloy film, where the value range of y is 8 < y ≤ 40.

[0018] Figure 4 It is a schematic diagram of the working mechanism of the selection layer based on the scandium-tellurium binary alloy.

[0019] Figure 5 It is a schematic diagram of the working mechanism of the phase change layer based on the scandium-tellurium binary alloy.

[0020] Figure 6 It is a schematic diagram of the working mechanism of the phase change memory device based on the scandium-tellurium binary alloy. Specific implementation manners

[0021] The present invention will be further described in detail below with reference to the accompanying drawings.

[0022] Figure 1 It is a schematic diagram of the structure of the phase change electronic device in an embodiment of the present invention. The device includes, from bottom to top in sequence: 1-bottom electrode, 2-phase change functional layer, 3-buffer layer, 4-selection layer, and 5-top electrode.

[0023] Figure 2 For Sc x Te 100-x The resistance-temperature curve of the alloy film, where the value range of x is 0 < x ≤ 8. The as-deposited film is in the crystalline state, and the resistance value is about 10 4 Ω. Heating at a rate of 10 °C / min, as the temperature rises, the resistance of the crystalline film decreases slowly. After heating to 300 °C and then cooling, as the temperature drops, the resistance of the crystalline film rises slowly, and the resistance at room temperature after cooling is close to the initial resistance value.

[0024] Figure 3 For Sc y Te 100-y The resistance-temperature curve of the alloy film, where the value range of y is 8 < y ≤ 40. The as-deposited film is in the amorphous state, and the resistance value is relatively high, about 6 × 10 7 Ω. Heating at a rate of 10 °C / min, as the temperature rises, the resistance of the amorphous film decreases linearly; when the temperature rises to ~160 °C, the resistance drops rapidly, indicating that the film begins to crystallize. After heating to​​​​​This diagram illustrates the working mechanism of a gated layer based on a scandium-tellurium binary alloy. It switches the circuit on and off by switching between a crystalline state and a molten state. Initially, the material is in a high-resistance crystalline state, and the circuit is off. When an electrical pulse exceeding a threshold voltage is applied, the material partially melts, forming a low-resistance molten conductive channel, and the circuit becomes conductive. Once the pulse stops, the molten region rapidly recrystallizes, returning to the high-resistance initial state, and the circuit automatically shuts off. This process is volatile.

[0026] Figure 5 This diagram illustrates the working mechanism of a phase transition layer based on a scandium-tellurium binary alloy. It stores information by switching between two stable states. The high-resistivity amorphous state represents logic state "0," and the low-resistivity crystalline state represents logic state "1." By applying a high-energy "erase pulse" (RESET pulse), the material can be melted and rapidly quenched to the amorphous state (logic state "0"). By applying a low-energy, long-width "write pulse" (SET pulse), the material can be heated above its crystallization temperature, transforming it into the crystalline state (logic state "1"). This process is non-volatile.

[0027] Figure 6 This is a schematic diagram illustrating the working mechanism of a phase-change memory device based on a scandium-tellurium binary alloy. It controls the on / off state of the circuit through a gating layer and the storage and erasure of data through a phase-change layer. In the initial state, the gating layer is crystalline, the circuit is off, and the phase-change layer is amorphous, representing logic state "0". When a write pulse is applied, the gating layer material melts, the circuit is turned on, and the pulse is further applied to the phase-change layer, causing it to change from amorphous to crystalline, resulting in logic state "1". When the pulse ends, the gating layer material returns to a crystalline state, the circuit is off, and the phase-change layer material remains crystalline, maintaining logic state "1". When an erase pulse is applied, the gating layer material melts, the circuit is turned on, and the pulse is further applied to the phase-change layer, causing it to change from crystalline to amorphous, resulting in logic state "0".

[0028] The present invention will be further illustrated below with specific embodiments.

[0029] Example 1 This embodiment is a 1S1R phase change memory device based on Sc-Te binary alloy.

[0030] The structure of the device is as follows Figure 1 As shown, the specific device structure and fabrication method are as follows: (1) On a Si substrate with a SiO2 insulating layer, titanium nitride (TiN) with a diameter of 80 nm is formed by magnetron sputtering as the bottom electrode 1.

[0031] (2) On the bottom electrode 1, a Sc layer with a thickness of 40 nm is deposited by magnetron co-sputtering of a Sc target and a Te target. 15 Te 85 Alloy thin film, as a non-volatile phase change layer 2.

[0032] (3) Without breaking the vacuum, continue to sputter a carbon (C) thin film with a thickness of 5 nm on the phase change layer 2 as a buffer layer 3.

[0033] (4) Continue to deposit a Sc2Te layer with a thickness of 40 nm on the buffer layer 3 by adjusting the sputtering power ratio. 98 Alloy film, as volatile gate layer 4.

[0034] (5) Finally, a 100nm thick tungsten (W) layer is deposited on the gated layer 4 through photolithography, lift-off and other processes to form the top electrode 5.

[0035] The device exhibits reliable 1S1R storage cell functionality, enabling stable data writing and erasure.

[0036] Example 2 This embodiment is another 1S1R phase change memory device based on Sc-Te binary alloy.

[0037] The structure of the device is similar to that of Embodiment 1, except that the thickness and composition of each functional layer are different.

[0038] (1) The material selection for each layer of the device is the same as in Example 1.

[0039] (2) The material of the non-volatile phase change layer 2 is Sc 40 Te 60 The thickness is 50nm.

[0040] (3) The thickness of the carbon buffer layer 4 is 3 nm.

[0041] (4) The material of the volatile gate layer 4 is Sc5Te 95 The thickness is 20nm.

[0042] The device also exhibits reliable 1S1R memory cell functionality, and its operating voltage and power consumption differ from those of Embodiment 1 due to the adjustment of the phase change layer and gating layer thickness, demonstrating the adjustability of the technical solution of the present invention.

Claims

1. A phase change memory device based on a scandium-tellurium binary alloy, characterized in that, The structure, from bottom to top, consists of a bottom electrode, a phase change layer, a buffer layer, a gated layer, and a top electrode. Among them, the gate layer and the phase change layer are both composed of scandium-tellurium Sc-Te binary alloy. The chemical formula of the gate layer material is Sc x Te 100-x , where 0 < x ≤ 8, and x is the atomic percentage of the element; the chemical formula of the phase change layer material is Sc y Te 100-y , where 8 < y ≤ 40, and y is the atomic percentage of the element.

2. The phase change memory device based on a scandium-tellurium binary alloy according to claim 1, characterized in that, The gating layer exhibits volatile threshold switching characteristics; Sc x Te 100-x The material is crystalline at room temperature, which is a high-resistivity state, and the device circuit is off. When an electrical pulse is applied, it becomes molten, which is a low-resistivity state, enabling the circuit to conduct. The applied pulse voltage range is 0.5-5V, and the pulse width is 10-1000ns. After the pulse stops, Sc x Te 100-x The material recrystallizes, which is in a high-resistivity state, and the circuit is in the off state.

3. The phase change memory device based on a scandium-tellurium binary alloy according to claim 1, characterized in that, The phase change layer exhibits non-volatile phase change memory (PCM) characteristics; Sc y Te 100-y The material exhibits a resistance difference of more than three orders of magnitude between its crystalline and amorphous states, enabling reliable data storage. Sc y Te 100-y The material is amorphous at room temperature, which is a high-resistivity state, representing the logic state "0"; after applying an electrical pulse, Sc y Te 100-y The material undergoes a phase transition to a crystalline state, which is a low-resistance state, equivalent to logic state "1". It retains its crystalline state even after the pulse stops; when the electrical pulse is applied again, Sc... y Te 100-y The material undergoes a phase transition to an amorphous state, which is a high-resistivity state and serves as the logic state "0". It can remain in the amorphous state even after the pulse stops.

4. The phase change memory device based on a scandium-tellurium binary alloy according to claim 1, characterized in that, The phase change memory device based on scandium-tellurium binary alloy controls the opening and closing of the circuit through a gating layer, and controls the storage and erasure of data through a phase change layer. In the initial state of the device, the gating layer is crystalline, the circuit is off, and the phase change layer is amorphous, which is logic state "0". When a write pulse is applied, the gating layer material is molten, the circuit is turned on, and the electrical pulse is further applied to the phase change layer, causing it to change from amorphous to crystalline, becoming logic state "1". When the pulse ends, the gate layer material returns to a crystalline state, the circuit is turned off, and the phase change layer material remains crystalline, maintaining the logic state "1". When an erase pulse is applied, the gate layer material is in a molten state, the circuit is turned on, and the electrical pulse is further applied to the phase change layer, causing it to change from a crystalline state to an amorphous state, becoming the logic state "0".

5. A phase change memory device based on a scandium-tellurium binary alloy according to claim 1, characterized in that, The thickness of the gate layer is 10-50 nm, and the thickness of the phase change layer is 10-50 nm. A buffer layer is disposed between the phase change layer and the gated layer, and its material is carbon with a thickness of 2-10 nm. The materials of the bottom electrode and the top electrode are one or a combination of W, TiN, and Pt.

6. A phase change memory device based on a scandium-tellurium binary alloy according to claim 1, characterized in that, The phase change layer is prepared by one of the following methods: magnetron sputtering, vacuum evaporation, atomic layer deposition, or chemical vapor deposition.

7. A phase change memory device based on a scandium-tellurium binary alloy according to claim 1, characterized in that, The device is used to construct high-density cross-point memory arrays, storage-class memory, and embedded non-volatile memory chips.

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