Semiconductor device with core bias electrode surrounded by vertical semiconductor channel

Abstract

A semiconductor device includes: an alternating stack of insulating layers and conductive layers; a memory opening extending vertically through the alternating stack; a memory opening filling structure, the memory opening fill structure is in the memory opening and includes a memory film, a vertical semiconductor channel laterally surrounded by the memory film, a drain region contacting a first end portion of the vertical semiconductor channel, a dielectric core surrounded by the vertical semiconductor channel, and a core bias electrode surrounded by the dielectric core. A source layer contacts a second end portion of the vertical semiconductor channel and an end portion of the core bias electrode.

Description

Cross-reference to related applications

[0001] This application claims the benefit and priority of U.S. Nonprovisional Patent Application Serial No. 18 / 660,791, filed May 10, 2024. Technical Field

[0002] This disclosure relates in general to the field of semiconductor devices, and more particularly to a three-dimensional semiconductor device including a core bias electrode surrounded by a vertical semiconductor channel and a method for manufacturing the same. Background Technology

[0003] A three-dimensional vertical NAND string with one bit per cell was disclosed in an article by T. Endoh et al. entitled “Novel Ultra High Density Memory With AStacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proceedings (2001), pp. 33-36. Summary of the Invention

[0004] According to one aspect of this disclosure, a semiconductor device includes: an alternating stack of insulating and conductive layers; a memory opening extending vertically through the alternating stack; a memory opening filling structure located in the memory opening and including a memory film, a vertical semiconductor channel laterally surrounded by the memory film, a drain region contacting a first end portion of the vertical semiconductor channel, a dielectric core surrounded by the vertical semiconductor channel, and a core bias electrode surrounded by the dielectric core; and a source layer contacting a second end portion of the vertical semiconductor channel and an end portion of the core bias electrode.

[0005] According to another aspect of this disclosure, a method of forming a device structure includes: forming an alternating stack of insulating layers and spacer material layers, wherein the spacer material layers are formed as conductive layers or subsequently replaced by conductive layers; forming a memory opening through the alternating stack; forming a memory opening filling structure in the memory opening, wherein the memory opening filling structure includes a memory film, a vertical semiconductor channel laterally surrounded by the memory film, a drain region contacting a first end portion of the vertical semiconductor channel, a dielectric core surrounded by the vertical semiconductor channel, and a core bias electrode surrounded by the dielectric core; and forming a source layer on a second end portion of the vertical semiconductor channel and on an end portion of the core bias electrode. Attached Figure Description

[0006] Figure 1This is a schematic vertical cross-sectional view of a first exemplary structure for forming a first semiconductor die after alternating stacking of a barrier insulating layer, a source electrode material layer, and an insulating layer and a sacrificial material layer over a carrier substrate, according to an embodiment of the present disclosure.

[0007] Figure 2 This is a schematic vertical cross-sectional view of a first exemplary structure after the formation of a stepped surface and a stepped dielectric material portion, according to an embodiment of the present disclosure.

[0008] Figure 3A This is a schematic vertical cross-sectional view of a first exemplary structure after the formation of the memory opening and the support opening, according to an embodiment of the present disclosure.

[0009] Figure 3B yes Figure 3A The top view of the first exemplary structure. Vertical plane A-A' is... Figure 3A The cutting plane of the vertical cross-section.

[0010] Figure 4 This is a schematic vertical cross-sectional view of a first exemplary structure after the formation of the support column structure, according to an embodiment of this disclosure.

[0011] Figures 5A to 5G It is a vertical cross-sectional view of the memory opening sequence during the formation of the memory opening filling structure according to an embodiment of the present disclosure.

[0012] Figure 6A This is a vertical cross-sectional view of a first exemplary structure after the formation of the memory opening filling structure according to an embodiment of the present disclosure.

[0013] Figure 6B yes Figure 6A The top view of the first exemplary structure. Vertical plane A-A' is... Figure 6A The cutting plane of the vertical cross-section.

[0014] Figure 7A This is a vertical cross-sectional view of a first exemplary structure after the formation of the isolation trench, according to an embodiment of the present disclosure.

[0015] Figure 7B yes Figure 7A The top view of the first exemplary structure. Vertical plane A-A' is... Figure 7A The cutting plane of the vertical cross-section.

[0016] Figure 8 This is a vertical cross-sectional view of a first exemplary structure after the formation of the source-stage cavity, according to an embodiment of the present disclosure.

[0017] Figures 9A to 9EThis is a sequential vertical cross-sectional view of a region of a first exemplary structure during the formation of a source contact layer according to an embodiment of the present disclosure.

[0018] Figure 10 This is a vertical cross-sectional view of a first exemplary structure after the formation of the source contact layer according to an embodiment of the present disclosure.

[0019] Figure 11 This is a vertical cross-sectional view of a first exemplary structure after the formation of a laterally extending cavity, according to an embodiment of the present disclosure.

[0020] Figures 12A to 12D This is a sequential vertical cross-sectional view of the regions of a first exemplary structure during the formation of a back-side barrier dielectric layer and a conductive layer in each laterally extending cavity, according to an embodiment of the present disclosure.

[0021] Figure 13A This is a vertical cross-sectional view of a first exemplary structure after the formation of a conductive layer, according to an embodiment of the present disclosure.

[0022] Figure 13B This is a vertical cross-sectional view of the region of the first exemplary structure that fills the memory opening.

[0023] Figure 14A This is a vertical cross-sectional view of a first exemplary structure after the formation of the transverse isolation trench filling structure and the contact via structure, according to an embodiment of the present disclosure.

[0024] Figure 14B yes Figure 14A The top view of the first exemplary structure. Vertical plane A-A' is... Figure 14A The cutting plane of the vertical cross-section.

[0025] Figure 15A This is a vertical cross-sectional view of a first exemplary structure after the formation of bit lines and bit line-level metal lines, according to an embodiment of this disclosure.

[0026] Figure 15B yes Figure 15A The top view of the first exemplary structure. Vertical plane A-A' is... Figure 15A The cutting plane of the vertical cross-section.

[0027] Figure 16 This is a vertical cross-sectional view of a first exemplary structure after the formation of a first semiconductor die, according to an embodiment of the present disclosure.

[0028] Figure 17 It is a vertical cross-sectional view of the logic die according to the implementation scheme of this disclosure.

[0029] Figure 18This is a vertical cross-sectional view of a first exemplary structure after the bonding assembly of the first semiconductor die and logic die is formed, according to an embodiment of the present disclosure.

[0030] Figure 19 This is a vertical cross-sectional view of a first exemplary structure after the carrier substrate has been removed from the first semiconductor die, according to an embodiment of the present disclosure.

[0031] Figure 20 This is a vertical cross-sectional view of a first exemplary structure after the formation of an additional back-side dielectric layer and a back-side connection pad cavity, according to an embodiment of the present disclosure.

[0032] Figure 21 This is a vertical cross-sectional view of a first exemplary structure after the back-side connection pads have been formed, according to an embodiment of the present disclosure.

[0033] Figure 22 This is a vertical cross-sectional view of a first exemplary structure after the formation of a passivation dielectric layer and a back-side contact pad, according to an embodiment of the present disclosure.

[0034] Figure 23 This is a schematic vertical cross-sectional view of a second exemplary structure for forming a first semiconductor die after forming a barrier insulating layer, a sacrificial semiconductor layer, a sacrificial insulating layer, a source semiconductor material layer, and an alternating stack of insulating and sacrificial material layers over a carrier substrate, according to an embodiment of the present disclosure.

[0035] Figure 24A This is a schematic vertical cross-sectional view of a second exemplary structure after the formation of the stepped surface, the stepped dielectric material portion, the memory opening, and the support opening, according to an embodiment of the present disclosure. Figure 24B yes Figure 24A The top view of the second exemplary structure. Vertical plane A-A' is... Figure 24A The cutting plane of the vertical cross-section.

[0036] Figure 25A This is a vertical cross-sectional view of a second exemplary structure after the formation of the support column structure and the memory opening filling structure, according to an embodiment of the present disclosure. Figure 25B yes Figure 25A The top view of the second exemplary structure. Vertical plane A-A' is... Figure 25A The cutting plane of the vertical cross-section. Figure 25C yes Figure 25A and Figure 25B A vertical cross-sectional view of the region surrounding the memory opening filling structure of the second exemplary structure.

[0037] Figure 26A This is a vertical cross-sectional view of a second exemplary structure after the formation of the isolation trench, according to an embodiment of the present disclosure. Figure 26B yes Figure 26A The top view of the second exemplary structure. Vertical plane A-A' is... Figure 26A The cutting plane of the vertical cross-section.

[0038] Figure 27 This is a vertical cross-sectional view of a second exemplary structure after the formation of the laterally extending cavity, according to an embodiment of the present disclosure.

[0039] Figure 28 This is a vertical cross-sectional view of a second exemplary structure after the formation of the conductive layer, according to an embodiment of the present disclosure.

[0040] Figure 29 This is a vertical cross-sectional view of a second exemplary structure after the formation of the transverse isolation trench filling structure and the contact via structure, according to an embodiment of the present disclosure.

[0041] Figure 30 This is a vertical cross-sectional view of a second exemplary structure after the formation of a first semiconductor die, according to an embodiment of the present disclosure.

[0042] Figure 31 This is a vertical cross-sectional view of a second exemplary structure after the bonding assembly of the first semiconductor die and logic die has been formed, according to an embodiment of the present disclosure.

[0043] Figure 32 This is a vertical cross-sectional view of a second exemplary structure after the removal of the carrier substrate and the sacrificial semiconductor layer, according to an embodiment of the present disclosure.

[0044] Figures 33A to 33F It is a sequential vertical cross-sectional view of the region surrounding the memory opening filling structure during the formation of the source layer, according to an embodiment of the present disclosure.

[0045] Figure 34 This is a vertical cross-sectional view of a second exemplary structure after the formation of the source layer, according to an embodiment of the present disclosure.

[0046] Figure 35 This is a vertical cross-sectional view of a second exemplary structure following the formation of an additional backside dielectric layer, backside connection pads, passivation dielectric layer, and backside contact pads, according to an embodiment of this disclosure. Detailed Implementation

[0047] As discussed above, embodiments of this disclosure relate to a three-dimensional semiconductor device including a core bias electrode surrounded by vertical semiconductor channels and a method for manufacturing the same, various aspects of which are described below. Embodiments of this disclosure can be used to form various structures including multi-level memory structures, non-limiting examples of which include semiconductor devices such as three-dimensional memory devices including multiple memory strings and / or three-dimensional semiconductor devices for vector-matrix multiplication (“VMM”) applications (i.e., VMM processors).

[0048] Specifically, memory devices can be used as in-memory computing architectures within VMM processors, where memory, logic, and processing operations are arranged side-by-side. In-memory processing devices are suitable for executing VMMs, which are critical operations for data processing and represent the most computationally intensive parts of machine learning (e.g., artificial intelligence) algorithms. Memory devices can be used to perform multiply-accumulate (MAC) operations to overcome communication bottlenecks between logic and memory devices. In-memory processing devices can be used to solve linear and differential equations, for signal and image processing, and as accelerators for artificial neural networks, as described by M. Marega et al. in “Large-Scale Integrated Vector-Matrix Multiplication Processor Based on Single-Layer Molybdenum Disulfide Memory” (Nat Electron 6, pp. 991–998 (2023)), which is incorporated herein by reference in its entirety.

[0049] The accompanying drawings are not to scale. Multiple instances of an element may be reproduced where only a single instance is illustrated, unless otherwise explicitly described or clearly indicated that a reproduction of the element does not exist. Ordinal numbers such as “first,” “second,” and “third” are used only to identify similar elements, and different ordinal numbers may be used in the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0050] Like reference numerals denote the same or similar elements. Unless otherwise specified, elements with the same reference numerals are considered to have the same composition and the same function. Unless otherwise specified, “contact” between elements means direct contact between elements providing an edge or surface shared by these elements. If two or more elements are not in direct contact with each other or are not in direct contact with each other, the two elements are “separated” from each other or “separated” from each other. As used herein, an element located “on” a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of an element and the surface of a second element, the element is “directly” located “on” the second element. As used herein, if there is a conductive path consisting of at least one conductive material between an element and a second element, the element is “electrically connected” to the second element. As used herein, a “prototype” structure or a “process” structure refers to a transient structure whose shape or composition is subsequently modified.

[0051] As used herein, a “layer” refers to a portion of material comprising a region of thickness. A layer may extend over the entire underlying or overlying structure, or its extent may be less than that of the underlying or overlying structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between or at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, or may have one or more layers on, above, and / or below it.

[0052] Typically, a semiconductor die or semiconductor package can include a memory chip. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit capable of independently executing commands or reporting status. Each die contains one or more planes (typically one or two). Despite some limitations, the same concurrent operations can be performed on each plane. Each plane contains multiple blocks, which are the smallest units that can be erased in a single erase operation. Each block contains multiple pages, which are the smallest programmable units, i.e., the smallest units on which read operations can be performed.

[0053] As used in this article, "semiconductor material" refers to a material with an electrical conductivity of 1.0 × 10⁻⁶. -5 S / m to 1.0×10 5 Materials in the S / m range. As used herein, "semiconductor material" refers to a material in which the electrical conductivity is in the absence of electrical dopants and is 1.0 × 10⁻⁶. -5Materials with electrical conductivity ranging from S / m to 1.0 S / m, and which, after appropriate doping with an electrical dopant, can produce conductivity ranging from 1.0 S / m to 1.0 × 10⁻⁶. 7 Doped materials in the S / m range. As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, “conductive material” refers to a material with a conductivity greater than 1.0 × 10⁻⁶. 5 Materials with a conductivity of S / m. As used herein, "insulating material" or "dielectric material" refers to a material with a conductivity of less than 1.0 × 10⁻⁶ m. -5 Materials with a S / m ratio. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with an electrically conductive agent at a sufficiently high atomic concentration. Whether formed as a crystalline material or transformed into a crystalline material through an annealing process (e.g., from an initial amorphous state), this semiconductor material will become a conductive material, i.e., providing a conductivity greater than 1.0 × 10⁻⁶. 5 The conductivity is S / m. "Doped semiconductor material" can be a heavily doped semiconductor material, or it can be a semiconductor material comprising electrically dopants (i.e., p-type dopants and / or n-type dopants) at a concentration of 1.0 × 10⁻⁶. -5 S / m to 1.0×10 7 Conductivity in the S / m range. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrically conductive agent. Therefore, a semiconductor material can be semiconductor or conductive, and can be intrinsic or doped. A doped semiconductor material can be semiconductor or conductive, depending on the atomic concentration of the electrically conductive agent therein. As used herein, "metallic material" refers to a conductive material that includes at least one metallic element. All conductivity measurements were performed under standard conditions.

[0054] The subthreshold swing (“SS”) of a field-effect transistor (FET) is a parameter describing how quickly the transistor transitions between on (high current) and off (low current) states. Memory devices used in VMM applications should have a narrow cell current (“Icell”) range (e.g., with the smallest possible ΔIcell / Icell ratio). In prior art memory devices, relatively small ΔIcell / Icell ratios (e.g., <20%) are achievable at higher Icell values, which leads to undesirable high power consumption. The ΔIcell / Icell ratio of a memory cell is controlled by the threshold voltage (“Vt”) width and subthreshold swing of the memory cell. For the narrow cell current range of VMM applications, a larger SS is desirable.

[0055] Embodiments of this disclosure provide a three-dimensional semiconductor (e.g., memory) device comprising a core bias electrode surrounded by a vertical semiconductor channel. The core bias electrode may be connected to a source line and thus serve as a back gate to increase the SS (stable voltage across) of the memory cell without negatively impacting the threshold voltage width of the memory cell. Specifically, the core bias electrode back gate (e.g., a voltage divider ground plane) may be operable to reduce the controllability of the channel potential in the subthreshold state of the controllable gate (e.g., a word line), thereby increasing the SS.

[0056] refer to Figure 1 This illustrates a first exemplary structure according to an embodiment of the present disclosure. The first exemplary structure includes a carrier substrate 9, which may be a semiconductor substrate or a conductive substrate. For example, the carrier substrate 9 may include a commercially available silicon wafer. Alternatively, the carrier substrate 9 may include any material relative to the insulating layer 32 and any dielectric material portions subsequently formed that are then selectively removed.

[0057] An insulating material layer may be formed on the top surface of the carrier substrate 9. This insulating material layer may subsequently be used as a barrier layer for processes removing the carrier substrate 9, and is referred to herein as barrier insulating layer 106, or back-side pad dielectric layer. If a polishing process, such as chemical mechanical polishing, is subsequently used to remove the carrier substrate 9, barrier insulating layer 106 may be used as a polishing barrier layer. If an etching process, such as wet etching, is subsequently used to remove the carrier substrate 9, barrier insulating layer 106 may be used as an etching barrier layer. In one embodiment, barrier insulating layer 106 comprises a dielectric material, such as undoped silicate glass, doped silicate glass, or silicon nitride. The thickness of barrier insulating layer 106 may range from 100 nm to 1,000 nm (e.g., 200 nm to 600 nm), but smaller and larger thicknesses are also possible.

[0058] During the process, the source level material layer 110' may be formed over the barrier insulating layer 106. The source level material layer 110' may include various layers subsequently modified to form the source level material layer. During formation, the source level material layer includes a source contact layer serving as the common source region of a vertical field-effect transistor in a three-dimensional semiconductor device. In one embodiment, the source level material layer 110' may include, from bottom to top, a lower source level semiconductor layer 112, an optional lower sacrificial pad 103, a source level sacrificial layer 104, an optional upper sacrificial pad 105, and an upper source level semiconductor layer 116.

[0059] The lower source semiconductor layer 112 and the upper source semiconductor layer 116 may comprise doped semiconductor materials, such as doped polycrystalline silicon or doped amorphous silicon. The conductivity type of the lower source semiconductor layer 112 and the upper source semiconductor layer 116 may be opposite to the conductivity of the vertical semiconductor channel to be formed subsequently. For example, if the vertical semiconductor channel to be formed subsequently has a first conductivity type of doping, then the lower source semiconductor layer 112 and the upper source semiconductor layer 116 have a second conductivity type of doping opposite to the first conductivity type. The thickness of each of the lower source semiconductor layer 112 and the upper source semiconductor layer 116 may range from 10 nm to 300 nm, such as 20 nm to 150 nm, but smaller and larger thicknesses are also possible.

[0060] The source-level sacrificial layer 104 includes a sacrificial material that can be selectively removed relative to the lower sacrificial pad 103 (or relative to the lower source-level semiconductor layer 112) and the upper sacrificial pad 105 (or relative to the upper source-level semiconductor layer 116). In one embodiment, the source-level sacrificial layer 104 may comprise a semiconductor material such as undoped amorphous silicon or a silicon-germanium alloy with a germanium atomic concentration greater than 20%. The thickness of the source-level sacrificial layer 104 may range from 30 nm to 400 nm, such as 60 nm to 200 nm, but smaller and larger thicknesses may also be used. The lower sacrificial pad 103 (if present) and the upper sacrificial pad 105 (if present) comprise materials that can be used as etch-stopping materials during the removal of the source-level sacrificial layer 104. For example, the lower sacrificial pad 103 and the upper sacrificial pad 105 may comprise silicon oxide, silicon nitride, and / or dielectric metal oxide. In one embodiment, each of the lower sacrificial pad 103 and the upper sacrificial pad 105 may include a silicon oxide layer having a thickness in the range of 2 nm to 30 nm, but smaller and larger thicknesses may also be used.

[0061] Alternating stacks of a first material layer and a second material layer may be formed over the process source level material layer 110'. In an alternative embodiment, the process source level material layer 110' and the barrier insulating layer 106 may be omitted, and the alternating stacks are formed directly on the surface of the carrier substrate 9. In the alternating stacks, the first material layer may be an insulating layer 32, and the second material layer may be a spacer material layer. In one embodiment, the spacer material layer may include a sacrificial material layer 42. In this case, alternating stacks (32, 42) of the insulating layer 32 and the sacrificial material layer 42 may be formed over the process source level material layer 110'. The insulating layer 32 comprises an insulating material such as undoped silicate glass or doped silicate glass, and the sacrificial material layer 42 comprises a sacrificial material such as silicon nitride or a silicon-germanium alloy. In one embodiment, the insulating layer 32 (i.e., the first material layer) may comprise a silicon oxide layer, and the sacrificial material layer 42 (i.e., the second material layer) may comprise a silicon nitride layer. The alternating stacks (32, 42) may comprise multiple repetitions of a unit layer stack including the insulating layer 32 and the sacrificial material layer 42. The total number of repetitions of the unit layer stack within the alternating stacks (32, 42) can be, for example, in the range of 8 to 1,024, such as 32 to 256, but smaller and larger repetitions are also possible. Hereinafter, the topmost insulating layer of insulating layer 32 is referred to as the topmost insulating layer 32T. The bottommost insulating layer of insulating layer 32 is the insulating layer 32 closest to the carrier substrate 9, and this insulating layer is referred to herein as the bottommost insulating layer 32B.

[0062] Each insulating layer in the insulating layers 32, except for the topmost insulating layer 32, may have a thickness in the range of 20 nm to 100 nm, such as 30 nm to 60 nm, but smaller and larger thicknesses are also possible. Each sacrificial material layer in the sacrificial material layers 42 may have a thickness in the range of 20 nm to 100 nm, such as 30 nm to 60 nm, but smaller and larger thicknesses are also possible. In one embodiment, the topmost insulating layer 32 may have a thickness of approximately half that of the other insulating layers 32. A first exemplary structure includes: a memory array region 100, in which a three-dimensional array of memory elements will subsequently be formed; a contact region 300, in which layer contact via structures for contact word lines will subsequently be formed; and a peripheral region 400 (also referred to as a connection region), in which connection via structures for providing vertically extending electrical signal paths will subsequently be formed.

[0063] While an embodiment in which the spacer material layer is formed as a sacrificial material layer 42 has been described, an alternative embodiment in which the spacer material layer is formed as a conductive layer is explicitly contemplated herein. In this alternative embodiment, the processing step for replacing the sacrificial material layer 42 with the conductive layer is not necessary and can therefore be omitted.

[0064] refer to Figure 2 A stepped surface is formed in the contact area 300. As used herein, a “stepped surface” refers to a set of surfaces comprising at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface and to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume, and portions of the alternatingly stacked (32, 42) are removed from the stepped cavity by forming the stepped surface. A “stepped cavity” refers to a cavity having a stepped surface.

[0065] The stepped cavity can have various stepped surfaces, such that the horizontal cross-sectional shape of the stepped cavity changes stepwise according to the vertical distance from the top surface of the source stage material layer 110' during the process. In one embodiment, the stepped cavity can be formed by repeatedly performing a set of processing steps. This set of processing steps may include, for example, a first type of etching process and a second type of etching process, the first type of etching process vertically increasing the depth of the cavity by one or more stages, and the second type of etching process laterally extending the area vertically etched in a subsequent first type of etching process. As used herein, a “stage” comprising alternating multiple structures is defined as the relative position of a pair of first and second material layers within the structure.

[0066] Each sacrificial material layer 42 within the alternating stacks (32, 42), except for the topmost sacrificial material layer 42, extends laterally further than any overlying sacrificial material layer 42 within the alternating stacks (32, 42) in the mezzanine region. The stepped surface of the alternating stacks (32, 42) extends continuously from the bottommost layer (such as the bottommost insulating layer 32B) within the alternating stacks (32, 42) to the topmost layer (such as the topmost insulating layer 32T) within the alternating stacks (32, 42).

[0067] A stepped dielectric portion 65 (i.e., an insulating filler portion) can be formed in a stepped cavity by depositing dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed, for example, from the top surface of the topmost insulating layer 32T by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the stepped dielectric portion 65, which can be an inverse stepped dielectric portion. As used herein, an "inverse stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases with the vertical distance from the top surface of the substrate on which the element is situated. If the stepped dielectric portion 65 is made of silicon oxide, the silicon oxide of the stepped dielectric portion 65 may or may not be doped with dopants such as B, P, and / or F. The stepped dielectric material portion 65 may include a first region and a second region, the first region being located in the contact region 300 and covering and contacting the stepped surfaces of the alternating stacks (32, 42) and having a variable thickness with a stepped variation, the second region being located within the peripheral region 400 and having an overall uniform thickness.

[0068] Optionally, the drain selection level isolation structure (not shown) may be formed through a subset of the topmost insulating layer 32T and the sacrificial material layer 42 located at the drain selection level. For example, the drain selection level isolation structure may be formed by forming a drain selection level lateral isolation trench and filling the drain selection level lateral isolation trench with a dielectric material such as silicon oxide. Excess dielectric material may be removed from above the top surface of the topmost insulating layer 32T.

[0069] refer to Figure 3A Referring to Figure 3C, an etch mask layer (not shown) may be formed over the alternating stack (32, 42), and this etch mask layer may be photolithographically patterned to form various openings therein. An anisotropic etching process may be performed to transfer the pattern of the openings in the etch mask layer through the alternating stack (32, 42). Various openings may be formed through the alternating stack (32, 42). The various openings may include memory openings 49 formed in the memory array region 100 and support openings 19 formed in the contact region 300. Each of the memory openings 49 and support openings 19 may extend vertically through the alternating stack (32, 42) and into the in-process source level material layer 110'. In one embodiment, the bottom surfaces of the memory openings 49 and support openings 19 may be formed within the lower source level semiconductor layer 112 or at the interface between the lower source level semiconductor layer and the barrier insulating layer 106.

[0070] The support opening 19 may have a diameter in the range of 60 nm to 400 nm (e.g., 120 nm to 300 nm), but may employ smaller and larger thicknesses. The memory opening 49 may have a diameter in the range of 60 nm to 400 nm (e.g., 120 nm to 300 nm), but may employ smaller and larger thicknesses.

[0071] In one embodiment, the memory array region 100 may be laterally spaced from the contact region 300 along a first horizontal direction hd1. Memory openings 49 may include rows of memory openings 49 arranged along the first horizontal direction hd1 and laterally spaced along a second horizontal direction hd2 perpendicular to the first horizontal direction hd2. Multiple clusters of memory openings 49 may be formed in the memory array region 100, each cluster comprising a corresponding two-dimensional periodic array of memory openings 49. The clusters of memory openings 49 may be laterally spaced along the second horizontal direction hd2.

[0072] refer to Figure 4 Optional etch-stop pads (not shown) and sacrificial filler material may be deposited in memory opening 49 and support opening. Optional etch-stop pads (if present) comprise a thin dielectric layer comprising silicon oxide, silicon nitride, or dielectric metal oxide and having a thickness in the range of 1 nm to 6 nm. Sacrificial filler material may comprise carbon-based materials (such as amorphous carbon or diamond-like carbon), semiconductor materials (such as amorphous silicon or polycrystalline silicon), dielectric filler materials (such as borosilicate glass or organosilicon glass), or polymeric materials. Excess sacrificial filler material may be removed from above a horizontal plane comprising the alternating stack (32, 42) by a planarization process (such as an etch-back process). The remaining portion of the sacrificial filler material filling memory opening 49 constitutes sacrificial memory opening filling structure 47. The remaining portion of the sacrificial filler material filling support opening 19 constitutes a sacrificial support opening filling structure (not shown).

[0073] A photoresist layer (not shown) may be applied over the alternating stacks (32, 42) and the stepped dielectric portion 65, and may be photolithographically patterned to cover the memory array region 100 but not the contact region 300. Portions of the sacrificial support opening-fill structure and optional etch-stop pads in the contact region 300 may be selectively removed relative to the materials of the stepped dielectric portion 65 and the alternating stacks (32, 42). For example, etching or ashing processes may be used to remove the sacrificial support opening-fill structure and optional etch-stop pads in the contact region 300. The photoresist layer may then be removed.

[0074] Dielectric filler material (such as silicon oxide) can be deposited in the support opening 19 using a conformal deposition process. Excess portions of the dielectric filler material can be removed, for example, from the top surface of the topmost insulating layer 32T using a recess etching process. Each portion of the dielectric filler material filling the corresponding support opening 19 constitutes a support pillar structure 20, which can be used to provide structural support to the insulating layer 32 and the stepped dielectric material portion 65 during the replacement of the sacrificial material layer 42 with a conductive layer.

[0075] Figures 5A to 5G It is a sequential vertical cross-sectional view of the memory opening 49 during the formation of the memory opening filling structure 58 (e.g., a NAND string for a VMM or a data storage NAND string) according to an embodiment of the present disclosure.

[0076] refer to Figure 5A The portions of the sacrificial memory opening fill structure 47 and the optional etch-stop pads in the memory array region 100 can be selectively removed relative to the stepped dielectric material portions 65 and the alternating stacks (32, 42). For example, etching or ashing processes can be used to remove the portions of the sacrificial memory opening fill structure 47 and the optional etch-stop pads in the memory array region 100. A void is formed in the volume of the memory opening 49.

[0077] refer to Figure 5B A layer stack including a memory material layer 54 can be conformally deposited. In an exemplary example, the layer stack may include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric pad 56. Typically, the memory material layer 54 may include any type of memory material, i.e., a material in which data bits can be stored. For example, the memory material layer 54 may include charge storage materials (such as continuous silicon nitride layers, discrete silicon nitride layer charge storage regions, or discrete conductive floating gates), ferroelectric materials, phase change materials, etc. When the memory material layer 54 includes a charge storage material, the optional dielectric pad 56 may include a tunneling dielectric layer.

[0078] The semiconductor channel material layer 60L can be deposited on top of the layer stack (52, 54, 56) by performing a conformal deposition process. If the semiconductor channel material layer 60L is doped, it can have a first conductivity type of doping, which can be p-type or n-type. In one embodiment, the first semiconductor material comprises a first doped silicon material having a first conductivity type of doping. In an exemplary example, the atomic concentration of the first conductivity type of dopant in the semiconductor channel material layer 60L can be 1.0 × 10⁻⁶. 13 / cm 3 Up to 3.0×10 17 / cm 3Within the range, such as 1.0 × 10 14 / cm 3 Up to 3.0×10 16 / cm 3 However, smaller and larger atomic concentrations can also be used.

[0079] A core dielectric liner layer 621L is conformally deposited over a semiconductor channel material layer 60L. The core dielectric liner layer 621L comprises a dielectric material, such as silicon oxide, aluminum oxide, or a dielectric metal oxide (e.g., hafnium oxide), and its thickness is sufficient to provide electrical isolation between the semiconductor channel material layer 60L and the electrode (referred to as the core bias electrode) subsequently formed within the cavity surrounded by the core dielectric liner layer 621L. The core dielectric liner layer 621L can be deposited using a conformal deposition process such as low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition, and can have a thickness ranging from 2 nm to 15 nm, such as 3 nm to 10 nm, but smaller and larger thicknesses are also possible.

[0080] refer to Figure 5C The conductive core material layer 66L can be conformally deposited within a remaining cavity laterally defined by the inner sidewalls of the core dielectric pad layer 621L. The conductive core material layer 66L comprises a conductive material, which may include a heavily doped semiconductor material or at least one metallic material. For example, the conductive core material layer 66L may include a heavily doped semiconductor material (such as heavily doped polycrystalline silicon or amorphous silicon) having a second conductivity type, which is the conductivity type of the lower source semiconductor layer 112 and the upper source semiconductor layer 116. Alternatively or otherwise, the conductive core material layer 66L may include at least one metallic material. For example, the conductive core material layer 66L may include conductive metal nitrides, such as titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride, and / or metals such as tungsten, molybdenum, ruthenium, cobalt, etc. In one embodiment, the conductive core material layer 66L may consist substantially of a heavily doped semiconductor material, such as having a 1×10⁻⁶ doped core material. 19 / cm 3 Up to 2×10 21 / cm 3 Such as 2×10 20 / cm 3 Up to 8×10 20 / cm 3 Heavily doped polycrystalline silicon or heavily doped amorphous silicon with an n-type (e.g., phosphorus and / or arsenic) doping concentration (which is subsequently converted to heavily doped polycrystalline silicon after an annealing process). The conductive core material layer 66L at least fills the upper portion of the volume defined by the inner cylindrical sidewalls of the core dielectric liner layer 621L, and may fill the entire volume.

[0081] refer to Figure 5DA recessed etching process can be performed to etch the portion of the conductive core material layer 66L that covers the horizontal plane above the top surface of the dielectric core pad layer 621L, and to etch additional portions of the conductive core material layer 66L located within the upper portion of the volume laterally defined by the inner cylindrical sidewalls of the core dielectric pad layer 621L. The remaining portion of the dielectric core pad layer 621L fills the lower portion of the volume laterally defined by the inner cylindrical sidewalls of the core dielectric pad layer 621L, and this remaining portion of the dielectric core pad layer constitutes the core bias electrode 66.

[0082] The top surface of the core bias electrode 66 is formed beneath at least one sacrificial material layer 42 of alternating stacks and over the remainder of the sacrificial material layers 42 in the alternating stacks (32, 42). In one embodiment, the total number of sacrificial material layers 42 covering the horizontal plane including the top surface of the core bias electrode 66 may range from 1 to 12, such as 1 to 4, but a larger number may also be used. In one embodiment, at least 95%, such as at least 98% and / or at least 99%, of all sacrificial material layers 42 may be located below the horizontal plane including the top surface of the core bias electrode 66. In one embodiment, a first subset (which is the major subset) of all sacrificial material layers 42 within the alternating stacks (32, 42) may be subsequently replaced with a first subset of conductive layers used as word lines (i.e., used as control gates), and a second subset of all sacrificial material layers 42 covering the first subset may be subsequently replaced with a second subset of conductive layers used as drain select electrode lines (e.g., used as drain-side select gates). In this configuration, the top surface of the core bias electrode 66 may be formed above the topmost surface of the first subset and below the bottommost surface of the second subset.

[0083] In summary, the core bias electrode 66 extends vertically through multiple spacer material layers (which may be sacrificial material layer 42) within an alternating stack (32, 42). The core bias electrode 66 is electrically isolated from the semiconductor channel material layer 60L via a core dielectric pad layer 621L. In one embodiment, the core bias electrode 66 is composed of at least one conductive material having a cylindrical shape, which may be, for example, a doped semiconductor material portion having a cylindrical shape.

[0084] refer to Figure 5E A dielectric core material layer 622L, including dielectric filling material, may be deposited in the unfilled volume of the memory opening 49 and over a horizontal extension of the core dielectric pad layer 621L. The dielectric core material layer 622L may comprise undoped silicate glass (i.e., silicon oxide) or doped silicate glass. The dielectric core material layer 622L may comprise the same material as the core dielectric pad layer 621L, or may comprise a different material.

[0085] refer to Figure 5F The dielectric core material layer 622L can be vertically recessed by performing a recess etching process. In one embodiment, the recess etching process can selectively etch the materials of the dielectric core material layer 622L and the core dielectric pad layer 621L relative to the material of the semiconductor channel material layer 60L. The recess etching process may include a reactive ion etching process or a timed wet etching process. The duration of the recess etching process can be selected such that the top surface of each remaining portion of the dielectric core material layer 622L is above a horizontal plane including the bottom surface of the topmost insulating layer 32T and below a horizontal plane including the topmost insulating layer 32T. Each remaining portion of the dielectric core material layer 622L in the corresponding memory opening 49 constitutes a cylindrical dielectric core portion 622. Each remaining portion of the core dielectric pad layer 621L retained in the corresponding memory opening 49 constitutes a core dielectric pad 621. Each successive combination of the core dielectric pad 621 and the cylindrical dielectric core portion 622 constitutes a dielectric core 62.

[0086] The core bias electrode 66 is encapsulated by a dielectric core 62. Specifically, the core bias electrode 66 is encapsulated on the sides by a core dielectric pad 621 and on the top by a cylindrical dielectric core portion 622. Each surface of the core bias electrode 66 is in direct contact only with the corresponding surface of the combination of the core dielectric pad 621 and the cylindrical dielectric core portion 622 of the dielectric core 62. In one embodiment, a first end face of the core bias electrode 66 contacts a first end face of the cylindrical dielectric core portion 622, and the periphery of the first end face of the core bias electrode 66 coincides with the periphery of the first end face of the cylindrical dielectric core portion 622. Thus, the dielectric core 62 completely encapsulates the core bias electrode 66 such that each surface of the core bias electrode 66 contacts a corresponding inner surface of the dielectric core 62 and does not contact any other structural elements other than the dielectric core 62.

[0087] refer to Figure 5G A doped semiconductor material having a second conductivity type can be deposited in each recessed region above the dielectric core 62. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, then the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be 5 × 10⁻⁶. 18 / cm 3 Up to 2×10 21 / cm 3 Within a certain range, but smaller or larger dopant concentrations can also be used. The doped semiconductor material can be, for example, doped polysilicon.

[0088] Excess portions of the deposited semiconductor material doped with a second conductivity type and horizontal portions of the semiconductor channel material layer 60L can be removed, for example, from above a horizontal plane including the top surface of the top insulating layer 32T using a planarization process. The planarization process may include a chemical mechanical planarization (CMP) process or a recessed etching process. Each remaining portion of the doped semiconductor material with a second conductivity type constitutes a drain region 63. The drain region 63 is vertically separated from the core bias electrode 66 by a cylindrical dielectric core portion 622. Each remaining portion of the semiconductor channel material layer 60L (which has doping with a first conductivity type) constitutes a vertical semiconductor channel 60. During the planarization process, horizontal extensions of the stack of optional barrier dielectric layer 52, memory material layer 54, and optional dielectric pad 56 can be removed from above a horizontal plane including the top surface of the top insulating layer 32T.

[0089] Each portion of the layer stack, including the memory material layer 54 retained in the respective memory opening 49, constitutes a memory film 50. In one embodiment, the memory film 50 may include an optional barrier dielectric layer 52, the memory material layer 54, and an optional dielectric pad (e.g., a tunneling dielectric layer) 56. The memory film 50, combined with each adjacent vertical semiconductor channel 60, constitutes a memory stack structure 55.

[0090] Memory aperture fill structures 58 are formed within each memory aperture 49. Each memory aperture fill structure 58 includes a memory film 50, a vertical semiconductor channel 60 laterally surrounded by the memory film 50, a drain region 63 contacting a first end portion of the vertical semiconductor channel 60, a dielectric core 62 including a cylindrical dielectric core portion 622 and a core dielectric pad 621, and a core bias electrode 66 embedded within the core dielectric pad 621. Thus, each memory aperture fill structure 58 includes a corresponding vertical stack of memory elements (which may include a portion of the memory material layer 54 located at the level of the sacrificial material layer 42). The core bias electrode 66 extends vertically through multiple spacer material layers (such as the sacrificial material layer 42) within the alternating stacks (32, 42). The core bias electrode 66 is electrically isolated from the vertical semiconductor channel 60 via the core dielectric pad 621. The core bias electrode 66 is encapsulated by two parts: a core dielectric pad 621 of the dielectric core 62 and a cylindrical dielectric core portion 622, and each surface of the core bias electrode 66 is in direct contact only with the corresponding surface of the dielectric core 62.

[0091] In one embodiment, the core bias electrode 66 comprises a doped semiconductor material portion having a cylindrical shape. In one embodiment, a first end face of the core bias electrode 66 contacts a first end face of the cylindrical dielectric core portion 622; and the periphery of the first end face of the core bias electrode 66 coincides with the periphery of the first end face of the cylindrical dielectric core portion 622. In one embodiment, the cylindrical sidewall of the cylindrical dielectric core portion 622 contacts a first surface segment of the inner cylindrical sidewall of the core dielectric pad 621. In one embodiment, the cylindrical sidewall of the core bias electrode 66 contacts a second surface segment of the inner cylindrical sidewall of the core dielectric pad 621. In one embodiment, the core dielectric pad 621 extends vertically through each sacrificial material layer 42 within the alternating stack (32, 42). In one embodiment, a second end face of the cylindrical dielectric core portion 622 contacts a drain region 63. In one embodiment, a first annular end face (i.e., the top annular end face) of the core dielectric pad 621 contacts the drain region 63. As used herein, an annular surface refers to a surface having an inner perimeter and an outer perimeter offset outward from the inner perimeter. Unless otherwise explicitly stated, it is assumed that each annular surface in this disclosure may have a uniform lateral offset distance between the inner and outer perimeters.

[0092] refer to Figure 6A and Figure 6B This illustrates a first exemplary structure after a memory opening fill structure 58 is formed within a memory opening 49. Each memory opening fill structure in the memory opening fill structure 58 may include a memory film 50 and a vertical semiconductor channel 60. In summary, it may be a combination of alternating stacks (32, 42) of insulating layer 32 and sacrificial material layer 42, a memory opening 49 extending vertically through the alternating stacks (32, 42), and a memory opening fill structure 58 located within the memory opening 49. Each memory opening fill structure in the memory opening fill structure 58 includes a corresponding vertical stack of memory elements, such as a portion of a memory material layer 54 located at the level of the sacrificial material layer 42.

[0093] refer to Figure 7A and Figure 7B Dielectric materials such as undoped silicate glass or doped silicate glass can be deposited on alternating stacks (32, 42) to form a contact-level dielectric layer 80. The thickness of the contact-level dielectric layer 80 can be in the range of 100 nm to 600 nm, such as 200 nm to 400 nm, but smaller and larger thicknesses are also possible.

[0094] A photoresist layer (not shown) may be applied over the contact-level dielectric layer 80 and may be photolithographically patterned to form elongated openings extending laterally along a first horizontal direction hd1 between adjacent clusters of the memory aperture filling structure 58. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80, the alternating stacks (32, 42), the stepped dielectric material portions 65, and the in-process source-level material layer 110'. Lateral isolation trenches 79 extending laterally along the first horizontal direction hd1 may be formed through the alternating stacks (32, 42), the stepped dielectric material portions 65, the contact-level dielectric layer 80, and the in-process source-level material layer 110'. Each lateral isolation trench 79 may include a corresponding pair of longitudinal sidewalls parallel to the first horizontal direction hd1 and extending vertically from the barrier insulating layer 106 to the top surface of the contact-level dielectric layer 80. The top surface of the insulating layer 106 is prevented from being physically exposed beneath each lateral isolation trench 79. The lateral isolation trenches 79 isolate adjacent memory blocks from each other along the second horizontal direction hd2. The photoresist layer can then be removed, for example, by ashing.

[0095] Figure 8 This is a vertical cross-sectional view of a first exemplary structure after the formation of the source-stage cavity, according to an embodiment of the present disclosure. Figures 9A to 9E This is a sequential vertical cross-sectional view of a region of a first exemplary structure during the formation of a source contact layer according to an embodiment of the present disclosure.

[0096] refer to Figure 8 and Figure 9A An etchant can be introduced into the lateral isolation trench 79 by performing an isotropic etching process. This etchant selectively etches the material of the source sacrificial layer 104 relative to the alternating stacks (32, 42), contact-level dielectric layer 80, stepped dielectric material portion 65, lower source-level semiconductor layer 112, upper source-level semiconductor layer 116, upper sacrificial pad 105 (if present), and lower sacrificial pad 103 (if present). For example, if the source sacrificial layer 104 comprises undoped amorphous silicon or a silicon-germanium alloy, a wet etching process using thermal trimethyl-2-hydroxyethyl ammonium hydroxide (“thermal TMY”) or tetramethyl ammonium hydroxide (TMAH) can be used to selectively remove the source sacrificial layer 104 relative to the alternating stacks (32, 42), contact-level dielectric layer 80, stepped dielectric material portion 65, lower source-level semiconductor layer 112, and upper source-level semiconductor layer 116. The source cavity 109 is formed in the volume from which the source level sacrificial layer 104 is removed.

[0097] Wet etching chemicals such as thermal TMY and TMAH are selective relative to doped semiconductor materials such as p-doped and / or n-doped semiconductor materials of the upper source semiconductor layer 116 and the lower source semiconductor layer 112. Therefore, using selective wet etching chemicals (such as thermal TMY and TMAH) for the wet etching process forming the source cavity 109 provides a large process window to resist variations in etching depth during the formation of the lateral isolation trench 79. Specifically, even if the sidewalls of the upper source semiconductor layer 116 are physically exposed, or even if the surface of the lower source semiconductor layer 112 is physically exposed during the formation of the source cavity 109, the incidental etching of the upper source semiconductor layer 116 and / or the lower source semiconductor layer 112 is minimal, and structural changes to the first exemplary structure caused by unintended physical exposure of the surfaces of the upper source semiconductor layer 116 and / or the lower source semiconductor layer 112 during the manufacturing steps do not lead to device failure. Each memory aperture filling structure in memory aperture filling structure 58 is physically exposed to source cavity 109. Specifically, each memory aperture filling structure in memory aperture filling structure 58 includes a sidewall physically exposed to source cavity 109.

[0098] refer to Figure 9B A set of first isotropic etching processes can be performed to etch the portion of the memory film 50 exposed to the source cavity 109. For example, a series of isotropic etchants (such as wet etchants) can be applied to the physically exposed portion of the memory film 50 to sequentially etch various component layers of the memory film 50 from the outside in, and physically expose the cylindrical surface of the vertical semiconductor channel 60 at the layer level of the source cavity 109. The upper sacrificial pad 105 (if present) and the lower sacrificial pad 103 (if present) can be incidentally etched during the removal of the portion of the memory film 50 located at the layer level of the source cavity 109. The volume of the source cavity 109 can be increased by removing the portion of the memory film 50 at the layer level of the source cavity 109 and the upper and lower sacrificial pads (103, 105). The top surface of the lower source semiconductor layer 112 and the bottom surface of the upper source semiconductor layer 116 can be physically exposed to the source cavity 109. Typically, the source cavity 109 is formed by selectively and isotropically etching the bottom portion of each memory film in the source sacrificial layer 104 and memory film 50 relative to at least one source semiconductor layer (such as the lower source semiconductor layer 112 and the upper source semiconductor layer 116) and the vertical semiconductor channel 60.

[0099] refer to Figure 9CA second isotropic etching process can be performed to remove the tubular portions of the vertical semiconductor channel 60 exposed in the source cavity 109. In one embodiment, the second isotropic etching process may include a wet etching process using thermal trimethyl-2-hydroxyethyl ammonium hydroxide (“thermal TMY”) or tetramethylammonium hydroxide (TMAH). The duration of the second isotropic etching process can be selected such that the tubular portions of each vertical semiconductor channel 60 are etched through, and the cylindrical surfaces of each core dielectric pad 621 are physically exposed around the source cavity 109, while incidental etching of the surface portions of the lower source semiconductor layer 112 and the upper source semiconductor layer 116 is minimized.

[0100] refer to Figure 9D A third isotropic etching process can be performed to remove the tubular portion of the core dielectric pad 621 exposed to the source cavity 109. In one embodiment, the third isotropic etching process may include a wet etching process using diluted hydrofluoric acid (if the core dielectric pad 621 comprises silicon oxide), a wet etching process using phosphoric acid (if the core dielectric pad 621 comprises aluminum oxide), a wet etching process using a mixture of hydrofluoric acid and nitric acid (if the core dielectric pad 621 comprises hafnium oxide), etc. The cylindrical surface of each core bias electrode 66 may be physically exposed to the source cavity 109. (See reference...) Figures 9B to 9D During the described processing steps, a set of discrete material plates 150 may be formed beneath each tubular volume surrounding a core bias electrode 66, which is incorporated into the source cavity 109. In one embodiment, each set of discrete material plates 150 may include: a first plate having the same material composition and thickness as the barrier dielectric layer 52; a second plate having the same material composition and thickness as the memory material layer 54; a third plate having the same material composition and thickness as the dielectric pad 56; a fourth plate having the same material composition and thickness as the vertical semiconductor channel 60; and a fifth plate 156 having the same material composition and thickness as the core dielectric pad 621.

[0101] refer to Figure 9E and Figure 10 A semiconductor material doped with a second conductivity type may be deposited on a semiconductor surface physically exposed around the source cavity 109. The physically exposed semiconductor surface includes an annular bottom end face of each vertical semiconductor channel 60, a cylindrical surface segment of the sidewall of each core bias electrode 66, and a horizontal surface of at least one source semiconductor layer (such as the bottom surface of the upper source semiconductor layer 116 and / or the top surface of the lower source semiconductor layer 112).

[0102] In one embodiment, a doped semiconductor material of a second conductivity type can be deposited on a physically exposed semiconductor surface surrounding a source cavity 109 using a selective semiconductor deposition process. During the selective semiconductor deposition process, a semiconductor precursor gas, an etchant gas, and a dopant gas can be simultaneously introduced into a process chamber including the first exemplary structure. For example, the semiconductor precursor gas may include silane, dichlorosilane, or dichlorosilane, the etchant gas may include gaseous hydrogen chloride, and the dopant gas may include hydrides of dopant atoms, such as phosphine, arsine, antimony, or diborane. In this case, the selective semiconductor deposition process grows a doped semiconductor material of a second conductivity type from the physically exposed semiconductor surface surrounding the source cavity 109. The deposited doped semiconductor material forms a source contact layer 114 that can contact the sidewalls of the vertical semiconductor channel 60. The atomic concentration of the second conductivity type dopant in the deposited semiconductor material can be 1 × 10⁻⁶. 19 / cm 3 Up to 2×10 21 / cm 3 Within the range, such as 2×10 20 / cm 3 Up to 8×10 20 / cm 3 The initially formed source contact layer 114 may consist substantially of semiconductor atoms and dopant atoms of a second conductivity type. Alternatively, at least one non-selective doping semiconductor material deposition process may be used to form the source contact layer 114. Optionally, one or more etch-back processes may be combined with multiple selective or non-selective deposition processes to provide a seamless and / or void-free source contact layer 114.

[0103] The duration of the selective semiconductor deposition process can be selected such that the source cavity 109 is filled with the source contact layer 114. In one embodiment, the source contact layer 114 can be formed by selectively depositing a doped semiconductor material having a second conductivity type from the semiconductor surface surrounding the source cavity 109. In one embodiment, the doped semiconductor material may include doped polysilicon. Therefore, the source level sacrificial layer 104 can be replaced by the source contact layer 114. A stack of layers including a lower source level semiconductor layer 112, a source contact layer 114, and an upper source level semiconductor layer 116 constitutes a source layer 110, which replaces the source level material layer 110' in the process. The source layer 110 contacts the end portion of each vertical semiconductor channel 60.

[0104] In one embodiment, each core dielectric pad 621 includes an annular end face that contacts the source layer 110, and specifically, contacts the annular end of the source contact layer 114 within the source layer 110. In one embodiment, a cylindrical surface segment of a first end portion of the inner sidewall of the vertical semiconductor channel 60 may contact the drain region 63. In one embodiment, an annular surface segment of a second end portion of the vertical semiconductor channel 60 contacts the source layer 110. Thus, the source layer 110 contacts the second end portion of each vertical semiconductor channel 60 and the end portion of each core bias electrode 66.

[0105] In one embodiment, within each memory opening filling structure 58, a first annular end face of the core dielectric pad 621 contacts the drain region 63, and a second annular end face of the core dielectric pad 621 contacts the source layer 110. In one embodiment, a cylindrical surface segment of the core bias electrode 66 contacts the source layer 110. In one embodiment, an annular end face of the vertical semiconductor channel 60 contacts the source layer 110, and the entire outer cylindrical sidewall of the vertical semiconductor channel 60 contacts the core dielectric pad 621.

[0106] refer to Figure 11 An isotropic etching process can be performed to selectively remove the sacrificial material layer 42 relative to the insulating layer 32, the barrier insulating layer 106, the memory opening-fill structure 58, the sacrificial etch stop pad 71, and the source layer 110. A laterally extending cavity 43 can be formed in the volume in which the sacrificial material layer 42 is removed. Sidewall surface segments of the memory opening-fill structure 58 can be physically exposed to the laterally extending cavity 43. In an exemplary example, if the sacrificial material layer 42 comprises silicon nitride, the isotropic etching process may include a wet etching process employing hot phosphoric acid, which is a process in which a first exemplary structure is immersed in phosphoric acid at or near the boiling point of phosphoric acid. Suitable cleaning processes can be performed as needed. In summary, the laterally extending cavity 43 can be formed by selectively removing the sacrificial material layer 42 relative to the insulating layer 32 and the memory opening-fill structure 58.

[0107] Figures 12A to 12D This is a sequential vertical cross-sectional view of the regions of a first exemplary structure formed during the formation of a back-side barrier dielectric layer 44 and a conductive layer 46 in each of the laterally extending cavities 43 according to an embodiment of the present disclosure.

[0108] refer to Figure 12A Examples are shown in Figure 11 The region of the first exemplary structure following the processing steps. Each memory opening fills the cylindrical outer surface segment of structure 58 and the horizontally extending surface of insulating layer 32, which can be exposed to the laterally extending cavity 43.

[0109] refer to Figure 12B A back-side barrier dielectric layer 44 is deposited in a laterally extending cavity 43. The back-side barrier dielectric layer 44 comprises a dielectric metal oxide material and / or is substantially composed of a dielectric metal oxide material such as aluminum oxide. The back-side barrier dielectric layer 44 can be deposited using a conformal deposition process and can have a uniform thickness overall. In one embodiment, the back-side barrier dielectric layer 44 can be deposited using an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process. The back-side barrier dielectric layer 44 can have a thickness in the range of 1 nm to 10 nm (e.g., 2 nm to 5 nm), but smaller and larger thicknesses are also possible.

[0110] refer to Figure 12C A conductive diffusion barrier layer 46A may be conformally deposited on the physically exposed surface of the back-side barrier dielectric layer 44. The diffusion barrier layer 46A may include tungsten nitride, titanium nitride, molybdenum nitride, or tantalum nitride. The thickness of the diffusion barrier layer 46A may be in the range of 1 nm to 8 nm (such as 2 nm to 5 nm), but smaller and larger thicknesses are also possible.

[0111] refer to Figure 12D The metal layer 46B can be deposited in the remaining volume of the laterally extending cavity 43. In one embodiment, the metal may include tungsten, molybdenum, ruthenium, or cobalt. The metal layer 46B can be deposited by a conformal deposition process, such as chemical vapor deposition, and can fill the remaining volume of the laterally extending cavity 43.

[0112] An anisotropic etching process can be performed to remove portions of the metal layer 46B and diffusion barrier layer 46A, and optionally the back-side barrier dielectric layer 44, from within the volume of the lateral isolation trench 79 and above the contact-level dielectric layer 80. Each consecutive remaining portion of the combination of the metal layer 46B and diffusion barrier layer 46A within the volume of the respective laterally extending cavity 43 constitutes a conductive layer 46. This forms an alternating stack (32, 46) of insulating layer 32 and conductive layer 46. The alternating stack (32, 46) of insulating layer 32 and conductive layer 46 can be laterally spaced from each other along the second horizontal direction hd2 via the lateral isolation trench 79.

[0113] refer to Figure 13A and Figure 13B Examples are shown in Figure 12D The first exemplary structure following the processing steps. In one embodiment, the conductive layer 46 within each alternating stack (32, 46) includes word lines and drain selection electrode lines covering the word lines. A core bias electrode 66 embedded within a memory opening-filling structure 58 in the alternating stack (32, 46) may extend vertically through each word line in the alternating stack (32, 46).

[0114] refer to Figure 14A and Figure 14B The insulating filler material may be conformally deposited in the lateral isolation trench 79. Excess insulating filler material may be removed from above the contact-level dielectric layer 80, for example, by a recess etching process. The filling of each remaining portion of the corresponding lateral isolation trench 79 with insulating filler material constitutes an isolation trench fill structure 76. Alternatively, each isolation trench fill structure 76 may include a combination of a tubular insulating spacer (not explicitly shown) and a conductive connection via structure (not explicitly shown) laterally surrounded by the tubular insulating spacer. In general, the isolation trench fill structure 76 with insulating sidewalls extends vertically from the bottom surface of the alternating stack (32, 46) to the top surface of the alternating stack (32, 46).

[0115] A photoresist layer (not shown) may be applied over the contact-level dielectric layer 80 and may be photolithographically patterned to form openings over each memory aperture filling structure in the memory aperture filling structure 58, over the horizontally extending surface of the stepped surface in the contact region 300, and in the peripheral region 400. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80 and the stepped dielectric portion 65. Drain contact via cavities may be formed over the memory aperture filling structure 58 through the contact-level dielectric layer 80. Layer contact via structures may be formed through the contact-level dielectric layer 80 and the stepped dielectric portion 65 on the top surface of a corresponding conductive layer in the conductive layer 46. Connection pad cavities may be formed through the contact-level dielectric layer 80 and the stepped dielectric portion 65 to the top surface of the source layer 110. The photoresist layer may subsequently be removed, for example, by ashing.

[0116] At least one conductive material (such as a combination of a metal barrier material and a metal filler material) may be deposited in the drain contact via cavity, the layer contact via cavity, and the connection pad cavity. Excess portions of the at least one conductive material can be removed from above a horizontal plane including the top surface of the contact-level dielectric layer 80 by a planarization process, which may employ a recess etching process and / or a chemical mechanical polishing process. The remaining portion of the drain contact via cavity filled with at least one conductive material constitutes a drain contact via structure 88, which contacts the top surface of a corresponding drain region in drain region 63. The remaining portion of the layer contact via cavity filled with at least one conductive material constitutes a layer contact via structure 86, which contacts the top surface of a corresponding conductive layer in conductive layer 46. The remaining portion of the connection pad cavity filled with at least one conductive material constitutes a connection via structure 84, which contacts the top surface of the source layer 110. In one embodiment, the connection via structure 84 may be formed as an array of connection via structures 84.

[0117] Common Reference Figures 1 to 14BA combination of a three-dimensional memory array and a dielectric material portion (such as a stepped dielectric material portion 65) may be formed on a first side of the source layer 110 covering the carrier substrate 9. The three-dimensional memory array comprises a three-dimensional array of memory elements embedded in alternating stacks (32, 46) of insulating layers 32 and conductive layers 46 on the first side of the source layer 110, and the dielectric material portion is formed adjacent to the alternating stacks (32, 46). A via structure 84 is formed through the dielectric material portion (such as the stepped dielectric material portion 65). In one embodiment, the conductive layer 46 within the alternating stacks (32, 46) has a variable lateral extent that varies with the vertical distance from the source layer 110. In one embodiment, the alternating stack (32, 46) includes a stepped surface, and the dielectric material portion includes a stepped dielectric material portion 65, which includes a first region contacting the stepped surface of the alternating stack (32, 46) and a second region laterally offset from the first region and having a uniform thickness. A connecting via structure 84 can extend vertically through the second region.

[0118] refer to Figure 15A and Figure 15B A connection-level dielectric layer 90 may be formed above the contact-level dielectric layer 80. Connection pad cavities may be formed through the connection-level dielectric layer 90 and may be filled with at least one conductive material (which may include at least one metallic material) to form connection-level via structures (98, 96). The connection-level via structures (98, 96) include a drain connection via structure 98 of a corresponding drain contact via structure in the contact-drain contact via structures 88, and a layer connection via structure 96 of a corresponding layer contact via structure in the contact layer contact via structures 86.

[0119] Bit-line level dielectric layer 120 may be formed above interconnect level dielectric layer 90. Bit-line level cavities may be formed through bit-line level dielectric layer 120 and may be filled with at least one conductive material (which may include at least one metallic material) to form bit-line level metal lines (128, 126). Bit-line level metal lines may include bit lines 128 extending laterally along a second horizontal direction hd2, and bit-line level interconnect metal lines 126 (not shown separately) for providing electrical connections to layer interconnect via structure 96.

[0120] refer to Figure 16Additional dielectric material layers and additional metal interconnect structures may be formed above the contact-level dielectric layer 80. The additional dielectric material layer may include at least one via-level dielectric layer, at least one additional line-level dielectric layer, and / or at least one additional line and via-level dielectric layer. The additional metal interconnect structures may include metal via structures, metal line structures, and / or integrated metal line and via structures. The additional dielectric material layer formed above the contact-level dielectric layer 80 is referred to herein as memory-side dielectric layer 960. The additional metal interconnect structures are collectively referred to as memory-side dielectric layer 960. Memory-side dielectric layer 960 includes bit-line level dielectric material layers with embedded bit lines 128, which are a subset of memory-side metal interconnect structures 980.

[0121] Metal bonding pads (referred herein to as memory-side bonding pads 988) may be formed at the topmost layer of the memory-side dielectric layer 960. The memory-side bonding pads 988 may be electrically connected to the memory-side metal interconnect structure 980 and various nodes of the three-dimensional memory array, which includes alternating stacks of insulating layers 32 and conductive layers 46 and memory opening-filling structures 58. A first semiconductor die (e.g., a memory die) 900 may thus be provided. The first semiconductor die 900 may be used for VMM processing.

[0122] A memory-side dielectric layer 960 is formed over alternating stacks (32, 46). A memory-side metal interconnect structure 980 is embedded in the memory-side dielectric layer 960. Memory-side bonding pads 988 may be embedded within the memory-side dielectric layer 960, and specifically embedded in the topmost layer of the memory-side dielectric layer 960. The memory-side bonding pads 988 may be electrically connected to the memory-side metal interconnect structure 980.

[0123] In one embodiment, the first semiconductor die 900 may include: a three-dimensional memory array comprising alternating stacks (32, 46) of insulating layer 32 and conductive layer 46; a two-dimensional array of memory openings 49 extending vertically through the alternating stacks (32, 46); and a two-dimensional array of memory opening-filling structures 58 located within the two-dimensional array of memory openings 49 and comprising corresponding vertical stacks of memory elements and corresponding vertical semiconductor channels 60; a two-dimensional array of drain contact via structures 88 electrically connected to a corresponding vertical semiconductor channel 60 in the vertical semiconductor channel 60; and a two-dimensional array of layer contact via structures 86 electrically connected to a corresponding conductive layer 46, a subset of the conductive layers serving as word lines of the three-dimensional memory array.

[0124] In summary, a three-dimensional memory array, a dielectric portion including a stepped dielectric portion 65, a connection via structure 84 extending vertically through the stepped dielectric portion 65, and memory-side bonding pads 988 may be disposed within a first semiconductor die 900. In one embodiment, the first semiconductor die 900 further includes a memory-side dielectric layer 960 and a memory-side metal interconnect structure 980, with the memory-side bonding pads 988 embedded within the memory-side dielectric layer 960. The three-dimensional memory array may include alternating stacks of insulating layers 32 and conductive layers 46, and a two-dimensional array of NAND strings (e.g., memory aperture-filled structure 58) extending vertically through the alternating stacks (32, 46). In one embodiment, the conductive layer 46 includes word lines of the two-dimensional array of NAND strings. In one embodiment, the memory-side metal interconnect structure 980 includes bit lines 128 of the two-dimensional array of NAND strings.

[0125] refer to Figure 17 A logic die 700 is provided. The logic die 700 includes peripheral circuitry 720 formed on a logic-side substrate 709. According to one aspect of this disclosure, the peripheral circuitry 720 may be configured to control the operation of a three-dimensional memory array in a first semiconductor die 900. For example, the peripheral circuitry 720 may include word line driver regions, bit line driver regions, sense amplifier regions, input / output buffers, etc. A logic-side metal interconnect structure 780 embedded within a logic-side dielectric layer 760 may be formed above the peripheral circuitry 720. The logic die 700 includes logic-side bonding pads 788 embedded within the logic-side dielectric layer 760.

[0126] refer to Figure 18 A bonded assembly can be formed by bonding a logic die 700 to a first semiconductor die 900. The logic die 700 can be attached to the first semiconductor die 900, for example, by bonding logic-side bonding pads 788 to memory-side bonding pads 988. The bonding between the first semiconductor die 900 and the logic die 700 can be performed using a wafer-to-wafer bonding process (in which a two-dimensional array of the first semiconductor die 900 is bonded to a two-dimensional array of the logic die 700), a die-to-wafer bonding process, or a die-to-die bonding process. The logic-side bonding pads 788 within each logic die 700 can be bonded to the corresponding memory-side bonding pads 988 within the first semiconductor die 900.

[0127] The logic die 700 can be attached to the first semiconductor die 900, for example, by bonding logic-side bonding pads 788 to memory-side bonding pads 988. The bonding between the first semiconductor die 900 and the logic die 700 can be performed using a wafer-to-wafer bonding process (in which a two-dimensional array of the first semiconductor die 900 is bonded to a two-dimensional array of the logic die 700), a die-to-die bonding process, or a die-to-die bonding process. The logic-side bonding pads 788 within each logic die 700 can be bonded to the corresponding memory-side bonding pads 988 within the first semiconductor die 900. In one embodiment, the logic-side bonding pads 788 can be bonded to the memory-side bonding pads 988 via metal-to-metal bonding (such as copper-to-copper bonding).

[0128] refer to Figure 19 The carrier substrate 9 can be removed, for example, by grinding, polishing, cleaving, isotropic etching, and / or anisotropic etching processes. If a polishing process, such as chemical mechanical polishing, is used to remove the carrier substrate 9, a barrier insulating layer 106 can then be used as a polishing barrier material layer. If an etching process, such as wet etching, is used to remove the carrier substrate 9, a barrier insulating layer 106 can then be used as an etching barrier material layer. Optional electrical contacts can be formed on the bottom side of the bonded components of the first semiconductor die 900 and the logic die 700.

[0129] refer to Figure 20 The back-side dielectric layers (107, 108) may be deposited on the second side of the source layer 110. For example, the back-side dielectric layers (107, 108) may be formed on a surface (which may be referred to as the distal surface or back-side surface) that prevents the physical exposure of the insulating layer 106. In one embodiment, the back-side dielectric layers (107, 108) may include an optional first back-side dielectric layer 107 and a second back-side dielectric layer 108. In an exemplary example, the first back-side dielectric layer (if present) 107 may include silicon nitride, silicon carbide silicon nitride (i.e., silicon carbonitride), or any other suitable dielectric material, and may have a thickness in the range of 30 nm to 120 nm, but may also have smaller and larger thicknesses. The second back-side dielectric layer 108 may include undoped silicate glass (i.e., silicon oxide) or doped silicate glass, and may have a thickness in the range of 150 nm to 400 nm, but may also have smaller and larger thicknesses.

[0130] A photoresist layer (not shown) may be applied over the back-side dielectric layers (107, 108) and may be photolithographically patterned to form various openings in the peripheral region 400, and optionally at least one elongated opening may be formed at or near the boundary between the peripheral region 400 and the contact region 300. The openings in the peripheral region 400 may be formed over a corresponding subset of the connecting via structures 84. In an exemplary example, each opening in the photoresist layer in the peripheral region 400 may have regional overlap with two two-dimensional arrays of the connecting via structures 84.

[0131] An anisotropic etching process can be performed to transfer the pattern of openings in the photoresist layer through the back dielectric layer (107, 108), the barrier insulating layer 106, and the source layer 110. Back connection pad cavities 167 extend vertically through the back dielectric layer (107, 108), the barrier insulating layer 106, and the source layer 110. A row of back connection pad cavities 167 arranged along a second horizontal direction hd2 may be formed within the peripheral region 400. In one embodiment, at least one separation trench 165 may optionally be formed between the peripheral region 400 and the contact region 300.

[0132] refer to Figure 21 The back-side isolation layer 162 may be deposited on the distal surface (i.e., the back surface) of the back-side dielectric layers (107, 108), on the back-side dielectric layers (107, 108), on the sidewalls preventing the physical exposure of the insulating layer 106 and the source layer 110, and on the physically exposed surface segments of the stepped dielectric material portion 65. The back-side isolation layer 162 comprises a dielectric material, such as undoped or doped silicate glass, and may be formed by chemical vapor deposition. The thickness of the horizontally extending portion of the back-side isolation layer 162 may range from 200 nm to 1,000 nm (e.g., 300 nm to 600 nm), but smaller and larger thicknesses are also possible. A separation trench 165 may completely fill a portion of the back-side isolation layer 162. An opening may be formed through the portion of the back-side isolation layer 162 above the region connecting the via structure 84.

[0133] A backside connection pad layer can be deposited, which may include a stack of backside metal barrier pads and backside metal material layers. The backside connection pad layer may be patterned as backside connection pad structures 164 and source connection pad structures 168. Each backside connection pad structure 164 may include a combination of a backside metal barrier pad 164B and a backside metal layer 164M. Each source connection pad structure 168 may include a combination of a source metal barrier pad 168B and a source metal layer 168M.

[0134] refer to Figure 22At least one passivation dielectric layer 176 may be formed above the distal surfaces of the back-side connection pad structure 164, the source connection pad structure 168, and the back-side isolation layer 162. The at least one passivation dielectric layer 176 may be patterned to form various back-side contact cavities, exposing the surfaces of the back-side connection pad structure 164 and the source connection pad structure 168. At least one conductive material may be deposited in the back-side contact cavities and may be patterned to provide back-side contact pads 184 and source contact pads 188. The back-side contact pads 184 extend vertically through at least one passivation dielectric layer 176 and contact the distal surfaces of the corresponding back-side connection pad structures in the back-side connection pad structure 164. The source contact pads 188 extend vertically through at least one passivation dielectric layer 176 and contact the distal surfaces of the corresponding source connection pad structures in the source connection pad structure 168. The back contact pad 184 and the source contact pad 188 can be configured as wire bonding pads, C4 bonding pads, or metal bonding pads for metal-to-metal bonding.

[0135] refer to Figure 23 This illustrates a second exemplary structure according to an embodiment of the present disclosure for forming a first semiconductor die (e.g., a memory die) 900 after alternating stacks (32, 42) of a barrier insulating layer 206, a sacrificial semiconductor layer 212, a sacrificial insulating layer 207, a source semiconductor material layer 216, and an insulating layer 32 and spacer material layers (such as a sacrificial material layer 42) over a carrier substrate 9.

[0136] The substrate 9 may be the same as in the first exemplary structure. The alternating stacking of the insulating layer 32 and the spacer material layer 42 may also be the same as in the first exemplary structure.

[0137] The barrier insulating layer 206 may include an insulating layer that can be used as a barrier layer during the removal of the carrier substrate 9. For example, the barrier insulating layer 206 may include a silicon oxide layer having a thickness in the range of 100 nm to 1,000 nm, but smaller and larger thicknesses may also be used.

[0138] The sacrificial semiconductor layer 212 comprises a semiconductor material that can subsequently be selectively removed relative to the material of the memory film to be formed and also selectively removed relative to the material of the sacrificial insulating layer 207. For example, the sacrificial semiconductor layer 212 may comprise polycrystalline silicon or amorphous silicon and may optionally be doped with dopants. If the vertical semiconductor channel to be formed subsequently has doping of a first conductivity type, the sacrificial semiconductor layer 212 may have doping of the first conductivity type, may have doping of a second conductivity type opposite to the first conductivity type, or may be substantially intrinsic. The thickness of the sacrificial semiconductor layer 212 may range from 100 nm to 500 nm, but smaller and larger thicknesses are also possible.

[0139] The sacrificial insulating layer 207 includes an insulating material that can be selectively removed relative to the material of the source semiconductor material layer 216. For example, the sacrificial insulating layer 207 may include silicon oxide and may have a thickness in the range of 30 nm to 100 nm, but smaller and larger thicknesses are also possible.

[0140] The source semiconductor material layer 216 may include a doped semiconductor material, such as doped polycrystalline silicon or doped amorphous silicon. The conductivity type of the source semiconductor material layer 216 may be opposite to the conductivity of the vertical semiconductor channel to be formed subsequently. For example, if the vertical semiconductor channel to be formed subsequently has a first conductivity type of doping, then the source semiconductor material layer 216 has a second conductivity type of doping opposite to the first conductivity type. The thickness of the source semiconductor material layer 216 may be in the range of 10 nm to 300 nm, such as 20 nm to 150 nm, but smaller and larger thicknesses are also possible.

[0141] refer to Figure 24A and Figure 24B Executable reference Figure 2 , Figure 3A and Figure 3B The described processing steps form a stepped surface, a stepped dielectric material portion 65, a memory opening 49, and a support opening 19. Given that the source material layer 110' in the first exemplary structure is replaced by a stack of sacrificial semiconductor layer 212, sacrificial insulating layer 207, and source semiconductor material layer 216 in the second exemplary structure, the etching chemistry of the anisotropic etching process can be modified as needed.

[0142] refer to Figures 25A to 25C Executable reference Figure 4 , Figures 5A to 5G The processing steps described in FIG. 6 are used to form a support pillar structure 20 in each support opening 19 and a memory opening fill structure 58 in each memory opening 49. The memory opening fill structure 58 in the second exemplary structure may have the same structural features as the memory opening fill structure 58 in the first exemplary structure, except that the stacking of the sacrificial semiconductor layer 212, the sacrificial insulating layer 207, and the source semiconductor material layer 216 replaces the source material layer 110' in the process of the first exemplary structure. Each memory opening fill structure 58 may have a corresponding bottom surface that contacts the corresponding recessed surface of the sacrificial semiconductor layer 212.

[0143] refer to Figure 26A and Figure 26B Executable reference Figure 7A and Figure 7BThe described processing steps form a contact-level dielectric layer 80 and a lateral isolation trench 79. An oxidation process can be performed to convert physically exposed surface portions of the sacrificial semiconductor layer 212 and the source semiconductor material layer 216 into semiconductor oxide portions (e.g., silicon oxide portions, not shown), which are then used to protect the sacrificial semiconductor layer 212 and the source semiconductor material layer 216 during the replacement of the sacrificial material layer 42 with a conductive layer.

[0144] refer to Figure 27 Executable reference Figure 11 The described processing steps form a laterally extending cavity 43.

[0145] refer to Figure 28 Executable reference Figures 12A to 12D , Figure 13A and Figure 13B The described processing steps form a conductive layer 46 within the laterally extending cavity 43. In one embodiment, the conductive layer 46 within each alternating stack (32, 46) includes word lines and drain selection electrode lines covering the word lines. A core bias electrode 66 embedded within a memory opening-filling structure 58 in the alternating stack (32, 46) extends vertically through each word line in the alternating stack (32, 46).

[0146] refer to Figure 29 Executable reference Figure 14A and Figure 14B The described processing steps form an isolation trench filling structure 76, a drain contact via structure 88, a layer contact via structure 86, and a connection via structure 84.

[0147] refer to Figure 30 Executable reference Figure 15A , Figure 15B and Figure 16 The described processing steps form various metal interconnect structures and various dielectric material layers. A first semiconductor die 900 may be provided.

[0148] refer to Figure 31 Executable reference Figure 17 and Figure 18 The described processing steps are for forming a bonded assembly of a first semiconductor die (e.g., a memory die) 900 and a logic die 700.

[0149] refer to Figure 32 Executable reference Figure 19 The described processing steps are for removing the carrier substrate 9. The barrier insulating layer 206 may be used as a polishing barrier material layer or as an etching barrier material layer during the removal of the carrier substrate 9.

[0150] Figures 33A to 33FThis is a sequential vertical cross-sectional view of the region surrounding the memory opening filling structure 58 during the formation of the source layer 210, according to an embodiment of the present disclosure.

[0151] refer to Figure 33A A first selective etching process can be performed to selectively remove the barrier insulating layer 206 relative to the material of the sacrificial semiconductor layer 212. For example, if the barrier insulating layer 206 comprises silicon oxide, a wet etching process using diluted hydrofluoric acid can be performed to selectively etch the barrier insulating layer 206 relative to the material of the sacrificial semiconductor layer 212.

[0152] Subsequently, a second selective etching process can be performed to selectively remove the sacrificial semiconductor layer 212 relative to the material of the sacrificial insulating layer 207. For example, if the sacrificial semiconductor layer 212 comprises polysilicon, a wet etching process using thermal trimethyl-2-hydroxyethyl ammonium hydroxide (“thermal TMY”) or tetramethyl ammonium hydroxide (TMAH) can be performed to selectively etch the sacrificial semiconductor layer 212 relative to the materials of the sacrificial insulating layer 207 and each memory film 50.

[0153] refer to Figure 33B A third selective etching process can be performed to remove the sacrificial insulating layer 207 and the end portions of each memory film 50 that are further away from the bonding interface between the first semiconductor die 900 and the logic die 700 than a horizontal plane including the distal surface of the source semiconductor material layer 216 (i.e., the physically exposed surface of the source semiconductor material layer 216). In an exemplary example, the sacrificial insulating layer 207 may comprise silicon oxide, and the third selective etching process may comprise a wet etching step using diluted hydrofluoric acid. The distal surface of the source semiconductor material layer 216 may be physically exposed. If any portion of the memory film 50 remains further away from the bonding interface than the distal surface of the source semiconductor material layer 216, at least one additional isotropic etching process (such as at least one wet etching process) may be performed to remove such remaining portions of the memory film 50. The end faces (which may be flat surfaces) and cylindrical surface segments of the outer walls of each vertical semiconductor channel 60 may be physically exposed.

[0154] refer to Figure 33C A self-planarization mask material (such as spin-coated carbon) can be applied to the physically exposed distal surface of the source semiconductor material layer 216 surrounding each vertical protrusion of the memory aperture fill structure 58. The self-planarization mask material forms a mask material layer 213. The height of the vertical protrusions of the memory aperture fill structure 58 can be selected such that the end face of the vertical semiconductor channel 60 is not covered by the mask material layer 213.

[0155] refer to Figure 33DA first etching process can be performed to remove the physically exposed end portions of the vertical semiconductor channel 60. The first etching process may include a first anisotropic etching process (such as reactive ion etching) or a first isotropic etching process (such as wet etching). The mask material layer 213 protects the source semiconductor material layer 216 during the first etching process. After the first etching process, the end portions of the core dielectric pad 621 can be physically exposed.

[0156] A second etching process can be performed to remove the physically exposed end portions of the core dielectric pad 621. The second etching process may include a second anisotropic etching process (such as reactive ion etching) or a second isotropic etching process (such as wet etching). The mask material layer 213 protects the source electrode semiconductor material layer 216 during the second etching process. After the second etching process, the end portions of the core bias electrode 66 are physically exposed.

[0157] refer to Figure 33E The mask material layer 213 can be selectively removed relative to the memory opening filling structure 58 and the source semiconductor material layer 216, for example, by ashing.

[0158] refer to Figure 33F and Figure 34 The source layer 210 is deposited above the source-level semiconductor material layer 216, contacting the core bias electrode 66 and the exposed end portion of the vertical semiconductor channel 60. The source layer 210 may comprise a heavily doped semiconductor material (such as heavily doped polysilicon) and / or a metallic material (such as a conductive metal nitride and / or a metal) having a second conductivity type. In one embodiment, the source layer 210 may be deposited by plasma-enhanced chemical vapor deposition. The thickness of the horizontally extended portion of the source layer 210 may range from 50 nm to 200 nm, but smaller and larger thicknesses are also possible.

[0159] In a second exemplary structure, each core dielectric pad 621 may contact the source layer 210. Within each memory opening fill structure 58, the vertical semiconductor channel 60 includes a first end portion that contacts the drain region 63. In one embodiment, an annular surface segment of the second end portion of the vertical semiconductor channel 60 contacts the source layer 210. In one embodiment, the source layer 210 contacts the second end portion of the vertical semiconductor channel 60 and also contacts the end portion of the core bias electrode 66.

[0160] Within each memory opening filling structure 58, a first annular end face of the core dielectric pad 621 contacts the drain region 63, and a second annular end face of the core dielectric pad 621 contacts the source layer 210. In one embodiment, a cylindrical surface segment of the core bias electrode 66 may contact the source layer 210. In one embodiment, a flat end face of the core bias electrode 66 may contact the source layer 210. In one embodiment, an annular end face of the vertical semiconductor channel 60 contacts the source layer 210, and a cylindrical surface segment of the outer cylindrical sidewall of the vertical semiconductor channel 60 contacts the core dielectric pad 621. In one embodiment, an end face of the core bias electrode 66 is adjacent to and laterally defined by the periphery of the sidewall of the core bias electrode 66, and contacts the source layer 210.

[0161] refer to Figure 35 The source layer 210 and the source-level semiconductor material layer 216 can be patterned. At least one back-side dielectric layer 161 can be formed over the source layer 210. (Executable reference) Figures 20 to 22 The described processing steps form a back-side connection pad cavity, a back-side isolation layer 162, a back-side connection pad structure 164, a source connection pad structure 168, at least one passivation dielectric layer 176, a back-side contact pad 184, and a source contact pad 188.

[0162] Referring to all the accompanying drawings and according to various embodiments of the present disclosure, a semiconductor device includes: an alternating stack (32, 46) of an insulating layer 32 and a conductive layer 46; a memory opening 49 extending vertically through the alternating stack (32, 46); a memory opening filling structure 58 located in the memory opening 49 and including a memory film 50, a vertical semiconductor channel 60 laterally surrounded by the memory film 50, a drain region 63 contacting a first end portion of the vertical semiconductor channel 60, a dielectric core 62 surrounded by the vertical semiconductor channel 60, and a core bias electrode 66 surrounded by the dielectric core 62; and a source layer (110 or 210) contacting a second end portion of the vertical semiconductor channel 60 and an end portion of the core bias electrode 66.

[0163] In one embodiment, a core bias electrode 66 extends vertically through a plurality of conductive layers 46 within an alternating stack (32, 46). In one embodiment, the conductive layers 46 include word lines and drain select electrode lines; and the core bias electrode 66 extends vertically through each of the word lines but not through the drain select electrode line.

[0164] In one embodiment, the dielectric core 62 includes a cylindrical dielectric core portion 622 and a core dielectric pad 621; a first end face of the core bias electrode 66 contacts the first end face of the cylindrical dielectric core portion 622; and the periphery of the first end face of the core bias electrode 66 coincides with the periphery of the first end face of the cylindrical dielectric core portion 622. In one embodiment, a second end face of the cylindrical dielectric core portion 622 contacts a drain region 63. In one embodiment, a cylindrical sidewall of the cylindrical dielectric core portion 622 contacts a first surface segment of the inner cylindrical sidewall of the core dielectric pad 621. In one embodiment, a cylindrical sidewall of the core bias electrode 66 contacts a second surface segment of the inner cylindrical sidewall of the core dielectric pad 621.

[0165] In one embodiment, the core dielectric pad 621 extends vertically through each conductive layer within the alternating stack (32, 46) and contacts the source layer (110 or 210). In one embodiment, an annular surface segment of the second end portion of the vertical semiconductor channel 60 contacts the source layer (110 or 210).

[0166] In one embodiment, the first annular end face of the core dielectric pad 621 contacts the drain region 63; and the second annular end face of the core dielectric pad 621 contacts the source layer (110 or 210). In one embodiment, the cylindrical surface segment of the core bias electrode 66 contacts the source layer (110 or 210).

[0167] In one embodiment, the annular end face of the vertical semiconductor channel 60 contacts the source layer 110; and the entire outer cylindrical sidewall of the vertical semiconductor channel 60 contacts the dielectric core 62.

[0168] In one embodiment, the end face of the core bias electrode 66 contacts the source layer 210. In one embodiment, the annular end face of the vertical semiconductor channel 60 contacts the source layer 210; and the cylindrical surface segment of the outer cylindrical sidewall of the vertical semiconductor channel 60 contacts the source layer (110 or 210).

[0169] In one embodiment, the core bias electrode 66 is essentially composed of a portion of doped semiconductor material (or any NAND process-compatible conductive material) having a cylindrical shape.

[0170] In one embodiment, a method includes performing vector-matrix multiplication using the aforementioned semiconductor device (e.g., a first semiconductor die 900).

[0171] While the foregoing relates to specific preferred embodiments, it should be understood that this disclosure is not limited thereto. Those skilled in the art will envision various modifications that can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. Compatibility is assumed between all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words “comprising” or “including” contemplate that the words “consistently consisting of” or “comprises of” replace all embodiments for which the words “comprising” or “including” are used. Whenever two or more elements are listed as alternatives in the same paragraph or different paragraphs, a Markush group comprising the list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb “capable” is used in this disclosure to describe the formation of an element or the execution of a processing step, it is also clearly envisioned that embodiments in which such element or such processing step is not performed are included, provided that the resulting apparatus or device is capable of providing equivalent results. Therefore, whenever omitting such an element or the formation of such a processing step can provide the same or equivalent result, the auxiliary verb "can" applied to the formation of an element or the execution of a processing step should also be interpreted as "can" or "may, or may not," with these equivalent results including slightly superior and slightly inferior results. In cases where embodiments employing specific structures and / or configurations are illustrated in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise known to be impossible for a person skilled in the art. If any publications, patent applications, and / or patents are cited herein, each of such documents is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, the semiconductor device comprising: Alternating stacking of insulating and conductive layers; A memory opening that extends vertically through the alternating stack; A memory opening filling structure is located in the memory opening and includes a memory film, a vertical semiconductor channel laterally surrounded by the memory film, a drain region contacting a first end portion of the vertical semiconductor channel, a dielectric core surrounded by the vertical semiconductor channel, and a core bias electrode surrounded by the dielectric core. and A source layer that contacts a second end portion of the vertical semiconductor channel and an end portion of the core bias electrode.

2. The semiconductor device of claim 1, wherein the core bias electrode extends vertically through a plurality of conductive layers within the alternating stack.

3. The semiconductor device according to claim 1, wherein: The conductive layer includes word lines and drain selection electrode lines; and The core bias electrode extends vertically through each of the word lines, but does not extend through the drain select electrode line.

4. The semiconductor device according to claim 1, wherein: The dielectric core includes a cylindrical dielectric core portion and a core dielectric liner; The first end face of the core bias electrode contacts the first end face of the cylindrical dielectric core portion; and The periphery of the first end face of the core bias electrode coincides with the periphery of the first end face of the cylindrical dielectric core portion.

5. The semiconductor device of claim 4, wherein the second end face of the cylindrical dielectric core portion contacts the drain region.

6. The semiconductor device of claim 4, wherein the cylindrical sidewall of the cylindrical dielectric core portion contacts a first surface segment of the inner cylindrical sidewall of the core dielectric pad.

7. The semiconductor device of claim 6, wherein the cylindrical sidewall of the core bias electrode contacts a second surface segment of the inner cylindrical sidewall of the core dielectric pad.

8. The semiconductor device of claim 4, wherein the core dielectric pad extends vertically through each conductive layer within the alternating stack and contacts the source layer.

9. The semiconductor device according to claim 4, wherein: The first annular end face of the dielectric core dielectric pad contacts the drain region; and The second annular end face of the core dielectric pad contacts the source layer.

10. The semiconductor device of claim 1, wherein the annular surface section of the second end portion of the vertical semiconductor channel contacts the source layer.

11. The semiconductor device of claim 1, wherein the cylindrical surface segment of the core bias electrode contacts the source layer.

12. The semiconductor device of claim 1, wherein the end face of the core bias electrode contacts the source layer.

13. The semiconductor device according to claim 1, wherein: The annular end face of the vertical semiconductor channel contacts the source layer; and The entire outer cylindrical sidewall of the vertical semiconductor channel contacts the dielectric core.

14. The semiconductor device of claim 1, wherein the annular end face of the vertical semiconductor channel and the cylindrical surface section of the outer cylindrical sidewall of the vertical semiconductor channel contact the source layer.

15. The semiconductor device of claim 1, wherein the core bias electrode is substantially composed of a portion of a doped semiconductor material or a conductive material having a cylindrical shape.

16. A method comprising performing vector-matrix multiplication using a semiconductor device according to claim 1.

17. A method of forming a semiconductor device, the method comprising: An alternating stack of insulating and spacer material layers is formed, wherein the spacer material layers are formed as conductive layers or subsequently replaced by conductive layers; Forming an opening through the alternating stacks of memory; A memory opening filling structure is formed in the memory opening, wherein the memory opening filling structure includes a memory film, a vertical semiconductor channel that is laterally surrounded by the memory film, a drain region that contacts a first end portion of the vertical semiconductor channel, a dielectric core surrounded by the vertical semiconductor channel, and a core bias electrode surrounded by the dielectric core. as well as A source layer is formed on the second end portion of the vertical semiconductor channel and on the end portion of the core bias electrode.

18. The method of claim 17, wherein forming the memory opening-filling structure comprises: A semiconductor channel material layer is formed in the memory opening and over the alternating stack; A core dielectric pad layer is formed above the semiconductor channel material layer; as well as A conductive material is deposited within the volume laterally surrounded by the core dielectric liner layer, and the conductive material is vertically recessed to form the core bias electrode.

19. The method of claim 17, wherein the core bias electrode extends vertically through a plurality of spacer material layers within the alternating stack.

20. The method of claim 17, wherein the core bias electrode is electrically isolated from the vertical semiconductor channel prior to the formation of the source layer.

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