Pulse type ground penetrating radar variable radio frequency direct sampling method and system

Abstract

The invention provides a pulse type ground penetrating radar variable radio frequency direct sampling method and system, and the method comprises the steps: S1, obtaining the preset parameters of a pulse type ground penetrating radar, and the preset parameters comprise the working frequency, the pulse repetition frequency, the expansion factor EF and the ADC maximum sampling rate; s2, calculating an ADC sampling clock frequency; s3, checking a calculation result; s4, controlling a clock chip to output a sampling clock and other auxiliary clocks, and controlling a programmable clock chip of the pulse type ground penetrating radar to output a sampling subsystem working clock, a synchronous clock of a D trigger and a sampling clock of an ADC according to calculation results of the steps S1 to S3; s5, generating a transmission pulse; and step S6, radio frequency direct sampling. According to the pulse type ground penetrating radar variable radio frequency direct sampling method, a delay module is not used, a small frequency difference does not need to be constructed by relying on a DDS, equivalent sampling time stepping is implicitly formed only by using ADC sampling clock frequency and transmitted pulse repetition frequency as references, and a pulse type ground penetrating radar variable radio frequency direct sampling scheme is achieved.

Description

Technical Field

[0001] This invention relates to a sampling technology solution for ground penetrating radar, and more particularly to a pulse ground penetrating radar variable radio frequency direct sampling method without using a delay module and DDS, and further to a system employing this pulse ground penetrating radar variable radio frequency direct sampling method. Background Technology

[0002] As ground-penetrating radar (GPR) is increasingly used in various applications, the demands for cost and performance are constantly rising. Currently, the most widely used pulse-type GPR operates on a pulse mode, detecting targets by emitting ultra-wideband pulses and receiving reflected echoes from the underground medium.

[0003] After decades of development, radar frequency ranges have reached approximately 50MHz – 2GHz or even higher, requiring a detection signal-to-noise ratio of no less than 66dB and a sampling rate (GHz) from 1.5GHz to over 6GHz. Therefore, higher demands have been placed on the design and implementation of the sampling subsystem.

[0004] Traditional equivalent sampling methods that rely on mixers are limited by the difficulty of designing high-performance mixers and the additional losses brought by mixers. They are complex in structure and have many intermediate links, making it increasingly difficult to meet the requirements of ground penetrating radar for high signal-to-noise ratio and wide dynamic range of sampling systems.

[0005] In recent years, the emerging RF direct sampling (RF Direct Sampling) scheme refers to an architecture that skips the down-conversion (mixing) stage in traditional receivers and directly samples the RF signal using an ADC. RF Direct Sampling avoids the problems of high circuit complexity, high cost, and high power consumption of traditional schemes, and introduces additional sources of distortion and noise, resulting in better resolution and performance.

[0006] However, in the field of pulse ground-penetrating radar, due to the large bandwidth and center frequency of the sampled signal ranging from 50MHz to 2GHz, high-speed direct RF sampling places excessively high demands on the ADC, making the power consumption and price prohibitive for civilian products emphasizing economy and portability. Therefore, equivalent sampling methods are typically employed to reduce costs and power consumption. However, existing sampling techniques still have their own inherent problems.

[0007] Stepped equivalent sampling, as described in existing RF direct sampling solutions, typically achieves equivalent sampling by finely stepping the sampling time within multiple pulse repetition cycles using programmable delay modules, delay lines, or phase scanning structures. Stepped sampling using delay devices usually requires a combination of multiple delay devices to meet the requirements of a wide range (typically hundreds of nanoseconds) and high precision (picosecond level) delays. Its accuracy depends on the consistency of analog or dedicated devices and the design of peripheral circuits such as temperature compensation. In practical engineering applications, consistency is difficult to guarantee, making stable implementation on general-purpose programmable logic platforms challenging. Furthermore, the system's adjustability is difficult to achieve, and the combination of delay devices may need to be replaced when requirements change.

[0008] The main technical problem with using the frequency difference method for direct RF sampling in this field is that the conventional frequency difference method relies on Direct Digital Synthesis (DDS) to construct two signals with a small frequency difference for difference frequency sampling. However, in this field, the sampling frequency of ADCs is usually above 100MHz. The pulse repetition frequency of the sampled signal is limited by the rate at which the analog circuit generates high-voltage Gaussian pulses, the time window limit of the received echo (ranging from hundreds of nanoseconds), and the need for multi-channel time-division operation to avoid interference. It is usually in the hundreds of kHz, differing by two orders of magnitude. Therefore, this sampling scheme is difficult to design to meet the requirements of a small frequency difference, which leads to difficulties in engineering implementation in practical applications. DDS refers to Direct Digital Synthesis.

[0009] Interleaved sampling, or time interleaving, is a technique that connects multiple ADC chips in parallel, allowing them to sample alternately and in parallel, thereby improving the overall system sampling rate. However, this approach is costly and consumes a lot of power, hindering its practical application.

[0010] Therefore, for the field of pulse ground-penetrating radar, it is of great significance to provide a sampling technology solution that does not use a delay module for step control and does not rely on DDS to generate two small frequency difference signals, in order to simplify the system structure and reasonably control the cost. Summary of the Invention

[0011] The technical problem this invention aims to solve is to provide a variable radio frequency (RF) direct sampling method for pulse ground-penetrating radar (GPR) that does not use a delay module and does not rely on a DDS. The method aims to implicitly form an equivalent sampling time step by rationally configuring the non-integer multiple relationship between the sampling clock frequency and the transmission pulse repetition frequency, using a general-purpose programmable clock chip and only the ADC sampling clock frequency and the transmission pulse repetition frequency as references. This achieves high-equivalent sampling rate echo waveform reconstruction, thus realizing the wide-frequency range variable RF direct sampling method required by pulse ground-penetrating radar. Furthermore, a system employing this pulse ground-penetrating radar variable RF direct sampling method is also provided.

[0012] To address this, the present invention provides a variable radio frequency direct sampling method for pulse ground-penetrating radar, comprising the following steps:

[0013] Step S1: Obtain the preset parameters of the pulse ground-penetrating radar, including the operating frequency. Pulse repetition frequency The spread factor EF and the maximum sampling rate of the ADC ;

[0014] Step S2, based on the pulse repetition frequency , expansion factor EF and ADC maximum sampling rate Through formula Calculate the ADC sampling clock frequency ,in, For intermediate parameters, ;

[0015] Step S3: Verify the calculation results using the formula. Verify ADC sampling frequency Repetition frequency of the emitted pulse If the non-integer multiple relationship between them is not satisfied, return to step S2 to check the calculation process; if it is satisfied, jump to step S4. It is a positive integer;

[0016] Step S4: Control the clock chip to output the sampling clock and other auxiliary clocks. Based on the calculation results of steps S1-S3, control the programmable clock chip of the pulse ground penetrating radar to output the working clock of the sampling subsystem, the synchronization clock of the D flip-flop, and the sampling clock of the ADC.

[0017] Step S5: Generate a transmission pulse, which is obtained by dividing the operating frequency Fs to obtain a pulse trigger signal. After being aligned and debouncing with the synchronous clock signal by a D flip-flop, the pulse repetition frequency is formed. It is then transmitted from the antenna after being formed into a first-order Gaussian pulse signal through a pulse shaping module;

[0018] Step S6, RF direct sampling: Driven by the sampling clock signal, the ADC performs RF direct sampling. The sampled data goes through EF pulse repetition cycles, and the output data is stepped according to the equivalent sampling time. After aligning the sampling points, the restored waveform is formed, with an equivalent sampling rate. for .

[0019] A further improvement of the present invention is that, in step S1, the expansion factor EF satisfies the following constraints. Where N≥10, This indicates the rounding up operation.

[0020] A further improvement of the present invention is that, in step S1, the expansion factor EF also satisfies the following constraints. .

[0021] A further improvement of the present invention is that, in step S1, the pulse repetition frequency... The value is selected as an integer multiple of 100 between 100K and 1MHz; in step S1, the pulse repetition frequency The value should be a multiple of 100 between 100K and 1MHz, and the operating frequency should be... Choose a frequency close to the maximum sampling frequency of the ADC between 50MHz and 200MHz. And satisfy The value.

[0022] A further improvement of the present invention is that, in step S1, the spread factor EF and the pulse repetition frequency... and operating frequency All parameters are set to preset parameters that can be obtained by looking up a table.

[0023] A further improvement of the present invention is that, in step S4, the frequency of the sampling subsystem's operating clock is the operating frequency. The operating clock frequency of the D flip-flop is F. D The frequency is F D With operating frequency Same frequency and phase.

[0024] The present invention also provides a pulse ground-penetrating radar variable radio frequency direct sampling system, which adopts the pulse ground-penetrating radar variable radio frequency direct sampling method as described above, and includes: a processing unit U1, an ADC chip U2, a clock chip U3, a D flip-flop U4, a pulse shaping circuit U5, a transmitting antenna U6, and a receiving antenna U7.

[0025] The processing unit U1 integrates an FPGA unit and an ARM unit. The FPGA unit is used to process high-speed signals, including the generation of radio frequency signals and ADC sampling data processing. The ARM unit is responsible for clock chip management, data management, and external data communication. The ADC chip U2 is an analog-to-digital converter. The clock chip U3 is a programmable clock generator, which sends the system operating clock (operating frequency Fs) to the processing unit U1 and sends the ADC sampling clock (ADC sampling frequency). The synchronous clock (synchronization frequency) is sent to the ADC chip U2. ) to the D flip-flop U4, wherein the ADC sampling clock Directly used for sampling; while the operating frequency and synchronization frequency The initial phase and frequency are the same, and are used as the system clock and the input clock of the D flip-flop, respectively; the D flip-flop U4 transmits and synchronizes the frequency. Synchronous pulse repetition frequency The pulse shaping circuit U5 sends the shaped first-order Gaussian pulse signal to the transmitting antenna U6, and the receiving antenna U7 is connected to the ADC chip U2.

[0026] A further improvement of the present invention is that the processing unit U1 synchronously receives the sampling data and sampling feedback clock uploaded by the ADC chip U2 using the LVDS interface, and the processing unit U1 sends a pulse trigger signal. After debouncing by the D flip-flop U4, a pulse repetition frequency is generated. .

[0027] A further improvement of the present invention is that the system workflow includes the following steps:

[0028] The standby process involves determining the system's state based on commands from the host computer or idle time. This is achieved by controlling the ADC chip U2 to enter sleep mode via the SPI interface and by using I... 2 The C-bus controls the clock chip U3 to go into sleep mode, and the processing unit U1 enters sleep mode and waits for WIFI / LAN to wake it up.

[0029] In the clock signal generation step, during system startup / wake-up, processing unit U1 obtains the extension factor EF and pulse repetition frequency by looking up a table based on the product model configured on the host computer. and operating frequency The control clock chip U3 generates and sends three clock signals, the frequencies of which are respectively the ADC sampling frequency. Operating frequency and synchronization frequency ;

[0030] In the pulse signal generation step, the FPGA unit utilizes the operating frequency A pulse trigger signal is generated after frequency division. After debouncing by the D flip-flop U4, the frequency is generated to match the synchronization frequency. Synchronous pulse trigger signals in phase are denoted as pulse repetition frequency. A first-order Gaussian pulse signal is generated by the pulse shaping circuit U5 and transmitted from the transmitting antenna U6.

[0031] In the ADC sampling step, the clock signal generated by the clock chip U3 directly drives the ADC chip U2. The ADC chip U2 performs direct radio frequency sampling on the signal received by the receiving antenna U7. The sampled data and sampling feedback clock are then sent to the processing unit U1 through the LVDS data interface.

[0032] The equivalent sampling processing step involves the processing unit U1 receiving sampled data and performing time-domain conversion under the drive of the sampling feedback clock, and then using the pulse-type ground-penetrating radar variable radio frequency direct sampling method to restore the received signal.

[0033] The multi-channel expansion step involves synchronously expanding the number of channels and pulse repetition frequency of the ADC chip U2. The number of channels supports the acquisition tasks of multi-channel ground-penetrating radar;

[0034] The multi-system cascading steps involve cascading the array radar in a daisy-chain configuration. The master node outputs a clock synchronization signal and a pulse synchronization signal. The clock chip U3 of the sub-node uses the clock synchronization signal output by the master node as its clock source. The processing unit U1 of the sub-node uses the pulse synchronization signal output by the master node as a reference for concurrent control, thereby completing the multi-channel ground-penetrating radar acquisition task required by the array radar.

[0035] A further improvement of the present invention is that, in the multi-channel expansion step, the number of expanded channels includes the number of channels at the receiving end. and the number of channels at the transmitting end and satisfy .

[0036] Compared with the prior art, the beneficial effect of the present invention is that the only thing that needs to be calculated and changed in the system is The expansion factor EF and pulse repetition frequency are obtained by looking up a table. and operating frequency After setting the fixed preset parameters, then calculate the intermediate parameters. It can be done through the formula Obtain the ADC sampling frequency And through the formula Verify ADC sampling frequency Repetition frequency of the emitted pulse The non-integer multiple relationship between them; finally, after EF pulse repetition cycles, according to the equivalent sampling time step. Align the sampling points to complete waveform reconstruction. Therefore, the equivalent sampling time step of this invention... Determined solely by the spread factor EF and the pulse repetition frequency On the one hand, it eliminates the need for any programmable delay modules, delay lines, or phase scanning circuits, effectively simplifying its hardware structure and reducing hardware design complexity. On the other hand, it eliminates the need to rely on DDS to construct the tiny frequency difference required for equivalent sampling using the conventional frequency difference method, and avoids the trade-off between pulse repetition frequencies and ADC sampling frequencies that differ by two orders of magnitude, resulting in a simple and easy-to-implement overall structure. Furthermore, the extension factor EF can be flexibly configured at different pulse repetition frequencies. With a fixed frequency, only the ADC sampling frequency needs to be dynamically adjusted. It can adapt to the sampling requirements of pulse ground-penetrating radars of different frequencies. Attached Figure Description

[0037] Figure 1 This is a schematic diagram of the workflow of one embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of the system framework structure according to another embodiment of the present invention;

[0039] Figure 3 This is a schematic diagram of an engineering implementation circuit of another embodiment of the present invention. Detailed Implementation

[0040] In the description of this invention, if directional descriptions are involved, such as "up," "down," "front," "back," "left," "right," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, it is only for the convenience of describing the invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. If a technical feature is referred to as "set," "fixed," "connected," or "installed" on another technical feature, it can be directly set, fixed, or connected to the other technical feature, or it can be indirectly set, fixed, connected, or installed on the other technical feature.

[0041] In the description of this invention, the term "several" means one or more; the term "multiple" means two or more; the terms "greater than," "less than," and "exceeding" are all understood to exclude the stated number; and the terms "above," "below," and "within" are all understood to include the stated number. The terms "first," "second," etc., are understood to be used only to distinguish identical or similar technical feature names, and should not be construed as implying / indicating the relative importance of the technical features, the number of technical features, or the sequential relationship between the technical features.

[0042] The preferred embodiments of the present invention will now be described in further detail with reference to the accompanying drawings.

[0043] like Figure 1 As shown, this embodiment provides a variable radio frequency direct sampling method for pulse ground-penetrating radar, including the following steps:

[0044] Step S1: Obtain the preset parameters of the pulse ground-penetrating radar, including the operating frequency. Pulse repetition frequency The spread factor EF and the maximum sampling rate of the ADC These preset parameters are determined directly or indirectly by the hardware, such as the pulse repetition frequency. and ADC maximum sampling rate Directly limited by device performance, the spread factor EF is determined by the center frequency of the ground-penetrating radar and the maximum sampling rate of the ADC. These preset parameters are determined during the overall radar design and usually do not need to be changed; therefore, they can be obtained by looking up a table.

[0045] Step S2, based on the pulse repetition frequency , expansion factor EF and ADC maximum sampling rate Through formula Calculate the ADC sampling clock frequency ,in, For intermediate parameters, ;

[0046] Step S3: Verify the calculation results using the formula. Verify ADC sampling frequency Repetition frequency of the emitted pulse If the non-integer multiple relationship between them is not satisfied, return to step S2 to check the calculation process; if it is satisfied, jump to step S4. It is a positive integer;

[0047] Step S4: Control the clock chip to output the sampling clock and other auxiliary clocks. Based on the calculation results of steps S1-S3 above, control the programmable clock chip of the pulse ground penetrating radar to output the operating clock (frequency of operating frequency Fs) of the sampling subsystem and the synchronization clock (frequency of synchronization frequency F) of the D flip-flop. D， The sampling clock of the ADC (with the same frequency and phase as the operating frequency Fs) and the sampling clock of the ADC (frequency is the pulse repetition frequency) Other auxiliary clocks include the operating clock of the sampling subsystem and the synchronization clock of the D flip-flops, corresponding to the operating frequency Fs and the synchronization frequency F, respectively. D ;

[0048] Step S5: Generate a transmission pulse, which is obtained by dividing the operating frequency Fs to obtain a pulse trigger signal. (the pulse trigger signal) The frequency is the pulse repetition frequency. After passing through a D flip-flop and a synchronous clock signal (frequency F), D After alignment and debouncing, the pulse repetition frequency is formed. It is then transmitted from the antenna after being formed into a first-order Gaussian pulse signal through a pulse shaping module;

[0049] Step S6, direct RF sampling. The sampling clock signal (frequency is the ADC sampling clock frequency) is used for sampling. Driven by the ADC, direct RF sampling is performed. The sampled data passes through EF pulse repetition cycles, and the output data is stepped according to the equivalent sampling time. After aligning the sampling points, the restored waveform is formed, with an equivalent sampling rate. for .

[0050] In this embodiment, the pulse repetition frequency The number of detection pulses emitted per second by a pulse ground-penetrating radar is limited by various factors such as the performance of the pulse transmission module circuit, the sampling window (detection depth), the asynchronous working interval of multiple channels, the number of superpositions, and the maximum acquisition speed, and is usually fixed. In step S1 of this embodiment, the pulse repetition frequency... The value is chosen as an integer multiple of 100 between 100K and 1MHz to simplify system processing. The ADC sampling frequency... This indicates the actual sampling frequency of the ADC chip U2, which is subject to the maximum available ADC sampling frequency. Limitations. To fully utilize ADC performance, the optimal ADC operating frequency should be calculated to be as close as possible to... The EF is the expansion factor, representing the number of signal cycles required to complete one equivalent sampling, and is subject to the equivalent sampling rate. The limitations. A positive integer, representing the ADC sampling frequency. With pulse repetition frequency The integer part of the ratio is the number of complete ADC sampling cycles contained within a single pulse repetition cycle.

[0051] In step S1 of this embodiment, the expansion factor EF satisfies the following constraints: ,in, This indicates the rounding up operation. N is an integer greater than 2, which is required by the Nyquist sampling theorem and is also called the Nyquist redundancy factor. By default, N≥10.

[0052] Preferably, in step S1 of this embodiment, the expansion factor EF also satisfies the following constraints. And usually, a multiple of 10 is chosen.

[0053] When the spread factor EF and the pulse repetition frequency and operating frequency Once the system parameters are determined, in step S2 of this embodiment, the first step is to use the formula... Calculate the intermediate parameter SL. This indicates a rounding up operation. The intermediate parameter SL is a user-defined intermediate parameter used as an auxiliary parameter for calculating the dynamically adjustable equivalent sampling frequency. It does not directly participate in system operation and represents the minimum integer value of the maximum number of complete sampling points that can be accommodated within a single pulse repetition period.

[0054] Then, through the formula Calculate the ADC sampling frequency .

[0055] In step S1 of this embodiment, the operating frequency of the system containing the pulse ground-penetrating radar is: Operating frequency The constraints to be satisfied are: and mod is the modulo operator; operating frequency Due to the limitations of FPGA unit processing capabilities, a frequency close to the maximum sampling frequency of the ADC is typically selected between 50MHz and 200MHz. A value that is an integer multiple of 10.

[0056] In step S3 of this embodiment, the ADC sampling frequency... Repetition frequency of the emitted pulse Satisfy the formula This indicates the existence of a non-integer multiple relationship, meaning that within two adjacent pulse repetition cycles, the sampling time will have a fixed equivalent time offset relative to the transmission time. Also known as equivalent sampling time step Therefore, after EF pulse repetition cycles, a complete equivalent sampling scan can be completed.

[0057] In step S4 of this embodiment, the frequency of the sampling subsystem's operating clock is the operating frequency. The operating clock frequency of the D flip-flop is F. D The frequency is F D With operating frequency Same frequency and phase.

[0058] In step S6 of this embodiment, after EF pulse repetition cycles, the sampling time is stepped according to the equivalent sampling time. Align the sampling points to complete waveform reconstruction; the system's equivalent sampling rate. Through formula Calculated.

[0059] As can be seen from the above formula, the ADC sampling frequency can be automatically calculated and adjusted by changing the spread factor EF while keeping the hardware parameters unchanged. This allows for the adjustment of the system's equivalent sampling rate. This adjustment only requires changing the frequency of one clock output channel via the FPGA unit, without needing to adjust hardware parameters, thus offering significant flexibility.

[0060] Next, this embodiment constructs an application example of variable radio frequency direct sampling for pulse ground-penetrating radar, which does not employ delay devices and differs from traditional frequency difference sampling by not requiring small frequency differences. The final pulse ground-penetrating radar has a center frequency of 600MHz, and its pulse repetition frequency is... The ADC sampling frequency is 300kHz. It is 199.8075MHz, which is the pulse repetition frequency. and ADC sampling frequency The significant differences allow the ADC to operate at full speed, and it is unique in the field. Typically, with a fixed value, only the ADC sampling frequency is changed. It can change the equivalent sampling rate without the need for other redundant devices such as DDS, and can meet the radio frequency direct sampling requirements of pulse ground penetrating radar with a center frequency of 1GHz or higher.

[0061] The system parameters in this embodiment are defined as follows: the center frequency of the pulse ground-penetrating radar. =600MHz, ADC maximum sampling frequency =200MHz, pulse repetition frequency The frequency is 300kHz, the Nyquist redundancy factor is N=10, and the expansion factor is EF=40.

[0062] In practical applications, the following steps and formulas can be used for calculation and verification. Among them, the operating frequency... The preferred options are as follows: taking into account both FPGA processing power and ADC speed, operating frequency... The value can be taken as 150MHz, which satisfies... Require.

[0063] The expansion factor EF is checked as follows: EF is preferably 40, which is greater than the calculated 30 and also divisible by 300kHz, satisfying the equivalent sampling bandwidth requirement for EF. The calculation process is as follows: =300KHz=300000Hz, which is divisible by 40; .

[0064] Regarding ADC sampling frequency The calculation is as follows: , 199807500Hz = 199.8075MHz.

[0065] The step verification is as follows: Equation The system is established so that it can form an equivalent time step of 1 / 40 within each pulse repetition period, meeting the design requirement of EF=40, and can complete the equivalent sampling within 40 pulse periods.

[0066] Preferably, the spread factor EF and pulse repetition frequency mentioned in this embodiment and operating frequency All parameters are set to preset parameters that can be obtained through table lookup. In other words, the corresponding extension factor EF and pulse repetition frequency can be preset in advance based on the product model configured on the host computer. and operating frequency In practical applications, these preset parameters can be obtained by looking up the table according to the product model, so as to speed up system deployment.

[0067] like Figure 2 and Figure 3 As shown, this embodiment also provides a pulse ground-penetrating radar variable radio frequency direct sampling system, which adopts the pulse ground-penetrating radar variable radio frequency direct sampling method as described above, and includes: processing unit U1, ADC chip U2, clock chip U3, D flip-flop U4, pulse shaping circuit U5, transmitting antenna U6 and receiving antenna U7; wherein, processing unit U1, ADC chip U2, clock chip U3 and D flip-flop U4 are the main components of the radio frequency direct sampling subsystem.

[0068] In this embodiment, the processing unit U1 integrates an FPGA unit and an ARM unit. The FPGA unit is used to process high-speed signals, including the generation of radio frequency signals and ADC sampling data processing. The ARM unit is responsible for clock chip management, data management, and external data communication. The ADC chip U2 is an analog-to-digital converter. The clock chip U3 is a programmable clock generator, which transmits the system operating clock (operating frequency). The ADC sampling clock (ADC sampling frequency) is sent to the processing unit U1. The synchronous clock (synchronization frequency) is sent to the ADC chip U2. ) to the D flip-flop U4, wherein the ADC sampling clock Directly used for sampling; while the operating frequency and synchronization frequency The initial phase and frequency are the same, and are used as the system clock and the input clock of the D flip-flop, respectively; the D flip-flop U4 transmits and synchronizes the frequency. Synchronous pulse repetition frequency The pulse shaping circuit U5 sends the shaped first-order Gaussian pulse signal to the transmitting antenna U6, and the receiving antenna U7 is connected to the ADC chip U2.

[0069] Preferably, the processing unit U1 can be a system-on-chip (SoC) architecture, integrating a 28nm FPGA and a dual-core ARM processor, internally using a high-speed AXI bus for data transmission. The FPGA focuses on processing high-speed signals, including RF signal generation and ADC sampling data processing; the ARM is responsible for clock chip management, data management, and auxiliary tasks such as external data communication, thereby reducing development difficulty and cycle time. The processing unit U1 synchronously receives the sampling data (ADC_DATA) and sampling feedback clock (ADC_CLK_OUT) uploaded by the ADC chip U2 via the LVDS interface, and the processing unit U1 sends a pulse trigger signal. After debouncing by the D flip-flop U4, a pulse repetition frequency is generated. . Figure 3 The temperature-compensated crystal oscillator has a main frequency of 25MHz, with frequency error and frequency stability of ±0.5ppm and jitter of 1.3ps.

[0070] In this embodiment, the sampling feedback clock refers to the ADC sampling output clock, i.e., ADC_CLK_OUT. The ADC samples under the drive of the sampling input clock (ADC_CLK). After sampling, the ADC outputs sampled data ADC_DATA and the sampling feedback clock ADC_CLK_OUT. The sampling feedback clock ADC_CLK_OUT is used to control the processing of the sampled data ADC_DATA.

[0071] Clock chip U3 can use I-support 2 This is a C-programmable interface clock generator capable of outputting four independent variable clocks. Under the LVDS interface, the output clock frequency range is 1-700MHz; phase jitter is as low as less than 1ps; and it supports external input clock sources to replace the local crystal oscillator. The ADC chip U2 can employ a 16-bit high-speed analog-to-digital converter, supports a 3-wire SPI control interface, an LVDS data interface, and an LVDS sampling clock with a maximum sampling rate of 200Msps. The clock synchronization signal input / output and pulse synchronization signal input / output interfaces work together to form a cascaded system in a daisy-chain configuration, supporting sampling systems for larger capacity array radars.

[0072] In this embodiment, the system workflow preferably includes the following steps:

[0073] The standby process involves determining the system's state based on commands from the host computer or idle time. This is achieved by controlling the ADC chip U2 to enter sleep mode via the SPI interface and by using I... 2 The C-bus controls the clock chip U3 to go into sleep mode, and the processing unit U1 enters sleep mode and waits for WIFI / LAN to wake it up.

[0074] In the clock signal generation step, during system startup / wake-up, processing unit U1 obtains the extension factor EF and pulse repetition frequency by looking up a table based on the product model configured on the host computer. and operating frequency And calculate other relevant parameters required by clock chip U2 according to the formula, and control clock chip U3 to output the sampling subsystem working clock (frequency Fs) and the D flip-flop working clock (frequency F). D， The sampling clock of the ADC (with the same frequency and phase as Fs) and the sampling clock of the ADC (frequency is There are three clock signals in total, which are sent to the SoC of processing unit U1, D flip-flop U4, and ADC chip U2 respectively. The ADC sampling frequency... Directly used for sampling. Operating frequency. and synchronization frequency The initial phase and frequency are the same, and it is only used for system clock and frequency division;

[0075] In the pulse signal generation step, the FPGA unit utilizes the operating frequency A pulse trigger signal is generated after frequency division. (and (With the same frequency and phase), after debouncing by the D flip-flop U4, a frequency identical to the synchronous frequency is formed. Synchronous pulse trigger signals in phase are denoted as pulse repetition frequency. A first-order Gaussian pulse signal is generated by the pulse shaping circuit U5 and transmitted from the transmitting antenna U6.

[0076] In the ADC sampling step, the clock signal generated by the clock chip U3 directly drives the ADC chip U2. The ADC chip U2 performs direct radio frequency sampling on the signal received by the receiving antenna U7. The sampled data (ADC_DATA) and the sampling feedback clock (ADC_CLK_OUT) are sent to the processing unit U1 through the LVDS data interface.

[0077] The equivalent sampling processing step involves the processing unit U1 receiving sampled data (ADC_DATA) and performing time-domain conversion under the drive of the sampling feedback clock (ADC_CLK_OUT). The received signal is then restored using the pulse-type ground-penetrating radar variable radio frequency direct sampling method. Preferably, the sampling work is further completed after stacking, zero-bias correction, and high-pass and low-pass filtering. These operations can be performed using existing technologies, so they will not be described in detail here.

[0078] The multi-channel expansion step involves synchronously expanding the ADC chip U2 and the pulse repetition frequency. The number of channels, including the number of channels at the receiving end. and the number of channels at the transmitting end and satisfy A single module can support multi-channel ground-penetrating radar acquisition tasks; at this time, the system channel count is [number missing]. .

[0079] In the multi-system cascading step, when forming an array radar, the systems are cascaded in a daisy-chain configuration. At this time, the master node outputs a clock synchronization signal and a pulse synchronization signal. The clock chip U3 of the child node does not use a local crystal oscillator but instead uses the clock synchronization signal output by the master node as its clock source. The processing unit U1 of the child node uses the pulse synchronization signal output by the master node as a reference for concurrent control, thus completing the multi-channel ground-penetrating radar acquisition task required by the array radar. In the multi-system cascading step, only two low-speed signals need to be transmitted (…). Networking can usually be completed at frequencies below 1MHz and clock signals typically between 20-25MHz.

[0080] In summary, this embodiment obtains the expansion factor EF and pulse repetition frequency by looking up a table. and operating frequency After fixing the parameters, first calculate the intermediate parameters. It can be done through the formula Obtain the ADC sampling frequency And through the formula Verify ADC sampling frequency Repetition frequency of the emitted pulse The non-integer multiple relationship between them; finally, after EF pulse repetition cycles, according to the equivalent sampling time step. Align the sampling points to complete waveform reconstruction.

[0081] Therefore, the equivalent sampling time step in this embodiment Based solely on ADC sampling frequency Spread factor EF and pulse repetition frequency The relationship between the three is established in this field. Under relatively fixed conditions, only EF needs to be configured for automatic calculation. That's it. On the one hand, it no longer requires any programmable delay modules, delay lines, or phase scanning circuits, effectively simplifying its hardware structure and reducing the difficulty of hardware design. On the other hand, it does not need to rely on DDS to construct the tiny frequency difference required for equivalent sampling using the conventional frequency difference method, nor does it need to make a trade-off between the pulse repetition frequency and the ADC sampling frequency, which differ by two orders of magnitude. The overall structure is simple and easy to implement, requiring no complex control logic, and the system has high stability.

[0082] Based on this, this embodiment enables the high-speed ADC to operate at full speed, meeting the data acquisition speed of ground-penetrating radar exceeding 100 kilometers per hour; the spread factor EF can be flexibly configured at pulse repetition frequency. With a fixed frequency, only the ADC sampling frequency needs to be dynamically adjusted. It can adapt to the sampling requirements of pulse ground-penetrating radars of different frequencies.

[0083] Furthermore, this embodiment can be cascaded and expanded, supporting mainstream single-channel and multi-channel low-frequency, mid-frequency, and high-frequency pulse ground-penetrating radar sampling without requiring hardware changes. In practical applications, it can be adapted to various different scenarios and the sampling rate can be dynamically adjusted via software, meeting the design and engineering requirements of various pulse ground-penetrating radar RF direct sampling systems, demonstrating strong adaptability.

[0084] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A variable radio frequency direct sampling method for pulse ground-penetrating radar, characterized in that, Includes the following steps: Step S1: Obtain the preset parameters of the pulse ground-penetrating radar, including the operating frequency. Pulse repetition frequency The spread factor EF and the maximum sampling rate of the ADC ; Step S2, based on the pulse repetition frequency , expansion factor EF and ADC maximum sampling rate Through formula Calculate the ADC sampling clock frequency ,in, For intermediate parameters, ; Step S3: Verify the calculation results using the formula. Verify ADC sampling frequency Repetition frequency of the emitted pulse If the non-integer multiple relationship between them is not satisfied, return to step S2 to check the calculation process; if it is satisfied, jump to step S4. It is a positive integer; Step S4: Control the clock chip to output the sampling clock and other auxiliary clocks. Based on the calculation results of steps S1-S3, control the programmable clock chip of the pulse ground penetrating radar to output the working clock of the sampling subsystem, the synchronization clock of the D flip-flop, and the sampling clock of the ADC. Step S5: Generate a transmission pulse, which is obtained by dividing the operating frequency Fs to obtain a pulse trigger signal. After being aligned and debouncing with the synchronous clock signal by a D flip-flop, the pulse repetition frequency is formed. It is then transmitted from the antenna after being formed into a first-order Gaussian pulse signal through a pulse shaping module; Step S6, RF direct sampling: Driven by the sampling clock signal, the ADC performs RF direct sampling. The sampled data goes through EF pulse repetition cycles, and the output data is stepped according to the equivalent sampling time. After aligning the sampling points, the restored waveform is formed, with an equivalent sampling rate. for .

2. The pulse-type ground-penetrating radar variable radio frequency direct sampling method according to claim 1, characterized in that, In step S1, the expansion factor EF satisfies the following constraints: Where N≥10, This indicates the rounding up operation.

3. The pulse-type ground-penetrating radar variable radio frequency direct sampling method according to claim 1, characterized in that, In step S1, the expansion factor EF also satisfies the following constraints. .

4. The pulse-type ground-penetrating radar variable radio frequency direct sampling method according to claim 1, characterized in that, In step S1, the pulse repetition frequency The value should be a multiple of 100 between 100K and 1MHz, and the operating frequency should be... Choose a frequency close to the maximum sampling frequency of the ADC between 50MHz and 200MHz. And satisfy The value.

5. The pulse-type ground-penetrating radar variable radio frequency direct sampling method according to claim 1, characterized in that, The expansion factor EF and the pulse repetition frequency and operating frequency All parameters are set to preset parameters that can be obtained by looking up a table.

6. The pulse-type ground-penetrating radar variable radio frequency direct sampling method according to claim 1, characterized in that, In step S4, the frequency of the sampling subsystem's operating clock is the operating frequency. The operating clock frequency of the D flip-flop is F. D The frequency is F D With operating frequency Same frequency and phase.

7. A pulse-type ground-penetrating radar variable radio frequency direct sampling system, characterized in that, The pulse-type ground-penetrating radar variable radio frequency direct sampling method as described in any one of claims 1 to 6 is adopted, and includes: a processing unit U1, an ADC chip U2, a clock chip U3, a D flip-flop U4, a pulse shaping circuit U5, a transmitting antenna U6, and a receiving antenna U7; The processing unit U1 integrates an FPGA unit and an ARM unit. The FPGA unit is used to process high-speed signals, including the generation of radio frequency signals and ADC sampling data processing. The ARM unit is responsible for clock chip management, data management, and communication with external data. The ADC chip U2 is an analog-to-digital converter. The clock chip U3 is a programmable clock generator. The clock chip U3 sends the system operating clock to the processing unit U1, sends the ADC sampling clock to the ADC chip U2, and sends a synchronization clock to the D flip-flop U4. The ADC sampling clock... Directly used for sampling; while the operating frequency and synchronization frequency The initial phase and frequency are the same, and are used as the system clock and the input clock of the D flip-flop, respectively; the D flip-flop U4 transmits and synchronizes the frequency. Synchronous pulse repetition frequency The pulse shaping circuit U5 sends the shaped first-order Gaussian pulse signal to the transmitting antenna U6, and the receiving antenna U7 is connected to the ADC chip U2.

8. The pulse-type ground-penetrating radar variable radio frequency direct sampling system according to claim 7, characterized in that, The processing unit U1 synchronously receives the sampling data and sampling feedback clock uploaded by the ADC chip U2 via the LVDS interface, and the processing unit U1 sends a pulse trigger signal. After debouncing by the D flip-flop U4, a pulse repetition frequency is generated. .

9. The pulse-type ground-penetrating radar variable radio frequency direct sampling system according to claim 7, characterized in that, The system workflow includes the following steps: Standby step, according to the host computer instruction or idle time judgment, the system enters standby state, through SPI interface control ADC chip U2 hibernate, through I 2 C bus control clock chip U3 hibernate, processing unit U1 enters hibernate waiting WIFI / LAN wake up; In the clock signal generation step, during system startup / wake-up, processing unit U1 obtains the extension factor EF and pulse repetition frequency by looking up a table based on the product model configured on the host computer. and operating frequency The control clock chip U3 generates and sends three clock signals, the frequencies of which are respectively the ADC sampling frequency. Operating frequency and synchronization frequency ; In the pulse signal generation step, the FPGA unit utilizes the operating frequency A pulse trigger signal is generated after frequency division. After debouncing by the D flip-flop U4, the frequency is generated to match the synchronization frequency. Synchronous pulse trigger signals in phase are denoted as pulse repetition frequency. A first-order Gaussian pulse signal is generated by the pulse shaping circuit U5 and transmitted from the transmitting antenna U6. In the ADC sampling step, the clock signal generated by the clock chip U3 directly drives the ADC chip U2. The ADC chip U2 performs direct radio frequency sampling on the signal received by the receiving antenna U7. The sampled data and sampling feedback clock are then sent to the processing unit U1 through the LVDS data interface. The equivalent sampling processing step involves the processing unit U1 receiving sampled data and performing time-domain conversion under the drive of the sampling feedback clock, and then using the pulse-type ground-penetrating radar variable radio frequency direct sampling method to restore the received signal. The multi-channel expansion step involves increasing the number of channels and pulse repetition frequency of the ADC chip U2. The number of channels supports the acquisition tasks of multi-channel ground-penetrating radar; The multi-system cascading steps involve cascading the array radar in a daisy-chain configuration. The master node outputs a clock synchronization signal and a pulse synchronization signal. The clock chip U3 of the sub-node uses the clock synchronization signal output by the master node as its clock source. The processing unit U1 of the sub-node uses the pulse synchronization signal output by the master node as a reference for concurrent control, thereby completing the multi-channel ground-penetrating radar acquisition task required by the array radar.

10. The pulse-type ground-penetrating radar variable radio frequency direct sampling system according to claim 9, characterized in that, In the multi-channel expansion step, the number of expanded channels includes the number of channels at the receiving end. and the number of channels at the transmitting end and satisfy .

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