Steering engine servo control system based on ZYNQ and SRIO high-speed interfaces

Abstract

The invention belongs to the technical field of steering engine servo control, and particularly discloses a steering engine servo control system based on ZYNQ and SRIO high-speed interfaces. The system comprises a ZYNQ main control chip, a single-ended crystal oscillator, a differential crystal oscillator, a sensor, an optical module and an optical cable, the ZYNQ main control chip comprises a PL end and a PS end, and the single-ended crystal oscillator is connected with the PS end and provides a working clock for the ZYNQ main control chip; the differential crystal oscillator and the optical module are connected with the PL end and are used for realizing photoelectric signal conversion; the sensor is connected to the PL end and is used for collecting related physical signals; one end of the optical cable is connected with the optical module and the other end is connected with superior equipment. According to the scheme, the technical problems that a traditional servo mechanism is low in communication rate, limited in single-frame capacity, poor in anti-interference capacity, large in TSN interface protocol stack resource overhead, poor in program transportability and low in development efficiency are solved.

Description

Technical Field

[0001] This invention belongs to the technical field of servo motor control, specifically relating to a servo motor control system based on ZYNQ and SRIO high-speed interfaces. Background Technology

[0002] With the rapid development of chip technology, the integration of chips is becoming increasingly higher. Fudan Microelectronics has developed a PSOC chip based on the FPGA+ARM architecture. This chip integrates the Processing System (PS) and Programmable Logic (PL) into one, and it is now widely used in the aerospace field. Servo mechanisms are important components in the aerospace field, usually used to control the flight attitude of the carrier. The servo mechanism is divided into a controller and a driver. The driver is responsible for amplifying the control signals, while the controller is responsible for processing the control signals and communicating with the upper-level equipment in real time. At this time, the performance of the communication interface is directly related to the operation of the entire carrier.

[0003] Currently, servo controllers often use RS422 / RS485 bus communication. However, due to its low communication speed, high transmission delay, susceptibility to interference, and small single-frame byte capacity, this bus can cause problems such as distortion of the carrier's motion trajectory, susceptibility to environmental interference, and unfavorability for high-dynamic and precise control.

[0004] A Chinese patent describes a servo mechanism control system based on TSN network communication. It mentions that using a TSN interface can solve the aforementioned problems. TSN is an Ethernet-based protocol stack, which has the following main issues:

[0005] 1) For the PL part, the protocol stack IP core consumes a lot of resources, and the compilation, placement and routing, executable file generation, and online debugging are very time-consuming during development;

[0006] 2) For the PS part, the protocol stack needs to use the LWIP protocol to parse Ethernet to obtain user data. The LWIP protocol stack is complex, which makes program coding, debugging and porting difficult, and also consumes CPU processing time.

[0007] 3) The PL side requires the use of a DMA IP core, which must be used with DDR. However, for some programs with small capacity that do not require DDR, additional components will be added, making circuit board routing difficult and increasing manufacturing costs.

[0008] 4) After the DMA transfer is completed, an interrupt will be sent to the PS. The interrupt initialization and interrupt handling mechanism on the PS side will increase the complexity of the program. Summary of the Invention

[0009] The purpose of this invention is to provide a servo control system based on ZYNQ and SRIO high-speed interfaces to solve the technical problems of low communication rate, limited single frame capacity, poor anti-interference ability, large TSN interface protocol stack resource overhead, poor program portability, and low development efficiency of traditional servo mechanisms.

[0010] To achieve the above objectives, the present invention adopts the following technical solution:

[0011] A servo control system based on ZYNQ and SRIO high-speed interfaces includes: a ZYNQ main control chip, a single-ended crystal oscillator, a differential crystal oscillator, a sensor, an optical module, and an optical cable. The ZYNQ main control chip includes a PL terminal and a PS terminal. The single-ended crystal oscillator is connected to the PS terminal to provide the operating clock for the ZYNQ main control chip. The differential crystal oscillator and the optical module are connected to the PL terminal. The sensor is connected to the PL terminal to collect relevant physical signals. One end of the optical cable is connected to the optical module, and the other end is connected to an upstream device.

[0012] Preferably, the system also includes a FLASH memory connected to the PS terminal for storing programs, which are automatically read by the ZYNQ main control chip upon power-up.

[0013] Preferably, the differential crystal oscillator is connected to the differential clock input pin of the LVDS interface at the PL terminal to provide a working clock for the LVDS interface.

[0014] Preferably, the optical module is connected to the LVDS interface at the PL end for photoelectric conversion.

[0015] Preferably, the PL terminal of the ZYNQ main control chip is used to control the sensor to acquire physical signals in real time, and at the same time communicates with the upper-level device through the SRIO communication interface to receive control commands sent by the upper-level device and return response commands.

[0016] Preferably, the PS terminal of the ZYNQ main control chip is used to parse the instructions sent by the upper-level device, execute the control algorithm to output control signals to make the carrier perform corresponding actions, and frame the response instructions.

[0017] Preferably, the PS and PL terminals of the ZYNQ main control chip interact with each other via the AXI bus.

[0018] Preferably, the ZYNQ main control chip receives the SRIO data from the PL terminal and places it into FIFO0, converts it into single-byte data, and then reads it from the PS terminal.

[0019] Preferably, the ZYNQ main control chip writes the single-byte instruction data to be sent from the PS end into FIFO1, converts it into a 64-bit width, and then reads and sends it out by the SRIO ip core on the PL end.

[0020] Preferably, the optical communication rate is 1Gbps.

[0021] In this invention, communication with the upper-level device is achieved through the SRIO interface. The main control chip of the servo mechanism is ZYNQ, and the SRIO IP core is configured in the PL. It is connected to the optical module through the LVDS interface. The optical module communicates with the upper-level device through the optical cable to achieve point-to-point data transmission and reception. The PL end of the main control chip is responsible for receiving and sending SRIO data, while the PS end is responsible for parsing instructions, returning results, and executing algorithms. The PL and PS exchange data through the AXI bus. Therefore, the DMAIP core is not required for the PL part, which can save PL end resources and increase development efficiency. The LWIP protocol stack is not required for the PS part to parse user data, which reduces program complexity. The entire system does not require DDR, thereby reducing development costs. 1Gbps instruction transmission and reception is achieved, which solves the technical problems of low communication rate, limited single frame capacity, poor anti-interference ability, large TSN interface protocol stack resource overhead, poor program portability, and low development efficiency of traditional servo mechanisms. The result is a real-time and stable communication effect. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a servo control system based on ZYNQ and SRIO high-speed interfaces in an embodiment of the present invention.

[0023] Figure 2 This is a schematic diagram of the software architecture of a servo control system based on ZYNQ and SRIO high-speed interfaces in an embodiment of the present invention.

[0024] Figure 3 This is a schematic diagram of the SRIO protocol timing of a servo control system based on ZYNQ and SRIO high-speed interfaces in an embodiment of the present invention.

[0025] Figure 4 This is a schematic diagram of the software execution flow of a servo control system based on ZYNQ and SRIO high-speed interfaces in an embodiment of the present invention.

[0026] Figure 5 This is a schematic diagram of the software execution flow of a servo control system based on ZYNQ and SRIO high-speed interfaces in an embodiment of the present invention. Detailed Implementation

[0027] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and are not to a precise scale, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0028] It should be noted that, in order to clearly illustrate the content of this invention, several embodiments are provided to further explain different implementations of the invention. These embodiments are enumerated rather than exhaustive. Furthermore, for the sake of brevity, content mentioned in the preceding embodiments is often omitted in the following embodiments. Therefore, content not mentioned in the later embodiments can be referred to in the preceding embodiments.

[0029] Example 1

[0030] A servo control system based on ZYNQ and SRIO high-speed interfaces includes: a ZYNQ main control chip, a single-ended crystal oscillator, a differential crystal oscillator, a sensor, an optical module, and an optical cable;

[0031] The ZYNQ main control chip includes a PL terminal and a PS terminal. A single-ended crystal oscillator is connected to the PS terminal to provide the working clock for the ZYNQ main control chip.

[0032] Differential crystal oscillator and optical module are connected to PL terminal; sensor is connected to PL terminal to collect relevant physical signals; one end of optical cable is connected to optical module and the other end is connected to upstream equipment.

[0033] As an optional implementation, the system also includes FLASH, which is connected to the PS terminal and used to store programs. It is automatically read by the ZYNQ main control chip when powered on.

[0034] As an optional implementation, the differential crystal oscillator is connected to the differential clock input pin of the PL-side LVDS interface to provide the operating clock for the LVDS interface.

[0035] As an optional implementation, the optical module is connected to the LVDS interface of the PL terminal to achieve photoelectric conversion.

[0036] As an optional implementation, the PL terminal of the ZYNQ main control chip is used to control the sensor to acquire physical signals in real time. At the same time, it communicates with the upper-level device through the SRIO communication interface, receives control commands sent by the upper-level device, and returns response commands.

[0037] As an optional implementation, the PS terminal of the ZYNQ main control chip is used to parse the instructions sent by the upper-level device, execute the control algorithm to output control signals to make the carrier perform corresponding actions, and frame the response instructions.

[0038] As an optional implementation, the PS and PL terminals of the ZYNQ main control chip interact with each other via the AXI bus.

[0039] As an optional implementation, the ZYNQ main control chip puts the SRIO data received from the PL end into FIFO0, converts it into single-byte data, and reads it from the PS end.

[0040] As an optional implementation, the ZYNQ main control chip writes the single-byte instruction data to be sent from the PS end into FIFO1, converts it into a 64-bit width, and then reads and sends it out by the SRIO ip core on the PL end.

[0041] As an optional implementation, the optical communication rate is 1Gbps.

[0042] Specifically, the aforementioned servo control system based on ZYNQ and SRIO high-speed interfaces is not limited to, for example... Figure 1 As shown, it includes a ZYNQ main control chip, a single-ended clock crystal oscillator, a differential clock crystal oscillator, a sensor, a FLASH, an optical module, and an optical cable.

[0043] The ZYNQ main control chip is divided into two parts: the PL end and the PS end. The single-ended clock crystal oscillator is connected to the PS end to provide the working clock for the ZYNQ chip. The differential clock crystal oscillator is connected to the differential clock input pin of the LVDS interface on the PS end to provide the working clock for the LVDS interface. The sensor is connected to the general I / O port on the PL end to collect relevant physical signals. The optical module is connected to the LVDS interface on the PL end. One end of the optical cable is connected to the optical port of the optical module, and the other end is connected to the upstream device. The optical communication rate is 1Gbps.

[0044] Software architecture is not limited to, for example Figure 2 As shown, the PL (Plug and Switch) terminal is responsible for controlling the sensor to acquire physical signals in real time. It also communicates with the upper-level processing system via the SRIO interface, receiving control commands from the upper-level system and returning response commands. The PS (Power Switch) terminal is responsible for parsing the commands sent by the upper-level processing system and executing the control algorithm, thereby outputting control signals to cause the carrier to perform corresponding actions. It also frames the response commands. The PS and PL interact via the AXI bus. The FLASH memory is used to store the program, which is automatically read by the ZYNQ chip upon power-up.

[0045] SRIO protocol timing is not limited to, for example Figure 3 As shown, since SRIO's timing format transmits 64-bit wide data per clock cycle, and its clock source is inconsistent with that of the AXI bus, cross-clock domain processing is required. Furthermore, to facilitate instruction parsing at the PS end, two asynchronous FIFOs can be used to convert between 64-bit wide data and 8-byte data, as follows: Figure 2 The dashed box at the PL end is shown. For received SRIO data, it is placed into FIFO0, converted into single-byte data, and read by the PS end. For single-byte instruction data to be sent by the PS end, the PS end first writes it into FIFO1, converts it into a 64-bit width, and then reads and sends it by the SRIO IP core.

[0046] The software execution flow for writing FIFO0 is not limited to, for example Figure 4As shown, the SRIO protocol uses the valid signal to determine whether data has been received. When the valid signal goes high, it means that data has been received and 64 bits of data can be written into the FIFO. At the same time, it checks whether the last signal is high. When the last signal is high, it means that the last 64 bits of data in a frame has been received. Once the SRIO data frame is written to the FIFO, the write operation ends and the system starts waiting for the valid signal to go high again.

[0047] The software execution flow for reading FIFO1 is not limited to, for example... Figure 5 As shown, after the program starts, it first checks if the FIFO is not empty and if the ready signal is high. If the conditions are met, it initiates a read from the FIFO. The data width read is 64 bits. Simultaneously, the valid signal is pulled high, and it is checked whether the read 64 bits are the end of a frame. If the conditions are met, the last signal is pulled high for one clock cycle and then pulled low, while the valid signal is pulled low. At this time, a frame of data is automatically sent by the SRIO IP core. If the conditions are not met, the read from the FIFO continues. After a frame of data is read, the entire process restarts.

[0048] In this embodiment, for the PL section, the SRIO IP core occupies less resources than the TSN, reducing the time spent on compilation, placement and routing, executable file generation, and online debugging. For the PS section, there is no need to use a complex LWIP protocol stack to parse user data; the PS end can directly read user data from the PL end, reducing the complexity of the PS end program and facilitating program coding, debugging, and porting, while reducing CPU processing time. The control system does not require DDR, reducing hardware development and manufacturing costs. The entire SRIO transmission process has no interrupt mechanism, further simplifying the program. Servo controllers often adopt a DSP+FPGA architecture design; this design can be implemented using only one PSOC, achieving high integration and reducing hardware development costs.

Claims

1. A rudder servo control system based on ZYNQ and SRIO high-speed interface, characterized in that, include: ZYNQ main control chip, single-ended crystal oscillator, differential crystal oscillator, sensor, optical module, optical cable; The ZYNQ main control chip includes a PL terminal and a PS terminal. A single-ended crystal oscillator is connected to the PS terminal to provide the working clock for the ZYNQ main control chip. Differential crystal oscillator and optical module are connected to the PL terminal; sensor is connected to the PL terminal to collect relevant physical signals; one end of optical cable is connected to the optical module and the other end is connected to the upstream device.

2. The servo control system based on ZYNQ and SRIO high-speed interfaces as described in claim 1, characterized in that, The system also includes FLASH, which is connected to the PS terminal and used to store programs. It is automatically read by the ZYNQ main control chip when powered on.

3. In the servo control system based on ZYNQ and SRIO high-speed interfaces as described in claim 1, the differential crystal oscillator is connected to the differential clock input pin of the LVDS interface at the PL terminal to provide a working clock for the LVDS interface.

4. In the servo control system based on ZYNQ and SRIO high-speed interfaces as described in claim 1, the optical module is connected to the LVDS interface of the PL terminal to realize photoelectric conversion.

5. The servo control system based on ZYNQ and SRIO high-speed interface as described in claim 1, wherein the PL terminal of the ZYNQ main control chip is used to control the sensor to collect physical signals in real time, and at the same time communicates with the upper-level device through the SRIO communication interface to receive control commands sent by the upper-level device and return response commands.

6. The servo control system based on ZYNQ and SRIO high-speed interfaces as described in claim 1, wherein the PS terminal of the ZYNQ main control chip is used to parse the instructions sent by the upper-level device, execute the control algorithm to output control signals to make the carrier perform corresponding actions, and simultaneously frame the response instructions.

7. The servo control system based on ZYNQ and SRIO high-speed interface as described in claim 1, wherein the PS and PL terminals of the ZYNQ main control chip interact with each other via an AXI bus.

8. The servo control system based on ZYNQ and SRIO high-speed interface as described in claim 7, wherein the ZYNQ main control chip puts the SRIO data received at the PL end into FIFO0, converts it into single-byte data, and reads it from the PS end.

9. The servo control system based on ZYNQ and SRIO high-speed interface as described in claim 8, wherein the ZYNQ main control chip writes the single-byte instruction data to be sent from the PS end into FIFO1, converts it into a 64-bit width, and then reads and sends it out by the SRIO IP core at the PL end.

10. The servo control system based on ZYNQ and SRIO high-speed interfaces as described in claim 1, wherein the optical communication rate is 1Gbps.

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