Upgrading method and system of interlocking system

Abstract

The invention discloses an upgrading method and system of an interlocking system, and relates to the technical field of system upgrading, and the method comprises the steps: triggering an upgrading stage of an existing interlocking system based on a night upgrading node; and a night upgrading event of the new system interlocking control equipment is triggered in the control box, so that the undisturbed design of the night upgrading event is realized. A plurality of upgrading items are determined based on the identification of the night upgrading event of the new system interlocking control equipment, and the overall upgrading progress of the new system interlocking control equipment is determined according to the item content of each upgrading item, the corresponding item upgrading progress and the night remaining time, so that the accuracy of the overall upgrading progress of the new system interlocking control equipment is improved. And in the next night control node, an accelerated upgrading mode of the new system interlocking control equipment is determined according to the remaining upgrading content and the overall upgrading progress of the new system interlocking control equipment, and it is ensured that upgrading of the new system interlocking control equipment is fully completed in the next night control node.

Description

Technical Field

[0001] This invention relates to the technical field of system upgrades, and more particularly to an upgrade method and system for an interlocking system. Background Technology

[0002] Currently, with the increasing operational years of urban rail transit lines, many signaling devices are nearing their design lifespan, and spare parts are also in short supply. This leads to unstable operation of the signaling system and a continuously rising failure rate, affecting not only citizens' daily travel but also posing certain safety hazards. Therefore, many lines are planning or have already upgraded their existing signaling systems. A crucial part of the entire signaling system upgrade process is the updating of the interlocking system, such as upgrading the model of the existing interlocking system or replacing it with an interlocking system from a different manufacturer. This involves upgrading the interlocking system, which is sometimes carried out during daytime hours, affecting the operation of urban rail transit lines. It also neglects daytime control nodes and nighttime upgrade nodes, affecting the non-disruptive design of nighttime upgrade events and failing to guarantee the operation of daytime control nodes. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides an upgrade method and system for an interlocking system.

[0004] This invention provides an upgrade method for an interlocking system, comprising: Collect the current time, and determine the daytime control node and nighttime upgrade node based on the current time, the existing interlocking system, and the corresponding upgrade information; trigger the upgrade phase of the existing interlocking system based on the nighttime upgrade node. During this upgrade phase, the existing interlocking system, trackside equipment, and new system interlocking control equipment are connected to the same control box, and the nighttime upgrade event of the new system interlocking control equipment is triggered in the control box, while the existing interlocking system is in a stopped state. Based on the identification of nighttime upgrade events of the new system interlocking control equipment, multiple upgrade projects are determined. The overall upgrade progress of the new system interlocking control equipment is determined according to the project content, the corresponding project upgrade progress and the remaining time at night, and the overall upgrade progress is dynamically controlled. During the daytime control node, the upgrade process of the new system interlocking control equipment is interrupted, and the system is switched to the existing interlocking system. At this time, the existing interlocking system switches from the stopped state to the working state. In the next night control node, mark the remaining upgrade content of the new system interlocking control equipment. Based on the remaining upgrade content and the overall upgrade progress of the new system interlocking control equipment, determine the accelerated upgrade mode of the new system interlocking control equipment to ensure that the upgrade of the new system interlocking control equipment is fully completed in the next night control node, and the new system interlocking control equipment will work in the next day control node.

[0005] This invention provides an upgrade system for an interlocking system, which is applied to the aforementioned upgrade method for the interlocking system.

[0006] Compared with the prior art, the beneficial effects of the present invention are: (1) Collect the current time, and determine the daytime control node and nighttime upgrade node based on the current time, the existing interlocking system and the corresponding upgrade information; trigger the upgrade phase of the existing interlocking system based on the nighttime upgrade node; in the upgrade phase, connect the existing interlocking system, trackside equipment and the new system interlocking control equipment to the same control box, and trigger the nighttime upgrade event of the new system interlocking control equipment in the control box. The existing interlocking system is in a stopped state. Further control is applied to the nighttime upgrade node, and the nighttime event of the nighttime upgrade node is fully utilized to achieve the non-disruptive design of the nighttime upgrade event.

[0007] (2) Based on the identification of nighttime upgrade events of the new system interlocking control equipment, multiple upgrade projects are determined. The overall upgrade progress of the new system interlocking control equipment is determined according to the project content, corresponding project upgrade progress and remaining nighttime time of each upgrade project. The overall upgrade progress is dynamically controlled. Multiple upgrade projects are introduced, realizing the overall consideration of the project content, corresponding project upgrade progress and remaining nighttime time of each upgrade project, which improves the accuracy of the overall upgrade progress of the new system interlocking control equipment.

[0008] (3) In the daytime control node, the upgrade process of the new system interlocking control equipment is interrupted and switched to the existing interlocking system. At this time, the existing interlocking system switches from the stopped state to the working state. In the next nighttime control node, the remaining upgrade content of the new system interlocking control equipment is marked. Based on the remaining upgrade content and the overall upgrade progress of the new system interlocking control equipment, the accelerated upgrade mode of the new system interlocking control equipment is determined, which ensures the operation of the daytime control node and realizes the switching between the nighttime control node, the daytime control node and the next nighttime control node. This ensures that the upgrade of the new system interlocking control equipment is fully completed in the next nighttime control node and that the new system interlocking control equipment works in the next daytime control node. Attached Figure Description

[0009] Figure 1This is a flowchart illustrating the upgrade method of the interlocking system in an embodiment of the present invention; Figure 2 This is a flowchart illustrating step S11 in the interlocking system upgrade method of this embodiment of the invention. Figure 3 This is a flowchart illustrating step S12 in the interlocking system upgrade method of the present invention. Figure 4 This is a flowchart illustrating step S13 in the interlocking system upgrade method of the present invention. Figure 5 This is a flowchart illustrating step S14 in the interlocking system upgrade method of this embodiment of the invention. Figure 6 This is a flowchart illustrating step S15 in the interlocking system upgrade method of this embodiment of the invention. Figure 7 This is a schematic diagram of the structural composition of the upgrade system of the interlocking system in an embodiment of the present invention. Detailed Implementation

[0010] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0011] Please see Figures 1 to 7 An upgrade method for an interlocking system, applied to system upgrade scenarios; the upgrade method for the interlocking system includes: Step S11: Collect the current time, and determine the daytime control node and nighttime upgrade node based on the current time, the existing interlocking system, and the corresponding upgrade information; trigger the upgrade phase of the existing interlocking system based on the nighttime upgrade node; Step S12: During this upgrade phase, the existing interlocking system, trackside equipment, and new system interlocking control equipment are connected to the same control box, and the nighttime upgrade event of the new system interlocking control equipment is triggered in the control box. The existing interlocking system is in a stopped state. Step S13: Based on the identification of nighttime upgrade events of the new system interlocking control equipment, identify multiple upgrade projects, determine the overall upgrade progress of the new system interlocking control equipment according to the project content, corresponding project upgrade progress and remaining nighttime time of each upgrade project, and dynamically control the overall upgrade progress; Step S14: In the daytime control node, interrupt the upgrade process of the new system interlocking control equipment and switch to the existing interlocking system. At this time, the existing interlocking system switches from the stopped state to the working state. Step S15: In the next night control node, mark the remaining upgrade content of the new system interlocking control equipment. Based on the remaining upgrade content and the overall upgrade progress of the new system interlocking control equipment, determine the accelerated upgrade mode of the new system interlocking control equipment to ensure that the upgrade of the new system interlocking control equipment is fully completed in the next night control node, and the new system interlocking control equipment will work in the next day control node.

[0012] refer to Figure 2 In step S11, the specific steps are as follows: S111: Control the time and mark the current time. At the same time, collect the normal working time of the existing interlocking system and the corresponding upgrade signal. Based on the analysis of the upgrade signal, determine the corresponding upgrade information. Determine the daytime control node and the nighttime upgrade node according to the current time, the normal working time of the existing interlocking system and the corresponding upgrade information. The daytime control node and the nighttime upgrade node are in different time periods. S112: In this nighttime upgrade node, based on the identification of the nighttime upgrade node, multiple upgrade dimensions of the existing interlocking system are determined, and the upgrade stage of the existing interlocking system is determined based on each upgrade dimension, the corresponding upgrade content, and the time range of the nighttime upgrade node.

[0013] In the embodiments of this application, time is controlled and the current time is marked. At the same time, the normal working time of the existing interlocking system and the corresponding upgrade signal are collected. The corresponding upgrade information is determined based on the parsing of the upgrade signal. The daytime control node and the nighttime upgrade node are determined according to the current time, the normal working time of the existing interlocking system and the corresponding upgrade information. The daytime control node and the nighttime upgrade node are in different time periods, which takes into account the overall consideration of the current time, the normal working time of the existing interlocking system and the corresponding upgrade information, and ensures the accuracy of the daytime control node and the nighttime upgrade node.

[0014] At this point, time is controlled and the current time is marked. The system relies on a system-level clock server or NTP synchronization mechanism to ensure the uniformity and accuracy of the time across the entire system. The current absolute time is recorded as the reference time point by periodically scanning the system clock. This process is usually completed in the underlying kernel mode of the operating system or in the RTOS to prevent time drift.

[0015] The system collects the normal working hours and corresponding upgrade signals of the existing interlocking system. It obtains the time window in which the system is in the "service / open" state by reading the operation timetable data or the operation status word in the SCAD interlocking system. At the same time, it receives upgrade signals containing specific protocol headers and instruction codes through HMI, maintenance terminal or remote dispatch center and performs source legality verification.

[0016] The system determines the corresponding upgrade information based on the analysis of upgrade signals, performs frame parsing according to predefined communication protocols, extracts key parameters such as target version number, subsystem ID, estimated downtime and upgrade type, maps them into internally executable upgrade task objects and generates an "upgrade information set" containing dependencies and security policies.

[0017] Based on the current time, normal working hours, and upgrade information, the system determines the daytime control node and the nighttime upgrade node. The system compares the current time with the normal working hours to exclude the necessary operating periods. Combining the upgrade time required, it searches for continuous time slices in the non-operating periods to calculate a starting time point as the "nighttime upgrade node" and marks the adjacent operating period as the "daytime control node". Strict mutual exclusion lock logic is set between the two to ensure the uniqueness of the state transition.

[0018] Specifically, the main control unit of the interlocking system locks the current time through a dedicated time synchronization server. The system kernel captures the current absolute time as 23:55:00 on November 15, 2025 at the moment it is ready to start the upgrade process, and marks this as the base timestamp T0 for this upgrade operation.

[0019] The system reads the configuration from the operation database and confirms that the normal operating hours are from 05:00:00 to 23:30:00 daily. During this period, any operation that affects signal output is prohibited. At the same time, at 23:50, the dispatch center sends an upgrade command message containing the instruction code "CMD_UPG_START" and the target version "V2.0" through the maintenance terminal. The system communication module successfully collects and verifies the signal.

[0020] The upgrade management module unpacks the message and determines that the upgrade involves updating the core interlocking logic and needs to be completed in a static environment. Based on this, the generated upgrade plan shows that the entire task requires at least 4 hours of continuous execution time. The system, based on the current time (23:55:00), which is close to the end of the day's operations (23:30:00), determines that it is about to enter a maintenance window. Calculations show that there is a 5-hour and 30-minute continuous non-operational time window from 23:30:00 to 05:00:00 the next day, which meets the 4-hour requirement for the upgrade. Therefore, the system sets 00:00:00 the next day as the "nighttime upgrade node" to initiate the upgrade reverse process, and sets the transition period from 23:30:00 on the same day to 00:00:00 the next day and 05:00:00 the next day as the boundaries of the "daytime control node," ensuring that version V1.5 remains operational before 00:00:00 and that version V2.0 deployment and recovery are completed before 05:00:00 the next day.

[0021] Furthermore, in this nighttime upgrade node, multiple upgrade dimensions of the existing interlocking system are determined based on the identification of the nighttime upgrade node. The upgrade stage of the existing interlocking system is determined based on each upgrade dimension, the corresponding upgrade content, and the time range of the nighttime upgrade node. This approach takes into account the overall consideration of each upgrade dimension, the corresponding upgrade content, and the time range of the nighttime upgrade node, ensuring the accuracy of the upgrade stage of the existing interlocking system.

[0022] At this point, based on the time determined in step S111, it is determined whether the current time is a nighttime upgrade node. Once the time is confirmed to have arrived, the upgrade process of the interlocking system is immediately triggered. The specific upgrade direction is identified based on the functions and characteristics of the interlocking system, covering dimensions such as software version upgrades to fix vulnerabilities and add new functions, hardware configuration upgrades to improve computing power and reliability, data configuration upgrades to add new line or equipment information, and interface protocol upgrades to ensure compatibility.

[0023] The system further determines the specific upgrade content and timeframe based on each upgrade dimension, clarifying details such as software changes from version X to version Y, hardware changes including processor and memory replacement, and database updates to add site information. It also estimates the time required for each upgrade task based on its complexity. Simultaneously, the entire process is divided into multiple stages according to the order of the upgrade content and the estimated timeframe. The system must strictly execute the upgrade tasks of each stage in the defined order and monitor the upgrade progress and status throughout the process to ensure the upgrade is completed smoothly within the predetermined time.

[0024] Specifically, when the time reaches 22:00, the system identifies and confirms that it is currently in the preset nighttime upgrade node, and then triggers the interlocking system upgrade process. Based on actual needs, the system identifies the upgrade dimensions involved in this operation as two aspects: software version and hardware configuration.

[0025] The system specified that the software upgrade would be from version 1.0 to version 2.0, and the hardware upgrade would involve replacing the processor with a more powerful one and increasing the memory. Based on the workload, the software upgrade was estimated to take 2 hours, and the hardware upgrade was estimated to take 1 hour. The system divided the upgrade process into two consecutive phases: the first phase, from 22:00 to 00:00, focused on completing the software upgrade from version 1.0 to 2.0; the second phase, from 00:00 to 01:00, involved replacing the processor and memory. The system strictly followed this sequence, monitoring progress in real time to ensure all upgrade work was completed before the 06:00 operational recovery time the following day.

[0026] refer to Figure 3 In step S12, the specific steps are as follows: S121: Real-time detection of this upgrade phase and marking of the new system interlocking control equipment. At this time, the existing interlocking system and the new system interlocking control equipment share the same trackside equipment and are controlled by the same control box. S122: The control box sets the corresponding control program and controls the mutual exclusion relationship between the existing interlocking system and the new system interlocking control equipment; at the same time, in the night control node, the control box triggers a night upgrade signal, and along the night upgrade signal, the new system interlocking control equipment triggers a night upgrade event, the new system interlocking control equipment performs the corresponding night upgrade, while the existing interlocking system is in a stopped state.

[0027] In the embodiments of this application, the upgrade phase is detected in real time, and the new system interlocking control equipment is marked. At this time, the existing interlocking system and the new system interlocking control equipment share the same trackside equipment and are controlled by the same control box, thus introducing the control of the same control box.

[0028] At this time, relying on the periodic scanning mechanism inside the PLC or the high-precision timed polling task of the host computer system, the CPU reads the value of the system clock register in each scanning cycle and compares it with the pre-stored "upgrade start timestamp". At the same time, it judges whether the operation mode flag has been flipped to "upgrade mode" by monitoring the status word in the digital input channel or communication protocol message, ensuring that the switch from "operation status" to "upgrade status" is based on precise time synchronization and logical judgment.

[0029] Once the system is identified as entering the upgrade phase, the control logic immediately assigns a logic activation state to the "new system interlock control device" in the PLC's internal data storage area or the host computer database. This is usually achieved by setting specific internal relays or flag bits. At the same time, a communication handshake signal is sent to the new system host to send a "master control enable" instruction and reset the corresponding flag bits of the existing interlock system, thus clarifying the signal routing at the software level.

[0030] All control cables of the existing trackside equipment are converged and connected to the common terminal module of the PLC switching box. The PLC switching box serves as the only physical intermediary hub. Its output side is connected to the output interfaces of the existing interlocking system and the new system interlocking control equipment through independent switch modules. This topology means that there is only one set of equipment at the physical execution level, and the driving source of this equipment is completely controlled by the matrix logic inside the PLC switching box at any time, realizing single-point control at the physical layer.

[0031] Specifically, the PLC switching box of the interlocking system runs a high-precision watchdog timer program. When the system time reaches the critical interval of 23:59:58 to 00:00:00, the PLC scans and detects that the preset "night upgrade window" flag has been activated. It captures the time jump through the internal high-speed counter and updates the system status word to "Upgrade_Active" in the next millisecond-level scan cycle.

[0032] After confirming the status update, the PLC switch box internal logic sets the address word MW100, which represents the new system status bit, to "1", indicating that the new system interlocking machine B has been marked as the online master controller. At the same time, it clears the address word MW101, which represents the existing system status bit, to zero. The PLC then sends a handshake message (such as 05 FF 00) to the new system interlocking machine B through the RS-485 serial communication bus, informing it that it has obtained control authorization.

[0033] The drive cables for all 15 sets of turnouts and the lighting cables for all 30 signal lights within Station A are connected to the common input terminal of the PLC switching box. The output terminals of the existing interlocking machine A and the new system interlocking machine B are connected to the input modules A and B of the PLC switching box, respectively. The relay contact matrix inside the PLC switching box determines whether to close "common terminal - input module A" or "common terminal - input module B" based on the marking status of MW100. At this time, although all trackside equipment is physically connected to two sets of main units, the actual electrical path is completely controlled by the single PLC switching box, ensuring physical uniqueness.

[0034] Furthermore, the control box is configured with corresponding control programs and manages the mutual exclusion relationship between the existing interlocking system and the new system interlocking control equipment. Simultaneously, in the night control node, a night upgrade signal is triggered based on the control box, and a night upgrade event of the new system interlocking control equipment is triggered along with the night upgrade signal. The new system interlocking control equipment performs the corresponding night upgrade, while the existing interlocking system is in a stopped state. This introduces the existing interlocking system being in a stopped state. At the same time, the night upgrade node is further controlled and its night events are fully utilized, achieving a non-disruptive design for the night upgrade event.

[0035] At this point, a dedicated control mode is written into the PLC storage medium based on the IEC 61131-3 standard, defining a finite state machine including "operation mode", "test / upgrade mode" and "double-break mode", and mapping specific digital output points to relay drive lines.

[0036] Control the mutual exclusion relationship between the existing interlocking system and the interlocking control equipment of the new system, build a hardware or software interlocking mechanism within the PLC program, and ensure that the control loop of the "new system" is forcibly reset when the control loop of the "new system" is set through Boolean logic operations. This covers both the bus level and the contact level to ensure that it is impossible for the relay contacts leading to the trackside equipment to be closed simultaneously in any clock cycle.

[0037] Based on the control box triggering the night upgrade signal, when the real-time clock enters the preset time window, the PLC actively sends a discrete signal transition or broadcast communication message as a system-wide synchronization clock notification to start the maintenance window. Subsequently, the night upgrade event of the new system's interlocking control equipment is triggered along with this night upgrade signal. After receiving the signal, the new system activates the "upgrade event" in the internal processor interrupt service routine, executes subroutines such as initialization test mode and loading configuration parameters, and enters the ready state.

[0038] The new system's interlocking control equipment undergoes a corresponding nighttime upgrade, while the existing interlocking system remains in a stopped state. The PLC connects the new system to the trackside equipment, enabling it to perform upgrade testing tasks. Simultaneously, through mutual exclusion logic, the physical circuit from the existing system to the trackside equipment is disconnected, physically blocking the control commands it issues, thereby maintaining the logical isolation of the existing system.

[0039] Specifically, the PLC switching box of the interlocking system is pre-installed with a control program written on the Schneider Unity Pro platform. M0 is defined as the "new system enable" bit, and M1 as the "old system enable" bit, and the program logic is firmware-locked. During the mutual exclusion control phase, the PLC executes instructions within its logic scan cycle. Once M0 is activated, the new system relay Q0.0 is set, and M1 and the old system relay Q0.1 are reset. The output module of the old system is forcibly disconnected via hardware circuitry, ensuring that only one system has physical control at any given time.

[0040] When the clock reaches 00:00:00, the digital output terminal Q2.0 of the PLC switching box outputs a high level. This signal, acting as a "nighttime upgrade trigger source," is broadcast to all relevant subsystems via the line connected to the system alarm bus. During the upgrade event trigger phase, the new system interlocking machine B detects that the "nighttime upgrade trigger source" signal on the bus is valid. Its operating system kernel triggers a "system upgrade interrupt," then loads test case data, initializes the communication stack, and sends an "online" status frame to the PLC switching box to prepare to take over control.

[0041] After receiving the readiness confirmation of the new system, the PLC switching box drives the internal relay to switch the control cable of turnout No. 1 from the old system port to the new system port. The new system interlocking machine B issues a fixed operation command to drive the switch machine to rotate through the new circuit to complete the test. Although the existing interlocking machine A continues to run, its output signal to the PLC switching box is isolated by the internal circuit breaker and is in a "logic online, physical bypass" stop state, which does not interfere with the nighttime upgrade test of the new system at all.

[0042] refer to Figure 4 In step S13, the specific steps are as follows: S131: Dynamically identify nighttime upgrade events of the interlocking control equipment of the new system, determine the corresponding project markers during the identification process, and determine the corresponding upgrade projects based on the tracing of each project marker, so as to collect multiple upgrade projects; S132: In multiple upgrade projects, the corresponding project content is determined based on the detection of each upgrade project, and the project upgrade progress of each upgrade project is dynamically marked. The first upgrade progress is determined based on the project content of each upgrade project and the remaining time at night. S133: Determine the second-level upgrade progress based on the project's progress and the remaining time at night for each upgrade project. Determine the overall upgrade progress of the new system's interlocking control equipment based on the first-level and second-level upgrade progress, so as to dynamically control the overall upgrade progress.

[0043] In the embodiments of this application, nighttime upgrade events of the interlocking control equipment of the new system are dynamically identified, and corresponding project tags are determined during the identification process. Based on the tracing of each project tag, the corresponding upgrade project is determined to collect multiple upgrade projects, which takes into account the overall consideration of tracing each project tag and ensures the accuracy of the corresponding upgrade project.

[0044] At this time, the nighttime upgrade events of the new system interlocking control equipment are dynamically identified. This relies on the system's event bus or interrupt listening mechanism. The background daemon polls the communication port with high priority. When a specific status word change or protocol header is detected, it is determined that the upgrade event has been triggered, and the event attributes such as software patch loading or firmware update are parsed in real time.

[0045] During the identification process, the corresponding project tag is determined. According to the predefined rule set, a unique identifier consisting of a timestamp, source device ID and task type code is assigned to each event element. The tag is created using a hash algorithm or UUID generation mechanism and written to the memory cache or real-time database as a data index for subsequent reference.

[0046] Based on the tracing of each project's tags, corresponding upgrade projects are identified. The generated tags are then used for reverse tracing queries in the engineering knowledge base or task mapping table. By using associated fields, abstract event tags are precisely mapped to specific engineering execution units, ensuring the correspondence between underlying signal events and upper-layer business logic tasks. Simultaneously, multiple upgrade projects are collected, and the traced specific engineering tasks are aggregated into an ordered upgrade task queue. Multiple independent events scattered throughout the communication stream are integrated into a set, and preliminary sorting is performed based on the logical dependencies between tasks, generating an upgrade project list that includes task weights, estimated time consumption, and resource requirements.

[0047] Specifically, the host computer monitoring software of the interlocking system detects that the new system interlocking machine B sends an "online upgrade" handshake message containing the signature code 0x5A via TCP / IP. The system kernel captures the data stream and parses it to find that the load contains two types of data packets: "application software image" and "station configuration data", thereby identifying the "nighttime upgrade event" that is taking place.

[0048] The host computer software instantly generates two project markers, TSK_A_SW_00:05:01 (representing a software upgrade task) and TSK_A_DB_00:05:02 (representing a database update task), based on the message characteristics, and writes them to the shared memory area, attaching a timestamp attribute to ensure uniqueness and traceability.

[0049] The system uses tags A and B to query the locally maintained "Interlocking System Upgrade Dictionary," associating TSK_A_SW with the project task of "Upgrading Interlocking Application Software from v1.5 to v2.0," and TSK_A_DB with the project task of "Signal and Turnout Control Table Parameter Synchronization," thus transforming the underlying communication signals into specific project tasks. Simultaneously, the system collects these two tasks into the "Current Upgrade Queue." Based on dependencies, it determines that the "Database Update" task depends on the completion of the "Software Upgrade" task. Therefore, the upgrade project list is organized into high-priority interlocking application software upgrades and low-priority signal and turnout control table parameter synchronization, and this queue is passed to the progress calculation module.

[0050] Furthermore, in multiple upgrade projects, the corresponding project content is determined based on the detection of each upgrade project, and the upgrade progress of each upgrade project is dynamically marked. The first-level upgrade progress is determined based on the project content of each upgrade project and the remaining time at night, which takes into account the overall consideration of the project content of each upgrade project and the remaining time at night, ensuring the accuracy of the first-level upgrade progress.

[0051] At this point, the technical attributes are determined by reading the metadata in the header of the project file, and integrity checks are performed using CRC32 or MD5 algorithms to ensure error-free data transmission. The version number and hardware dependency description are analyzed for compatibility checks to match the current device architecture, and the resource list inside the project is parsed to extract the specific project content.

[0052] The system dynamically marks the progress of each upgrade project, establishes a real-time status monitoring mechanism to continuously track the execution status, maintains a status array mapping enumeration type status in system memory, calculates and updates the percentage progress marker in real time by monitoring the transmission confirmation packets of the underlying protocol or the write pointer of the storage medium, and uses interrupt service routines or callback functions to ensure that the display delay is minimized.

[0053] The first-stage upgrade progress is determined based on the project content of each upgrade project and the remaining time at night. This is a macro-level evaluation indicator based on time resource constraints. The remaining estimated time for each project is calculated based on the amount of data extracted and the historical rate benchmark. The time difference between the current time and the "daytime control node" is calculated by reading the hardware clock. The total estimated time of all unfinished projects is compared with the remaining time at night. If the total estimated time is within the safety factor range, the progress is judged as "normal" or "surplus". If it exceeds the limit, it is judged as "lagging" or "critical". This serves as an important basis for the system to decide whether to enter the acceleration mode.

[0054] Specifically, the system checks the collected upgrade items and confirms that the file size of item P1 (interlocking software) is 500MB and the CRC check passes. The target is Flash sector 0 of the new system interlocking machine B. The system also confirms that item P2 (station data) contains the configuration parameters of 20 sets of turnouts and 30 signal lights and that the version number V2.0 compatibility test passes. Based on this, the system confirms that the item content is clear and the hardware environment meets the requirements.

[0055] The system HMI displays a progress bar in real time. When it detects that P1 is in the "INSTALLING" stage and has written 300MB / 500MB to Flash, the system dynamically updates the progress mark of P1 to 60%. Meanwhile, when it detects that P2 is in a queue waiting state, its progress mark remains at 0%. The background process refreshes these marks every 500 milliseconds to reflect the latest execution status.

[0056] Based on the current write rate, the system determines that P1 will take another 1 hour to complete and P2 is expected to take 1.5 hours. The total remaining estimated time is calculated to be 2.5 hours. This is compared with the remaining 3 hours of nighttime time between the current time 02:00 and the operation recovery time 05:00. Since 2.5 hours is less than 3 hours, the system determines that the current time resources are sufficient. The first-level progress indicator is calculated to be approximately 36% with a time margin of 0.5 hours. Finally, "First-level progress status: normal" is generated, allowing the current rate to continue execution and reserving 0.5 hours for the final system back-end verification.

[0057] Therefore, the second-stage upgrade schedule is determined based on the project progress of each upgrade item and the remaining time at night. The overall upgrade schedule of the new system's interlocking control equipment is then determined based on the first-stage and second-stage upgrade schedules to dynamically control the overall upgrade schedule. This approach takes into account both the first-stage and second-stage upgrade schedules, ensuring the accuracy of the overall upgrade schedule for the new system's interlocking control equipment. Furthermore, by introducing multiple upgrade items, the overall consideration of the project content, corresponding upgrade schedule, and remaining time at night for each upgrade item is achieved, further improving the accuracy of the overall upgrade schedule for the new system's interlocking control equipment.

[0058] At this point, the system calculates the remaining time required to complete each project based on the current processing rate of different project types and the remaining workload of each project. It compares the maximum remaining time of each project with the remaining time at night and monitors the slope of the progress curve. If the progress slope shows a downward trend or the remaining time window is insufficient to cover the longest task, the second-level progress is determined to be in a "lagging high load" state. Otherwise, it is in a "low load controllable" state, in order to capture the risk of inevitably timeout at the current speed.

[0059] The overall upgrade progress of the interlocking control equipment of the new system is determined based on the progress of the first and second upgrades. The two-dimensional indicators are synthesized into unified decision parameters through a multi-sensor data fusion algorithm. Different weight coefficients are assigned to the two and the quantified values ​​are input into the decision matrix. The system outputs a comprehensive state value covering "advanced", "normal", "critical" to "blocked", which serves as the sole input source for the system's global scheduling algorithm.

[0060] The overall upgrade progress is dynamically monitored, and closed-loop feedback control is executed based on the overall progress status. When the overall progress value falls to the preset alarm threshold, a red warning is triggered on the HMI interface and an alarm message is pushed. If the progress is judged to be "lagging", an adaptive adjustment strategy is automatically triggered, such as suspending low-priority tasks, increasing I / O scheduling priority, or switching to parallel multi-threaded download mode, in order to forcibly increase the processing speed and force the progress curve to return to the normal trajectory.

[0061] Specifically, the system analysis indicates that the current state is 3:00 AM, with only 2 hours remaining before the 5:00 AM operation resumption. Project P1 (interlocking software) is 85% complete and is expected to take another 30 minutes. Project P2 (ATS communication test) is 10% complete, and due to the simulated train operation taking 50% longer than expected for a single test cycle, the system detects that the progress of P2 is increasing at a relatively flat rate. At the current rate, it is expected to take 2.5 hours to complete. Therefore, the system determines that the estimated time for P2 is greater than the remaining time at night, and thus the progress of the second upgrade is classified as "high risk / time overflow".

[0062] The system conducted a fusion analysis, classifying the first-level progress as "critical" and the second-level progress as "lagging". Through weighted algorithm calculation, it was found that the "lagging" factor lowered the overall score, and the overall upgrade progress of the new system's interlocking control equipment was ultimately rated as "severely lagging (red alert)".

[0063] Based on the "severe delay" status, the host computer automatically popped up a "progress anomaly" dialog box and activated the "accelerated upgrade mode". The system downgraded the P2 simulation scenario from "full-function test" to "core link handshake test" to skip non-critical redundant test cases. At the same time, the PLC switching box auxiliary system temporarily adjusted the I / O sampling cycle from 100ms to 50ms to speed up the signal response speed. Through the above dynamic control, the estimated time for P2 was reduced from 2.5 hours to 1.5 hours, ensuring that the overall upgrade was successfully completed and switched back to the operational state before 05:00.

[0064] refer to Figure 5 In step S14, the specific steps are as follows: S141: Real-time daytime control node, determines the stop upgrade signal based on the identification of the daytime control node, determines the corresponding stop upgrade command based on the parsing of the stop upgrade signal, and triggers the interruption of the upgrade process of the new system interlock control equipment according to the stop upgrade command, and the new system interlock control equipment is in the stop upgrade state; S142: Based on the re-identification of the daytime control node, the corresponding normal operation signal is determined, and the normal operation signal is output to the existing interlocking system. The existing interlocking system triggers the corresponding state switching event based on the normal operation signal. At this time, the existing interlocking system switches from the stopped state to the working state.

[0065] In the embodiments of this application, the real-time daytime control node determines a stop upgrade signal based on the identification of the daytime control node, determines a corresponding stop upgrade command based on the parsing of the stop upgrade signal, and triggers the interruption of the upgrade process of the new system interlock control device according to the stop upgrade command. The new system interlock control device is in a stop upgrade state, which is compatible with the overall consideration of parsing the stop upgrade signal and ensures the accuracy of the corresponding stop upgrade command.

[0066] At this point, the system maintains time synchronization via NTP or a dedicated GPS clock source. The control logic scans the current system time at millisecond intervals and continuously compares it with a preset "daytime control node" time threshold. Once the comparison result matches or the time difference is less than a preset trigger margin, the system determines that it has entered the daytime control node. Subsequently, based on the identification of the daytime control node, a stop upgrade signal is determined. When the time node is successfully identified, the system's central processing unit triggers a high-priority system event at the kernel level, defining it as a "stop upgrade signal." This signal is manifested as a toggle of a global variable or flag bit and is broadcast to all relevant slave devices via a hardware interrupt vector to ensure that the entire distributed system synchronously perceives the end of the upgrade cycle.

[0067] Based on the parsing of the stop upgrade signal, the corresponding stop upgrade instruction is determined. After receiving the signal, the master control device generates a specific control frame through the protocol parsing module, calls the predefined instruction set and matches the message header, and encapsulates the stop upgrade signal into an instruction that conforms to the industrial communication protocol format, including the target device address, operation type, check code and security context information.

[0068] The upgrade process of the new system interlock control equipment is interrupted by the stop upgrade command. The command is sent to the new system equipment through the industrial network. After receiving and verifying the message, the equipment sends an unmasked interrupt to the CPU. The operating system immediately suspends the currently running upgrade task thread and saves the context. For non-atomic operations, a transaction rollback mechanism is executed to clean up temporary data, and the sending of test data to the underlying hardware is stopped. The equipment then enters a safe "static" or "standby" state, the internal state machine is locked, and the issuance of control messages at the application layer is stopped.

[0069] Specifically, the PLC switching box of the interlocking system runs the background monitoring task. At the moment of transition from 04:59:59 to 05:00:00, the high-speed counter of the PLC captures that the system clock has reached the preset T_Day_Start threshold. The system immediately sets the flag bit M_Day_Node_Flag in the data block DB10, successfully identifying that the daytime control node has arrived.

[0070] Based on the setting of the flag bit, the PLC's operating system kernel triggers event-driven logic to generate a stop upgrade signal named SIG_STOP_UPG. This signal is written to the system's shared memory area with the highest priority, immediately overwriting any ongoing low-level operations.

[0071] After detecting the signal, the host computer of the interlocking system invokes the communication protocol stack to parse it into a standard Modbus TCP command message, explicitly instructing the new system interlocking machine B at address 0x05 to immediately stop its current operation. The command is transmitted to the new system interlocking machine B via the network. After the network card receives the message and verifies its CRC checksum, it sends a hardware interrupt to the CPU main control board. The CPU suspends the current Flash write operation, saves the current write progress to the non-volatile memory log area, and forcibly terminates the upgrade main process. The HMI panel status of the new system interlocking machine B changes from "UPGRADING" to "HALTED / STANDBY". At this point, although the device is powered on, there is no drive current at the output port, indicating that it is completely in a stopped upgrade state awaiting further system switching instructions.

[0072] Furthermore, based on the re-identification of the daytime control node, the corresponding normal operation signal is determined and output to the existing interlocking system. The existing interlocking system triggers the corresponding state switching event based on the normal operation signal. At this time, the existing interlocking system switches from the stopped state to the working state, which takes into account the overall consideration of the re-identification of the daytime control node and ensures the accuracy of the corresponding normal operation signal.

[0073] At this point, the system reads the real-time clock again to confirm that the current time has fully entered the effective range of the "daytime control node", and verifies that the new system interlocking equipment is in a silent state of "stop upgrading" through polling or heartbeat mechanism. Under the premise that both time and state conditions are met, an authorized data packet containing digital signature and timestamp is generated as a "normal working signal".

[0074] The normal operation signal is output to the existing interlocking system. The PLC switching box or host computer sends the signal to the existing interlocking system through redundant industrial Ethernet or hard-wired digital output channels. After receiving the signal, the existing interlocking system performs link layer verification and sends back an ACK confirmation frame. After receiving the confirmation, the PLC switching box maintains the continuous output of the signal as the basis for maintaining normal operation.

[0075] The existing interlocking system triggers corresponding state switching events based on normal operation signals. The communication interface unit maps the received signals to control words of the internal bus. Changes in these control words trigger the operating system scheduler to generate high-priority "state switching events," waking up the main control logic tasks that are in suspended or hibernation mode, and executing the initialization sequence to load the operating timetable and route data.

[0076] The existing interlocking system switches from the stopped state to the working state in sync with the logic wake-up. The PLC switching box drives the internal relays to operate according to the preset interlocking logic, disconnecting the physical contacts on the new system side and closing the physical contacts on the existing system side. The existing interlocking system gains control of the trackside equipment. The I / O module starts scanning the status of the field equipment and drives the output relays according to the interlocking logic. The software status flag inside the system flips to "working" and displays "System operating normally" on the human-machine interface.

[0077] Specifically, at 05:00:01, the host computer of the interlocking system reconfirms the time and detects that there is no data flow on the Ethernet port of the new system interlocking machine B. The host computer software then generates a "normal operation signal" message containing a timestamp and operation code CMD_RUN, and attaches an MD5 checksum, and sends it to the existing interlocking system through the switch.

[0078] The message is transmitted to the existing communication processor of interlocking machine A via a redundant RJ45 interface. After interlocking machine A receives and verifies the message, it returns an acknowledgment. The PLC switching box maintains an "activation" high-voltage level signal for interlocking machine A as a continuous hard-wired endorsement. When the CPU module of interlocking machine A detects that the communication port has received a CMD_RUN instruction, an internal interrupt is generated. The operating system immediately suspends the "sleep monitoring task" and loads the Operation_System.exe process, reading the station configuration data stored in NVRAM to restore the train operation record state before the interruption last night.

[0079] The PLC switching box internal control relay K_New_System de-energizes and disconnects, while K_Existing_System energizes and engages. The control cable of turnout No. 1 on site is physically switched to the output terminal of interlocking machine A. Interlocking machine A begins to issue positioning operation commands to turnout No. 1 and receives corresponding feedback. The red "Stop" indicator light on the panel goes out, and the green "Work" indicator light illuminates, marking that the interlocking system has successfully switched from the stop state to the working state, and the line officially begins daytime passenger operation.

[0080] refer to Figure 6 In step S15, the specific steps are as follows: S151: After the daytime control node ends, the next nighttime control node is monitored in real time. At this time, the upgrade process of the new system interlocking control equipment is detected to determine the remaining upgrade content of the new system interlocking control equipment. S152: Determine the acceleration factor based on the remaining upgrade content and the overall upgrade progress of the new system interlocking control equipment; determine the acceleration upgrade mode of the new system interlocking control equipment according to the mapping relationship table between the acceleration factor and the acceleration mode; S153: In the accelerated upgrade mode, the current load of the new system interlocking control equipment is optimized, and the upgrade efficiency of each upgrade item of the new system interlocking control equipment is adjusted to ensure that the upgrade of the new system interlocking control equipment is fully completed in the next night control node. At the same time, the new system interlocking control equipment is switched with the existing interlocking system and loaded into the next day control node, so that the new system interlocking control equipment can work in the next day control node.

[0081] In the embodiments of this application, after the daytime control node ends, the next nighttime control node is monitored in real time. At this time, the upgrade process of the new system interlocking control equipment is detected to determine the remaining upgrade content of the new system interlocking control equipment. This takes into account the overall consideration of detecting the upgrade process of the new system interlocking control equipment, and ensures the accuracy of the remaining upgrade content of the new system interlocking control equipment.

[0082] At this time, the system uses a GPS timing module or NTP protocol to keep the clock synchronized. The background daemon reads the system's real-time clock at a preset period and continuously compares it with the pre-configured "next night control node" timestamp. Combined with the system's operating status, the monitoring flag is determined. Once the real-time time crosses the preset threshold, the finite state machine inside the system triggers a state flip, determining that the "night maintenance / upgrade window" has been opened.

[0083] The upgrade process of the interlocking control equipment of the new system is monitored. The aim is to accurately obtain the breakpoint location of the new system in the previous upgrade through diagnostic analysis. The system reads the system log and transaction record file in the non-volatile memory through a dedicated diagnostic interface, analyzes the "transaction commit" status in the log to check whether the I / O operations in the previous upgrade process are complete, confirms the data block status by comparison and verification, and reconstructs the execution trajectory tree of the previous upgrade in memory, marking the last successfully executed transaction ID.

[0084] The system generates a list of tasks to be done through difference calculation, subtracts successfully completed tasks from the preset "full upgrade list", adds incomplete or failed tasks back to the task queue, segments partially completed tasks based on breakpoint information and defines only incomplete segments as "remaining upgrade content", and reassigns metadata tags to each remaining content to form an accurate "incremental upgrade list to be executed".

[0085] Specifically, during the daytime, the interlocking system operates normally using the existing system while the new system's interlocking machine B is in standby mode. The host computer software of the interlocking system runs a clock monitoring task in real time. When the system time jumps from 23:59:59 to 00:00:00, the monitoring logic captures this time jump. The system sets the Night_Window_Active flag in its internal register, officially notifying all subsystems that the non-operational time window for the new day has opened, and the upgrade operation for the new system's interlocking machine B can be resumed.

[0086] The host computer connects to the new system interlocking machine B via TCP / IP to download yesterday's upgrade log file. The log parsing engine scan found that Core_Firmware_v2.0.bin showed a COMPLETED status, while ATS_Interface_Config.xml showed an INTERRUPTED status, with the last record indicating that the connection was lost while writing the 500th / 1000th block. The system determined that the breakpoint of Task 2 was at the 500th data block and that the data was incomplete, requiring rollback or overwrite.

[0087] After comparing the full inventory with the logs, the system generates a list of "remaining upgrade content". It determines that data blocks 500 to 1000 of the ATS interface configuration need to be rewritten. At the same time, it finds that the Station_Graphic.db status is PENDING. The system finally determines that tonight's to-do tasks include "the lower half of the ATS interface configuration" and "the complete station graphics library", and marks these two tasks as high priority and inputs them into the upgrade scheduler's waiting queue.

[0088] Furthermore, an acceleration coefficient is determined based on the remaining upgrade content and the overall upgrade progress of the new system interlocking control equipment; the acceleration upgrade mode of the new system interlocking control equipment is determined according to the mapping relationship table between the acceleration coefficient and the acceleration mode, which takes into account the overall consideration of the mapping relationship table between the acceleration coefficient and the acceleration mode, and ensures the accuracy of the acceleration upgrade mode of the new system interlocking control equipment.

[0089] At this point, the system calculates the total data volume, logical operation volume, and I / O operation count of all pending tasks by parsing the remaining upgrade content. It then estimates the estimated time required to complete these tasks under the standard configuration by combining the historical benchmark rate. Simultaneously, it reads the current time and calculates the available time window between the current time and the next daytime control node. Based on the worst-case principle, it calculates the acceleration factor. If the factor is greater than 1.0, it indicates that the acceleration strategy must be enabled; otherwise, the standard mode is maintained.

[0090] The system determines the acceleration upgrade mode of the interlocking control equipment of the new system based on the mapping table of acceleration coefficient and acceleration mode. The system uses a lookup table pre-stored in memory to define the correspondence between different coefficient ranges and operating modes. The calculated coefficient values ​​are matched in the mapping table. Once a match is successful, the configuration script corresponding to the mode is called to prepare to apply the configuration containing the settings for operating system kernel and hardware register parameters to the interlocking control equipment of the new system.

[0091] Specifically, the system detected that the "remaining upgrade content" includes the remaining 200MB of data for ATS interface configuration continuation and 800MB of data for loading the new site graphics library. Based on the standard rate plus CPU processing overhead, the estimated total time is 180 minutes. The current time is 00:00 and the next daytime control node is 05:00. Considering that one hour must be reserved before 04:00 for final interlocking tests and reverse connection verification, the actual effective working window is 150 minutes. Based on the calculation α=180 / 150=1.2, acceleration is required. In the stage of determining the accelerated upgrade mode, the system consulted the preset mapping relationship table and found that the calculated acceleration coefficient of 1.2 falls within the interval (1.0,1.5], which corresponds to "Mode B: Parallel Accelerated Upgrade Mode".

[0092] The system then adjusted the configuration parameters of the new system interlock control equipment to "Mode B" setting, including adjusting the data transmission thread pool size from single thread to 4 concurrent threads, raising the upgrade process priority from Normal to High and disabling CPU power saving mode to lock the highest frequency, and switching the disk I / O scheduling algorithm from CFQ to Deadline to reduce read and write latency. It successfully determined the "parallel accelerated upgrade mode" suitable for the current urgency to complete the remaining tasks.

[0093] Therefore, in the accelerated upgrade mode, the current load of the new system interlocking control equipment is optimized, and the upgrade efficiency of each upgrade item of the new system interlocking control equipment is adjusted to ensure that the upgrade of the new system interlocking control equipment is fully completed within the next night control node. At the same time, the new system interlocking control equipment is switched with the existing interlocking system and loaded onto the next day control node, realizing the operation of the new system interlocking control equipment in the next day control node. This introduces the operation of the new system interlocking control equipment in the next day control node, while ensuring the operation of the day control node, and realizing the switching between the night control node, day control node, and the next night control node. This ensures that the upgrade of the new system interlocking control equipment is fully completed within the next night control node, and that the new system interlocking control equipment operates in the next day control node.

[0094] At this point, the system utilizes a real-time scheduling strategy to prioritize upgrade-related processes to the highest level, allowing them to obtain CPU time slices before non-critical background tasks. Simultaneously, it proactively identifies and suspends auxiliary services with low real-time requirements to free up memory space and reduce bus contention. Furthermore, it binds the upgrade process threads to the most powerful CPU core and prohibits frequency throttling, ensuring the core always runs at its highest performance level. Subsequently, the upgrade efficiency of various upgrade projects for the new system's interlocking control equipment is adjusted. Specific technical methods are employed for different task types. For projects involving large amounts of data read / write, file system mount parameters are adjusted to enable Direct I / O mode, increase the TCP window size, and enable jumbo frames. For logic-intensive projects, the multi-core advantage is leveraged to break down large tasks into multi-threaded concurrent processing. For hardware board interaction projects, the backplane bus arbitration priority is adjusted to accelerate response.

[0095] The system samples the upgrade progress at a rate of seconds and extrapolates the estimated completion time in real time. If the predicted deadline is approaching, a deep acceleration strategy is triggered. Once all project status flags are updated to COMPLETED and the consistency check passes, the upgrade is deemed to be fully completed and the upgrade image is locked.

[0096] The host computer sends a double-confirmed cutover command to the PLC switching box. The PLC's internal logic drives relays or solid-state switches to disconnect the existing system circuit and close the new system circuit. The new system receives status feedback from the trackside equipment, confirming the physical link is connected and gaining logical control. It is then loaded onto the next daytime control node, enabling the new system's interlocking control equipment to operate on that node. The new system loads the day's operating timetable, temporary speed limit instructions, and train operation plan. The ATS establishes a communication session and sends a route request. The new system's internal state machine officially jumps to the operating state, continuously executing interlocking logic operations and outputting control commands to ensure normal train operation.

[0097] Specifically, the host computer of the interlocking system in "parallel acceleration mode" locks the CPU core frequency of the new system interlocking machine B at 3.5GHz and disables hibernation mode. At the same time, it sends a command to forcibly shut down the "debug log service" and "performance monitoring probe", releasing about 15% of memory resources to fully ensure the operation of the upgrade task.

[0098] For the continuation of ATS interface configuration, the system adjusts the TCP window from the default 64KB to 1MB, increasing the transmission rate to 900Mbps; for loading the station graphics library, the system splits the originally serially loaded 20 station data into 4 threads in parallel and enables Direct I / O mode to write directly to flash memory, which increases the writing speed by 3 times.

[0099] At 04:00 AM, the system detected that all remaining tasks had been completed ahead of schedule and the consistency check CRC was correct. The HMI panel of interlocking machine B displayed "Upgrade Complete, Status Locked," and the system entered the cutover state. The host computer sent a cutover command to the PLC switching box. The PLC's internal relay K_New was energized and engaged, while K_Old was de-energized and disconnected. The physical cables switched instantly, and the control signals of the trackside equipment were completely transferred from the old interlocking machine A to the new interlocking machine B. The new interlocking machine B detected the indication voltage from the turnout and confirmed that the connection was normal.

[0100] At 04:30 AM, the new system loaded the departure plan for the first train, and the indicator light on the interlocking machine B changed from yellow to green. At 05:00 AM, the first train departed from the depot. The new interlocking system successfully responded to the route request and arranged the first route. The interlocking system was officially taken over by the new system's interlocking control equipment, enabling normal operation of the control nodes during the next day.

[0101] Please see Figure 7 , Figure 7 This is a schematic diagram of the structural composition of the upgrade system of the interlocking system in this embodiment of the invention; the upgrade system of the interlocking system includes: Upgrade phase module 21 is used to collect the current time, determine the daytime control node and the nighttime upgrade node based on the current time, the existing interlocking system and the corresponding upgrade information; and trigger the upgrade phase of the existing interlocking system based on the nighttime upgrade node. The night upgrade event module 22 is used to connect the existing interlocking system, trackside equipment and new system interlocking control equipment to the same control box during the upgrade phase, and to trigger the night upgrade event of the new system interlocking control equipment in the control box, while the existing interlocking system is in a stopped state. The overall upgrade progress module 23 is used to identify multiple upgrade projects based on the nighttime upgrade events of the new system interlocking control equipment, determine the overall upgrade progress of the new system interlocking control equipment according to the project content of each upgrade project, the corresponding project upgrade progress and the remaining time at night, and dynamically control the overall upgrade progress. The daytime control module 24 is used to interrupt the upgrade process of the new system interlocking control equipment in the daytime control node and switch to the existing interlocking system. At this time, the existing interlocking system switches from the stopped state to the working state. The accelerated upgrade module 25 is used to mark the remaining upgrade content of the new system interlocking control equipment in the next night control node, and determine the accelerated upgrade mode of the new system interlocking control equipment based on the remaining upgrade content and the overall upgrade progress of the new system interlocking control equipment, so as to ensure that the upgrade of the new system interlocking control equipment is fully completed in the next night control node, and the new system interlocking control equipment operates in the next day control node.

[0102] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

Claims

1. A method of upgrading an interlocking system, characterized by, include: Collect the current time, and determine the daytime control node and nighttime upgrade node based on the current time, the existing interlocking system, and the corresponding upgrade information; This nighttime upgrade node triggers the upgrade phase of the existing interlocking system; During this upgrade phase, the existing interlocking system, trackside equipment, and new system interlocking control equipment are connected to the same control box, and the nighttime upgrade event of the new system interlocking control equipment is triggered in the control box, while the existing interlocking system is in a stopped state. Based on the identification of nighttime upgrade events of the new system interlocking control equipment, multiple upgrade projects are determined. The overall upgrade progress of the new system interlocking control equipment is determined according to the project content, the corresponding project upgrade progress and the remaining time at night, and the overall upgrade progress is dynamically controlled. During the daytime control node, the upgrade process of the new system interlocking control equipment is interrupted, and the system is switched to the existing interlocking system. At this time, the existing interlocking system switches from the stopped state to the working state. In the next night control node, mark the remaining upgrade content of the new system interlocking control equipment. Based on the remaining upgrade content and the overall upgrade progress of the new system interlocking control equipment, determine the accelerated upgrade mode of the new system interlocking control equipment to ensure that the upgrade of the new system interlocking control equipment is fully completed in the next night control node, and the new system interlocking control equipment will work in the next day control node.

2. The method of upgrading an interlocking system according to claim 1, wherein, The current time is collected, and the daytime control node and nighttime upgrade node are determined based on the current time, the existing interlocking system, and the corresponding upgrade information; Based on this nighttime upgrade node, the existing interlocking system is triggered into an upgrade phase, including: Time is monitored and the current time is marked. At the same time, the normal working time of the existing interlocking system and the corresponding upgrade signal are collected. The corresponding upgrade information is determined based on the analysis of the upgrade signal. The daytime control node and the nighttime upgrade node are determined according to the current time, the normal working time of the existing interlocking system and the corresponding upgrade information. The daytime control node and the nighttime upgrade node are in different time periods. In this nighttime upgrade node, multiple upgrade dimensions of the existing interlocking system are determined based on the identification of the nighttime upgrade node. The upgrade stage of the existing interlocking system is determined based on each upgrade dimension, the corresponding upgrade content, and the time range of the nighttime upgrade node.

3. The method of upgrading an interlocking system of claim 1, wherein, During this upgrade phase, the existing interlocking system, trackside equipment, and new system interlocking control equipment are connected to the same control box. A nighttime upgrade event for the new system interlocking control equipment is triggered within this control box, while the existing interlocking system remains in a stopped state. This includes: The upgrade phase is monitored in real time, and the new system interlocking control equipment is marked. At this time, the existing interlocking system and the new system interlocking control equipment share the same trackside equipment and are controlled by the same control box. The control box sets the corresponding control program and manages the mutual exclusion relationship between the existing interlocking system and the new system interlocking control equipment. At the same time, in the night control node, the control box triggers a night upgrade signal, and along the night upgrade signal, it triggers a night upgrade event for the new system interlocking control equipment. The new system interlocking control equipment performs the corresponding night upgrade, while the existing interlocking system is in a stopped state.

4. The method of upgrading an interlocking system of claim 1, wherein, The identification of nighttime upgrade events based on the new system interlocking control equipment determines multiple upgrade projects. The overall upgrade progress of the new system interlocking control equipment is determined based on the project content, corresponding upgrade progress, and remaining nighttime time for each upgrade project. The overall upgrade progress is then dynamically monitored, including: The nighttime upgrade events of the interlocking control equipment of the new system are dynamically identified, and the corresponding project tags are determined during the identification process. Based on the tracing of each project tag, the corresponding upgrade project is determined, so as to collect multiple upgrade projects.

5. The method of upgrading an interlocking system according to claim 4, wherein, The identification of nighttime upgrade events based on the new system interlocking control equipment determines multiple upgrade projects. The overall upgrade progress of the new system interlocking control equipment is determined based on the project content, corresponding upgrade progress, and remaining nighttime time for each upgrade project. The overall upgrade progress is then dynamically monitored. This also includes: In multiple upgrade projects, the corresponding project content is determined based on the detection of each upgrade project, and the upgrade progress of each upgrade project is dynamically marked. The first upgrade progress is determined based on the project content of each upgrade project and the remaining time at night. The second-stage upgrade schedule is determined based on the project's progress and remaining time at night for each upgrade project. The overall upgrade schedule of the new system's interlocking control equipment is then determined based on the first-stage and second-stage upgrade schedules, so as to dynamically control the overall upgrade schedule.

6. The method of upgrading an interlocking system of claim 1, wherein, During the daytime control node, the upgrade process of the new system interlocking control equipment is interrupted, and the system is switched to the existing interlocking system. At this time, the existing interlocking system switches from a stopped state to an operating state, including: The real-time daytime control node determines the stop upgrade signal based on the identification of the daytime control node, determines the corresponding stop upgrade command based on the parsing of the stop upgrade signal, and triggers the interruption of the upgrade process of the new system interlock control equipment according to the stop upgrade command, and the new system interlock control equipment is in a stop upgrade state.

7. The method for upgrading an interlocking system according to claim 6, characterized in that, The process of interrupting the upgrade of the new system interlocking control equipment in the daytime control node and switching to the existing interlocking system, at which time the existing interlocking system switches from a stopped state to an operating state, also includes: Based on the re-identification of the daytime control node, the corresponding normal operation signal is determined and output to the existing interlocking system. The existing interlocking system triggers the corresponding state switching event based on the normal operation signal. At this time, the existing interlocking system switches from the stopped state to the working state.

8. The method for upgrading an interlocking system according to claim 1, characterized in that, In the next nighttime control node, the remaining upgrade content of the new system interlocking control equipment is marked. Based on the remaining upgrade content and the overall upgrade progress of the new system interlocking control equipment, an accelerated upgrade mode for the new system interlocking control equipment is determined to ensure that the upgrade of the new system interlocking control equipment is fully completed within the next nighttime control node, and the new system interlocking control equipment operates in the next daytime control node, including: After the daytime control node ends, the next nighttime control node is monitored in real time. At this time, the upgrade process of the new system interlocking control equipment is detected to determine the remaining upgrade content of the new system interlocking control equipment. Based on the remaining upgrade content and the overall upgrade progress of the new system interlocking control equipment, an acceleration coefficient is determined; based on the mapping relationship table between the acceleration coefficient and the acceleration mode, the acceleration upgrade mode of the new system interlocking control equipment is determined.

9. The method for upgrading an interlocking system according to claim 8, characterized in that, In the next nighttime control node, the remaining upgrade content of the new system interlocking control equipment is marked. Based on the remaining upgrade content and the overall upgrade progress of the new system interlocking control equipment, an accelerated upgrade mode for the new system interlocking control equipment is determined to ensure that the upgrade of the new system interlocking control equipment is fully completed within the next nighttime control node, and that the new system interlocking control equipment operates in the next daytime control node. This also includes: In the accelerated upgrade mode, the current load of the new system interlocking control equipment is optimized, and the upgrade efficiency of each upgrade project of the new system interlocking control equipment is adjusted to ensure that the upgrade of the new system interlocking control equipment is fully completed in the next night control node. At the same time, the new system interlocking control equipment is switched with the existing interlocking system and loaded into the next day control node, so that the new system interlocking control equipment can work in the next day control node.

10. An upgrade system for an interlocking system, characterized in that, The interlocking system upgrade system is applied to the interlocking system upgrade method as described in any one of claims 1-9.

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