Communication method and equipment based on SPI (Serial Peripheral Interface) protocol

Abstract

The invention discloses a communication method and device based on an SPI protocol, and the method comprises the steps: mapping a physical base address of an SPI controller in a system-on-chip to a virtual address space to obtain a virtual address access interface, and directly accessing a register of the SPI controller through the interface. And then, completing initial configuration of the SPI controller based on the virtual address access interface. And then, data to be sent are written into a data register of the SPI controller through the virtual address access interface, and the SPI controller forms an SPI message with the data and sends the SPI message. And in the data transmission process, polling the status bit of the SPI controller status register through the virtual address access interface, and confirming whether the to-be-sent data is sent or not according to the status bit.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a communication method and device based on the SPI protocol. Background Technology

[0002] In the field of embedded systems, System-on-Chips (SoCs) are widely used in industrial control, intelligent sensing, and data acquisition scenarios due to their high integration and low power consumption. Serial Peripheral Interface (SPI), as a synchronous serial communication protocol, has become the core method for data interaction between SoCs and external devices due to its high-speed, full-duplex communication characteristics. For example, SoCs can interact with external devices such as sensors, memory, or displays via the SPI protocol.

[0003] In order to improve the universality and compatibility of SPI communication and adapt to different types of SPI external devices, existing technologies introduce additional abstraction layers and operation logic into the SPI controller driver of the Linux system. The transmission of SPI messages needs to go through multiple levels of function calls in the SPI driver framework, including the SPI core layer, SPI controller driver, and SPI device driver. This results in limited SPI message transmission efficiency and makes it difficult to meet the communication efficiency requirements of related technologies. Summary of the Invention

[0004] To address the aforementioned issues, this application provides a communication method and device based on the SPI protocol.

[0005] The embodiments of this application disclose the following technical solutions:

[0006] In a first aspect, embodiments of this application provide a communication method based on the SPI protocol, the method comprising:

[0007] The physical base address of the Serial Peripheral Interface (SPI) controller in the system-on-a-chip is mapped to the virtual address space to obtain the virtual address access interface of the SPI controller; wherein, the virtual address access interface is used to directly access the registers of the SPI controller;

[0008] The SPI controller is initialized and configured based on the virtual address access interface.

[0009] The data to be sent is written into the data register of the SPI controller through the virtual address access interface, so that the SPI controller assembles the data to be sent into a message and sends it.

[0010] The status bits of the SPI controller's status register are polled through the virtual address access interface;

[0011] The status register is used to determine whether the data to be sent has been successfully transmitted.

[0012] In one possible implementation, the initialization configuration of the SPI controller based on the virtual address access interface includes:

[0013] Access the first control register of the SPI controller according to the address offset of the virtual address access interface and the first control register, and configure the communication mode, transmission mode, frame format and communication word length of the SPI controller;

[0014] Access the slave enable register of the SPI controller through the virtual address access interface and the offset address of the slave enable register to select the target chip select signal;

[0015] The communication rate is set by accessing the baud rate register of the SPI controller through the virtual address access interface and the offset address of the baud rate register.

[0016] In one possible implementation, configuring the communication mode, transmission mode, and frame format of the SPI controller includes:

[0017] Configure the serial clock polarity and serial clock phase of the first control register to 0, so that the communication mode of the SPI controller is SPI mode 0;

[0018] Configure the transmission mode bit of the first control register to transmit and receive simultaneously;

[0019] Configure the frame format bits of the first control register to the Motorola SPI frame format.

[0020] In one possible implementation, the method further includes, before initializing the SPI controller:

[0021] Access the enable register of the SPI controller according to the offset address of the virtual address access interface and the enable register, set the enable register to 0, and disable the SPI controller;

[0022] After initializing and configuring the SPI controller, the method further includes:

[0023] Access the enable register of the SPI controller according to the virtual address access interface and the offset address of the enable register, set the enable register to 1, and enable the SPI controller.

[0024] In one possible implementation, the step of accessing the SPI controller's baud rate register via the virtual address access interface and the offset address of the baud rate register to set the communication rate includes:

[0025] Obtain the base frequency of the system-on-a-chip;

[0026] Calculate the frequency division coefficient based on the base frequency and the target communication rate;

[0027] The frequency division coefficient is written into the baud rate register through the virtual address access interface and the offset address access of the baud rate register to set the communication rate of the SPI controller.

[0028] In one possible implementation, the method further includes:

[0029] The receive first-in-first-out non-empty flag of the status register is polled by the virtual address access interface and the offset address of the status register.

[0030] When the receive first-in-first-out non-empty flag is 1, the data in the data register is read and cached through the virtual address access interface and the offset address of the data register.

[0031] In one possible implementation, confirming whether the data to be sent has been sent based on the status bit of the status register includes:

[0032] The transmit first-in-first-out empty flag and the module working flag of the status register are read through the virtual address access interface and the offset address of the status register.

[0033] When the first-in-first-out empty flag is 1 and the module working flag is 0, it is confirmed that the data to be sent has been sent.

[0034] Secondly, embodiments of this application disclose a communication device based on the SPI protocol, the device comprising:

[0035] A mapping module is used to map the physical base address of the Serial Peripheral Interface (SPI) controller in the system-on-a-chip to a virtual address space to obtain the virtual address access interface of the SPI controller; wherein, the virtual address access interface is used to directly access the registers of the SPI controller;

[0036] The configuration module is used to initialize and configure the SPI controller based on the virtual address access interface;

[0037] The sending module is used to write the data to be sent into the data register of the SPI controller through the virtual address access interface, so that the SPI controller can assemble the data to be sent into a message and send it.

[0038] The polling module is used to poll the status bits of the status register of the SPI controller through the virtual address access interface;

[0039] The confirmation module is used to confirm whether the data to be sent has been sent completely based on the status bits of the status register.

[0040] In one possible implementation, the configuration module is specifically used to access the first control register of the SPI controller based on the address offset between the virtual address access interface and the first control register, and configure the communication mode, transmission mode, and frame format of the SPI controller; access the slave enable register of the SPI controller through the offset address between the virtual address access interface and the slave enable register, and select the target chip select signal; access the baud rate register of the SPI controller through the offset address between the virtual address access interface and the baud rate register, and set the communication rate; and access the first control register of the SPI controller through the offset address between the virtual address access interface and the control register, and determine the communication word length.

[0041] In one possible implementation, the configuration module is specifically configured to set the serial clock polarity and serial clock phase of the first control register to 0, so that the communication mode of the SPI controller is SPI mode 0; configure the transmission mode bit of the first control register to transmit and receive mode; and configure the frame format bit of the first control register to Motorola SPI frame format.

[0042] In one possible implementation, before initializing the SPI controller, the configuration module is further configured to access the SPI controller's enable register based on the offset address of the virtual address access interface and the enable register, set the enable register to 0, and disable the SPI controller.

[0043] After initializing and configuring the SPI controller, the configuration module is further configured to access the enable register of the SPI controller according to the offset address of the virtual address access interface and the enable register, set the enable register to 1, and enable the SPI controller.

[0044] In one possible implementation, the configuration module is specifically used to obtain the base frequency of the system-on-a-chip; calculate the division factor based on the base frequency and the target communication rate; and write the division factor into the baud rate register through the virtual address access interface and the offset address access of the baud rate register to set the communication rate of the SPI controller.

[0045] In one possible implementation, the polling module is further configured to poll the receive-first-out (FFIFO) non-empty flag of the status register through the virtual address access interface and the offset address of the status register; when the receive-first-out (FFIFO) non-empty flag is 1, the data in the data register is read through the virtual address access interface and the offset address of the data register and cached.

[0046] In one possible implementation, the confirmation module is specifically used to read the transmit first-in-first-out empty flag and the module working flag of the status register through the virtual address access interface and the offset address of the status register; when the transmit first-in-first-out empty flag is 1 and the module working flag is 0, the module confirms that the data to be transmitted has been transmitted.

[0047] Thirdly, embodiments of this application disclose a control device, including a processor and a memory, wherein the memory is used to store programs, instructions or code, and the processor is used to execute the programs, instructions or code in the memory to perform the communication method based on the SPI protocol as described in any of the first aspects.

[0048] Fourthly, embodiments of this application disclose a computer-readable storage medium, characterized in that it stores a computer program, which is loaded by a processor to execute the communication method based on the SPI protocol as described in any of the first aspects.

[0049] This application provides a communication method and device based on the SPI protocol. The method maps the physical base address of the SPI controller in a system-on-a-chip to a virtual address space to obtain a virtual address access interface, through which the SPI controller's registers can be directly accessed. Then, the SPI controller's initialization configuration is completed based on this virtual address access interface. Subsequently, the data to be sent is written to the SPI controller's data register via the virtual address access interface, and the SPI controller assembles the data into an SPI message and sends it. During data transmission, the status bits of the SPI controller's status register are polled through the virtual address access interface, and the status bits are used to confirm whether the data to be sent has been successfully transmitted.

[0050] This application embodiment obtains a virtual address access interface for direct access to the SPI controller registers through a mapping from physical addresses to virtual addresses. This eliminates redundant operations such as function calls and permission checks caused by the multi-level abstraction of the SPI driver framework, reducing latency introduced by intermediate steps. Simultaneously, initialization configuration, data writing, and status polling are performed directly through this interface, avoiding performance bottlenecks caused by frequent GPIO register reads, significantly shortening SPI message transmission time, and improving the overall efficiency of SPI communication. Furthermore, the status register's status bits accurately confirm the data transmission completion status, ensuring communication reliability and effectively leveraging the hardware communication potential of the SPI controller. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 A flowchart illustrating a communication method based on the SPI protocol provided in an embodiment of this application;

[0053] Figure 2 A schematic diagram illustrating the initialization configuration of an SPI controller provided in an embodiment of this application;

[0054] Figure 3 This application provides a schematic diagram of a data transmission process based on the SPI protocol.

[0055] Figure 4 This is a schematic diagram of a communication device based on the SPI protocol provided in an embodiment of this application. Detailed Implementation

[0056] As described above, in existing technologies, Linux systems implement SPI communication through a standardized SPI driver framework. This framework comprises the SPI core layer, the SPI controller driver, and the SPI device driver. The SPI core layer manages the registration and matching of the bus, devices, and drivers; the SPI controller driver provides the interface for interacting with the SPI controller; and the SPI device driver implements protocol adaptation for specific external devices. During the communication initialization phase, the SPI controller driver needs to configure the SPI controller's general configuration parameters and common configuration parameters through a multi-level abstract interface.

[0057] During the SPI message transmission phase, SPI messages sent by the application layer need to be called by the SPI device driver, the SPI core layer, and the SPI controller driver before they can be delivered to the SPI controller. Simultaneously, to ensure communication reliability, the SPI controller driver frequently reads the General Purpose Input / Output (GPIO) registers to confirm the status of external devices. After the current message transmission is completed, the system resources occupied by the SPI driver framework must be released before the transmission of the next message can begin. Furthermore, to improve performance, existing technologies can employ optimization techniques such as adjusting the SPI clock rate, optimizing the bus division ratio, enabling i-cache and d-cache, and enabling Direct Memory Access (DMA) transfers. However, these techniques are all based on localized adjustments to the existing SPI driver framework architecture, with limited optimization effects and cannot fundamentally solve the problem of low SPI message transmission efficiency.

[0058] To address this technical problem, this application provides a communication method and device based on the SPI protocol. The method maps the physical base address of the SPI controller in the system-on-a-chip to a virtual address space to obtain a virtual address access interface, through which the SPI controller's registers can be directly accessed. Then, the SPI controller's initialization configuration is completed based on this virtual address access interface. Subsequently, the data to be sent is written to the SPI controller's data register via the virtual address access interface, and the SPI controller assembles the data into an SPI message and sends it. During data transmission, the status bits of the SPI controller's status register are polled through the virtual address access interface, and the status bits are used to confirm whether the data to be sent has been successfully transmitted.

[0059] This application embodiment obtains a virtual address access interface for direct access to the SPI controller through a mapping from physical addresses to virtual addresses. This eliminates redundant operations such as function calls and permission checks caused by the multi-level abstraction of the SPI driver framework, reducing latency introduced by intermediate steps. Simultaneously, initialization configuration, data writing, and status polling are performed directly through this interface, avoiding performance bottlenecks caused by frequent GPIO register reads, significantly shortening SPI message transmission time, and improving the overall efficiency of SPI communication. Furthermore, the status register's status bits accurately confirm the data transmission completion status, ensuring communication reliability and effectively leveraging the hardware communication potential of the SPI controller.

[0060] The communication method provided in this application is applicable to embedded hardware devices equipped with a System-on-a-Chip (SoC) and running a Linux operating system, and is suitable for scenarios with stringent requirements for real-time performance and low latency in SPI communication. For example, in the field of industrial control, Programmable Logic Controllers (PLCs) interact with high-speed sensors and actuators via the SPI interface, requiring rapid transmission of control commands and feedback data to ensure precise synchronization of the production process. In intelligent sensing terminals, environmental monitoring devices collect data such as temperature, humidity, or gas concentration in real time via the SPI protocol, requiring shorter message intervals to increase data sampling frequency. Furthermore, in hardware such as automotive electronic devices or high-speed data acquisition cards, this method can directly control the SPI controller, fully leveraging the device's communication potential to meet the demands for high-throughput, low-latency SPI data transmission, ensuring stable and efficient operation of the hardware under complex working conditions.

[0061] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0062] See Figure 1 , Figure 1 This is a flowchart illustrating a communication method based on the SPI protocol provided in an embodiment of this application. The execution subject of this method can be a server, a desktop computer, or other electronic devices capable of computational functions. The following description uses a server as the execution subject, and the method includes:

[0063] S101: The server maps the physical base address of the SPI controller in the system-on-a-chip to the virtual address space to obtain the virtual address access interface of the SPI controller.

[0064] The virtual address access interface is used to directly access the registers of the SPI controller;

[0065] The physical base address refers to the actual address of the SPI controller within the System-on-a-Chip (SoC), serving as the underlying address identifier for accessing the controller hardware. Typically, the system software layer or application layer cannot directly access the physical base address. The virtual address space is a memory address range allocated by the Linux operating system for applications or kernel modules, and it can be associated with the physical base address through an address mapping mechanism. The virtual address access interface is the access point formed after the physical base address is mapped to the virtual address space. The system software layer or application layer can directly read and write various registers of the SPI controller through the virtual address access interface without going through the SPI driver framework.

[0066] In this embodiment, the server can use the ioremap function provided by the Linux operating system to map the physical base address of the SPI controller to a virtual address. The physical base address is usually fixed by the chip hardware design. After the server determines the physical base address of the SPI controller in the SOC, it calls the ioremap function and passes the physical base address and the address space length corresponding to the SPI controller's register group to the ioremap function. After the ioremap function executes, it returns a virtual address, which constitutes the virtual address access interface.

[0067] After mapping, the system software layer or application layer can directly read and write various registers of the SPI controller through the virtual address access interface. For example, when accessing the SSIENR register, the SSIENR register can be directly located using the address combination of the SPI controller's virtual address and the offset address of the SSIENR register, without going through the multi-level function calls and permission verification processes of the SPI driver framework, thus achieving direct access to the hardware register. Simultaneously, the mapping process strictly adheres to the memory management specifications of the Linux operating system, ensuring the legality and stability of virtual address access and avoiding memory access conflicts.

[0068] In this embodiment of the application, the register group of the SPI controller includes, for example, the registers shown in Table 1.

[0069] Table 1

[0070] register Offset address Bit width illustrate First control register 0x00 17bit Control Register 0, CTRL0 Second control register 0x04 16bit Control Register 1, CTRL1 Enable register 0x08 1 bit SSI Enable Register SSI, SSIENR, Reset value: 0x0 Control Register 0x0C 3bit Microwire Control Register (MWCR), reset value: 0x0 Slave Enable Register 0x10 3bit Slave Enable Register, SER, Reset value: 0x0 baud rate register 0x14 16bit Baud Rate Register, BAUDR, Reset value: 0x0 Send First-In-First-Out Threshold 0x18 8bit Transmit FIFO Threshold Level, TXFTLR, Reset value: 0x0 Receive First-In-First-Out Threshold 0x1C 8bit Receive FIFO Threshold Level, RXFTLR, Reset value: 0x0 Status Register 0x28 7 bit Status Register, SR, Reset value: 0x0 Receive First-In-First-Out Underflow Interrupt Clear Register 0x40 1 bit Receive FIFO Underflow Interrupt Clear Register, RXUICR, Reset value: 0x0 Multi-master contention interrupt clear register 0x44 1 bit Multi-Master Interrupt Clear Register, MSTICR, Reset value: 0x0 Interrupt Clear Register 0x48 1 bit Interrupt Clear Register (ICR), Reset value: 0x0 Direct access to memory control registers 0x4C 2bit DMA Control Register, DMACR, Reset value: 0x0 direct memory access to send data threshold 0x50 8bit DMA Transmit Data Level, DMATDLR, Reset value: 0x0 direct memory access data reception threshold 0x54 8bit DMA Receive Data Level, DMARDLR, Reset value: 0x0 Data register 0x60-0xCC 32bit Data Register, DR Master-Slave Selection Register 0x100 32bit Master / Slave Selection Register, MSTR Receive sampling delay register 0xFD 8bit RXD Sample Delay Register, RX_SAMPLE_DELAY, Reset value: 0x0

[0071] S102: The server accesses the SPI controller via a virtual address interface to perform initial configuration.

[0072] During the initialization configuration process, the server initializes the CTRLR0 register, SER register, and BAUDR register based on the virtual address access interface.

[0073] This application's embodiments directly configure the SPI controller's registers based on the virtual address access interface, avoiding the redundant processes of SPI driver framework configuration in existing technologies, and ensuring the efficiency and accuracy of parameter configuration. Compared to indirect configuration through the SPI driver framework, directly manipulating registers reduces intermediate steps such as parameter forwarding, format conversion, and permission verification, thus shortening configuration time.

[0074] The parameters configured for the SPI controller before SPI communication begins include dedicated configuration parameters and general configuration parameters. Dedicated configuration parameters are strongly dependent on specific chip systems and target communication scenarios, including communication mode, chip select signal, transmission rate, and communication word length, and must be precisely configured according to hardware characteristics and application requirements. General configuration parameters are basic configuration parameters applicable to various chip systems and general SPI communication scenarios, such as basic register function enablements, basic frame format definitions, and default transmission mode configurations. These do not require adjustment based on specific application scenarios to meet the basic logic requirements of SPI communication.

[0075] To ensure the validity and stability of parameter writing during the initialization configuration process, specific operations need to be performed on the SSIENR register before and after configuration.

[0076] like Figure 2 As shown, Figure 2 This is a schematic diagram illustrating the initialization configuration process of an SPI controller according to an embodiment of this application. In this embodiment, before initializing the SPI controller, the server accesses the SSIENR register based on the virtual address access interface and the offset address of the SSIENR register, sets the SSIENR register to 0, disables the SPI controller, and ensures that subsequent configuration parameters can be successfully written to the register. Since some configuration registers are locked when the SPI controller is enabled to ensure communication stability, this locking can be released after disabling it. By setting the SSIENR register to 0, the SPI controller's operation is disabled, making all configuration registers of the SPI controller writable.

[0077] After initializing and configuring the SPI controller, the server accesses the SSIENR register again based on the virtual address access interface and the offset address of the SSIENR register, sets the SSIENR register to 1, enables the SPI controller, makes all configuration parameters effective, and completes the SPI controller initialization.

[0078] In related technologies, both dedicated configuration parameters and general configuration parameters need to be configured before each SPI communication. However, in this application embodiment, based on the virtual address access interface, only the dedicated configuration parameters are precisely set, without the need to repeatedly set the general configuration parameters. The general configuration parameters directly use the default values ​​that are fixed in the SOC or preset at the bottom layer of the Linux operating system, without the need for repeated operations, thus simplifying the configuration process.

[0079] In this embodiment of the application, the offset addresses of different registers in the register group corresponding to the SPI controller are different. The server can directly access different registers based on the virtual address access interface and the offset address of the registers, and can directly configure the dedicated configuration parameters without the need for the SPI driver framework.

[0080] Specifically, such as Figure 2 As shown, the server accesses the first control register based on the address offset of the virtual address access interface and the CTRLR0 register to configure the communication mode, transmission mode, frame format, and communication word length of the SPI controller; the server accesses the slave enable register through the virtual address access interface and the offset address of the SER register to select the target chip select signal; the server accesses the baud rate register through the virtual address access interface and the offset address of the baud rate register to set the communication rate.

[0081] Throughout the initialization and configuration process, the virtual address access interface and the offset addresses of each register are used to directly operate the registers, bypassing the multi-level abstraction logic of the SPI driver framework. The operation is only performed on dedicated configuration parameters and the default values ​​of general configuration parameters are reused. This reduces configuration steps and time consumption, while ensuring the accuracy of parameter configuration. This allows the SPI controller to quickly enter the communication-ready state adapted to the target scenario, providing a stable hardware foundation for subsequent low-latency data transmission.

[0082] The targeted settings of dedicated configuration parameters enable the SPI controller to accurately match the hardware characteristics of the SOC and the communication requirements of the SPI external device, laying a solid foundation for subsequent low-latency, high-reliability data transmission. During the initialization configuration process, the parameter configuration of the CTRL0 register is a core step. The parameters of the CTRL0 register determine the communication timing, transmission logic, and data format of the SPI controller, which is fundamental to ensuring normal interaction between the SPI controller and the SPI external device.

[0083] like Figure 2As shown in this embodiment, during the configuration process of the CTRLR0 register by the server, the serial clock polarity (SCPOL) and serial clock phase (SCPH) of the CTRLR0 register are configured to 0, so that the communication mode of the SPI controller is SPI mode 0; the transmission mode (Transmission ModeMOD) bit of the CTRLR0 register is configured to transmit and receive simultaneously; and the frame format (FRF) bit of the CTRLR0 register is configured to Motorola SPI frame format.

[0084] The server accesses and configures the CTRL0 register via a virtual address access interface and an offset address. Regarding communication mode configuration, the server sets the serial clock polarity bit of the CTRL0 register to 0, ensuring the serial clock signal (SCLK) remains low when the SPI controller is in idle mode. Simultaneously, the server sets the serial clock phase to 0, causing the SPI controller to begin data sampling and transmission on the first rising edge of the SCLK signal. This determines the SPI controller's communication mode as SPI mode 0. SPI mode 0 is the most widely used standard mode in SPI communication, adaptable to the timing requirements of most external SPI slave devices, and avoids data transmission errors caused by clock polarity or phase mismatch.

[0085] In terms of transmission mode configuration, the server configures the transmission mode bit of the CTRL0 register to transmit and receive simultaneously. This configuration enables the SPI controller to have full-duplex communication capabilities, allowing it to simultaneously receive data returned from external slave devices while sending data to them. This eliminates the need for staged transmission and reception operations, significantly improving the efficiency of data interaction, and is particularly suitable for scenarios requiring bidirectional real-time data transmission.

[0086] The server configures the frame format bits of the CTRL0 register to the Motorola SPI frame format. The Motorola SPI frame format is a universal standard format in SPI communication, and its data transmission bit order, synchronization logic, and verification rules are supported by the vast majority of SPI external devices. This ensures that data frames sent by the SPI controller can be correctly parsed by external slave devices, and that data frames returned from external devices can be accurately recognized by the SPI controller, avoiding communication failures due to frame format incompatibility.

[0087] Communication rate is also a key parameter affecting SPI data transmission efficiency. In this embodiment, the server can access and configure the BAUDR register through the virtual address access interface and the offset address of the BAUDR register.

[0088] Specifically, the server obtains the SOC's base frequency and calculates the division factor based on the base frequency and the target communication rate. Then, the server writes the division factor into the BAUDR register through the virtual address access interface and the offset address access of the BAUDR register to set the communication rate of the SPI controller.

[0089] The baseband of the SOC is fixed in the SOC design. The calculation logic of the frequency division factor is the ratio of the system-on-chip baseband to the target communication rate, and the ratio is rounded up to ensure rate accuracy. In this embodiment, taking a baseband of 166.66 MHz and a target communication rate of 12 MHz as an example, the specific calculation process is 166.66 ÷ 12 ≈ 13.888, which is rounded up to obtain the frequency division factor, represented in hexadecimal as 0xE. The server accesses the BAUDR register through the virtual address access interface and the offset address of the BAUDR register, and writes the calculated frequency division factor 0xE into the BAUDR register.

[0090] S103: The server writes the data to be sent into the data register of the SPI controller through the virtual address access interface, so that the SPI controller can assemble the data to be sent into a message and send it.

[0091] The length of the data to be sent is the same as the length of the communication word configured in step S102 to avoid transmission errors caused by data length mismatch.

[0092] like Figure 3 As shown, Figure 3 This is a schematic diagram illustrating a data transmission process based on the SPI protocol, as provided in this application embodiment. The server accesses the DR register via the virtual address access interface and the DR register, and writes the data to be transmitted into the corresponding bit fields of the DR register according to the Motorola SPI frame format requirements. After the data is written, the SPI controller executes subsequent operations according to the initial configuration parameters, automatically pulls the chip select signal low, and sends a strobe command to the external device. Simultaneously, the SIP controller generates an SCLK clock signal according to the timing requirements of SPI mode 0, and transmits the data to be transmitted in the DR register bit by bit through the MOSI lines to the external device according to the frame format. Throughout the entire process, the hardware logic of the SPI controller automatically completes message assembly, timing control, and signal transmission without additional intervention from the software or application layers.

[0093] This embodiment of the application writes data directly to the DR register through the virtual address access interface and the offset address of the DR register. The redundant process of the SPI driver framework significantly shortens the transmission latency from the application layer to the hardware transmitter. Reducing the forwarding and processing stages of data within the SPI driver framework allows data to quickly reach the hardware buffer, improving the response speed of data transmission.

[0094] S104: The server polls the status bits of the SPI controller's status register through the virtual address access interface.

[0095] After writing the data to be sent into the DR register, such as Figure 3 As shown, the server can access the SR register in real time based on the virtual address access interface and the offset address of the SR register. The Receive FIFO Not Empty (RFNE) flag in the SR register is used to indicate whether the data buffer of the SPI controller stores data returned by the external device. When the RFNE bit is 1, it means that the DR register contains valid data and a read operation can be performed; when the RFNE bit is 0, it means that the DR register is empty and it is necessary to continue waiting.

[0096] The full-duplex nature of SPI communication requires synchronous data transmission and reception. After the data to be transmitted is written and transmission is initiated, the return data from the external device needs to be monitored in real time to ensure the integrity of bidirectional data interaction. The server reads the value of the status bit in the SR register at a preset period and interprets the level state of the RFNE bit. When the RFNE bit is 0, it indicates that the data buffer unit of the SPI controller is empty, meaning that the external device has not yet returned response data. At this time, the server continues to poll until the RFNE bit state changes. When the RFNE bit is 1, it indicates that the data buffer unit has stored the data returned by the external device, and the server stops periodically reading the status bit of the SR register.

[0097] In this embodiment, when the RFNE bit is 1, the server reads and caches the data in the DR register through the virtual address access interface and the offset address of the DR register. The data length returned by the external device is the same as the communication word length. For example, if the communication word length is configured to be 24 bits, the data returned by the external device is also 3 bytes. When reading, the corresponding 24-bit data segment in the DR register is directly extracted, ignoring invalid values ​​of irrelevant bits.

[0098] After reading, the 3 bytes of returned data are stored in the preset receive message buffer, completing the closed-loop operation of data reception. Throughout the process, both polling and read operations interact directly with the hardware registers through the virtual address access interface, without needing to go through the forwarding or data processing flow of the SPI driver framework.

[0099] The server also polls the Transmit FIFO Empty (TFE) flag and the BUSY flag in the SR register. The TFE flag indicates the Transmit FIFO status: a TFE of 1 indicates all data has been transmitted and the Transmit FIFO is empty; a TFE of 0 indicates data remains to be transmitted. The BUSY flag indicates the SPI controller's operating status: a BUSY of 1 indicates the SPI controller is in data transmission; a BUSY of 0 indicates the SPI controller is idle.

[0100] This application embodiment directly polls the status register through a virtual address access interface, avoiding the drawbacks of relying on interrupt responses from the SPI driver framework or reading feedback status via GPIO, and significantly reducing the latency of status monitoring.

[0101] S105: The server confirms whether the data to be sent has been sent based on the status bits in the status register.

[0102] In this embodiment, when the TFE bit is 1, it indicates that there is no data to be sent in the SPI controller's first-in-first-out transmission process, and all the data to be sent has been retrieved by the SPI controller and sent to the external device; if the TFE bit is 0, it indicates that some data has not yet been sent and we need to continue waiting.

[0103] For the BUSY bit, when the bit is 0, it indicates that the SPI controller has finished data transmission and is no longer in operation; the SCLK clock signal stops, and the chip select signal returns to a high level. If the BUSY bit is 1, it means that the controller is still performing transmission-related operations and needs to be continuously monitored.

[0104] When the TFE bit is 1 and the BUSY bit is 0, the server determines that the data to be sent has been completed. If either condition is not met, the server will continue to poll the SR register periodically until both the TFE bit and the BUSY bit reach the target level, ensuring the accuracy of the transmission completion judgment and avoiding problems such as premature termination of transmission or excessive waiting caused by misjudgment of a single status bit.

[0105] This application embodiment confirms the completion of transmission by verifying the status bit, avoiding the lag and uncertainty of relying on SPI driver framework feedback or GPIO signal judgment, shortening the judgment time, and further reducing the overall latency of SPI messages.

[0106] Meanwhile, the combined verification of the TFE and BUSY bits ensures that all data to be sent has been transmitted and confirms that the controller has returned to idle status, reserving a stable hardware state for subsequent message transmission and avoiding message overlap or timing conflicts. Furthermore, this judgment method requires no additional calculations or protocol parsing; the judgment can be completed solely through hardware status bit feedback, simplifying the judgment logic and reducing CPU resource consumption.

[0107] Based on the above method embodiments, this application also provides a communication device based on the SPI protocol, such as... Figure 4 As shown, the device includes:

[0108] The mapping module 401 is used to map the physical base address of the serial peripheral interface (SPI) controller in the system-on-a-chip to the virtual address space to obtain the virtual address access interface of the SPI controller; wherein, the virtual address access interface is used to directly access the registers of the SPI controller.

[0109] Configuration module 402 is used to perform initialization configuration of the SPI controller based on the virtual address access interface;

[0110] The sending module 403 is used to write the data to be sent into the data register of the SPI controller through the virtual address access interface, so that the SPI controller can assemble the data to be sent into a message and send it.

[0111] Polling module 404 is used to poll the status bits of the status register of the SPI controller through the virtual address access interface;

[0112] The confirmation module 405 is used to confirm whether the data to be sent has been sent completely based on the status bit of the status register.

[0113] In one possible implementation, the configuration module 402 is specifically used to access the first control register of the SPI controller according to the address offset of the virtual address access interface and the first control register, and configure the communication mode, transmission mode and frame format of the SPI controller; access the slave enable register of the SPI controller through the offset address of the virtual address access interface and the slave enable register, and select the target chip select signal; access the baud rate register of the SPI controller through the offset address of the virtual address access interface and the baud rate register, and set the communication rate; and access the first control register of the SPI controller through the offset address of the virtual address access interface and the control register, and determine the communication word length.

[0114] In one possible implementation, the configuration module 402 is specifically configured to set the serial clock polarity and serial clock phase of the first control register to 0, so that the communication mode of the SPI controller is SPI mode 0; configure the transmission mode bit of the first control register to transmit and receive mode; and configure the frame format bit of the first control register to Motorola SPI frame format.

[0115] In one possible implementation, before initializing the SPI controller, the configuration module 402 is further configured to access the enable register of the SPI controller according to the offset address of the virtual address access interface and the enable register, set the enable register to 0, and disable the SPI controller.

[0116] After initializing the SPI controller, the configuration module 402 is further configured to access the enable register of the SPI controller according to the offset address of the virtual address access interface and the enable register, set the enable register to 1, and enable the SPI controller.

[0117] In one possible implementation, the configuration module 402 is specifically used to obtain the base frequency of the system-on-a-chip; calculate the frequency division coefficient based on the base frequency and the target communication rate; and write the frequency division coefficient into the baud rate register through the virtual address access interface and the offset address access of the baud rate register to set the communication rate of the SPI controller.

[0118] In one possible implementation, the polling module 404 is further configured to poll the receive-first-out (FFIFO) non-empty flag of the status register through the virtual address access interface and the offset address of the status register; when the receive-first-out (FFIFO) non-empty flag is 1, the data in the data register is read through the virtual address access interface and the offset address of the data register and cached.

[0119] In one possible implementation, the confirmation module 405 is specifically used to read the transmit first-in-first-out empty flag and the module working flag of the status register through the virtual address access interface and the offset address of the status register; when the transmit first-in-first-out empty flag is 1 and the module working flag is 0, the data to be sent is confirmed to have been sent.

[0120] This application also provides a control device. The control device may include a memory and a processor. The processor is used to execute the SPI protocol-based communication method described in any of the above embodiments. The memory may be random access memory (RAM), flash memory, read-only memory (ROM), non-volatile read-only memory (EPROM), registers, hard disk, removable disk, etc.

[0121] Memory can store computer instructions, which, when executed by a processor, can be used to perform communication methods based on the SPI protocol. Memory can also store data.

[0122] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product. A computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the flow or function according to the embodiments of this application is generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape) or a semiconductor medium (e.g., solid-state disk (SSD)).

[0123] This application also provides a readable storage medium for storing the methods provided in the above embodiments. For example, RAM, flash memory, ROM, EPROM, registers, hard disk, removable disk, or any other form of storage medium in the art.

[0124] In the embodiments of this application, the terms "first" and "second" (if they exist) are used only as name identifiers and do not represent the order of first and second.

[0125] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. Regarding the methods disclosed in the embodiments, since they correspond to the product embodiments disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the description of the product embodiments.

[0126] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A communication method based on the SPI protocol, characterized in that, The method includes: The physical base address of the Serial Peripheral Interface (SPI) controller in the system-on-a-chip is mapped to the virtual address space to obtain the virtual address access interface of the SPI controller; wherein, the virtual address access interface is used to directly access the registers of the SPI controller; The SPI controller is initialized and configured based on the virtual address access interface. The data to be sent is written into the data register of the SPI controller through the virtual address access interface, so that the SPI controller assembles the data to be sent into a message and sends it. The status bits of the SPI controller's status register are polled through the virtual address access interface; The status register is used to determine whether the data to be sent has been successfully transmitted.

2. The method according to claim 1, characterized in that, The initialization configuration of the SPI controller based on the virtual address access interface includes: Access the first control register of the SPI controller according to the address offset of the virtual address access interface and the first control register, and configure the communication mode, transmission mode, frame format and communication word length of the SPI controller; Access the slave enable register of the SPI controller through the virtual address access interface and the offset address of the slave enable register to select the target chip select signal; The communication rate is set by accessing the baud rate register of the SPI controller through the virtual address access interface and the offset address of the baud rate register.

3. The method according to claim 2, characterized in that, The configuration of the SPI controller's communication mode, transmission mode, and frame format includes: Configure the serial clock polarity and serial clock phase of the first control register to 0, so that the communication mode of the SPI controller is SPI mode 0; Configure the transmission mode bit of the first control register to transmit and receive simultaneously; Configure the frame format bits of the first control register to the Motorola SPI frame format.

4. The method according to claim 2, characterized in that, Before initializing and configuring the SPI controller, the method further includes: Access the enable register of the SPI controller according to the offset address of the virtual address access interface and the enable register, set the enable register to 0, and disable the SPI controller; After initializing and configuring the SPI controller, the method further includes: Access the enable register of the SPI controller according to the virtual address access interface and the offset address of the enable register, set the enable register to 1, and enable the SPI controller.

5. The method according to claim 2, characterized in that, The step of accessing the SPI controller's baud rate register through the virtual address access interface and the offset address of the baud rate register to set the communication rate includes: Obtain the base frequency of the system-on-a-chip; Calculate the frequency division coefficient based on the base frequency and the target communication rate; The frequency division coefficient is written into the baud rate register through the virtual address access interface and the offset address access of the baud rate register to set the communication rate of the SPI controller.

6. The method according to claim 1, characterized in that, The method further includes: The receive first-in-first-out non-empty flag of the status register is polled by the virtual address access interface and the offset address of the status register. When the receive first-in-first-out non-empty flag is 1, the data in the data register is read and cached through the virtual address access interface and the offset address of the data register.

7. The method according to claim 1, characterized in that, The step of confirming whether the data to be sent has been sent completely based on the status bit of the status register includes: The transmit first-in-first-out empty flag and the module working flag of the status register are read through the virtual address access interface and the offset address of the status register. When the first-in-first-out empty flag is 1 and the module working flag is 0, it is confirmed that the data to be sent has been sent.

8. A communication device based on the SPI protocol, characterized in that, The device includes: A mapping module is used to map the physical base address of the serial peripheral interface (SPI) controller in the system-on-a-chip to a virtual address space to obtain the virtual address access interface of the SPI controller; wherein, the virtual address access interface is used to directly access the registers of the SPI controller; The configuration module is used to initialize and configure the SPI controller based on the virtual address access interface; The sending module is used to write the data to be sent into the data register of the SPI controller through the virtual address access interface, so that the SPI controller can assemble the data to be sent into a message and send it. The polling module is used to poll the status bits of the status register of the SPI controller through the virtual address access interface; The confirmation module is used to confirm whether the data to be sent has been sent completely based on the status bits of the status register.

9. A control device, characterized in that, It includes a processor and a memory, the memory being used to store programs, instructions, or code, and the processor being used to execute the programs, instructions, or code in the memory to perform the communication method based on the SPI protocol as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The device contains a computer program that is loaded by a processor to execute the communication method based on the SPI protocol as described in any one of claims 1-7.

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