Field effect transistor packaging defect self-checking system and method for AI server

Abstract

The invention provides an AI server-oriented field effect transistor packaging defect self-checking system and method. The method comprises the following steps: acquiring a first surface reflection image and a second surface reflection image at the top of a field effect transistor packaging body; extracting a pin contour mask of a field effect transistor pin area from a fusion reflection feature image generated by the first surface reflection image and the second surface reflection image; acquiring a third lateral scattering image in the direction of a third illumination axis; segmenting a pin region of interest from the third lateral scattering image based on a pin contour mask, and extracting a plurality of brightness profile curves in the pin region of interest along the direction perpendicular to the pin length; and identifying a mismatch index of the pin space topology form through all the brightness profile curves, and when the mismatch index is greater than a preset mismatch threshold value, determining that the field effect transistor has a packaging defect. According to the technical scheme provided by the invention, the packaging defect of pin topology form mismatch in the field effect transistor packaging process can be identified.

Description

Technical Field

[0001] This application relates to the field of packaging defect detection technology, and more specifically, to a self-inspection system and method for field-effect transistor packaging defects for AI servers. Background Technology

[0002] In semiconductor manufacturing and back-end packaging processes, the package plays a crucial role in providing mechanical support, environmental protection, and electrical interconnection for the chip. However, the packaging process is prone to various defects such as lead wire breakage, solder joint defects, plastic delamination, warping, and foreign contaminants, which seriously affect the reliability and lifespan of the device. Traditional manual visual inspection is difficult to meet the development needs of miniaturization and high density of modern electronic devices. Therefore, automatic defect detection technology based on machine vision and artificial intelligence has emerged. This technology can achieve rapid, accurate, and non-contact defect identification and classification, significantly improving production yield and product quality.

[0003] In existing packaging defect detection, the main approach is based on machine vision systems. First, high-resolution industrial cameras acquire images or 3D point cloud data of the packaged device. Then, image processing algorithms preprocess the images. Finally, feature extraction and analysis are used to identify defects, ultimately outputting the location, type, and severity level of the defect. However, in the detection of MOSFET packaging defects for AI servers, existing machine vision-based methods rely on vertical or high-angle illumination from the top of the package to capture surface scratches, breaks, or foreign object defects. For spatial topological mismatches (i.e., subtle bends or twists) in the pins, the traditional method's illumination path and imaging angle result in insufficient capture of geometric information from the pin sides. Furthermore, strong top specular reflection creates highlight areas, obscuring the grayscale gradient details characterizing the pin's 3D deformation. This hinders the identification of packaging defects caused by poor packaging processes leading to topological mismatches in MOSFET pins. Therefore, identifying packaging defects caused by pin topological mismatches during MOSFET packaging has become a major challenge for the industry. Summary of the Invention

[0004] This application provides a self-inspection system and method for field-effect transistor (FET) packaging defects for AI servers, which can identify packaging defects such as pin topology mismatch during the FET packaging process.

[0005] In a first aspect, this application provides a self-inspection method for field-effect transistor packaging defects in AI servers, comprising the following steps: Illumination is provided by a first ring light source and a second ring light source in the first illumination axis direction and the second illumination axis direction orthogonal to the top of the field effect transistor package, and corresponding first surface reflection images and second surface reflection images are acquired. The first surface reflection image and the second surface reflection image are subjected to weighted differential fusion processing to generate a fused reflection feature image, and the pin contour mask of the field-effect transistor pin region is extracted from the fused reflection feature image; In the direction of the third illumination axis below the plane of the field-effect transistor package, a non-polarized third linear light source is used to illuminate the pin area of ​​the field-effect transistor and the corresponding third lateral scattering image is acquired. Based on the pin profile mask, the region of interest of the pin is segmented from the third lateral scattering image, and a multi-scale line scan brightness profile analysis is performed on the region of interest of the pin. Then, multiple brightness profile curves are extracted along the direction perpendicular to the pin length in the brightness profile analysis. The mismatch index of the pin space topology is identified by all the brightness profile curves. When the mismatch index is greater than the preset mismatch threshold, it is determined that the field-effect transistor has a packaging defect.

[0006] In some embodiments, illumination is provided by a first ring light source and a second ring light source in the direction of the first illumination axis and the second illumination axis orthogonal to the top of the field-effect transistor package, and the corresponding first surface reflection image and second surface reflection image are acquired. Specifically, this includes: A first ring light source and a second ring light source are mounted at a predetermined position on the top of the field-effect transistor package, such that the illumination axes of the first ring light source and the second ring light source are arranged orthogonally, and the polarization direction of the first ring light source is set as the first polarization direction and the polarization direction of the second ring light source is set as the second polarization direction. After calibrating the illumination angle and intensity of the first and second ring light sources, the first ring light source is turned on alone, and the reflection image of the first surface on the top of the field-effect transistor package is acquired. The first ring light source is turned off and the second ring light source is turned on separately, and the reflection image of the second surface on the top of the field-effect transistor package is acquired.

[0007] In some embodiments, performing weighted differential fusion processing on the first surface reflection image and the second surface reflection image to generate a fused reflection feature image specifically includes: The first surface reflection image and the second surface reflection image are subjected to grayscale normalization processing to obtain the grayscale normalized first surface reflection image and the grayscale normalized second surface reflection image; Adaptive weighting coefficients are calculated based on the contrast features of the first surface reflection image and the second surface reflection image after gray-level normalization, resulting in the first weighting coefficient and the second weighting coefficient. The first weighting coefficient is used to weight the gray-level normalized first surface reflection image, and the second weighting coefficient is used to weight the gray-level normalized second surface reflection image, to obtain the weighted first surface reflection image and the weighted second surface reflection image. Pixel-level weighted difference operations are performed on the weighted first surface reflection image and the weighted second surface reflection image to obtain the difference feature image; The differential feature images are fused and enhanced to generate fused reflection feature images.

[0008] In some embodiments, extracting the pin contour mask of the field-effect transistor pin region from the fused reflection feature image specifically includes: The fused reflection feature image is preprocessed with Gaussian filtering to obtain a denoised fused reflection feature image; An adaptive threshold segmentation algorithm is used to process the denoised fused reflection feature image to obtain a binary image of the pin candidate region; Perform morphological opening and closing operations on the binary image of the candidate pin region to obtain the optimized binary image of the pin region. The pin edge contour is extracted from the optimized binary image of the pin region to obtain the pin contour information; The pin profile information is subjected to profile fitting and filling processing to generate a pin profile mask for the field-effect transistor pin region.

[0009] In some embodiments, segmenting the region of interest of the pin from the third lateral scattering image based on the pin contour mask specifically includes: The pin profile mask and the third side-scattering image are rigidly registered to obtain the registered third side-scattering image; The registered third lateral scattering image is then subjected to a pixel-level AND operation with the pin contour mask to obtain a candidate image of the pin region. Morphological filtering is performed on the candidate image of the pin region to obtain the optimized candidate image of the pin region; Connectivity analysis is performed on the optimized candidate images of the pin region to determine the region of interest for the pin.

[0010] In some embodiments, performing multi-scale line-scan brightness profile analysis on the region of interest of the pin, and then extracting multiple brightness profile curves along a direction perpendicular to the pin length in the brightness profile analysis specifically includes: A linear fitting detection along the pin length direction is performed on the region of interest of the pin to obtain a reference for the pin length direction; Based on the pin length direction reference, the scale level and scan step of the multi-scale line scan are set to obtain the multi-scale scan parameter set; The multi-scale scanning parameter set is used to perform a multi-scale line scan along the direction perpendicular to the pin length on the region of interest of the pin to obtain the original brightness data of the multi-scale scan; The original brightness data from the multi-scale scanning is subjected to profile interpolation and Gaussian smoothing to obtain a noise-reduced multi-scale brightness profile dataset. Extract the brightness value sequence corresponding to each scan line position from the noise-reduced multi-scale brightness profile dataset to generate multiple brightness profile curves along the direction perpendicular to the pin length.

[0011] In some embodiments, an image of the reflection from the first surface of the top of the field-effect transistor package is acquired using an industrial camera.

[0012] Secondly, this application provides a self-testing system for MOSFET packaging defects in AI servers, used to perform a self-testing method for MOSFET packaging defects in AI servers. The system includes: The acquisition module is used to illuminate the top of the field-effect transistor package with a first ring light source and a second ring light source in the direction of the first illumination axis and the second illumination axis orthogonal to each other, and to acquire the corresponding first surface reflection image and second surface reflection image. The processing module is used to perform weighted differential fusion processing on the first surface reflection image and the second surface reflection image to generate a fused reflection feature image, and extract the pin contour mask of the field-effect transistor pin region from the fused reflection feature image; The acquisition module is also used to illuminate the pin area of ​​the field-effect transistor with a non-polarized third linear light source in the direction of the third illumination axis below the plane of the field-effect transistor package, and to acquire the corresponding third lateral scattering image. The processing module is also used to segment the pin region of interest from the third lateral scattering image based on the pin contour mask, and to perform multi-scale line scan brightness profile analysis on the pin region of interest, thereby extracting multiple brightness profile curves along the direction perpendicular to the pin length in the brightness profile analysis. The execution module is used to identify the mismatch index of the pin space topology through all the brightness profile curves. When the mismatch index is greater than the preset mismatch threshold, it is determined that the field-effect transistor has a packaging defect.

[0013] Thirdly, this application provides a computer device, the computer device including a memory and a processor, the memory storing code, the processor being configured to acquire the code and execute the above-described self-inspection method for field-effect transistor packaging defects for AI servers.

[0014] Fourthly, this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described self-testing method for field-effect transistor packaging defects for AI servers.

[0015] The technical solutions provided by the embodiments disclosed in this application have the following beneficial effects: The self-inspection system and method for field-effect transistor (FET) package defects for AI servers provided in this application firstly illuminates the FET package using a first ring light source and a second ring light source in the first and second illumination axis directions orthogonal to the top of the FET package, and acquires corresponding first and second surface reflection images. Secondly, the first and second surface reflection images are weighted and differentially fused to generate a fused reflection feature image, and the pin contour mask of the FET pin region is extracted from the fused reflection feature image. Further, the FET pin region is illuminated using a non-polarized third linear light source in the third illumination axis direction below the FET package plane, and the corresponding third side-scattering image is acquired. Then, based on the pin contour mask, the pin region of interest is segmented from the third side-scattering image, and a multi-scale line scan brightness profile analysis is performed on the pin region of interest. In the brightness profile analysis, multiple brightness profile curves are extracted along the direction perpendicular to the pin length. Finally, the mismatch index of the pin spatial topology is identified through all the brightness profile curves. When the mismatch index is greater than a preset mismatch threshold, the FET is determined to have a package defect.

[0016] Therefore, this application can identify packaging defects caused by pin topology mismatch during the MOSFET packaging process. First, by using orthogonal first and second ring light sources to illuminate from two axial directions and acquire surface reflection images, the reflection characteristics of the MOSFET pin top can be completely captured from different angles, effectively eliminating the shadow blind spots caused by single-angle illumination and improving the clarity of the pin top contour. Second, by performing weighted differential fusion processing on the dual-surface reflection images and extracting the pin contour mask, the complementary features of the dual-angle images can be fused, suppressing interference from background noise and uneven illumination, generating a more prominent fused reflection image, and thus obtaining a precise pin contour mask, providing a reliable spatial reference for subsequent lateral scattering image region segmentation. Furthermore, by using a non-polarized third linear light source below the package plane to illuminate and acquire a third lateral scattering image, the pin sidewall area can be specifically illuminated. The non-polarized light source avoids the sidewall brightness unevenness problem caused by polarization interference, completely capturing the lateral morphological features of the pin and compensating for the top surface mismatch. This method addresses the technical limitations of traditional methods, such as the inability of particulate reflectance images to identify sidewall defects. It avoids the shortcomings of traditional methods where insufficient capture of geometric information from the pin's side surface is due to lighting path and imaging angle limitations. Furthermore, strong top specular reflection creates highlight areas that obscure the grayscale gradient details characterizing the pin's three-dimensional deformation. Next, based on a pin contour mask, the region of interest is segmented, and multi-scale line scanning brightness profile analysis is performed. This accurately defines the analysis range, eliminates interference from irrelevant background areas, and the multi-scale line scanning addresses both the macroscopic overall morphology of the pin's sidewall and the detection of microscopic fine defects. The extracted multiple brightness profile curves visually represent the differences in sidewall morphology at different pin locations. Finally, the mismatch index of the pin's spatial topology is calculated using the brightness profile curves to effectively identify the degree of spatial topological mismatch. The mismatch index is then compared with a preset threshold to determine the defect, achieving accurate pin defect identification. In summary, the technical solution provided in this application can identify pin topological mismatch packaging defects during the field-effect transistor packaging process. Attached Figure Description

[0017] Figure 1 This is an exemplary flowchart of a self-testing method for defects in the packaging of a field-effect transistor for an AI server, according to some embodiments of this application. Figure 2 This is an exemplary flowchart illustrating the determination of a fused reflection feature image according to some embodiments of this application; Figure 3 This is a schematic diagram of a self-testing system for defects in the packaging of a field-effect transistor for AI servers, as shown in some embodiments of this application. Figure 4 This is a schematic diagram of the structure of a computer device that implements a self-testing method for defects in the packaging of a field-effect transistor for an AI server, according to some embodiments of this application. Detailed Implementation

[0018] To better understand the technical solution of this application, the technical solution of this application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] refer to Figure 1 This figure is an exemplary flowchart of a self-testing method for defects in the packaging of a field-effect transistor for an AI server, according to some embodiments of this application. The figure mainly includes the following steps: In step S101, a first ring light source and a second ring light source are used to illuminate the top of the field-effect transistor package in the direction of the first illumination axis and the direction of the second illumination axis, which are orthogonal to each other, and the corresponding first surface reflection image and second surface reflection image are acquired.

[0020] It should be noted that the field-effect transistor (FET) package in this application refers to the FET package for AI servers. The FET package for AI servers in this application is a special package form adapted to the high computing power, high power density, and 24 / 7 high reliability operation requirements of AI servers. It is different from the FET packages in ordinary consumer electronics or industrial control fields. It mostly adopts miniaturized flat integrated structures such as QFN and DFN, and is equipped with a high conductivity copper alloy lead frame to shorten the current transmission path and reduce parasitic parameters. At the same time, the package substrate is made of ceramic-copper composite material and exposed pads are set. It is combined with high temperature resistant and heat aging resistant epoxy resin molding material to enhance heat dissipation performance. The pins are arranged symmetrically, and some high-end packages add an electromagnetic shielding layer to suppress electromagnetic interference generated by high-frequency switching. The fine pitch and short pin characteristics of this type of package make it prone to micro-cracks at the root, burrs at the end, lateral bending and other minor defects that are difficult to be identified by the naked eye.

[0021] In some embodiments, illumination is provided by a first ring light source and a second ring light source in the direction of the first illumination axis and the second illumination axis orthogonal to the top of the field-effect transistor package, and the corresponding first surface reflection image and second surface reflection image are acquired by the following steps: A first ring light source and a second ring light source are mounted at a predetermined position on the top of the field-effect transistor package, such that the illumination axes of the first ring light source and the second ring light source are arranged orthogonally, and the polarization direction of the first ring light source is set as the first polarization direction and the polarization direction of the second ring light source is set as the second polarization direction. After calibrating the illumination angle and intensity of the first and second ring light sources, the first ring light source is turned on alone, and the reflection image of the first surface on the top of the field-effect transistor package is acquired. The first ring light source is turned off and the second ring light source is turned on separately, and the reflection image of the second surface on the top of the field-effect transistor package is acquired.

[0022] In specific implementation, firstly, using a precision optical adjustment fixture, the first and second ring light sources are mounted at a preset position on top of the MOSFET package. The multi-dimensional fine-tuning function of the adjustment fixture ensures that the illumination axes of the two light sources are orthogonal, meaning the projections of the central rays from the two light sources onto the top plane of the MOSFET package form a 90° angle. Simultaneously, the polarization direction of the first ring light source is set to the first polarization direction using the built-in polarizer adjustment component, and the polarization direction of the second ring light source is set to the second polarization direction. The precision optical adjustment fixture is a standard optical fixture with micron-level positioning accuracy, and the polarizer adjustment component is a commonly used accessory for ring light sources that can set the target polarization direction. Secondly, a calibration method based on image grayscale uniformity is used to calibrate the illumination angle and intensity of the first and second ring light sources. Specifically, either ring light source is first turned on, and then... The camera acquires an initial image of the top of the package. The grayscale distribution features are extracted using an existing grayscale histogram analysis algorithm. The uniformity of the grayscale distribution is used to determine the suitability of the illumination angle and intensity. If the distribution is uneven, the illumination angle is fine-tuned using an adjustment frame, and the current is adjusted via the light source driver module to change the illumination intensity. This acquisition and analysis process is repeated until the grayscale distribution is uniform, completing the calibration. The light source driver module is a standard component controlling the brightness of the light source; intensity adjustment is achieved by changing the input current. After calibration, the first ring light source is turned on independently, and an industrial camera acquires a first surface reflection image of the top of the MOSFET package. This first surface reflection image refers to the image of the reflected light from the top of the MOSFET package under the illumination of the first ring light source. Finally, the first ring light source is turned off, and a second ring light source is turned on independently. Similarly, an industrial camera acquires a second surface reflection image of the top of the MOSFET package.

[0023] It should be noted that the second surface reflection image in this application refers to the reflection light imaging result of the top of the field-effect transistor package under the illumination of the second ring light source. The first surface reflection image and the second surface reflection image can capture the surface reflection features of the top of the field-effect transistor package under the illumination of ring light sources in the orthogonal illumination axis direction and different polarization directions, respectively. The two images can completely cover the surface details of the detection area on the top of the package through differentiated illumination angles and polarization attributes, effectively distinguish the difference in reflection characteristics between the pin area and the main body of the package, and avoid the detection blind spots and feature masking problems existing in single-direction or single-polarization light source illumination, providing basic data input for subsequent weighted differential fusion processing of the two images.

[0024] In step S102, the first surface reflection image and the second surface reflection image are subjected to weighted differential fusion processing to generate a fused reflection feature image, and the pin contour mask of the field-effect transistor pin region is extracted from the fused reflection feature image.

[0025] In some embodiments, reference Figure 2 As shown in the figure, this is an exemplary flowchart of determining a fused reflection feature image according to some embodiments of this application. In this embodiment, the first surface reflection image and the second surface reflection image are subjected to weighted differential fusion processing to generate a fused reflection feature image, which can be achieved by the following steps: In step S1021, the first surface reflection image and the second surface reflection image are subjected to grayscale normalization processing to obtain the grayscale normalized first surface reflection image and the grayscale normalized second surface reflection image. In step S1022, adaptive weighting coefficients are calculated based on the contrast features of the first surface reflection image and the second surface reflection image after gray-level normalization, to obtain the first weighting coefficient and the second weighting coefficient. In step S1023, the first weighting coefficient is used to weight the gray-level normalized first surface reflection image, and the second weighting coefficient is used to weight the gray-level normalized second surface reflection image, to obtain the weighted first surface reflection image and the weighted second surface reflection image. In step S1024, pixel-level weighted difference operation is performed on the weighted first surface reflection image and the weighted second surface reflection image to obtain the difference feature image; In step S1025, the differential feature image is fused and enhanced to generate a fused reflection feature image.

[0026] In specific implementation, firstly, the acquired first and second surface reflection images are processed using a linear gray-level normalization method. Specifically, the maximum and minimum pixel gray values ​​of the first and second surface reflection images are calculated respectively, and each pixel gray value is mapped to the standard gray-level range of 0-255 to obtain the gray-level normalized first and second surface reflection images. The gray-level normalized first and second surface reflection images refer to the first and second surface reflection images after gray-level range standardization. Next, the gray-level variances of the first and second surface reflection images after gray-level normalization are calculated separately. The magnitude of the gray-level variance directly represents the contrast strength of the image; the larger the value, the more significant the gray-level difference between the target area and the background area in the image, and the higher the contrast. The gray-level variances of the two images are summed to obtain the total variance. Then, the gray-level variances of the first and second surface reflection images are divided by this total variance to normalize the weighting coefficients, ensuring that the sum of the two weighting coefficients is 1. The two normalized values ​​obtained are the first weighting coefficients. The first weighting coefficient refers to the numerical parameter representing the weight ratio of the first surface reflection image during the fusion process, and the second weighting coefficient refers to the numerical parameter representing the weight ratio of the second surface reflection image during the fusion process. Further, the first weighting coefficient is multiplied at the pixel level by the gray-level normalized first surface reflection image, and the second weighting coefficient is multiplied at the pixel level by the gray-level normalized second surface reflection image, resulting in a weighted first surface reflection image and a weighted second surface reflection image. Then, pixel-level weighted difference is performed on the weighted first surface reflection image and the weighted second surface reflection image. The operation specifically involves subtracting the pixel values ​​at corresponding positions in the weighted first surface reflection image and the weighted second surface reflection image, and taking the absolute value to extract the differential reflection features of the two images, thus obtaining a differential feature image. The differential feature image refers to the intermediate image that represents the differential reflection features of the weighted first surface reflection image and the weighted second surface reflection image. Finally, the differential feature image is fused and enhanced using an existing histogram equalization method. Specifically, this is done by adjusting the distribution pattern of the image's grayscale histogram to improve the overall contrast of the image, strengthen the feature differences between the pin area and the background area, and generate a fused reflection feature image.

[0027] It should be noted that the fused reflection feature image in this application refers to a feature-enhanced optical image obtained by weighted differential fusion of the first surface reflection image and the second surface reflection image acquired under the illumination of ring light sources with different polarization directions along the orthogonal illumination axis. This fused reflection feature image integrates the differential surface reflection features of the first surface reflection image and the second surface reflection image. It effectively suppresses the background noise and detection blind zone generated by single light source illumination through weighted differential fusion, while enhancing the grayscale contrast and edge feature recognition between the MOSFET pin area and the main body of the package. It is the core basic image data for subsequent accurate extraction of the pin contour mask from the image.

[0028] In some embodiments, the extraction of the pin contour mask of the field-effect transistor pin region from the fused reflection feature image is achieved by the following steps: The fused reflection feature image is preprocessed with Gaussian filtering to obtain a denoised fused reflection feature image; An adaptive threshold segmentation algorithm is used to process the denoised fused reflection feature image to obtain a binary image of the pin candidate region; Perform morphological opening and closing operations on the binary image of the candidate pin region to obtain the optimized binary image of the pin region. The pin edge contour is extracted from the optimized binary image of the pin region to obtain the pin contour information; The pin profile information is subjected to profile fitting and filling processing to generate a pin profile mask for the field-effect transistor pin region.

[0029] In specific implementation, firstly, a Gaussian filtering algorithm is used to preprocess the fused reflection feature image by performing convolution operations. A weighted average of the gray values ​​of each pixel and its neighboring pixels in the fused reflection feature image is calculated using a set filtering kernel, thereby eliminating Gaussian noise and salt-and-pepper noise introduced during image acquisition, resulting in a denoised fused reflection feature image. The denoised fused reflection feature image refers to the fused reflection feature image that has undergone noise suppression. Secondly, the denoised fused reflection feature image is divided into local sub-blocks that completely cover the entire image using a 3×3 window. Then, the gray values ​​of all pixels within each local sub-block are calculated. The grayscale mean and grayscale variance are used to determine the local segmentation threshold for the corresponding sub-block (i.e., local segmentation threshold = grayscale mean ± correction coefficient × grayscale variance; the correction coefficient is an empirical parameter in the field of machine vision, and its core value range is usually set within the range of 0.1 to 2.0). Binarization is performed on the pixels within each local sub-block. Pixels with grayscale values ​​higher than the corresponding local segmentation threshold are identified as foreground pixels and assigned a value of 255, while pixels with grayscale values ​​lower than or equal to the corresponding local segmentation threshold are identified as background pixels and assigned a value of 0. Then, all binarized local sub-blocks are processed according to... The positions in the original image are stitched together to obtain a binary image of the pin candidate region containing only the foreground and background pin candidate regions. This binary image refers to a binary image that initially distinguishes the pin candidate region from the background region. Further, morphological opening and closing operations are used to process the binary image of the pin candidate region. First, the opening operation (erosion) eliminates isolated noise points and small burrs in the image. Then, the dilation operation restores the original contour shape of the pin region. Subsequently, the closing operation (dilation) fills in small holes inside the pin region. Finally, the erosion operation corrects the edge contour of the pin region. An optimized binary image of the pin region is obtained, which refers to a binary image of the pin region after noise interference is eliminated. Then, the Canny edge detection operator in image processing technology is used to extract edges from the optimized binary image of the pin region to obtain pin contour information, which refers to the set of pixels representing the edge position of the field-effect transistor pin region. Finally, the least squares method is used to perform curve fitting on the pin contour information to correct the edge offset generated during the contour extraction process. Then, the fitted closed contour is filled with the internal region to generate a pin contour mask of the field-effect transistor pin region.

[0030] It should be noted that the pin contour mask of the field-effect transistor (FET) pin area in this application refers to a binary template image that retains the pin area contour and internal area. The FET pin area is the core functional area for electrical connection and signal transmission between the FET and external circuits. The integrity and regularity of its spatial topology directly determine the assembly accuracy and electrical performance stability of the device. In this FET package defect self-inspection scheme, accurately determining the pin area can provide a clear target range for segmenting the pin region of interest based on the pin contour mask, effectively eliminating interference from irrelevant background areas such as the package body. At the same time, it defines a precise detection boundary for brightness profile analysis of multi-scale line scanning along the vertical pin length direction, ensuring that the extraction of the brightness profile curve is only for the effective area of ​​the pin.

[0031] In step S103, a non-polarized third linear light source is used to illuminate the pin area of ​​the field-effect transistor in the direction of the third illumination axis below the plane of the field-effect transistor package, and the corresponding third lateral scattering image is acquired.

[0032] In some embodiments, illuminating the pin region of the field-effect transistor (FET) with a non-polarized third linear light source in a third illumination axis direction below the plane of the FET package, and acquiring the corresponding third side-scattered image, is achieved through the following steps: A third illumination axis direction below the plane of the field-effect transistor package is determined, and a non-polarized third linear light source is erected in the direction of the third illumination axis. After adjusting the illumination angle and intensity of the third linear light source, the third linear light source is turned on separately to provide lateral illumination to the pin area of ​​the field-effect transistor and to acquire the corresponding third lateral scattering image.

[0033] In practice, firstly, the spatial position of the pin area is obtained based on the extracted pin contour mask. Then, the direction of the third illumination axis, which is lower than the plane of the MOSFET package, is determined by combining the plane height reference of the MOSFET package. Typically, the plane height reference of the package is used as the reference zero point. The distance between the plane containing the third illumination axis and this reference zero point needs to be controlled within 1 / 3 to 2 / 3 of the height of the pin extending out of the package. The logic behind setting this range is that if the distance below the package plane is too small, the illumination direction of the third linear light source tends to be close to top illumination, which cannot effectively excite the lateral scattered light of the pin to highlight the side contour defects. If the distance is too large, the light is easily blocked by the bottom of the package or the detection platform, making it difficult to cover the effective lateral detection area of ​​the pin. Then, a light source positioning fixture is used. A non-polarized third linear light source is fixed in the direction of the third illumination axis, which refers to the direction of the light source center illumination below the plane of the field-effect transistor package for lateral supplementary lighting of the pin area. Next, the illumination intensity of the third linear light source is adjusted by adjusting the driving current of the third linear light source. The illumination intensity refers to the power density parameter of the light projected by the third linear light source onto the pin area. Then, based on the lateral test image acquired after adjusting the illumination intensity, the pitch angle of the third linear light source is finely adjusted to adjust the illumination angle of the third linear light source. After adjusting the illumination angle and illumination intensity of the third linear light source, the third linear light source is turned on alone to provide lateral illumination to the pin area of ​​the field-effect transistor, and the corresponding third lateral scattering image is acquired by an industrial camera.

[0034] It should be noted that the third lateral scattering image in this application refers to an optical image that carries the lateral surface morphology and scattering characteristics of the field-effect transistor pin. The third lateral scattering image can effectively identify the scattering characteristics of the lateral surface of the field-effect transistor pin, serving as an effective supplement to the reflection image under top orthogonal illumination. It compensates for the blind spot in detection where the top view cannot clearly present the pin sidewall morphology. This image can accurately highlight defects such as micro-burrs, local defects, and lateral bending of the pin sidewall that are difficult to identify under top illumination. At the same time, it can reflect the spatial attitude deviation of the pin relative to the package plane. The lateral feature data it carries can be combined with the pin top contour information extracted by fusing the reflection feature image, providing three-dimensional feature support for the accurate correction of the pin spatial topology mismatch index, and effectively eliminating the possibility of misjudgment when relying solely on the top image for defect judgment.

[0035] In step S104, the region of interest for the pin is segmented from the third lateral scattering image based on the pin profile mask, and a multi-scale line scan brightness profile analysis is performed on the region of interest for the pin. Then, multiple brightness profile curves are extracted along the direction perpendicular to the pin length in the brightness profile analysis.

[0036] In some embodiments, segmenting the region of interest of the pin from the third lateral scattering image based on the pin profile mask is achieved using the following steps: The pin profile mask and the third side-scattering image are rigidly registered to obtain the registered third side-scattering image; The registered third lateral scattering image is then subjected to a pixel-level AND operation with the pin contour mask to obtain a candidate image of the pin region. Morphological filtering is performed on the candidate image of the pin region to obtain the optimized candidate image of the pin region; Connectivity analysis is performed on the optimized candidate images of the pin region to determine the region of interest for the pin.

[0037] In specific implementation, firstly, contour feature points of the pin region are extracted from the pin contour mask. These contour feature points include corner points and endpoints. Simultaneously, an edge detection algorithm is used to extract corresponding contour feature points of the pin's lateral edges from the third lateral scattering image. This constructs a mask feature point set and a scattering image feature point set. The mask feature point set and the scattering image feature point set refer to the sets of feature points representing key positions of the pin region in the pin contour mask and the third lateral scattering image, respectively. Then, a gray-level cross-correlation matching algorithm is used to match the two sets of feature points, filtering out corresponding feature point pairs in spatial location. Finally, the least squares method is used to fit and calculate the corresponding feature point pairs to obtain the solution. The rigid transformation parameters used for registration include translation, rotation angle, and scaling factor. These rigid transformation parameters are geometric transformation parameters that enable spatial alignment between the third side-scattered image and the pin contour mask. Based on the solved rigid transformation parameters, a geometric transformation operation is performed on the third side-scattered image, and bilinear interpolation is used to resample the pixel grayscale values ​​of the transformed image to obtain the registered third side-scattered image. This registered third side-scattered image is one that perfectly matches the spatial position of the pin contour mask and allows for direct pixel-level calculations. Next, the registered third side-scattered image is compared with the pin contour mask... A pixel-level AND operation is performed, that is, a logical multiplication is performed on the pixel values ​​of the corresponding positions in the third lateral scattering image and the pin contour mask. Only the pixel information of the lateral scattering image corresponding to the foreground region in the pin contour mask is retained, and invalid pixels in the background region are removed to obtain the pin region candidate image. The pin region candidate image refers to the selected pin lateral region image. Then, morphological filtering is used to optimize the pin region candidate image. An opening operation of erosion followed by dilation is used to eliminate isolated noise points and small artifacts in the image. Then, a closing operation of dilation followed by erosion is used to fill the small holes inside the pin region to obtain the optimized pin region candidate image. Image selection refers to removing noise and hole defects from the image to reveal the lateral region morphology of the pin. Finally, a connected component analysis algorithm is used to process the optimized pin region candidate image. By scanning, all interconnected pixel regions in the optimized pin region candidate image are marked and the morphological parameters of each region are calculated. The morphological parameters are the region areas. Then, based on a preset pin morphological feature threshold, connected regions that meet the requirements are selected as pin regions of interest. That is, connected regions whose areas corresponding to the morphological parameters are within the area threshold range are selected as pin regions of interest. This will not be elaborated here. The specific area threshold range can be set according to actual needs or based on expert knowledge.

[0038] It should be noted that, in this application, the region of interest for the pin refers to the image region that includes the effective lateral detection area of ​​the MOSFET pin. The core function of determining the region of interest for the pin is to accurately delineate the analysis range for pin lateral defect detection from the third lateral scattering image, effectively eliminating the influence of irrelevant interference factors such as the background area of ​​the package, the reflective noise of the detection platform, and stray light from the light source. This ensures that all subsequent feature extraction and defect analysis operations are focused on the effective lateral area of ​​the pin, providing a unified spatial benchmark for the subsequent integration of the top and lateral morphological features of the pin and the construction of a complete analysis model of the pin's spatial topology, thereby avoiding misjudgment of defects caused by interference features from irrelevant areas.

[0039] In some embodiments, multi-scale line-scan brightness profile analysis is performed on the region of interest of the pin, and multiple brightness profile curves are extracted along a direction perpendicular to the pin length in the brightness profile analysis, which is achieved by the following steps: A linear fitting detection along the pin length direction is performed on the region of interest of the pin to obtain a reference for the pin length direction; Based on the pin length direction reference, the scale level and scan step of the multi-scale line scan are set to obtain the multi-scale scan parameter set; The multi-scale scanning parameter set is used to perform a multi-scale line scan along the direction perpendicular to the pin length on the region of interest of the pin to obtain the original brightness data of the multi-scale scan; The original brightness data from the multi-scale scanning is subjected to profile interpolation and Gaussian smoothing to obtain a noise-reduced multi-scale brightness profile dataset. Extract the brightness value sequence corresponding to each scan line position from the noise-reduced multi-scale brightness profile dataset to generate multiple brightness profile curves along the direction perpendicular to the pin length.

[0040] In specific implementation, firstly, the Canny edge detection algorithm is used to extract the edges of the region of interest (ROI) of the pin, obtaining a set of pixels representing the edge contours on both sides of the pin. The pixel coordinates of this set are used as input data and substituted into a least-squares linear fitting model to solve for the parameters. By minimizing the sum of squared perpendicular distances from the pixels in this set to the fitted line, the slope and intercept parameters of the fitted line are calculated. This fitted line is then used as a reference direction traversing the ROI of the pin, thereby determining the pin length direction reference that characterizes the pin's extension direction. This pin length direction reference is used to define the scanning direction and ensure... The scan line is a reference straight line perpendicular to the pin extension direction. Secondly, based on the pin length direction reference, the scale level and scan step size of the multi-scale line scan are set to obtain a multi-scale scan parameter set. The scale level can be set to three levels according to actual needs. For example, the first scale level scan line length is 80 pixels, used to focus on the core area of ​​the pin to detect sidewall flatness; the second scale level scan line length is 100 pixels, used to cover the entire width of the pin to detect edge contours; and the third scale level scan line length is 120 pixels, used to cover the surrounding area of ​​the pin to detect the presence of epitaxial burrs. Simultaneously, the scan step size is set according to actual needs. The multi-scale scanning parameter set refers to the set of parameters used to standardize the multi-scale line scanning process. Further, based on the multi-scale scanning parameter set, a line-by-line scanning operation is performed on the pin's region of interest along a direction perpendicular to the pin's length direction reference. The grayscale values ​​of all pixels on each scan line are collected and recorded in positional order to obtain the original multi-scale scanning brightness data. This original multi-scale scanning brightness data refers to the set of scan line grayscale value sequences obtained by performing a line-by-line scanning operation on the pin's region of interest. Then, the original multi-scale scanning brightness data is further processed... Linear interpolation of the luminance profile is performed to fill in the missing luminance values ​​caused by pixel discreteness during the scanning process. A Gaussian filtering algorithm is then used to filter the original luminance data of the multi-scale scanning after interpolation, resulting in a denoised multi-scale luminance profile dataset. The denoised multi-scale luminance profile dataset refers to the set of luminance value sequences that have undergone interpolation and noise suppression. Finally, from the denoised multi-scale luminance profile dataset, the corresponding grayscale value sequences are extracted according to different scale levels and scan line positions. The position coordinates of each sequence are used as the horizontal axis and the grayscale value is used as the vertical axis for data mapping, generating multiple luminance profile curves along the direction perpendicular to the pin length.

[0041] It should be noted that the multiple brightness profile curves along the direction perpendicular to the pin length in this application refer to a set of curves that can characterize the grayscale distribution characteristics at different lateral positions of the pin. The multiple brightness profile curves are used to characterize the brightness distribution characteristics at different positions and scales along the direction perpendicular to the pin length within the region of interest of the pin. The shape of these curves is directly related to the morphological characteristics of the pin sidewall. The brightness profile curves corresponding to a normal and flat pin sidewall exhibit a uniform and symmetrical shape. However, when there are defects such as burrs, defects, or lateral bending on the pin sidewall, the curves will show local brightness abrupt changes, morphological distortions, or symmetry disruptions. At the same time, brightness profile curves at different scale levels can focus on the minute and fine defects and macroscopic overall defects of the pin sidewall, respectively, providing multi-dimensional data support for the accurate location and classification of defects.

[0042] In step S105, the mismatch index of the pin space topology is identified by all the brightness profile curves. When the mismatch index is greater than the preset mismatch threshold, it is determined that the field-effect transistor has a packaging defect.

[0043] In some embodiments, the mismatch index of the pin space topology is identified by all brightness profile curves using the following steps: Construct a standard brightness profile curve template for a field-effect transistor with defect-free pins; All brightness profile curves are normalized and aligned with the standard brightness profile curve template to obtain the normalized brightness profile curve to be detected. Calculate the morphological difference value between each normalized brightness profile curve to be detected and the standard brightness profile curve template to obtain a set of morphological difference values ​​for a single curve. The mismatch index of the pin space topology is determined based on the pin region position weights and the set of single curve shape difference values.

[0044] In practice, firstly, a large number of qualified samples of defect-free pins of the same type of field-effect transistor are collected. The same multi-scale line scanning and brightness profile analysis operations are performed on each qualified sample to obtain multiple sets of brightness profile curves under defect-free conditions. Individual differences and noise interference are eliminated using statistical averaging to construct a standard brightness profile curve template representing the normal topological morphology of the pins. This standard brightness profile curve template refers to a benchmark model of the brightness profile curve under defect-free conditions used to determine whether a pin has defects. Secondly, the core parameters of the standard brightness profile curve template are extracted. These core parameters include the total number of pixels, maximum brightness, and minimum brightness of the standard brightness profile curve template. The mean value of brightness and luminance are used to construct a normalized and aligned set of reference parameters. Then, for each brightness profile curve, a linear interpolation algorithm is used to resample the number of pixels, adjusting the curve length to perfectly match the total number of pixels in the standard brightness profile curve template, achieving normalized matching in the curve length dimension. Next, a linear transformation formula is used to calibrate the brightness amplitude of the length-normalized brightness profile curve, mapping the brightness value range of the brightness profile curve to the brightness value range of the standard brightness profile curve template, achieving normalized matching in the curve amplitude dimension. Finally, using the geometric midpoint of the standard brightness profile curve template as a reference, the brightness profiles with normalized length and amplitude are... The curve is translated and calibrated to obtain a normalized brightness profile curve to be tested. This normalized brightness profile curve refers to a curve that perfectly matches the standard template in both length and amplitude dimensions and can be directly compared in shape. Further, a mean square error algorithm is used to perform point-by-point comparison calculations between each normalized brightness profile curve and the standard brightness profile curve template, solving for the sum of the squares and mean values ​​of the deviations of the corresponding pixel brightness values ​​between the two curves. This sum is used as the shape difference value of a single brightness profile curve. The shape difference values ​​of all single brightness profile curves are combined to obtain a set of single curve shape difference values. This set of single curve shape difference values ​​refers to... The system consists of a set of numerical values ​​representing the degree of deviation between each test curve and the standard template. Finally, positional weights are assigned based on the sensitivity of different regions of the pin to defects, with the root and end regions having higher weights than the middle region. For example, the weight coefficients of the brightness profile curves corresponding to the root and end regions can both be set to 0.6, while the middle region of the pin has a relatively stable structure and a low defect rate, so its weight coefficient is set to 0.2. This is not a limitation. A weighted average algorithm is used to calculate the set of morphological difference values ​​of a single curve, and the calculation result is used as a quantitative parameter to measure the degree of deviation of the overall pin topology from the normal state, thereby obtaining the mismatch index of the pin spatial topology.

[0045] It should be noted that in this application, the mismatch index refers to an indicator used to determine whether there are packaging defects in the pins of a field-effect transistor. The mismatch index of the pin space topology serves as a quantitative evaluation indicator to measure the deviation of the pin space topology of the field-effect transistor under test from the defect-free standard state. It comprehensively integrates the differences in the brightness profile curve shape of different regions of the pin and the regional defect sensitivity weight. It can not only accurately determine whether there are sidewall defects such as burrs, defects, and lateral bending that are difficult to be identified from the top view by comparing with the preset qualified threshold, but also quantitatively characterize the severity of the defects according to the value of the mismatch index.

[0046] In specific implementation, the mismatch index is compared with a preset mismatch threshold. When the mismatch index is greater than the preset mismatch threshold, it is determined that the field-effect transistor has a packaging defect. When the mismatch index is less than or equal to the preset mismatch threshold, it is determined that the field-effect transistor does not have a packaging defect. The preset mismatch threshold can be set according to actual needs or according to expert knowledge, and is not limited here.

[0047] Furthermore, in another aspect of this application, in some embodiments, this application provides a self-inspection system for field-effect transistor packaging defects for AI servers, referencing... Figure 3 The figure is a schematic diagram of a self-testing system for defects in the packaging of a field-effect transistor (FET) for an AI server, according to some embodiments of this application. This self-testing system includes: a data acquisition module 201, a processing module 202, and an execution module 203, which are described below: The acquisition module 201 in this application is mainly used to illuminate the top of the field-effect transistor package with a first ring light source and a second ring light source in the direction of the first illumination axis and the second illumination axis orthogonal to each other, and to acquire the corresponding first surface reflection image and second surface reflection image. Processing module 202, in this application, is mainly used to perform weighted differential fusion processing on the first surface reflection image and the second surface reflection image to generate a fused reflection feature image, and to extract the pin contour mask of the field effect transistor pin region from the fused reflection feature image; The acquisition module 201 is also used to illuminate the pin area of ​​the field-effect transistor with a non-polarized third linear light source in the direction of the third illumination axis below the plane of the field-effect transistor package, and to acquire the corresponding third lateral scattering image. In addition, the processing module 202 is also used to segment the pin region of interest from the third lateral scattering image based on the pin contour mask, and perform multi-scale line scan brightness profile analysis on the pin region of interest, and then extract multiple brightness profile curves along the direction perpendicular to the pin length in the brightness profile analysis. The execution module 203 in this application is mainly used to identify the mismatch index of the pin space topology through all the brightness profile curves. When the mismatch index is greater than the preset mismatch threshold, it is determined that the field-effect transistor has a packaging defect.

[0048] In addition, this application also provides a computer device, the computer device including a memory and a processor, the memory storing code, the processor being configured to acquire the code and execute the above-described self-testing method for field-effect transistor packaging defects for AI servers.

[0049] In some embodiments, reference Figure 4 The figure is a schematic diagram of the structure of a computer device implementing a self-testing method for defects in the packaging of a field-effect transistor (FET) for an AI server, according to some embodiments of this application. The self-testing method for defects in the packaging of a FET for an AI server in the above embodiments can... Figure 4 The computer device shown is used to implement this, and the computer device includes at least one processor 301, a communication bus 302, a memory 303, and at least one communication interface 304.

[0050] The processor 301 can be a general-purpose central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more devices used to control the execution of the field-effect transistor package defect self-testing method for AI servers in this application.

[0051] The communication bus 302 can be used to transmit information between the aforementioned components.

[0052] The memory 303 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disks or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory 303 may exist independently and be connected to the processor 301 via the communication bus 302. The memory 303 may also be integrated with the processor 301.

[0053] The memory 303 stores program code for executing the solution of this application, and its execution is controlled by the processor 301. The processor 301 executes the program code stored in the memory 303. The program code may include one or more software modules. In the above embodiment, the determination of the self-testing method for field-effect transistor packaging defects for AI servers can be implemented by the processor 301 and one or more software modules in the program code in the memory 303.

[0054] Communication interface 304 uses any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area networks (WLAN), etc.

[0055] In a specific implementation, as one example, a computer device may include multiple processors, each of which may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. Here, a processor may refer to one or more devices, circuits, and / or processing cores used to process data (e.g., computer program instructions).

[0056] The aforementioned computer device can be a general-purpose computer device or a special-purpose computer device. In specific implementations, the computer device can be a desktop computer, a portable computer, a network server, a handheld digital assistant (PDA), a mobile phone, a tablet computer, a wireless terminal device, a communication device, or an embedded device. This application does not limit the type of computer device.

[0057] In addition, this application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described self-testing method for field-effect transistor packaging defects for AI servers.

[0058] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0059] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. An AI server-oriented field effect tube package defect self-checking method, characterized in that, Includes the following steps: Illumination is provided by a first ring light source and a second ring light source in the first illumination axis direction and the second illumination axis direction orthogonal to the top of the field effect transistor package, and corresponding first surface reflection images and second surface reflection images are acquired. The first surface reflection image and the second surface reflection image are subjected to weighted differential fusion processing to generate a fused reflection feature image, and the pin contour mask of the field-effect transistor pin region is extracted from the fused reflection feature image; In the direction of the third illumination axis below the plane of the field-effect transistor package, a non-polarized third linear light source is used to illuminate the pin area of ​​the field-effect transistor and the corresponding third lateral scattering image is acquired. Based on the pin profile mask, the region of interest of the pin is segmented from the third lateral scattering image, and a multi-scale line scan brightness profile analysis is performed on the region of interest of the pin. Then, multiple brightness profile curves are extracted along the direction perpendicular to the pin length in the brightness profile analysis. The mismatch index of the pin space topology is identified by all the brightness profile curves. When the mismatch index is greater than the preset mismatch threshold, it is determined that the field-effect transistor has a packaging defect.

2. The method of claim 1, wherein, Illumination is provided by a first ring light source and a second ring light source in the first illumination axis direction and the second illumination axis direction orthogonal to the top of the field-effect transistor package, and the corresponding first surface reflection image and second surface reflection image are acquired. Specifically, this includes: A first ring light source and a second ring light source are mounted at a predetermined position on the top of the field-effect transistor package, such that the illumination axes of the first ring light source and the second ring light source are arranged orthogonally, and the polarization direction of the first ring light source is set as the first polarization direction and the polarization direction of the second ring light source is set as the second polarization direction. After calibrating the illumination angle and intensity of the first and second ring light sources, the first ring light source is turned on alone, and the reflection image of the first surface on the top of the field-effect transistor package is acquired. The first ring light source is turned off and the second ring light source is turned on separately, and the reflection image of the second surface on the top of the field-effect transistor package is acquired.

3. The method of claim 1, wherein, The weighted differential fusion processing of the first surface reflection image and the second surface reflection image to generate a fused reflection feature image specifically includes: The first surface reflection image and the second surface reflection image are subjected to grayscale normalization processing to obtain the grayscale normalized first surface reflection image and the grayscale normalized second surface reflection image; Adaptive weighting coefficients are calculated based on the contrast features of the first surface reflection image and the second surface reflection image after gray-level normalization, resulting in the first weighting coefficient and the second weighting coefficient. The first weighting coefficient is used to weight the gray-level normalized first surface reflection image, and the second weighting coefficient is used to weight the gray-level normalized second surface reflection image, to obtain the weighted first surface reflection image and the weighted second surface reflection image. Pixel-level weighted difference operations are performed on the weighted first surface reflection image and the weighted second surface reflection image to obtain the difference feature image; The differential feature images are fused and enhanced to generate fused reflection feature images.

4. The method as described in claim 1, characterized in that, Extracting the pin contour mask of the field-effect transistor pin region from the fused reflection feature image specifically includes: The fused reflection feature image is preprocessed with Gaussian filtering to obtain a denoised fused reflection feature image; An adaptive threshold segmentation algorithm is used to process the denoised fused reflection feature image to obtain a binary image of the pin candidate region; Perform morphological opening and closing operations on the binary image of the candidate pin region to obtain the optimized binary image of the pin region. The pin edge contour is extracted from the optimized binary image of the pin region to obtain the pin contour information; The pin profile information is subjected to profile fitting and filling processing to generate a pin profile mask for the field-effect transistor pin region.

5. The method as described in claim 1, characterized in that, Segmenting the region of interest (ROI) of the pin from the third lateral scattering image based on the pin contour mask specifically includes: The pin profile mask and the third side-scattering image are rigidly registered to obtain the registered third side-scattering image; The registered third lateral scattering image is then subjected to a pixel-level AND operation with the pin contour mask to obtain a candidate image of the pin region. Morphological filtering is performed on the candidate image of the pin region to obtain the optimized candidate image of the pin region; Connectivity analysis is performed on the optimized candidate images of the pin region to determine the region of interest for the pin.

6. The method as described in claim 1, characterized in that, Multi-scale line-scan brightness profile analysis is performed on the region of interest of the pin, and multiple brightness profile curves are extracted along the direction perpendicular to the pin length in the brightness profile analysis. Specifically, this includes: A linear fitting detection along the pin length direction is performed on the region of interest of the pin to obtain a reference for the pin length direction; Based on the pin length direction reference, the scale level and scan step of the multi-scale line scan are set to obtain the multi-scale scan parameter set; The multi-scale scanning parameter set is used to perform a multi-scale line scan along the direction perpendicular to the pin length on the region of interest of the pin to obtain the original brightness data of the multi-scale scan; The original brightness data from the multi-scale scanning is subjected to profile interpolation and Gaussian smoothing to obtain a noise-reduced multi-scale brightness profile dataset. Extract the brightness value sequence corresponding to each scan line position from the noise-reduced multi-scale brightness profile dataset to generate multiple brightness profile curves along the direction perpendicular to the pin length.

7. The method as described in claim 2, characterized in that, An image of the reflection from the first surface of the top of the field-effect transistor package is captured using an industrial camera.

8. A self-testing system for defects in the packaging of field-effect transistors (FETs) for AI servers, used to execute the self-testing method for defects in the packaging of field-effect transistors for AI servers as described in any one of claims 1 to 7, characterized in that, The system includes: The acquisition module is used to illuminate the top of the field-effect transistor package with a first ring light source and a second ring light source in the direction of the first illumination axis and the second illumination axis orthogonal to each other, and to acquire the corresponding first surface reflection image and second surface reflection image. The processing module is used to perform weighted differential fusion processing on the first surface reflection image and the second surface reflection image to generate a fused reflection feature image, and extract the pin contour mask of the field-effect transistor pin region from the fused reflection feature image; The acquisition module is also used to illuminate the pin area of ​​the field-effect transistor with a non-polarized third linear light source in the direction of the third illumination axis below the plane of the field-effect transistor package, and to acquire the corresponding third lateral scattering image. The processing module is also used to segment the pin region of interest from the third lateral scattering image based on the pin contour mask, and to perform multi-scale line scan brightness profile analysis on the pin region of interest, thereby extracting multiple brightness profile curves along the direction perpendicular to the pin length in the brightness profile analysis. The execution module is used to identify the mismatch index of the pin space topology through all the brightness profile curves. When the mismatch index is greater than the preset mismatch threshold, it is determined that the field-effect transistor has a packaging defect.

9. A computer device, characterized in that, The computer device includes a memory and a processor, the memory storing code, and the processor being configured to retrieve the code and execute the self-inspection method for field-effect transistor package defects for AI servers as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the self-testing method for field-effect transistor packaging defects for AI servers as described in any one of claims 1 to 7.

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