Ripple control circuit based on frequency locking control and switching converter

Abstract

The invention provides a ripple control circuit based on frequency locking control and a switching converter, and the ripple control circuit comprises a first frequency-voltage conversion circuit which converts a complete period into a first voltage according to a driving signal of the switching converter; the second frequency-voltage conversion circuit is used for converting the work period into a second voltage according to a driving signal of the switching converter; the adjusting circuit generates a first adjusting signal according to the first voltage and the reference voltage when the first voltage is smaller than the second voltage, and the switching converter controls the complete period to be constant according to the first adjusting signal and controls the magnitude of the inductive current average value according to the magnitude of the load; the second voltage = K * the first voltage, and K is greater than 1. The ripple control circuit is provided based on the design of an existing frequency-locked loop, on one hand, frequency locking is achieved, and on the other hand, along with continuous reduction of a load, the ripple control circuit controls the conduction time of a power tube to be gradually reduced, so that inductive current ripples are gradually reduced, and output voltage ripples are reduced.

Description

Technical Field

[0001] This invention belongs to the field of switching power supplies, specifically relating to a ripple control circuit and a switching converter based on frequency locking control. Background Technology

[0002] like Figure 1 As shown, taking constant on-time control as an example, to achieve constant-frequency control of the switching converter, our company proposes using a frequency-locked loop to achieve a constant operating frequency. Specifically, the conversion circuit converts the reference frequency into a voltage Vref and the operating frequency into a voltage Vcs. The on-time of the main power transistor and the freewheeling transistor is then adjusted based on the voltage difference between the two, locking the on-time of the main power transistor and the freewheeling transistor to the reference period corresponding to the reference frequency, thereby achieving a constant operating frequency. Specifically, as shown... Figure 2 As shown, in CCM mode, the frequency-to-voltage conversion circuit converts the power transistor's on-time into voltage V1, thereby achieving constant power transistor on-time through feedback regulation, i.e., fixed-frequency control. As the load decreases, the switching converter exits CCM mode and enters DCM mode. In DCM mode, the frequency-to-voltage conversion circuit converts the power transistor's on-time into voltage V1, thereby achieving constant power transistor on-time through feedback regulation. Simultaneously, the switching converter increases the power transistor's off-time according to the decreasing load.

[0003] Therefore, because the conduction time of the power transistor controlled by the frequency-locked loop is constant, the inductor current ripple remains consistent in both CCM and DCM modes. However, in practical applications, it is necessary to reduce the output voltage ripple in some scenarios. Existing technologies often achieve this by reducing the energy transferred within a single switching cycle and lowering the inductor current ripple. However, further reduction of inductor current ripple often requires the introduction of additional control circuits, which inevitably leads to increased production costs and more complex control strategies. Summary of the Invention

[0004] To address the technical problem that frequency-locked loops prevent the inductor current ripple from maintaining consistency, thus hindering control of the power transistor's on-time and reducing output voltage ripple, this invention proposes a ripple control circuit and switching converter based on frequency-locked control. The frequency-locked control-based ripple control circuit includes:

[0005] The first frequency-to-voltage conversion circuit converts the complete cycle into a first voltage according to the drive signal of the switching converter;

[0006] The second frequency-to-voltage conversion circuit converts the operating cycle into a second voltage based on the drive signal of the switching converter;

[0007] The regulating circuit generates a first regulating signal based on the first voltage and a reference voltage when the first voltage is less than the second voltage. The switching converter controls the complete cycle to be constant based on the first regulating signal and controls the magnitude of the average inductor current based on the load size.

[0008] Wherein, when the first frequency-to-voltage conversion circuit and the second frequency-to-voltage conversion circuit convert the preset time into a voltage signal respectively, the second voltage = K * the first voltage, where K is greater than 1.

[0009] Furthermore, when the second voltage is less than or equal to the first voltage, the regulating circuit generates a second regulating signal based on the second voltage and the reference voltage. The switching converter controls the duty cycle to be constant based on the second regulating signal and controls the non-conducting time of the power transistor according to the load size.

[0010] Furthermore, the switching converter controls the complete cycle to remain constant as the reference cycle according to the first adjustment signal.

[0011] The switching converter controls its operating cycle to remain constant according to the second adjustment signal.

[0012]

[0013] The reference voltage represents the reference period.

[0014] Furthermore, when the switching converter controls the complete cycle to be constant according to the first adjustment signal, the switching converter controls the average value of the inductor current to be positively correlated with the load.

[0015] Furthermore, when the switching converter controls the operating cycle to be constant according to the second adjustment signal, the non-conduction time of the power transistor controlled by the switching converter is negatively correlated with the load.

[0016] Furthermore, in frequency locking control,

[0017] In both CCM and DCM modes, the switching converter controls the complete cycle to remain constant according to the first adjustment signal, so that the switching frequency of the switching converter remains constant at the reference frequency.

[0018] Alternatively, in DCM mode, the switching converter controls the duty cycle to remain constant according to the second adjustment signal, so that the operating frequency of the switching converter is constant at K*reference frequency;

[0019] The reference voltage represents the reference frequency.

[0020] Preferably, the first frequency-to-voltage conversion circuit includes a first capacitor, and the first frequency-to-voltage conversion circuit controls a first current to charge the first capacitor during a complete cycle, and the voltage of the first capacitor is a first voltage;

[0021] The second frequency-to-voltage conversion circuit includes a second capacitor. During the operating cycle, the second frequency-to-voltage conversion circuit controls a second current to charge the second capacitor, and the voltage of the second capacitor is a second voltage.

[0022] Wherein, the second current = K * the first current, and the capacitance values ​​of the first capacitor and the second capacitor are the same.

[0023] Furthermore, it also includes a signal processing circuit, which outputs a first clock signal based on the driving signal, and outputs a second clock signal based on the driving signal and the zero-crossing detection signal.

[0024] The first frequency-to-voltage conversion circuit receives a first clock signal and converts the duration of the first level state of the first clock signal into a first voltage.

[0025] The second frequency-to-voltage conversion circuit receives a second clock signal and converts the duration of the first level state of the second clock signal into a second voltage.

[0026] Preferably, the signal processing circuit includes a frequency divider and a logic circuit. The frequency divider divides the driving signal by two to output the first clock signal, and the logic circuit inverts the first clock signal and then performs an OR logic processing with the zero-crossing detection signal to output the second clock signal.

[0027] Preferably, the first frequency-to-voltage conversion circuit further includes a third capacitor connected in parallel with the first capacitor and a first reset switch connected in parallel with the first capacitor. The third capacitor is used to sample and hold the first voltage, and the first reset switch is used to reset the first capacitor.

[0028] The second frequency-to-voltage conversion circuit further includes a fourth capacitor connected in parallel with the second capacitor and a second reset switch connected in parallel with the second capacitor. The fourth capacitor is used to sample and hold the second voltage, and the second reset switch is used to reset the second capacitor.

[0029] Furthermore, the adjustment circuit performs differential operation on the first voltage and the reference voltage to obtain the first adjustment signal; the adjustment circuit performs differential operation on the second voltage and the reference voltage to obtain the second adjustment signal.

[0030] Furthermore, the control modes of the switching converter include constant period control and constant on-time control.

[0031] A switching converter, the switching converter including the ripple control circuit described above.

[0032] This invention proposes a ripple control circuit based on the design of existing frequency-locked loops. This ripple control circuit can achieve frequency locking on the one hand, and on the other hand, as the load decreases and the switching converter enters DCM mode from BCM mode, the ripple control circuit can control the conduction time of the power transistor to gradually decrease, thereby gradually reducing the inductor current ripple and reducing the output voltage ripple. Attached Figure Description

[0033] Figure 1 This is a structural diagram of the frequency-locked loop proposed by our company;

[0034] Figure 2 for Figure 1 Waveform changes during operation of the frequency-locked loop;

[0035] Figure 3 This is a block diagram of the ripple control circuit proposed in this invention;

[0036] Figure 4 The circuit diagram for the ripple control circuit is shown below.

[0037] Figure 5 The waveforms of each signal change when switching from CCM mode to DCM mode. Detailed Implementation

[0038] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0039] Based on the background technology, the frequency-locked loop control of our company maintains a constant power transistor conduction time in the switching converter, thereby ensuring consistent inductor current ripple in both CCM and DCM modes. Therefore, existing frequency-locked loops cannot smoothly control inductor current ripple reduction in DCM mode, thus failing to reduce output voltage ripple.

[0040] Based on the above situation, this invention proposes a ripple control circuit based on frequency locking control. This ripple control circuit can smoothly control the reduction of inductor current ripple in DCM mode, and this ripple control circuit is based on... Figure 1 The frequency-locked loop design shown is illustrated. That is, the ripple control circuit proposed in this invention uses... Figure 1 Based on the frequency-locked loop circuit shown, circuit improvements and adjustments to the control strategy are made to reduce inductor current ripple.

[0041] Specifically, such as Figure 3 As shown, the ripple control circuit proposed in this invention includes:

[0042] The first frequency-to-voltage conversion circuit converts the complete cycle into the first voltage according to the drive signal of the switching converter. In CCM mode, the complete cycle is the on-time of the power transistor, and in DCM mode, the complete cycle is the sum of the on-time and off-time of the power transistor.

[0043] The second frequency-to-voltage conversion circuit converts the drive signal of the switching converter into a second voltage, where the duty cycle is the on-time of the power transistor.

[0044] The regulating circuit generates a first regulating signal based on the first voltage and the reference voltage when the first voltage is less than the second voltage. The switching converter controls the full cycle to be constant based on the first regulating signal and controls the average value of the inductor current based on the load size.

[0045] When the second voltage is less than or equal to the first voltage, the regulating circuit generates a second regulating signal based on the second voltage and the reference voltage. The switching converter controls the duty cycle to be constant based on the second regulating signal and controls the non-conducting time of the power transistor according to the load size.

[0046] Among them, the first frequency-to-voltage conversion circuit and the second frequency-to-voltage conversion circuit need to meet certain conditions. When the first frequency-to-voltage conversion circuit and the second frequency-to-voltage conversion circuit convert the same time period into voltage, the first frequency-to-voltage conversion circuit outputs the first voltage, and the second frequency-to-voltage conversion circuit outputs the second voltage. The second voltage = K * the first voltage, where K is greater than 1.

[0047] Based on the above analysis, the output voltages of the first frequency-to-voltage conversion circuit and the second frequency-to-voltage conversion circuit have a certain proportional relationship (under the same operating conditions). Therefore, it is obvious that:

[0048] (1) In CCM mode (when the load size is constant), since the complete cycle is equal to the working cycle, the second voltage is always greater than the first voltage. The regulating circuit outputs the first regulating signal according to the first voltage and the reference voltage. The switching converter controls the complete cycle / working cycle to be constant as the reference cycle according to the first regulating signal, thereby realizing the constant switching frequency / working frequency. Switching frequency = 1 / complete cycle, working frequency = 1 / working cycle.

[0049] The reference voltage is output by a third frequency-to-voltage conversion circuit. This circuit converts the duration of the first level state of the reference clock signal into a reference voltage based on the reference clock signal. The reference voltage characterizes the reference period and reference frequency. Preferably, the first and third frequency-to-voltage conversion circuits are configured identically; that is, when both circuits convert the same time period into voltage, the output voltage of the first circuit is equal to the output voltage of the third circuit, thus ensuring that the switching frequency / operating frequency remains constant at the reference frequency.

[0050] (2) As the load decreases, the switching converter exits CCM mode and enters DCM mode. In the first stage, as the load decreases, the average inductor current gradually decreases, and the second voltage of the second frequency-voltage output generally shows a gradual decrease. However, the first voltage output by the first frequency-voltage conversion circuit is still lower than the second voltage. Therefore, in the first stage, the complete cycle remains constant as the reference cycle, but the average inductor current gradually decreases, the inductor current ripple gradually decreases, and the output voltage ripple gradually decreases. Obviously, the first stage includes CCM mode, BCM mode, and DCM mode.

[0051] Furthermore, in the first stage, if the load stops changing at a certain point in time, the switching converter will remain constant for the entire cycle according to the first adjustment signal, the average inductor current will remain unchanged, and the inductor current ripple will remain unchanged.

[0052] Furthermore, if the load continues to decrease, the second voltage continues to decrease. When the second voltage changes to be less than or equal to the first voltage, the second stage begins. In the second stage, the regulating circuit outputs a second regulating signal based on the second voltage and the reference voltage. The switching converter controls its operating cycle to remain constant based on the second regulating signal. Thereafter, the on-time of the power transistor remains constant, and the inductor current ripple remains constant. As the load decreases, the off-time of the power transistor gradually increases.

[0053] In the second stage, the switching converter maintains a constant duty cycle according to the second adjustment signal, thus ensuring a constant operating frequency. This frequency-locked control achieves a constant reciprocal of the power transistor's turn-on and turn-off cycles. Specifically, in the second stage, the second voltage equals the first voltage in the first stage, and the first voltage equals the reference voltage. Therefore, the duty cycle in the second stage equals the complete cycle / K of the first stage, which in turn equals the reference cycle / K. Thus, in DCM mode, when the switching converter controls its duty cycle according to the second adjustment signal, the switching converter's duty cycle will remain constant at the complete cycle / K of the first stage, and the inductor current ripple will become 1 / K of the inductor current ripple in CCM mode.

[0054] Based on the above analysis, this invention proposes a ripple control circuit based on the existing frequency-locked loop design. This ripple control circuit can lock the frequency (switching frequency or operating frequency) on the one hand, and on the other hand, as the load decreases and the switching converter enters the DCM mode from the BCM mode, the ripple control circuit can control the conduction time of the power transistor to gradually decrease, thereby gradually reducing the inductor current ripple and reducing the output voltage ripple.

[0055] The ripple control circuit proposed in this invention will be further explained below with reference to the specific circuit structure.

[0056] like Figure 3 and Figure 4 As shown, the first frequency-to-voltage conversion circuit includes a first capacitor C1 and a first current source I1, which are connected in series via a first switch M1. The second frequency-to-voltage conversion circuit includes a second capacitor C2 and a second current source I2, which are connected in series via a second switch M2. The third frequency-to-voltage conversion circuit includes a third capacitor C3 and a third current source I3, which are connected in series via a third switch M3. The first capacitor C1, the second capacitor C2, and the third capacitor C3 are identical capacitors. The output current of the first current source I1 is 1 / K of the output current of the second current source I2, where K > 1. Preferably, the output current of the third current source I3 is equal to the output current of the first current source I1. The adjustment circuit includes an operational amplifier OP. The first input terminal of the operational amplifier OP is connected to the output terminal of the third voltage-to-frequency conversion circuit. The second input terminal of the operational amplifier OP is connected to the output terminal of the first voltage-to-frequency conversion circuit via a first selection switch K1 and to the output terminal of the second voltage-to-frequency conversion circuit via a second selection switch K2. The signal processing circuit includes a frequency divider and logic circuits. Taking pulse width modulation (PWM) as an example, the frequency divider receives the PWM signal from the switching converter and divides the PWM signal by two to generate a first clock signal CLKA. The logic circuit inverts the first clock signal CLKA and then performs an OR operation with the zero-crossing detection signal ZCD to output a second clock signal CLKB. The first clock signal CLKA controls the on / off state of the first switch M1, and the second clock signal CLKB controls the on / off state of the second switch M2. The third frequency-to-voltage conversion circuit receives a preset clock signal output from the oscillator. The preset clock signal represents the reference period Tref and the reference frequency f. ref The preset clock signal controls the on / off state of the third switch M3.

[0057] In one embodiment, taking COT control as an example (the switching converter is not limited to this control method; other control schemes are also applicable, such as constant period control), K is set to 2. Figure 5This demonstrates the entire process of the switching converter switching from CCM mode to DCM mode as the load decreases. From cycle T1 to T3, the switching converter operates in CCM mode; in cycle T4, it enters BCM mode; and from cycle T5 to T8, it enters DCM mode.

[0058] The first clock signal CLKA, in a low-level state, controls the first switch M1 to turn on, so that the first current source I1 charges the first capacitor C1 to obtain the first voltage V1; the second clock signal CLKB, in a low-level state, controls the second switch M2 to turn on, so that the second current source I2 charges the second capacitor C2 to obtain the second voltage V2.

[0059] During cycles T1 to T4, the first frequency-to-voltage conversion circuit samples the on-time (Ton + Toff) of the power transistor, and the second frequency-to-voltage conversion circuit also samples the on-time (Ton + Toff). Since I2 = 2 * I1, it is obvious that V2 = 2 * V1. At this time, by comparing V2 and V1, a selection signal is output to control the first selection switch K1 to turn on. The operational amplifier OP receives V1 and Vref to output a first adjustment signal. Feedback adjustment is performed based on the first adjustment signal to achieve a reference period Tref for the cycle from T1 to T4, with the switching frequency remaining constant at the reference frequency f. ref During periods T1 to T4: I1*(Ton+Toff)=I1*Tref=Vref. Simultaneously, during periods T1 to T4, as the load gradually decreases, the switching converter controls the average inductor current to gradually decrease, thereby reducing the average output current. There are several ways to control the average inductor current based on the load size. For example... Figure 5 As shown, this is achieved by reducing the valley value. Alternatively, it can be achieved by reducing the peak value, reducing Ton, etc. The specific method used depends on the actual needs.

[0060] During cycles T5 to T6, the first frequency-to-voltage conversion circuit samples the sum of the power transistor's on-time and off-time (Ton + Toff + Td), while the second frequency-to-voltage conversion circuit samples the power transistor's on-time (Ton + Toff). During this process, the first voltage V1 remains constant, while the second voltage V2 gradually decreases. However, V2 is still greater than V1, so the operational amplifier OP continues to receive V1 and Vref to output the first adjustment signal, controlling the period from T5 to T6 as the reference period Tref, and keeping the switching frequency constant at the reference frequency f. refSimilarly, during the period from T5 to T6, I1*(Ton+Toff+Td)=I1*Tref=Vref. Meanwhile, during the period from T5 to T6, as the load gradually decreases, the switching converter will further reduce the average inductor current to lower the output current.

[0061] During cycle T7, V2 decreases to equal V1. Therefore, by comparing V1 and V2, the second selection switch K2 is turned on. The operational amplifier OP receives V2 and Vref to output the second adjustment signal, controlling the power transistor's on-time during cycle T7 to be half of the reference cycle Tref. When V1 = V2, 2*I1*(Ton'+Toff') = I1*(Ton+Toff+Td) = I1*Tref = Vref. Here, Ton+Toff+Td is the complete cycle of cycle T6, and Ton'+Toff' is the on-time of the power transistor during cycle T7. Therefore, Ton'+Toff' = Tref / 2. Thus, during cycle T7, the switching converter controls the operating cycle to remain constant at half of the reference cycle Tref according to the second adjustment signal, and the operating frequency to remain constant at the reference frequency 2*f. ref .

[0062] During the period from T8 to T9, the load is further reduced. At this time, since the second frequency-to-voltage conversion circuit samples the on-time of the power transistor, and the switching converter controls the on-time of the power transistor to be constant, the inductor current ripple remains unchanged, and the non-conducting time of the power transistor increases.

[0063] like Figure 4 As shown, the first frequency-to-voltage conversion circuit further includes a third capacitor C3 connected in parallel with the first capacitor C1, and a first reset switch Q1 connected in parallel with the first capacitor C1. The third capacitor C3 is used to sample and hold the first voltage V1, and the first reset switch Q1 is used to reset the first capacitor C1. The second frequency-to-voltage conversion circuit further includes a fourth capacitor C4 connected in parallel with the second capacitor C2, and a second reset switch Q2 connected in parallel with the second capacitor C2. The fourth capacitor C4 is used to sample and hold the second voltage V2, and the second reset switch Q2 is used to reset the second capacitor C2. It is a conventional technique that outputs a pulse signal at the end of sampling for both the first and second capacitors within a single cycle to control the sample-and-hold and reset functions. This will not be described in detail here.

[0064] It should be noted that, in order to simplify the design of the ripple signal control circuit and ensure that the first and second capacitors have sufficient time to reset to zero, the first and second frequency-to-voltage conversion circuits in this embodiment sample every other cycle. Therefore, in actual control, the on-time of the power transistor in DCM mode may have decreased to 1 / K of the reference period Tref, but due to the phase difference of one cycle, the second selection switch K2 cannot be switched on in time, thus controlling the second selection switch K2 when the second voltage V2 < Vref. However, this will not affect the result that the on-time of the power transistor is constant at 1 / K of the reference period Tref. Eventually, feedback adjustment will make the on-time of the power transistor constant at 1 / K of the reference period Tref. In other embodiments, the design of the ripple signal control circuit can also be optimized so that the first and second frequency-to-voltage conversion circuits sample continuously every cycle. In this design, the reset problem of the capacitors needs to be carefully considered.

[0065] It should be noted that, Figure 5 The diagram shows the load continuously decreasing from cycle T1 to T8. However, in reality, the load remains constant during cycle T5. Correspondingly, subsequent cycles repeat the process of cycle T5. In this case, the complete cycle is constant, the inductor current ripple no longer decreases but remains stable, and the power transistor's on-time no longer shortens but remains constant. Similarly, the load can stop changing within any cycle shown in the diagram. Furthermore, there are multiple switching cycles between any two adjacent cycles from T1 to T4. Cycles T1 to T4 only illustrate the specific situation when the load is stable at a certain value; the dynamic adjustment process within adjacent cycles is the combined effect of the entire system, including not only the aforementioned ripple control.

[0066] also, Figure 5 The illustration shows a scenario where the load gradually decreases. In reality, the load can also gradually increase. When the load gradually increases, the ripple control circuit operates as described above, but its operation is the reverse of the previous process. In DCM mode, when the switching converter maintains a constant duty cycle based on the second adjustment signal, as the load gradually increases, the non-conducting time of the power transistor gradually decreases while the on-time remains constant. The first voltage V1 gradually decreases, while the second voltage V2 remains constant. When the first voltage V1 decreases to below the second voltage V2, the switching converter switches to using the complete cycle controlled by the first adjustment signal as the reference cycle. Furthermore, as the load increases, the average inductor current gradually increases, and the second voltage V2 generally shows a gradual increasing trend. The process of gradually increasing load is not detailed here; for a more specific example, refer to the process of gradually decreasing load, as the two processes are reversed.

[0067] The above embodiment uses K=2 for explanation. Similarly, the operation of the ripple control circuit is as described above when K takes other values. In CCM mode, the switching converter controls the complete cycle to be constant at the reference period Tref according to the first adjustment signal. As the load gradually decreases, the switching converter switches at a certain moment to control the working cycle to be constant at 1 / K of the reference period Tref according to the second adjustment signal. Thus, as the load decreases, the ripple control circuit not only locks the switching frequency but also smoothly reduces the on-time of the power transistor and the inductor current ripple, thereby reducing the output voltage ripple.

[0068] The present invention also proposes a switching converter that includes the ripple control circuit described above.

[0069] It should be noted that the specific implementations and corresponding illustrations provided are merely one way of describing the implementation method of the present invention, and are not intended to limit the specific structure of the implementation scheme of the present invention. Various changes or modifications can be made to these implementation schemes without departing from the principles and essence of the present invention, but all such changes and modifications fall within the protection scope of the present invention.

[0070] Although the embodiments are described and illustrated separately above, some common technologies are involved. Those skilled in the art can replace and integrate them between the embodiments. If there is any content not explicitly described in one embodiment, then another embodiment that is described can be referred to.

[0071] The embodiments described above do not constitute a limitation on the scope of protection of this technical solution. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the above embodiments should be included within the scope of protection of this technical solution.

Claims

1. A ripple control circuit based on frequency locking control, characterized in that, include: The first frequency-to-voltage conversion circuit converts the complete cycle into a first voltage according to the drive signal of the switching converter; The second frequency-to-voltage conversion circuit converts the operating cycle into a second voltage based on the drive signal of the switching converter; The regulating circuit generates a first regulating signal based on the first voltage and a reference voltage when the first voltage is less than the second voltage. The switching converter controls the complete cycle to be constant based on the first regulating signal and controls the magnitude of the average inductor current based on the load size. Wherein, when the first frequency-to-voltage conversion circuit and the second frequency-to-voltage conversion circuit convert the preset time into a voltage signal respectively, the second voltage = K * the first voltage, where K is greater than 1.

2. The ripple control circuit as described in claim 1, characterized in that, When the second voltage is less than or equal to the first voltage, the regulating circuit generates a second regulating signal based on the second voltage and the reference voltage. The switching converter controls the duty cycle to be constant based on the second regulating signal and controls the non-conducting time of the power transistor based on the load size.

3. The ripple control circuit as described in claim 2, characterized in that, The switching converter controls the complete cycle to remain constant as the reference cycle according to the first adjustment signal. The switching converter controls its operating cycle to remain constant according to the second adjustment signal. The reference voltage represents the reference period.

4. The ripple control circuit as described in claim 1, characterized in that, When the switching converter controls the complete cycle to be constant according to the first adjustment signal, the switching converter controls the average value of the inductor current to be positively correlated with the load.

5. The ripple control circuit as described in claim 2, characterized in that, When the switching converter controls the operating cycle to be constant according to the second adjustment signal, the non-conduction time of the power transistor controlled by the switching converter is negatively correlated with the load.

6. The ripple control circuit as described in claim 1, characterized in that, In frequency locking control In both CCM and DCM modes, the switching converter controls the complete cycle to remain constant according to the first adjustment signal, so that the switching frequency of the switching converter remains constant at the reference frequency. Alternatively, in DCM mode, the switching converter controls the duty cycle to remain constant according to the second adjustment signal, so that the operating frequency of the switching converter is constant at K*reference frequency; The reference voltage represents the reference frequency.

7. The ripple control circuit as described in claim 1, characterized in that, The first frequency-to-voltage conversion circuit includes a first capacitor. During a complete cycle, the first frequency-to-voltage conversion circuit controls a first current to charge the first capacitor, and the voltage of the first capacitor is a first voltage. The second frequency-to-voltage conversion circuit includes a second capacitor. During the operating cycle, the second frequency-to-voltage conversion circuit controls a second current to charge the second capacitor, and the voltage of the second capacitor is a second voltage. Wherein, the second current = K * the first current, and the capacitance values ​​of the first capacitor and the second capacitor are the same.

8. The ripple control circuit as described in claim 7, characterized in that, It also includes a signal processing circuit, which outputs a first clock signal based on the drive signal, and outputs a second clock signal based on the drive signal and the zero-crossing detection signal. The first frequency-to-voltage conversion circuit receives a first clock signal and converts the duration of the first level state of the first clock signal into a first voltage. The second frequency-to-voltage conversion circuit receives a second clock signal and converts the duration of the first level state of the second clock signal into a second voltage.

9. The ripple control circuit as described in claim 8, characterized in that, The signal processing circuit includes a frequency divider and a logic circuit. The frequency divider divides the driving signal by two to output the first clock signal. The logic circuit inverts the first clock signal and then performs an OR logic processing with the zero-crossing detection signal to output the second clock signal.

10. The ripple control circuit as described in claim 7, characterized in that, The first frequency-to-voltage conversion circuit further includes a third capacitor connected in parallel with the first capacitor and a first reset switch connected in parallel with the first capacitor. The third capacitor is used to sample and hold the first voltage, and the first reset switch is used to reset the first capacitor. The second frequency-to-voltage conversion circuit further includes a fourth capacitor connected in parallel with the second capacitor and a second reset switch connected in parallel with the second capacitor. The fourth capacitor is used to sample and hold the second voltage, and the second reset switch is used to reset the second capacitor.

11. The ripple control circuit as described in claim 1, characterized in that, The adjustment circuit uses a differential operational amplifier to obtain the first adjustment signal by applying a differential operational amplifier to the first voltage and the reference voltage; the adjustment circuit uses a differential operational amplifier to obtain the second adjustment signal by applying a differential operational amplifier to the second voltage and the reference voltage.

12. The ripple control circuit as described in claim 1, characterized in that, The control modes of the switching converter include constant period control and constant on-time control.

13. A switching converter, characterized in that, The switching converter includes the ripple control circuit according to any one of claims 1-12.

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