High-noise suppression frequency-locked loop circuit based on closed-loop power supply tuning and control method

Abstract

The invention belongs to the technical field of integrated circuit design, and discloses a high-noise suppression frequency-locked loop circuit based on closed-loop power supply tuning and a control method. A current comparator in the frequency-locked loop circuit is used for generating an error current signal; the loop filter is used for generating a control voltage based on the error current signal; the low dropout linear regulator receives the control voltage and takes the output voltage as the power supply voltage and the frequency tuning voltage of the voltage-controlled oscillator at the same time; the voltage-controlled oscillator performs frequency tuning through the change of the output voltage to generate an output clock signal; and the frequency divider is used for carrying out frequency division on the output clock signal, generating a feedback clock signal and transmitting the feedback clock signal to the current comparator to be compared with the reference current so as to form a closed-loop control path. The output voltage of the low dropout linear regulator is multiplexed as the tuning voltage of the voltage-controlled oscillator and is introduced into the frequency-locked loop feedback loop, so that an independent, clean and voltage-adjustable power supply domain is provided, and the frequency stability and the phase purity are improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a high noise suppression frequency-locked loop circuit and control method based on closed-loop power supply tuning. Background Technology

[0002] Frequency-locked loop circuits, as key modules in modern integrated circuit systems, are widely used in clock generation, frequency synthesis, and data recovery.

[0003] In traditional frequency-locked loop (LLL) designs, the voltage-controlled oscillator (VCO) is typically powered directly by the system's main power supply. However, the main power supply contains significant noise from digital circuit switching, analog circuit operation, and external interference sources. This noise couples to the VCO through the power lines, directly affecting the stability of the oscillation frequency and causing severe phase noise and frequency jitter in the output clock signal. Particularly in on-chip systems, the high-speed switching of digital circuits generates substantial voltage fluctuations on the power and ground lines. These fluctuations propagate through the common power network to the LLL circuit, severely degrading its performance.

[0004] Currently, while some methods exist to mitigate the impact of power supply noise, such as increasing power supply decoupling capacitors or using independent power supply pins, these methods only alleviate the problem to a certain extent and cannot fundamentally solve the interference of power supply noise on voltage-controlled oscillators. Furthermore, power supply decoupling capacitors have limited effectiveness in suppressing high-frequency noise, while independent power supply pins increase chip packaging costs and design complexity, and still cannot completely isolate noise.

[0005] Furthermore, traditional voltage-controlled oscillators (VCOs) in frequency-locked loops employ direct voltage control, where changes in the control voltage directly adjust the oscillation frequency. This approach has two significant drawbacks: noise on the control voltage is directly coupled to the oscillation frequency, resulting in frequency modulation noise; and the conversion characteristics from control voltage to frequency are often nonlinear, affecting the adjustment accuracy and stability of the frequency-locked loop. Simultaneously, voltage-domain phase-frequency detectors are susceptible to power supply noise and substrate noise, resulting in low comparison accuracy and making precise frequency locking difficult to achieve in noisy environments. Summary of the Invention

[0006] The purpose of this invention is to provide a high noise suppression frequency-locked loop circuit and control method based on closed-loop power supply tuning, so as to achieve high noise suppression, high frequency accuracy and adaptive power consumption optimization.

[0007] To address the aforementioned technical problems, this invention provides a high-noise suppression frequency-locked loop circuit based on closed-loop power supply tuning, comprising: A current comparator is used to compare a reference current with a feedback current and generate an error current signal based on the comparison result. A loop filter, connected to the current comparator, is used to generate a control voltage based on the error current signal; The low dropout linear regulator, as a component of the closed-loop feedback path of the frequency-locked loop circuit, receives the control voltage output from the loop filter at its input terminal and connects to a voltage-controlled oscillator at its output terminal. It is used to convert the control voltage into a dynamically adjustable output voltage and to use the output voltage as both the power supply voltage and the frequency tuning voltage of the voltage-controlled oscillator. The voltage-controlled oscillator is connected to the low-dropout linear regulator and is frequency-tuned by the change of the output voltage to generate an output clock signal. The frequency divider, connected to the voltage-controlled oscillator and the current comparator, is used to divide the output clock signal to generate a feedback clock signal, and then send the feedback clock signal to the current comparator to form a closed-loop control path.

[0008] Furthermore, the current comparator includes a first operational amplifier, a second operational amplifier, a first resistor, a first capacitor, a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor; The non-inverting input of the first operational amplifier is connected to a first reference voltage; The gate of the first PMOS transistor is connected to the output terminal of the first operational amplifier, the source is connected to the power supply voltage, and the drain is connected to the inverting input terminal of the first operational amplifier. The drain of the first PMOS transistor is also grounded through the first resistor. The gate of the second PMOS transistor is connected to the output terminal of the first operational amplifier, the source is connected to a reference current, and a comparison connection point is formed at the drain. The non-inverting input of the second operational amplifier is connected to a second reference voltage; The gate of the first NMOS transistor is connected to the output terminal of the second operational amplifier, the drain is connected to the comparator connection point, and the source is connected to the inverting input terminal of the second operational amplifier. The source of the first NMOS transistor is also grounded through the first capacitor.

[0009] Furthermore, the current comparator also includes a switching network, which includes a second capacitor, a third capacitor, a first switch, a second switch, a third switch, and a fourth switch; One end of the first switch and the second switch are connected to the source of the first NMOS transistor, and the other end are respectively connected to one end of the second capacitor and one end of the third capacitor. The other ends of the second capacitor and the third capacitor are both connected to ground. The first switch and the second switch are controlled by a first clock signal and a second clock signal, respectively. The third switch is connected between one end of the second capacitor and ground, and is controlled by the second clock signal; The fourth switch is connected between one end of the third capacitor and ground, and is controlled by the first clock signal.

[0010] Furthermore, the loop filter includes a second resistor and a fourth capacitor; One end of the second resistor is connected to the comparison connection point, and the other end is grounded through the fourth capacitor.

[0011] Furthermore, the low-dropout linear regulator includes a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor, a fifth capacitor, and a sixth capacitor; The drain of the second NMOS transistor is connected to the first current source, the gate is connected to the first bias voltage, and the source is grounded through the second current source. The source of the third PMOS transistor is connected to the power supply voltage, and the gate is connected between the first current source and the drain of the second NMOS transistor, forming an X connection point. The source of the fourth PMOS transistor is connected to the drain of the third PMOS transistor, forming a Z-connection point; the drain of the fourth PMOS transistor is grounded through the second current source, and the gate is connected to the control voltage. One end of the fifth capacitor is connected between the source of the second NMOS transistor and the second current source, forming a Y connection point; the other end of the fifth capacitor is connected to the Z connection point. The Z-connection point outputs the output voltage; One end of the sixth capacitor is connected to the Z connection point, and the other end is grounded.

[0012] Furthermore, the voltage-controlled oscillator includes a bias voltage supply unit, multiple cascaded delay units, and an output buffer unit; The bias voltage providing unit provides a bias current to each of the delay cascade units according to the output voltage; Multiple delay cascade units are connected in series, with the output of the last delay cascade unit outputting a first voltage signal. The delay cascade unit is used to generate a ring oscillation and adjust the oscillation frequency according to the output voltage. The output buffer unit is connected to the output terminal of the delay cascade unit, and the first voltage signal is output as the output clock signal after being buffered by the output buffer unit.

[0013] Furthermore, the bias voltage providing unit includes a fifth PMOS transistor, an enable switch, and a third NMOS transistor; The source of the fifth PMOS transistor is connected to the output voltage, the gate is connected to the second bias voltage, and the drain is connected to the first terminal of the enable switch. The second terminal of the enable switch is connected to the first enable signal, the third terminal is connected to the second enable signal, and the fourth terminal is connected to the drain and gate of the third NMOS transistor. The source of the third NMOS transistor is grounded.

[0014] Furthermore, each of the aforementioned delay cascade units includes a sixth PMOS transistor, a fourth NMOS transistor, and an inverter; The source of the sixth PMOS transistor is connected to the output voltage, the gate is connected to the second bias voltage, and the drain is connected to the first terminal of the inverter. The gate of the fourth NMOS transistor is connected to the fourth terminal of the enable switch, the drain is connected to the second terminal of the inverter, and the source is grounded. The third terminal of the inverter serves as the input terminal of each of the delay cascade units, and the fourth terminal serves as the output terminal of each of the delay cascade units.

[0015] Furthermore, the output buffer unit includes multiple inverters connected in series, with the last inverter outputting the output clock signal.

[0016] On the other hand, this application also provides a high noise suppression frequency-locked loop control method based on closed-loop power supply tuning, including the following steps: The reference current and the feedback current are compared to generate an error current signal; The error current signal is filtered to generate a control voltage. The output voltage is dynamically adjusted according to the control voltage. The output voltage is used as the power supply voltage and frequency tuning voltage of the voltage-controlled oscillator to generate an output clock signal; The output clock signal is divided to generate a feedback clock signal, which is then converted into a feedback current and compared with the reference current to form a closed-loop control.

[0017] Compared with the prior art, the present invention has at least the following beneficial effects: This invention reuses the output voltage of a low-dropout linear regulator as the frequency tuning voltage of a voltage-controlled oscillator (VCO) and incorporates it into a frequency-locked loop feedback circuit. Leveraging the inherent high power supply rejection ratio (PSRR) of the low-dropout linear regulator, an independent, clean, and voltage-adjustable power supply domain is constructed around the VCO. This allows power supply noise to be filtered by a high PSRR and dynamically corrected through loop feedback before entering the VCO, reducing the coupling of power supply noise to the output clock phase and improving frequency stability and phase purity. Simultaneously, a current comparator accurately compares the reference current and the feedback current, eliminating dependence on process parameters such as power supply voltage and transistor threshold voltage, resulting in superior noise immunity and linearity. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the high noise suppression frequency-locked loop circuit based on closed-loop power supply tuning in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the current comparator and loop filter in Embodiment 1 of the present invention; Figure 3 This is a schematic diagram of the low-dropout linear regulator in Embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the voltage-controlled oscillator in Embodiment 1 of the present invention; Figure 5 This is a flowchart illustrating the high noise suppression frequency-locked loop control method based on closed-loop power supply tuning in Embodiment 2 of the present invention.

[0019] Reference numerals: U1, First operational amplifier; U2, Second operational amplifier; R1, First resistor; C1, First capacitor; MP1, First PMOS transistor; MP2, Second PMOS transistor; MN1, First NMOS transistor; VDD, Power supply voltage; Vctrl, Control voltage; C2, Second capacitor; C3, Third capacitor; S1, First switch; S2, Second switch; S3, Third switch; S4, Fourth switch; R2, Second resistor; C4, Fourth capacitor; MP3, Third PMOS transistor; MP4, Fourth PMOS transistor; MN2, Second NMOS transistor; C5, First... Five capacitors; C6, sixth capacitor; VB1, first bias voltage; VDD_VCO, output voltage; CLK_OUT, output clock signal; MP5, fifth PMOS transistor; MN3, third NMOS transistor; VB2, second bias voltage; ENB, first enable signal; ENI, second enable signal; MP6, sixth PMOS transistor; MN4, fourth NMOS transistor; IUP, reference current; IDN, feedback current; IREF, reference current; VREF1, first reference voltage; VREF2, second reference voltage; I1, first current source; I2, second current source. Detailed Implementation

[0020] Based on the teachings of this specification, those skilled in the art can form new technical solutions by combining different implementation methods without creating technical contradictions. Such variations should be considered to fall within the protection scope of this application.

[0021] The following will describe in more detail, with reference to the schematic diagrams, a high noise suppression frequency-locked loop circuit and control method based on closed-loop power supply tuning according to the present invention, wherein preferred embodiments of the present invention are shown. It should be understood that those skilled in the art can modify the present invention described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as being of broad knowledge to those skilled in the art and is not intended to limit the present invention.

[0022] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0023] Example 1 like Figures 1 to 4 As shown, this embodiment of the invention proposes a high noise suppression frequency-locked loop circuit based on closed-loop power supply tuning, including a current comparator, a loop filter, a low dropout linear regulator, a voltage-controlled oscillator, and a frequency divider.

[0024] The current comparator is used to compare the reference current IUP with the feedback current IDN, and generates an error current signal based on the comparison result.

[0025] The loop filter is connected to the current comparator and is used to generate a control voltage Vctrl based on the error current signal. The loop filter integrates and filters the error current signal, converting the current signal into a voltage signal to generate a smooth and stable control voltage Vctrl.

[0026] The low-dropout linear regulator is connected to the loop filter and serves as part of the closed-loop feedback path of the frequency-locked loop circuit. Its input terminal receives the control voltage Vctrl output by the loop filter, and its output terminal is connected to a voltage-controlled oscillator (VCO) to convert the control voltage Vctrl into a dynamically adjustable output voltage VDD_VCO. The output voltage VDD_VCO is used as both the power supply voltage and the frequency tuning voltage of the VCO.

[0027] The voltage-controlled oscillator (VCO) is connected to the low-dropout linear regulator (LDL-RCS) and its frequency is tuned by changes in the output voltage VDD_VCO to generate the output clock signal CLK_OUT. The oscillation frequency of the VCO is controlled by the output voltage VDD_VCO. Since the VCO is powered by the LDL-RCS, it is not directly affected by mains power supply noise, thus achieving better frequency stability and lower phase noise.

[0028] The frequency divider is connected to the voltage-controlled oscillator and the current comparator. It is used to divide the output clock signal CLK_OUT to generate a feedback clock signal, which is then sent to the current comparator for comparison with the reference current IUP, forming a closed-loop control path. Through this closed-loop feedback mechanism, the frequency locking loop can automatically adjust and lock onto the target frequency.

[0029] In this embodiment, as Figure 2As shown, the current comparator includes a first operational amplifier U1, a second operational amplifier U2, a first resistor R1, a first capacitor C1, a first PMOS transistor MP1, a second PMOS transistor MP2, and a first NMOS transistor MN1.

[0030] The non-inverting input of the first operational amplifier U1 is connected to a first reference voltage VREF1. The gate of the first PMOS transistor MP1 is connected to the output of the first operational amplifier U1, the source is connected to the power supply voltage VDD, and the drain is connected to the inverting input of the first operational amplifier U1. The drain of the first PMOS transistor MP1 is also grounded through the first resistor R1. The first operational amplifier U1, the first PMOS transistor MP1, and the first resistor R1 constitute a reference current IUP generation circuit. The negative feedback of the first operational amplifier U1 stabilizes the drain voltage of the first PMOS transistor MP1 at the value of the first reference voltage VREF1. The current flowing through the first resistor R1 is the reference current IUP.

[0031] The gate of the second PMOS transistor MP2 is connected to the output terminal of the first operational amplifier U1, the source is connected to the reference current IREF, and a comparator connection point is formed at the drain. The gates of the second PMOS transistor MP2 and the first PMOS transistor MP1 are connected together to form a current mirror structure, and the second PMOS transistor MP2 can accurately replicate the reference current IUP to the comparator connection point.

[0032] The non-inverting input of the second operational amplifier U2 is connected to the second reference voltage VREF2. The gate of the first NMOS transistor MN1 is connected to the output of the second operational amplifier U2, the drain is connected to the comparator connection point, and the source is connected to the inverting input of the second operational amplifier U2. The source of the first NMOS transistor MN1 is also grounded through the first capacitor C1.

[0033] Continue as Figure 2 As shown, the current comparator also includes a switching network, which includes a second capacitor C2, a third capacitor C3, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4.

[0034] One end of the first switch S1 and the second switch S2 are connected to the source of the first NMOS transistor MN1, and the other end is connected to one end of the second capacitor C2 and one end of the third capacitor C3, respectively. The other ends of the second capacitor C2 and the third capacitor C3 are both connected to ground. The first switch S1 and the second switch S2 are controlled by the first clock signal CLKN and the second clock signal CLKP, respectively. The third switch S3 is connected between one end of the second capacitor C2 and ground and is controlled by the second clock signal CLKP. The fourth switch S4 is connected between one end of the third capacitor C3 and ground and is controlled by the first clock signal CLKN.

[0035] The switching network employs two complementary, non-overlapping clock signals (first clock signal CLKN and second clock signal CLKP) to control the switches, alternately operating on two capacitors (second capacitor C2 and third capacitor C3). This achieves dual-channel alternating sampling, improving the accuracy and linearity of current comparison. Specifically, when the first clock signal CLKN is high, the first switch S1 is turned on, the second capacitor C2 samples and integrates the feedback current IDN, and simultaneously the fourth switch S4 is turned on, resetting the third capacitor C3. When the second clock signal CLKP is high, the second switch S2 is turned on, the third capacitor C3 samples and integrates the feedback current IDN, and simultaneously the third switch S3 is turned on, resetting the second capacitor C2.

[0036] The current comparator linearly maps the first reference voltage VREF1 to the reference current IREF. VREF1 is the value of the first reference voltage VREF1, IREF is the value of the reference current IREF, and R1 is the resistance value of the first resistor R1.

[0037] The feedback current IDN is generated by the periodic charging and discharging of the second capacitor C2 and the third capacitor C3 driven by the non-overlapping clock (i.e., the first clock signal CLKN / the second clock signal CLKP), and satisfies the following conditions: .

[0038] Where C_2 is the capacitance value of the second capacitor C2 or the third capacitor C3, VREF2 is the magnitude of the second reference voltage, and f_b is the feedback frequency ( (where N is the division ratio and f_out is the output frequency).

[0039] When the entire circuit is in steady state and the current balance condition IUP=IDN is forcibly satisfied, the output frequency expression is derived by combining the frequency relationship: This expression indicates that the output frequency is determined only by the ratio of the two reference voltages, the division ratio, the process constants of the first resistor R1 and the second capacitor C2 or the third capacitor C3, and is decoupled from parameters such as absolute power supply voltage, temperature and transistor threshold voltage, thus giving the circuit inherent high process, voltage and temperature robustness.

[0040] In this embodiment, continue as follows Figure 2 As shown, the loop filter includes a second resistor R2 and a fourth capacitor C4.

[0041] One end of the second resistor R2 is connected to the comparison connection point, and the other end is grounded through the fourth capacitor C4. The loop filter adopts a first-order RC low-pass filter structure, and an integration network is formed by the second resistor R2 and the fourth capacitor C4. The error current signal from the current comparator flows through the second resistor R2, is integrated across the fourth capacitor C4 to generate a control voltage Vctrl, which is then used to adjust the output frequency of the voltage-controlled oscillator.

[0042] In this embodiment, as Figure 3 As shown, the low-dropout linear regulator includes a third PMOS transistor MP3, a fourth PMOS transistor MP4, a second NMOS transistor MN2, a fifth capacitor C5, and a sixth capacitor C6.

[0043] The drain of the second NMOS transistor MN2 is connected to the first current source I1, the gate is connected to the first bias voltage VB1, and the source is grounded through the second current source I2.

[0044] The source of the third PMOS transistor MP3 is connected to the power supply voltage VDD, and its gate is connected between the drain of the first current source I1 and the drain of the second NMOS transistor MN2, forming an X connection point.

[0045] The source of the fourth PMOS transistor MP4 is connected to the drain of the third PMOS transistor MP3, forming a Z connection point; the drain of the fourth PMOS transistor MP4 is grounded through the second current source I2, and the gate is connected to the control voltage Vctrl.

[0046] One end of the fifth capacitor C5 is connected between the source of the second NMOS transistor MN2 and the second current source I2, forming a Y-connection point; the other end of the fifth capacitor C5 is connected to the Z-connection point. The fifth capacitor C5 constitutes a Miller compensation capacitor, connected between the input and output stages, utilizing the Miller effect to achieve pole separation and improve the frequency stability of the low-dropout linear regulator. Through the compensation effect of the fifth capacitor C5, loop oscillation can be effectively prevented.

[0047] The Z-connection point outputs the output voltage VDD_VCO. One end of the sixth capacitor C6 is connected to the Z-connection point, and the other end is grounded. The sixth capacitor C6 serves as an output filter capacitor and energy storage capacitor, used to smooth transient fluctuations in the output voltage VDD_VCO and suppress high-frequency noise. When the load current changes suddenly, the sixth capacitor C6 can provide transient current to maintain the stability of the output voltage VDD_VCO.

[0048] The low-dropout linear regulator, through a three-stage amplification structure consisting of the second NMOS transistor MN2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4, achieves high gain and large drive capability, providing a stable and reliable power supply voltage VDD for the voltage-controlled oscillator (VCO). Changes in the control voltage Vctrl are converted into changes in the output voltage VDD_VCO via the fourth PMOS transistor MP4, thereby achieving precise frequency adjustment of the VCO. Simultaneously, the low-dropout linear regulator exhibits excellent power supply rejection ratio (PSRR) performance, effectively isolating noise interference from the main power supply, providing a clean operating power supply for the VCO, and significantly reducing the oscillator's phase noise and frequency jitter.

[0049] In this embodiment, as Figure 4 As shown, the voltage-controlled oscillator includes a bias voltage supply unit, multiple delay cascade units, and an output buffer unit.

[0050] The bias voltage providing unit provides a bias current to each of the delay cascade units based on the output voltage VDD_VCO. The bias voltage providing unit receives the output voltage VDD_VCO from the low-dropout linear regulator as its power supply and generates a stable bias current, which is then distributed to each delay cascade unit. Through unified bias current control, the delay time of each delay cascade unit remains consistent, and the stability and linearity of the oscillation frequency are improved.

[0051] Multiple cascaded delay units are connected in series, with the last unit outputting a first voltage signal. These cascaded delay units generate a ring oscillation and adjust the oscillation frequency based on the output voltage. The multiple cascaded delay units constitute the basic structure of a ring oscillator, forming a positive feedback loop through their connection. Each cascaded delay unit provides a certain signal delay, and the cumulative delay across multiple stages forms an oscillation period. The number of stages in the cascaded delay unit must be odd to satisfy the oscillation condition; more stages result in a lower oscillation frequency but a wider frequency adjustment range.

[0052] In one specific embodiment, the number of delay cascade units is three. Of course, those skilled in the art can choose the number of delay cascade units based on design decisions such as target frequency, phase noise requirements, power budget, and matching with other loop parameters. For example, five or seven units are used, and no specific limitation is made here.

[0053] The output buffer unit is connected to the output terminal of the delay cascade unit. The first voltage signal is buffered by the output buffer unit and then output as the output clock signal CLK_OUT. Since the output signal of the delay cascade unit may have issues such as slow edges and insufficient amplitude, the output buffer unit shapes and drives the first voltage signal to obtain an output clock signal CLK_OUT with standard logic levels and fast rise and fall edges. Furthermore, the output buffer unit also acts as an isolation unit, preventing the impact of subsequent load changes on the oscillator, thus improving the quality and stability of the output clock signal CLK_OUT.

[0054] Furthermore, the bias voltage providing unit includes a fifth PMOS transistor MP5, an enable switch, and a third NMOS transistor MN3.

[0055] The source of the fifth PMOS transistor MP5 is connected to the output voltage VDD_VCO, the gate is connected to the second bias voltage VB2, and the drain is connected to the first terminal of the enable switch. The second terminal of the enable switch is connected to the first enable signal ENB, the third terminal is connected to the second enable signal ENI, and the fourth terminal is connected to the drain and gate of the third NMOS transistor MN3. The source of the third NMOS transistor MN3 is grounded.

[0056] The enable switch implements a transmission gate structure, which is complementaryly controlled by the first enable signal ENB and the second enable signal ENI. When the voltage-controlled oscillator needs to be started, the enable switch is turned on by the first enable signal ENB, transferring the current of the fifth PMOS transistor MP5 to the third NMOS transistor MN3; when the voltage-controlled oscillator needs to be turned off to save power, the enable switch is turned off by the second enable signal ENI, cutting off the current path. The fourth terminal of the enable switch serves as an output node, outputting a bias voltage.

[0057] The bias voltage providing unit provides a current source through the fifth PMOS transistor MP5. Controlled by the enable switch, a bias voltage is established on the third NMOS transistor MN3, providing a unified bias reference for the entire voltage-controlled oscillator. Changes in the output voltage VDD_VCO alter the current of the fifth PMOS transistor MP5, thereby changing the bias voltage and ultimately affecting the delay time and oscillation frequency of each cascaded delay unit, thus achieving the voltage-controlled frequency tuning function.

[0058] In this embodiment, each of the delay cascade units includes a sixth PMOS transistor MP6, a fourth NMOS transistor MN4, and an inverter.

[0059] The source of the sixth PMOS transistor MP6 is connected to the output voltage VDD_VCO, the gate is connected to the second bias voltage VB2, and the drain is connected to the first terminal of the inverter. The sixth PMOS transistor MP6 acts as a current source load, providing pull-up current to the inverter. The gate of the sixth PMOS transistor MP6 receives the second bias voltage VB2, sharing the same bias voltage as the fifth PMOS transistor MP5 in the bias voltage providing unit, forming a current mirror structure. Through the current mirror, the sixth PMOS transistor MP6 replicates the current characteristics of the fifth PMOS transistor MP5, providing a stable and controllable charging current to the inverter. The source of the sixth PMOS transistor MP6 is directly connected to the output voltage VDD_VCO, ensuring that the delay unit is entirely powered by an independent power supply provided by the low-dropout linear regulator, effectively isolating it from the influence of main power supply noise.

[0060] The gate of the fourth NMOS transistor MN4 is connected to the fourth terminal of the enable switch, its drain is connected to the second terminal of the inverter, and its source is grounded. The fourth NMOS transistor MN4 acts as a current source load, providing pull-down current to the inverter. The gate of the fourth NMOS transistor MN4 is connected to the bias voltage generated by the bias voltage providing unit, receiving unified bias control. The fourth NMOS transistor MN4 and the third NMOS transistor MN3 form a current mirror relationship, replicating the current characteristics of the third NMOS transistor MN3 to provide a stable discharge current for the inverter.

[0061] The third terminal of the inverter serves as the input terminal of each of the delay cascade units, and the fourth terminal serves as the output terminal of each of the delay cascade units. The charging and discharging speed of the inverter is precisely controlled by the controllable current provided by the sixth PMOS transistor MP6 and the fourth NMOS transistor MN4, thereby adjusting the delay time. When the input signal changes, the capacitive load at the output terminal is charged through the sixth PMOS transistor MP6 or discharged through the fourth NMOS transistor MN4; the charging and discharging time determines the delay time. The larger the current in the sixth PMOS transistor MP6 and the fourth NMOS transistor MN4, the faster the charging and discharging speed, the shorter the delay time, and the higher the oscillation frequency.

[0062] The cascaded delay unit achieves low-noise, high-linearity delay adjustment through current source control. Due to independent power supplies and unified bias control, the characteristics of each delay unit maintain good consistency, improving the stability and predictability of the oscillation frequency. Simultaneously, the current source structure naturally suppresses power supply noise, further reducing phase noise.

[0063] Furthermore, the output buffer unit includes multiple inverters connected in series, with the last inverter outputting the output clock signal CLK_OUT. The output buffer unit employs a multi-stage cascaded inverter structure, where each stage inverts and amplifies the signal. Through multi-stage buffering, the signal's driving capability is progressively enhanced, ultimately enabling the driving of larger load capacitors.

[0064] The inverter stages are typically designed to be even to maintain the phase relationship between the output signal and the output signal of the delay unit. The size of each inverter stage increases progressively in a certain proportion, forming a gradually increasing drive structure. This ensures sufficient drive capability while avoiding increased delay and edge degradation caused by excessive load on a single stage. The output buffer unit also serves as an isolation unit, isolating the load changes of subsequent stages from the core circuit of the oscillator and preventing load fluctuations from affecting the stability of the oscillation frequency.

[0065] In one specific embodiment, the number of inverters is two, which satisfies the requirement of in-phase buffering. Those skilled in the art can weigh the ratio of the load to be driven to the output capability of the preceding stage, combined with factors such as delay, power consumption, and area, and for example, the number could also be four, six, etc., without specific limitations here.

[0066] The voltage-controlled oscillator (VCO) described in this application adopts a multi-stage ring architecture, specifically configured as a current-starved ring oscillator. This allows the bias point of the tail current source or load transistor of the VCO to be directly modulated by the supply voltage (i.e., the output voltage VDD_VCO). When the control voltage Vctrl output by the loop filter in the frequency-locked loop feedback circuit increases, the output voltage VDD_VCO of the low-dropout linear regulator will increase synchronously and linearly. Accompanying the increase in output voltage VDD_VCO, the gate voltage of the core MOS transistor inside the VCO (i.e., the PMOS in the bias voltage supply unit and the PMOS transistor in each of the delay cascade units) increases synchronously, thereby driving the bias current to increase linearly.

[0067] The oscillation frequency of the voltage-controlled oscillator follows the inherent frequency relationship of a current-starved ring oscillator, and its expression is: ; Where f_osc represents the oscillation frequency of the voltage-controlled oscillator; N represents the number of stages in the delay cascade unit in the ring oscillator; C represents the total load capacitance driven by the output node of each stage of the delay cascade unit (including node parasitic capacitance and external circuit load capacitance); I represents the core bias current flowing through each stage of the delay cascade unit of the oscillator, the magnitude of which is determined by the operating state of the core MOS transistor inside the voltage-controlled oscillator.

[0068] Although the output voltage VDD_VCO exists in the denominator of the above frequency expression, the core bias current and the output voltage VDD_VCO have a strict linear positive correlation, and the oscillation frequency has a positive tuning relationship with the output voltage VDD_VCO. This allows the voltage-controlled oscillator to achieve a precise frequency response by dynamically adjusting the output voltage VDD_VCO according to the frequency locking requirements of the frequency lock loop.

[0069] This application, through the aforementioned design, reuses the frequency tuning voltage and power supply voltage of the voltage-controlled oscillator (VCO) of the low-dropout linear regulator (LDL-LED), eliminating the need for a separate tuning voltage port and associated internal tuning circuitry found in traditional VCO architectures. Simultaneously, leveraging the inherent high power supply rejection ratio (PSRR) of the LDL-LED, an independent, clean, and voltage-adjustable power supply domain is constructed. This allows power supply noise to be filtered by a high rejection ratio and dynamically corrected through loop feedback before entering the VCO, significantly reducing the impact of noise coupling on the VCO output clock and substantially improving the phase stability and frequency purity of the output clock.

[0070] Example 2 like Figure 5 As shown, this embodiment proposes a high-noise suppression frequency-locked loop control method based on closed-loop power supply tuning, including the following steps: S1. Compare the reference current IUP and the feedback current IDN to generate an error current signal.

[0071] The magnitude of the error current signal reflects the degree of frequency deviation, and the direction reflects the positive or negative sign of the deviation.

[0072] S2. The error current signal is filtered to generate a control voltage Vctrl. A loop filter performs a low-pass filter on the error current signal to remove high-frequency noise and extract low-frequency error information. Simultaneously, the loop filter integrates the error current signal, converting it into a voltage signal. This integration ensures that even if the error signal is small, sufficient control voltage Vctrl can be generated over a long period, achieving frequency locking with zero steady-state error. The magnitude and trend of the control voltage Vctrl reflect the direction and amplitude of frequency adjustment.

[0073] S3. Dynamically adjust the output voltage VDD_VCO according to the control voltage Vctrl.

[0074] S4. Using the output voltage VDD_VCO as the power supply voltage and frequency tuning voltage of the voltage-controlled oscillator, generate the output clock signal CLK_OUT.

[0075] The voltage-controlled oscillator (VCO) receives the output voltage VDD_VCO from the low-dropout linear regulator as its power supply voltage and frequency tuning voltage. The level of the output voltage VDD_VCO directly affects the charging and discharging rate of the internal delay unit of the VCO, thereby controlling the oscillation frequency. Furthermore, because the VCO is powered by an independent power supply, its operation is not directly affected by the noise of the main power supply, resulting in significantly improved oscillation frequency stability and a marked reduction in phase noise.

[0076] S5. Divide the output clock signal CLK_OUT to generate a feedback clock signal, convert the feedback clock signal into a feedback current IDN, and compare it with the reference current IUP to form a closed-loop control.

[0077] The output clock signal CLK_OUT is frequency-divided by a frequency divider to obtain a lower frequency feedback clock signal. The division ratio determines the ratio between the output frequency and the reference frequency; by setting different division ratios, frequency multiplication can be achieved. The feedback clock signal is converted into a feedback current IDN by a current conversion circuit, which carries information about the actual output frequency. The feedback current IDN is sent back to the current comparator and compared with the reference current IUP to form a complete closed-loop control path.

[0078] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A high-noise suppression frequency-locked loop circuit based on closed-loop power supply tuning, characterized in that, include: A current comparator is used to compare a reference current with a feedback current and generate an error current signal based on the comparison result. A loop filter, connected to the current comparator, is used to generate a control voltage based on the error current signal; The low dropout linear regulator, as a component of the closed-loop feedback path of the frequency-locked loop circuit, receives the control voltage output from the loop filter at its input terminal and connects to a voltage-controlled oscillator at its output terminal. It is used to convert the control voltage into a dynamically adjustable output voltage and to use the output voltage as both the power supply voltage and the frequency tuning voltage of the voltage-controlled oscillator. The voltage-controlled oscillator is connected to the low-dropout linear regulator and is frequency-tuned by the change of the output voltage to generate an output clock signal. The frequency divider, connected to the voltage-controlled oscillator and the current comparator, is used to divide the output clock signal to generate a feedback clock signal, and then send the feedback clock signal to the current comparator to form a closed-loop control path.

2. The high noise suppression frequency-locked loop circuit based on closed-loop power supply tuning as described in claim 1, characterized in that, The current comparator includes a first operational amplifier, a second operational amplifier, a first resistor, a first capacitor, a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor; The non-inverting input of the first operational amplifier is connected to a first reference voltage; The gate of the first PMOS transistor is connected to the output terminal of the first operational amplifier, the source is connected to the power supply voltage, and the drain is connected to the inverting input terminal of the first operational amplifier. The drain of the first PMOS transistor is also grounded through the first resistor. The gate of the second PMOS transistor is connected to the output terminal of the first operational amplifier, the source is connected to a reference current, and a comparison connection point is formed at the drain. The non-inverting input of the second operational amplifier is connected to a second reference voltage; The gate of the first NMOS transistor is connected to the output terminal of the second operational amplifier, the drain is connected to the comparator connection point, and the source is connected to the inverting input terminal of the second operational amplifier. The source of the first NMOS transistor is also grounded through the first capacitor.

3. The high noise suppression frequency-locked loop circuit based on closed-loop power supply tuning as described in claim 2, characterized in that, The current comparator further includes a switching network, which includes a second capacitor, a third capacitor, a first switch, a second switch, a third switch, and a fourth switch; One end of the first switch and the second switch are connected to the source of the first NMOS transistor, and the other end are respectively connected to one end of the second capacitor and one end of the third capacitor. The other ends of the second capacitor and the third capacitor are both connected to ground. The first switch and the second switch are controlled by a first clock signal and a second clock signal, respectively. The third switch is connected between one end of the second capacitor and ground, and is controlled by the second clock signal; The fourth switch is connected between one end of the third capacitor and ground, and is controlled by the first clock signal.

4. The high noise suppression frequency-locked loop circuit based on closed-loop power supply tuning as described in claim 2, characterized in that, The loop filter includes a second resistor and a fourth capacitor; One end of the second resistor is connected to the comparison connection point, and the other end is grounded through the fourth capacitor.

5. The high noise suppression frequency-locked loop circuit based on closed-loop power supply tuning as described in claim 1, characterized in that, The low-dropout linear regulator includes a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor, a fifth capacitor, and a sixth capacitor; The drain of the second NMOS transistor is connected to the first current source, the gate is connected to the first bias voltage, and the source is grounded through the second current source. The source of the third PMOS transistor is connected to the power supply voltage, and the gate is connected between the first current source and the drain of the second NMOS transistor, forming an X connection point. The source of the fourth PMOS transistor is connected to the drain of the third PMOS transistor, forming a Z-connection point; the drain of the fourth PMOS transistor is grounded through the second current source, and the gate is connected to the control voltage. One end of the fifth capacitor is connected between the source of the second NMOS transistor and the second current source, forming a Y connection point; the other end of the fifth capacitor is connected to the Z connection point. The Z-connection point outputs the output voltage; One end of the sixth capacitor is connected to the Z connection point, and the other end is grounded.

6. The high noise suppression frequency-locked loop circuit based on closed-loop power supply tuning as described in claim 1, characterized in that, The voltage-controlled oscillator includes a bias voltage supply unit, multiple delay cascade units, and an output buffer unit; The bias voltage providing unit provides a bias current to each of the delay cascade units according to the output voltage; Multiple delay cascade units are connected in series, with the output of the last delay cascade unit outputting a first voltage signal. The delay cascade unit is used to generate a ring oscillation and adjust the oscillation frequency according to the output voltage. The output buffer unit is connected to the output terminal of the delay cascade unit, and the first voltage signal is output as the output clock signal after being buffered by the output buffer unit.

7. The high noise suppression frequency-locked loop circuit based on closed-loop power supply tuning as described in claim 6, characterized in that, The bias voltage providing unit includes a fifth PMOS transistor, an enable switch, and a third NMOS transistor; The source of the fifth PMOS transistor is connected to the output voltage, the gate is connected to the second bias voltage, and the drain is connected to the first terminal of the enable switch. The second terminal of the enable switch is connected to the first enable signal, the third terminal is connected to the second enable signal, and the fourth terminal is connected to the drain and gate of the third NMOS transistor. The source of the third NMOS transistor is grounded.

8. The high noise suppression frequency-locked loop circuit based on closed-loop power supply tuning as described in claim 6, characterized in that, Each of the aforementioned delay cascade units includes a sixth PMOS transistor, a fourth NMOS transistor, and an inverter; The source of the sixth PMOS transistor is connected to the output voltage, the gate is connected to the second bias voltage, and the drain is connected to the first terminal of the inverter. The gate of the fourth NMOS transistor is connected to the fourth terminal of the enable switch, the drain is connected to the second terminal of the inverter, and the source is grounded. The third terminal of the inverter serves as the input terminal of each of the delay cascade units, and the fourth terminal serves as the output terminal of each of the delay cascade units.

9. The high noise suppression frequency-locked loop circuit based on closed-loop power supply tuning as described in claim 6, characterized in that, The output buffer unit includes multiple inverters connected in series, with the last inverter outputting the output clock signal.

10. A high-noise suppression frequency-locked loop control method based on closed-loop power supply tuning, characterized in that, Includes the following steps: The reference current and the feedback current are compared to generate an error current signal; The error current signal is filtered to generate a control voltage. The output voltage is dynamically adjusted according to the control voltage. The output voltage is used as the power supply voltage and frequency tuning voltage of the voltage-controlled oscillator to generate an output clock signal; The output clock signal is divided to generate a feedback clock signal, which is then converted into a feedback current and compared with the reference current to form a closed-loop control.

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