Phase locking method based on binary search, delay phase-locked loop and storage medium

Abstract

The invention discloses a phase locking method based on binary search, a delay phase-locked loop and a storage medium, and the method comprises the following steps: S1, initializing a digital-to-analog converter code into a minimum delay corresponding value of a differential voltage-controlled delay line, and setting an initial search step length; s2, in each control clock period, adjusting a current digital-to-analog converter code according to a polarity signal output by a phase discriminator, increasing or decreasing the current digital-to-analog converter code by a current search step length, and halving the search step length; and S3, the step S2 is repeated until the search step length is reduced to 1, and a phase locking state is achieved. According to the invention, the digital code which is output by the phase discriminator and represents the phase relationship between the reference clock and the input clock can be received, the delay is searched in a linear search mode, the control signal is sent to the delay line, and the clock delay is changed until the clock meeting the requirement is generated.

Description

Technical Field

[0001] This invention relates to the field of semiconductor phase-locked loop circuit technology, and in particular to a phase-locked loop method and approach based on binary search. Background Technology

[0002] In recent years, all-digital DLLs (AD-DLLs) have been extensively studied due to their superior scalability, lower power consumption, and faster lock-in time (TLock) under CMOS processes. These AD-DLLs rely entirely on digital modules, including digitally controlled delay lines (DCDLs), digital phase detectors (PDs), and digitally controlled loops (DCLs). The delay cells (DEs) within the DCDL are fully digital and are typically implemented using capacitor arrays or multiplexed delay lines to control propagation delay. However, AD-DLLs struggle to provide the high resolution required for high-performance wired links.

[0003] Conversely, analog and digital DLLs based on digital-to-analog converters (DACs), such as A-DLLs and DB-DLLs, can achieve higher operating frequencies and resolutions through highly optimized voltage-controlled delay lines (VCDLs) and phase detectors (PDs). High resolution is achieved through fine-grained control of the VCDL's bias or power supply. However, the enhanced time resolution in A-DLLs and DB-DLLs comes at the cost of increased lock-in duration (TLock), which is inversely proportional to time resolution. Furthermore, to prevent harmonic lock-in (i.e., locking onto an incorrect multiple of the required delay between the feedback and reference clocks), the initial conditions of the VCDL bias or power supply voltage must ensure that the feedback clock leads the reference clock at the PD input. Therefore, the DAC or charge pump (CP) must typically be initialized at the minimum encoding, resulting in a longer TLock.

[0004] One potential solution to long lock-in times is to use a coarse-fine tuning pattern, which adjusts the DAC encoding or capacitance ratio in large steps during DLL initialization until the PD detects the first polarity change of the phase difference (Δϕ) between the feedback clock and the reference clock. Once this occurs, the step size is reduced to achieve fine-grained resolution until the lock-in bias condition (Δϕ≈0) is met. While the coarse-fine tuning scheme improves lock-in time, it can lead to clock failure conditions, where the clock stops propagating in the VCDL due to a large bias overshoot. This condition is irreversible because the PD loses tracking of the Δϕ polarity, requiring a restart of the DLL initialization process and adjustment of parameters such as the coarse-tuning step size or the capacitive load of the DE within the VCDL. Importantly, in many DLL designs, this problem can lead to erroneous lock-in conditions that are not detected until late in the initialization process, potentially affecting subsystems that rely on the DLL output clock.

[0005] An extension of the AD-DLL lock-in time approach is to measure Δϕ using a time-to-digital converter (TDC), allowing the control code to be adjusted directly (or closer to) the lock-in condition in fewer steps. This is similar to the adaptive frequency calibration method used in phase-locked loops (PLLs). Summary of the Invention

[0006] To address the shortcomings of the prior art, the technical problem to be solved by this invention is: to propose a phase-locked loop (PLL) method based on binary search, a delay PLL, and a storage medium, which can receive the digital code representing the phase relationship between the reference clock and the input clock output by the phase detector, search for the delay using a linear search method and send control signals to the delay line, thereby changing the clock delay until a clock that meets the requirements is generated.

[0007] One technical solution adopted by this invention is to provide a phase-locked loop method based on binary search, which includes the following steps: S1: Initialize the digital-to-analog converter code to the minimum delay value corresponding to the differential voltage-controlled delay line, and set the initial search step size; the digital-to-analog converter code adopts the BS control mechanism, and the finite state machine is generated by traversing the binary tree; S2: In each control clock cycle, adjust the current digital-to-analog converter code according to the polarity signal output by the phase detector, increase or decrease the current digital-to-analog converter code by one current search step, and halve the search step; S3: Repeat step S2 until the search step size is reduced to 1, reaching the phase-locked state.

[0008] Furthermore, the method also includes the following steps: S4: Continuously monitor the clock signal output by the differential voltage-controlled delay line. If the clock signal stops during the execution of step S2, restore the digital-to-analog converter code to the last operating value, halve the current search step size, and continue to execute step S2.

[0009] Furthermore, step S1 includes the following sub-steps: S11: Initialize the digital-to-analog converter code to "0". Code "0" corresponds to the minimum delay of the differential voltage-controlled delay line to prevent harmonic lock-in. S12: Set the initial search step size to the middle value of the digital-to-analog converter code range.

[0010] Furthermore, step S2 includes the following sub-steps: S21: In each control clock cycle, read the polarity signal output by the phase detector, where the polarity signal is the phase difference polarity between the reference clock and the feedback clock; S22: Adjust the current digital-to-analog converter code according to the polarity of the polarity signal; if the polarity signal indicates that the reference clock is leading, increase the current search step by one; if the polarity signal indicates that the feedback clock is leading, decrease the current search step by one. S23: Shift the current search step size one position to the right to halve it.

[0011] Furthermore, step S2 also includes the following sub-steps: S24: Store the current digital-to-analog converter code as the working code, and retain the value of the previous digital-to-analog converter code.

[0012] Furthermore, step S3 includes the following sub-steps: S31: Determine if the current search step size is equal to 1; S32: If the search step size is equal to 1, then phase locking is completed and a locking completion flag is output; S33: If the search step size is not equal to 1, repeat step S2.

[0013] Furthermore, step S4 includes the following sub-steps: S41: Continuously sample the clock signal output by VCDL through a clock fault detector; S42: When the clock stops toggling, output a clock stop flag signal; S43: If a clock stop flag signal is detected during the execution of step S2, the recovery process is triggered to restore the digital-to-analog converter code to the last known working value and halve the current search step size; S44: If the clock stop condition persists, mark the error state and enter the waiting reset state.

[0014] The second technical solution adopted in this invention is a delay phase-locked loop based on binary search, comprising: a differential voltage-controlled delay line, a phase detector, a digital loop controller, a clock divider, and a digital-to-analog converter; the differential voltage-controlled delay line is used to generate a delayed version of the input clock, the phase detector is used to detect the phase difference between the reference clock and the feedback clock and output a polarity signal, the digital-to-analog converter is used to generate a bias voltage controlling the delay of the differential voltage-controlled delay line according to a digital code, and the digital loop controller is configured to execute a phase-locked loop method based on binary search, the method comprising: S1: Initialize the digital-to-analog converter code to the minimum delay corresponding value of the differential voltage-controlled delay line, and set the initial search step size; S2: In each control clock cycle, adjust the current digital-to-analog converter code according to the polarity signal output by the phase detector, increase or decrease the current digital-to-analog converter code by one current search step, and halve the search step; S3: Repeat step S2 until the search step size is reduced to 1, reaching the phase-locked state.

[0015] Furthermore, the digital loop controller is configured to perform a phase-locked loop method based on binary search, the method further comprising: S4: Continuously monitor the clock signal output by the differential voltage-controlled delay line. If the clock signal stops during the execution of step S2, restore the digital-to-analog converter code to the last operating value, halve the current search step size, and continue to execute step S2.

[0016] The third technical solution adopted by the present invention is a computer-readable storage medium storing at least one instruction, at least one program, code set, or instruction set, wherein the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the phase-locked loop method based on binary search as described in any of the above embodiments.

[0017] The binary search-based phase-locked loop method, delay phase-locked loop, and storage medium of the present invention have at least the following beneficial effects: 1. Rapid Lock-in: The system takes an extremely short time to reach a stable and accurate phase alignment state from startup. This directly determines the device's response speed after switching between sleep, startup, or mode, improving user experience and system efficiency.

[0018] 2. High resolution: The minimum time interval that a DLL can identify and adjust is extremely small, typically reaching picosecond or even sub-picosecond levels. Higher resolution results in more precise phase alignment of the clock signal, reducing timing errors and forming the cornerstone of accuracy in high-speed data transmission.

[0019] 3. Low jitter: The short-term fluctuations in clock signal edges over time are very small. This can be understood as the "stability" of the clock cycle. Low jitter means the clock signal is very "clean," which can significantly reduce the bit error rate of high-speed data transmission and improve system reliability.

[0020] 4. High energy efficiency: It consumes very little energy when performing specific functions (such as generating a stable clock). This translates to high performance per watt. This is crucial for battery-powered mobile devices and large data centers, effectively extending battery life or reducing operating costs.

[0021] 5. Strong robustness: The ability to maintain stable key system performance when faced with internal and external "interference" such as differences in manufacturing processes, changes in operating temperature, and fluctuations in power supply voltage. Ensuring that the chip can operate reliably in different usage environments and after long-term use is crucial for product quality and consistency. Attached Figure Description

[0022] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a flowchart of the phase-locked loop method based on binary search of the present invention.

[0023] Figure 2 This is a typical DB-DLL structure diagram of the present invention.

[0024] Figure 3 This is a structural diagram of the BS controller of the present invention. Detailed Implementation

[0025] The invention will now be further described with reference to the accompanying drawings.

[0026] Please see Figure 1 The above is a flowchart of the phase-locked loop method based on binary search according to the present invention. The method may include the following steps: S1. Initialize the digital-to-analog converter (DAC) code to the minimum delay value corresponding to the differential voltage-controlled delay line (DCCD) and set the initial search step size. The DAC code adopts a Black-Scholes (BS) control mechanism, and the finite state machine is generated by traversing a binary tree. This S1 step is the starting point of the BS (Binary Search) algorithm. By initializing the DAC code to the minimum delay value (e.g., 0), harmonic lock-in (i.e., locking onto an incorrect multiple of the delay) is effectively prevented, which is a defect of traditional DLLs emphasized in the disclosure. At the same time, setting the initial search step size to the middle value of the code range allows the algorithm to start from the midpoint of the search range and quickly narrow down the locking range. This directly contributes to fast locking (locking time reduced by 5-10 times) and high reliability, avoiding long search times or erroneous locking caused by improper initial conditions.

[0027] This S1 step may include the following sub-steps: S11. Initialize the digital-to-analog converter code to "0". Code "0" corresponds to the minimum delay of the differential voltage-controlled delay line to prevent harmonic lock-in. S12. Set the initial search step size to the midpoint of the DAC code range. This is step S11-S12. Steps S11-S12 initialize the DAC code to 0 (minimum delay) and set the step size to the midpoint. This makes the initialization process more specific, strengthens the effect of preventing harmonic lock-in, optimizes the search starting point, and further optimizes the lock-in speed. The explicitness of the sub-steps also improves the feasibility of the solution.

[0028] S2. In each control clock cycle, the current digital-to-analog converter (DAC) code is adjusted according to the polarity signal output by the phase detector. The current DAC code is increased or decreased by one current search step size, and the search step size is halved. This S2 step is the core iterative process of the BS algorithm. By adjusting the code according to the phase difference polarity (PDER) and halving the search step size, a binary tree traversal search is achieved, halving the search space in each iteration. This significantly improves the convergence speed and reduces the number of locking steps compared to traditional linear or coarse-fine adjustment methods. The disclosure states that the BS algorithm reduces the locking time by 5-10 times while maintaining high resolution (because the step size is halved to eventually reach a minimum step size of 1, achieving sub-picosecond accuracy). In addition, the halving operation has low cost in the digital domain (such as right shift), improving energy efficiency.

[0029] This S2 step may include the following sub-steps: S21. In each control clock cycle, read the polarity signal output by the phase detector, where the polarity signal is the phase difference polarity between the reference clock and the feedback clock. S22. Adjust the current digital-to-analog converter code according to the polarity of the polarity signal; if the polarity signal indicates that the reference clock is leading, increase the current search step by one; if the polarity signal indicates that the feedback clock is leading, decrease the current search step by one. S23. The current search step size is halved by shifting it one bit to the right. Steps S21-S23 involve reading the polarity signal and adjusting the code accordingly. This ensures the correct execution of the BS algorithm by explicitly determining the polarity (increasing the step size if the reference clock leads, and decreasing it if the feedback clock leads), thus avoiding phase error accumulation. Step S23 (halving the step size by shifting it to the right) highlights the efficiency of the digital domain, contributing to low power consumption and high energy efficiency.

[0030] This S2 step may also include the following sub-steps: S24. Store the current DAC code as the working code and retain the previous DAC code value. This S24 step requires storing both the current and previous DAC codes, which is the basis for the fault recovery mechanism. This supports step S4, ensuring that a "last known working value" is available for recovery, thereby enhancing fault tolerance. This improves system stability and prevents data loss.

[0031] S3. Repeat step S2 until the search step size is reduced to 1, achieving phase-locked state. This step S3 defines the convergence condition for locking. When the search step size is reduced to 1, the system declares phase lock (Δφ≈0), ensuring accurate phase alignment. This provides a stable locked state, reducing output clock jitter and thus improving the reliability of high-speed data transmission. Repeating the iteration until the minimum step size also ensures high-resolution implementation.

[0032] This S3 step may include the following sub-steps: S31. Determine if the current search step size is equal to 1; S32. If the search step size is equal to 1, then phase locking is completed and a locking completion flag is output. S33. If the search step size is not equal to 1, repeat step S2. These steps S31-S33, by determining whether the step size is equal to 1 and providing a lock flag, make the lock status detection more explicit. This facilitates system monitoring and control, contributing to user-friendliness and system integrability. Outputting the lock flag also helps in timely response, improving overall efficiency.

[0033] The method may also include the following steps: S4. Continuously monitor the clock signal output by the differential voltage-controlled delay line. If a clock signal stall is detected during step S2, restore the digital-to-analog converter code to its last operating value, halve the current search step size, and continue executing step S2. This step S4 is the core iterative process of the BS algorithm. By adjusting the code according to the phase difference polarity (PDER) and halving the search step size, a binary tree traversal search is achieved, halving the search space in each iteration. This significantly improves the convergence speed and reduces the number of locking steps compared to traditional linear or coarse-fine adjustment methods. The disclosure states that the BS algorithm reduces the locking time by 5-10 times while maintaining high resolution (because the step size is halved to eventually reach a minimum step size of 1, achieving sub-picosecond accuracy). In addition, the halving operation has low cost in the digital domain (e.g., right shift), improving energy efficiency.

[0034] This S4 step may include the following sub-steps: S41. Continuously sample the clock signal output by VCDL through the clock fault detector; S42. When the clock stops toggling, output a clock stop flag signal; S43. If a clock stop flag signal is detected during the execution of step S2, the recovery process is triggered to restore the digital-to-analog converter code to the last known working value and halve the current search step size. S44. If the clock stall condition persists, mark the error state and enter a wait-for-reset state. These steps S41-S44 utilize fault detection (e.g., sampling the clock signal, outputting the stall flag) and recovery procedures (e.g., code recovery, step size halving). This makes fault handling more systematic, including error state handling, further enhancing robustness. The disclosure emphasizes that this mechanism prevents subsystems from being affected, ensuring high-quality locking.

[0035] The principle of this method is as follows: A typical DB-DLL consists of a differential VCDL, PD, digital loop control or filter (DLC), clock divider (÷N), and DAC, such as Figure 2 As shown. The delay is dynamically controlled by the VCDL to ensure that Δϕ is locked regardless of changes in PVT and frequency. The VCDL generates multiple equally spaced phases of the input differential clock (CLKIN,P, CLKIN,N). The VCDL circuit is a chain-matched DE with variable load capacitance and / or variable drive strength, generating multiple equally spaced clock phases. The drive strength is modulated by changing the power supply or using a current-starved topology with a bias voltage. The DAC generates the bias or power supply voltage (VCTRL) for the DE.

[0036] The phase difference Δϕ is measured by the PD, which generates a binary output (PDER). For example, if CLKREF leads, the PDER is logic "1", otherwise logic "0". The PD controls the DLC, which adjusts the DAC code to ensure Δϕ≈0. Due to the binary nature of the PDER and the presence of jitter, the DLL will jitter by at least ±1 code even after locking. The DLC is controlled by CLKCTRL, which is a divided version of the input clock (CLKIN). Running the DLC at a lower frequency is necessary because synthesizing digital logic at very high frequencies is often challenging, and the DAC's settling time is relatively long compared to the input frequency. Therefore, the update rate or loop bandwidth is primarily determined by the DLC and DAC.

[0037] To reduce lock-in time, the DLC employs a BS control mechanism, where a finite state machine (FSM) generates DAC codes by traversing a binary tree. The BS control includes an accumulator, a shift register for adjusting the step size, and registers storing the current and previous DAC codes. The FSM is timed by a configurable clock divider supporting division ratios of N=1, 2, 4, 6, and 8. This clock divider reduces loop bandwidth, enhances the timing margin of the synchronization circuitry within the FSM, and minimizes output clock jitter. A toggle detector samples the CLKREF and issues a toggling flag when a clock stall condition occurs.

[0038] Instead of performing a linear or polynomial search, BS starts with code 0 (i.e., lowest latency) to prevent harmonic locking and then jumps directly to the midpoint of the code range. Depending on the polarity of the PDER, the search increases or decreases the code, halving the step size with each iteration. Fortunately, dividing by two in the digital domain is relatively inexpensive, requiring only a right shift of the binary code in the shift register. BS continues until the step size reaches 1, achieving the desired locking condition.

[0039] During reset and initialization, the step size is set to the midpoint of the code range, with the initial code being zero, although both the initial step size and code are configurable. The previous code (codepre) is always stored in case of clock failure conditions. In each iteration, the code is incremented or decremented based on the polarity of the PDER, and the step size is halved by right-shifting (>>) a logic "1" in the step size register. The toggling signal is then sampled. If toggling is high, the BS process continues until the step size reaches 1, at which point locking is declared by pulling the flag high.

[0040] If a clock stall condition (toggling=0) occurs, the code will revert to the last known working value, halve the step size for finer bias adjustments, and raise the `stall_event` flag. In the next cycle of `CLK_CTRL`, the code updates to the previous working value plus or minus a smaller step size. Even with this finer adjustment, if the clock stall condition persists, the FSM will flag an error and enter a wait state until the DLL is reset.

[0041] The structure diagram of the BS controller section is shown as follows: Figure 3 As shown. Two 10-bit FF registers store the previous and current DAC code values. A shift register manages the BS step size adjustment by shifting a logic "1" to the right. A 2:1 multiplexer (mux) selects the current or previous code based on the toggling state. The accumulator adjusts the 10-bit code by step[8:0] based on the PDER state. If toggling=0, the FF holding the previous code is disabled, and the mux passes the last known working code to the accumulator. When step[0] is "1", the lock flag is pulled high. When a clock fault is detected (toggling=0), the DAC code is restored to its last known good value, which is stored in the codepre register. The search step size is then adjusted (increased or decreased) based on the polarity of the PDER signal. The BS algorithm continues until the minimum step size of 1 is reached, at which point the DLL enters the lock condition.

[0042] The following example illustrates the process of this method: It utilizes a 3nm FinFET CMOS process, covering a wide frequency range from 533MHz to 4.26GHz. Its core architecture and operation flow are as follows: System Architecture: The DLL includes a differential voltage-controlled delay line (VCDL), a Bang-Bang phase detector (BBPD), a clock divider (÷N), a 10-bit digital-to-analog converter (DAC), and a digital loop controller (DLC). The VCDL consists of a chain of 10 pseudo-differential current-starved inverter (PS-CSI) delay units, with the delay precisely controlled by analog bias voltages (VCTRLP, VCTRLN) generated by the DAC. Each delay unit is equipped with a capacitor array selected by control signals (CBEN[1:0]) and a tail current transistor number adjusted by control signals (BWP[3:0], BWN[3:0]) to cover a wide frequency range from 533MHz to 4.26GHz.

[0043] Binary Search (BS) Locking Process: The DLC embeds a Finite State Machine (FSM) as the BS controller. At the start of the locking process, the DAC code is initialized to 0 (corresponding to the minimum delay of the VCDL), and the search step size is initialized to half of the full scale (e.g., 512 steps for a 10-bit DAC). The FSM performs the following operations in each control clock (CLK_CTRL) cycle: Based on the polarity of the BBPD output signal (PDER) (indicating the phase lead / lag relationship between the reference clock CLKREF and the feedback clock CLKFB), the current DAC code is increased or decreased by one current step size. The search step size is shifted right by one bit (i.e., halved). This process is repeated until the step size is reduced to 1, at which point the DLL enters the locked state and pulls the lock completion flag high. This process is completed within B+1 cycles (B is the DAC resolution). In this 10-bit DAC embodiment, the locking time is 11 control clock cycles, and the measured time at 4.26 GHz is less than 10.5 ns.

[0044] Clock Fault Detection and Recovery Mechanism: To address clock faults that may be caused by large initial steps in the BS, a toggle detector is integrated. This detector continuously samples the clock signal output by the VCDL (such as CLKREF). If it detects that the clock has stopped toggling, it immediately outputs a flag signal (toggling=0).

[0045] When the BS controller's FSM detects toggling=0, it automatically triggers the recovery process: The DAC code is restored to the last known working code value (stored in the codepre register). The current search step size is halved, allowing the BS process to continue with finer steps. This mechanism ensures that the DLL can quickly self-correct in the event of a clock outage without a complete restart, guaranteeing the robustness and determinism of the locking process.

[0046] This invention also provides a delay phase-locked loop based on binary search, comprising: a differential voltage-controlled delay line, a phase detector, a digital loop controller, a clock divider, and a digital-to-analog converter; the differential voltage-controlled delay line is used to generate a delayed version of the input clock, the phase detector is used to detect the phase difference between the reference clock and the feedback clock and output a polarity signal, the digital-to-analog converter is used to generate a bias voltage controlling the delay of the differential voltage-controlled delay line according to a digital code, and the digital loop controller is configured to execute a phase-locked loop method based on binary search, the method comprising: S1: Initialize the digital-to-analog converter code to the minimum delay corresponding value of the differential voltage-controlled delay line, and set the initial search step size; S2: In each control clock cycle, adjust the current digital-to-analog converter code according to the polarity signal output by the phase detector, increase or decrease the current digital-to-analog converter code by one current search step, and halve the search step; S3: Repeat step S2 until the search step size is reduced to 1, reaching the phase-locked state.

[0047] In some implementations, the digital loop controller is configured to perform a phase-locked loop method based on binary search, the method further comprising: S4: Continuously monitor the clock signal output by the differential voltage-controlled delay line. If the clock signal stops during the execution of step S2, restore the digital-to-analog converter code to the last operating value, halve the current search step size, and continue to execute step S2.

[0048] In one embodiment of this application, a computer device is provided, the computer device including a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the phase-locked loop method based on binary search as described in any of the above embodiments.

[0049] In one embodiment of this application, a computer-readable storage medium is provided, which stores at least one instruction, at least one program, code set, or instruction set, wherein the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the phase-locked loop method based on binary search as described in any of the above embodiments.

[0050] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and RAMbus dynamic RAM (RDRAM), etc.

[0051] The above description merely illustrates preferred embodiments of the present invention and is quite specific and detailed; however, it should not be construed as limiting the scope of the invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the inventive concept, and these all fall within the scope of protection of the present invention. Therefore, the scope of protection of this invention should be determined by the appended claims.

Claims

1. A phase-locked loop method based on binary search, characterized in that, The method includes the following steps: S1. Initialize the digital-to-analog converter code to the minimum delay value corresponding to the differential voltage-controlled delay line, and set the initial search step size; the digital-to-analog converter code adopts the BS control mechanism, and the finite state machine is generated by traversing the binary tree; S2. In each control clock cycle, adjust the current digital-to-analog converter code according to the polarity signal output by the phase detector, increase or decrease the current digital-to-analog converter code by one current search step, and halve the search step; S3. Repeat step S2 until the search step size is reduced to 1, reaching the phase-locked state.

2. The phase-locked loop method based on binary search as described in claim 1, characterized in that, The method also includes the following steps: S4. Continuously monitor the clock signal output by the differential voltage-controlled delay line. If the clock signal stops during the execution of step S2, restore the digital-to-analog converter code to the last working value, halve the current search step size, and continue to execute step S2.

3. The phase-locked loop method based on binary search as described in claim 1, characterized in that, Step S1 includes the following sub-steps: S11. Initialize the digital-to-analog converter code to "0". Code "0" corresponds to the minimum delay of the differential voltage-controlled delay line. S12. Set the initial search step size to the middle value of the digital-to-analog converter code range.

4. The phase-locked loop method based on binary search as described in claim 1, characterized in that, Step S2 includes the following sub-steps: S21. In each control clock cycle, read the polarity signal output by the phase detector, where the polarity signal is the phase difference polarity between the reference clock and the feedback clock. S22. Adjust the current digital-to-analog converter code according to the polarity of the polarity signal; If the polarity signal indicates that the reference clock is leading, then increase the current search step by one; If the polarity signal indicates that the feedback clock is leading, then reduce the current search step by one. S23. Shift the current search step size one position to the right to halve the current step size.

5. The phase-locked loop method based on binary search as described in claim 4, characterized in that, Step S2 further includes the following sub-steps: S24: Store the current digital-to-analog converter code as the working code, and retain the value of the previous digital-to-analog converter code.

6. The phase-locked loop method based on binary search as described in claim 1, characterized in that, Step S3 includes the following sub-steps: S31. Determine if the current search step size is equal to 1; S32. If the search step size is equal to 1, then phase locking is completed and a locking completion flag is output. S33. If the search step size is not equal to 1, repeat step S2.

7. The phase-locked loop method based on binary search as described in claim 2, characterized in that, Step S4 includes the following sub-steps: S41. Continuously sample the clock signal output by VCDL through the clock fault detector; S42. When the clock stops toggling, output a clock stop flag signal; S43. If a clock stop flag signal is detected during the execution of step S2, the recovery process is triggered to restore the digital-to-analog converter code to the last known working value and halve the current search step size. S44. If the clock stop condition persists, mark the error state and enter the waiting reset state.

8. A delay-locked loop based on binary search, comprising: Differential voltage-controlled delay line, phase detector, digital loop control, clock divider and digital-to-analog converter; The differential voltage-controlled delay line is used to generate a delayed version of the input clock; the phase detector is used to detect the phase difference between the reference clock and the feedback clock and output a polarity signal; the digital-to-analog converter is used to generate a bias voltage controlling the delay of the differential voltage-controlled delay line according to a digital code; the digital loop controller is configured to execute a phase-locked loop method based on binary search, the method comprising: S1. Initialize the digital-to-analog converter code to the minimum delay value corresponding to the differential voltage-controlled delay line, and set the initial search step size; S2. In each control clock cycle, adjust the current digital-to-analog converter code according to the polarity signal output by the phase detector, increase or decrease the current digital-to-analog converter code by one current search step, and halve the search step; S3. Repeat step S2 until the search step size is reduced to 1, reaching the phase-locked state.

9. The delay-locked loop based on binary search as described in claim 8, characterized in that, The digital loop controller is configured to execute a phase-locked loop method based on binary search, the method further comprising: S4: Continuously monitor the clock signal output by the differential voltage-controlled delay line. If the clock signal stops during the execution of step S2, restore the digital-to-analog converter code to the last operating value, halve the current search step size, and continue to execute step S2.

10. A computer-readable storage medium, characterized in that, The storage medium stores at least one instruction, at least one program, code set, or instruction set, wherein the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by a processor to implement the phase-locked loop method based on binary search as described in any one of claims 1-7.

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